阅读说明：本技术 半导体存储装置及其制造方法 (Semiconductor memory device and method of manufacturing the same ) 是由 福岛崇 藤田淳也 南云俊治 于 2019-02-14 设计创作，主要内容包括：实施方式提供一种半导体存储装置及其制造方法,降低在半导体存储装置所含的周边电路元件产生不良的概率。实施方式的半导体存储装置(1)具备：半导体衬底(21),具有第1面；第1半导体层(41),设置在所述半导体衬底的所述第1面的第1区域上；晶体管(51),设置在所述第1半导体层的上方；第2半导体层(41),设置在所述半导体衬底的所述第1面的第2区域上；层间绝缘体(42),设置在所述第1半导体层与所述第2半导体层之间；积层体,设置在所述半导体衬底的所述第1面的第3区域上,且包含交替积层的绝缘体(32)与导电体(31)。(Embodiments provide a semiconductor memory device and a method of manufacturing the same, which reduce the probability of defects occurring in peripheral circuit elements included in the semiconductor memory device. A semiconductor memory device (1) according to an embodiment includes: a semiconductor substrate (21) having a 1 st surface; a 1 st semiconductor layer (41) provided on a 1 st region of the 1 st face of the semiconductor substrate; a transistor (51) provided above the 1 st semiconductor layer; a 2 nd semiconductor layer (41) provided on a 2 nd region of the 1 st face of the semiconductor substrate; an interlayer insulator (42) disposed between the 1 st semiconductor layer and the 2 nd semiconductor layer; and a multilayer body provided on the 3 rd region of the 1 st surface of the semiconductor substrate and including insulators (32) and conductors (31) stacked alternately.)

1. A semiconductor memory device includes:

a semiconductor substrate having a 1 st face;

a 1 st semiconductor layer provided on a 1 st region of the 1 st face of the semiconductor substrate;

a transistor disposed above the 1 st semiconductor layer;

a 2 nd semiconductor layer provided on a 2 nd region of the 1 st face of the semiconductor substrate;

an insulator disposed between the 1 st semiconductor layer and the 2 nd semiconductor layer; and

and a multilayer body provided on the 3 rd region of the 1 st surface of the semiconductor substrate and including insulators and conductors stacked alternately.

2. The semiconductor memory device according to claim 1, wherein the 1 st semiconductor layer has a portion below having a length of the 1 st direction smaller than a length of the 1 st direction of an uppermost surface of the 1 st semiconductor layer.

3. The semiconductor memory device according to claim 1, wherein a length of a 1 st direction of an uppermost surface of the 1 st semiconductor layer is larger than a length of the 1 st direction of a lowermost surface of the 1 st semiconductor layer.

4. The semiconductor memory device according to claim 1, wherein a side surface of the 1 st semiconductor layer has no facet.

5. The semiconductor memory device according to claim 1, wherein the semiconductor substrate is single crystal, and the 1 st semiconductor layer is polycrystalline.

6. The semiconductor memory device according to claim 1, wherein an uppermost surface of the 1 st semiconductor layer is located above an uppermost surface of the semiconductor substrate.

7. The semiconductor memory device according to claim 1, wherein an uppermost surface of the 1 st semiconductor layer is located above an intermediate position in a lamination direction of the multilayer body.

8. The semiconductor memory device according to claim 1, wherein an uppermost surface of the 1 st semiconductor layer is located at the same position as an uppermost surface of the multilayer body in a lamination direction.

9. A method for manufacturing a semiconductor memory device includes the steps of:

forming an insulator over the 1 st face of the semiconductor substrate;

etching the insulator to expose a 1 st region of the 1 st surface of the semiconductor substrate;

forming a semiconductor layer on a 1 st region of the exposed 1 st surface of the semiconductor substrate; and

a transistor is formed over the semiconductor layer.

Technical Field

Background

A NAND flash memory in which memory cells are three-dimensionally stacked is known.

Disclosure of Invention

Drawings

Fig. 1 is a block diagram showing an example of the overall configuration of the semiconductor memory device according to embodiment 1.

Fig. 2 is a block diagram showing an example of a circuit configuration of a memory cell array of the semiconductor memory device according to embodiment 1.

Fig. 3 is a cross-sectional view showing an example of a cross-sectional structure of the semiconductor memory device according to embodiment 1.

Fig. 4 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 1.

Fig. 5 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 1.

Fig. 6 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 1.

Fig. 7 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 1.

Fig. 8 is a plan view showing an example of a pattern shape of a peripheral circuit portion in the manufacturing process of the semiconductor memory device according to embodiment 1.

Fig. 9 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 1.

Fig. 10 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 1.

Fig. 11 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 1.

Fig. 12 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 1.

Fig. 13 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 1.

Fig. 14 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 1.

Fig. 15 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 1.

Fig. 16 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 1.

Fig. 17 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 1.

Fig. 18 is a cross-sectional view showing an example of a manufacturing process of a semiconductor memory device according to a modification of embodiment 1.

Fig. 19 is a cross-sectional view showing an example of a manufacturing process of a semiconductor memory device according to a modification of embodiment 1.

Fig. 20 is a cross-sectional view showing an example of a cross-sectional structure of the semiconductor memory device according to embodiment 2.

Fig. 21 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 2.

Fig. 22 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 2.

Fig. 23 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 2.

Fig. 24 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 2.

Fig. 25 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 2.

Fig. 26 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 2.

Fig. 27 is a cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to embodiment 2.

Fig. 28 is a cross-sectional view showing an example of a cross-sectional structure of the semiconductor memory device according to embodiment 3.

Fig. 29 is a cross-sectional view showing an example of a cross-sectional structure of the semiconductor memory device according to embodiment 4.

Embodiments relate to a semiconductor memory device.