阅读说明：本技术 形成自对准触点 (Forming self-aligned contacts ) 是由 范淑贞 B·普拉纳萨蒂哈伦 A·格林 谢瑞龙 M·V·雷蒙德 S·连 于 2018-07-16 设计创作，主要内容包括：提供了通过在形成触点之前形成栅极侧壁间隔物和栅极来形成自对准触点的技术。在一个方面,一种形成自对准触点的方法包括以下步骤：在衬底上形成多个栅极侧壁间隔物；将栅极侧壁间隔物埋入电介质中；通过从栅极侧壁间隔物之间的将要形成栅极的区域选择性地去除电介质来形成栅极沟槽；在栅极沟槽中形成栅极；通过选择性地从栅极侧壁间隔物之间的将要形成自对准触点的区域去除电介质来形成触点沟槽；在触点沟槽中形成自对准触点。还提供了具有自对准触点的器件结构。(Techniques are provided for forming self-aligned contacts by forming gate sidewall spacers and gates prior to forming the contacts. In one aspect, a method of forming a self-aligned contact includes the steps of: forming a plurality of gate sidewall spacers on a substrate; burying gate sidewall spacers in the dielectric; forming a gate trench by selectively removing dielectric from a region between the gate sidewall spacers where a gate is to be formed; forming a gate in the gate trench; forming a contact trench by selectively removing dielectric from a region between the gate sidewall spacers where a self-aligned contact is to be formed; self-aligned contacts are formed in the contact trenches. Device structures having self-aligned contacts are also provided.)

1. A method of forming a self-aligned contact, the method comprising the steps of:

forming a plurality of gate sidewall spacers on a substrate;

burying the gate sidewall spacers in a dielectric;

forming a gate trench by selectively removing the dielectric from regions between the gate sidewall spacers where gates are to be formed;

forming the gate in the gate trench;

forming a contact trench by selectively removing the dielectric from regions between the gate sidewall spacers where self-aligned contacts are to be formed; and

self-aligned contacts are formed in the contact trenches.

2. The method of claim 1, further comprising the steps of:

forming a layer of spacer material on the substrate; and

patterning the layer of spacer material to form the gate sidewall spacers on the substrate.

3. The method of claim 2, wherein Sidewall Image Transfer (SIT) is used to pattern the layer of spacer material to form the gate sidewall spacers on the substrate.

4. The method of claim 3, further comprising the steps of:

forming a mandrel on the layer of spacer material;

forming a composite SIT spacer on opposing sides of the mandrel, wherein the composite SIT spacer comprises: i) a first spacer on an opposite side of the mandrel, and ii) a second spacer on one side of the first spacer on an opposite side of the mandrel.

5. The method of claim 4, further comprising the steps of:

removing the mandrels selective to the composite spacers;

patterning the layer of spacer material using the composite spacers;

selectively removing the second spacers; and

patterning the layer of spacer material using the first spacers.

6. The method of claim 1, further comprising the steps of:

forming a mask overlying between the gate sidewall spacers the regions where the self-aligned contacts are to be formed prior to selectively removing the dielectric from the regions between the gate sidewall spacers where gates are to be formed.

7. The method of claim 1, wherein the gate comprises a replacement metal gate, and wherein forming the gate in the gate trench comprises:

depositing a gate dielectric into the gate trench;

depositing a work function setting metal on the gate dielectric; and

depositing a fill metal on the work function setting metal.

8. The method of claim 7, wherein the gate dielectric comprises a high- κ material selected from the group consisting of hafnium oxide and lanthanum oxide.

9. The method of claim 7, wherein the workfunction setting metal is selected from the group consisting of: titanium nitride, tantalum nitride, and tungsten.

10. The method of claim 7, wherein the filler metal comprises aluminum.

11. The method of claim 1, wherein the self-aligned contact comprises a trench silicide.

12. The method of claim 11, wherein the trench silicide comprises nickel silicide.

13. The method of claim 1, further comprising the steps of:

at least one of the gates is selectively removed.

14. The method of claim 13, further comprising the steps of:

every other one of the gates is selectively removed.

15. The method of claim 13, further comprising the steps of:

all gates are masked except for the gate to be selectively removed.

16. The method of claim 13, further comprising the steps of:

filling at least the gate trench from which at least one of the gates has been selectively removed with an insulator.

17. The method of claim 16, wherein the insulator comprises a nitride material.

18. A device structure, comprising:

a plurality of gate sidewall spacers on the substrate; and

a gate and a contact self-aligned to the gate in a region between the gate sidewall spacers,

wherein each gate comprises a metal gate, and wherein each of the contacts comprises a trench silicide.

19. The device structure of claim 18, wherein at least one of the regions between the gate sidewall spacers comprises an insulator.

20. The device structure of claim 18, wherein the metal gate comprises:

a gate dielectric;

a work function setting metal on the gate dielectric; and

the workfunction setting metal is a fill metal on the metal.

21. The device structure of claim 18, wherein the gate sidewall spacers comprise a material selected from the group consisting of: silicon nitride, silicon carbonitride, silicon boron carbonitride, silicon oxy carbonitride and combinations thereof.

Technical Field

The present invention relates to techniques for forming self-aligned contacts, and more particularly, to forming self-aligned contacts by forming gate sidewall spacers (e.g., using Sidewall Image Transfer (SIT) techniques) and gates prior to forming the contacts.

Background

The replacement metal gate (or RMG) process has the advantage of protecting the gate stack from potentially damaging conditions because it is placed at the end of the process. For example, using RMG, a sacrificial or dummy gate is used as a placeholder, e.g., to place source and drain regions, etc. With a conventional RMG process flow, a dielectric is then deposited around the dummy gate, which allows the dummy gate to be replaced by a (replacement) metal gate stack. Source and drain contacts may then be formed between the metal gate stacks.

However, using scaled device technology involves smaller feature sizes than can reasonably be achieved using direct patterning technology. For example, the gate-to-gate spacing becomes so small that placing contacts between metal gate stacks is extremely challenging. Shrinking the size of the contacts is not always a viable option because it leads to an increase in the resistance of the contacts.

Therefore, scalable process techniques for forming self-aligned contacts would be desirable.

Disclosure of Invention

In one aspect of the invention, a method of forming a self-aligned contact is provided. The method comprises the following steps: forming a plurality of gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming a gate trench by selectively removing dielectric from a region between the gate sidewall spacers in which the gate is to be formed; forming a gate in the gate trench; forming a contact trench by selectively removing dielectric from a region between gate sidewall spacers, wherein a self-aligned contact is to be formed in the region between the gate sidewall spacers; and forming a self-aligned contact in the contact trench. Accordingly, embodiments of the present invention provide techniques for forming self-aligned contacts by forming gate sidewall spacers and gates prior to forming the contacts.

In another aspect of the invention, a device structure is provided. The device structure includes: a plurality of gate sidewall spacers on the substrate; and a gate and contacts self-aligned to the gate in regions between the gate sidewall spacers, wherein each gate comprises a metal gate, and wherein each contact comprises a trench silicide.

A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.

Drawings

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 is a cross-sectional view illustrating a starting platform for self-aligned contact formation comprising a substrate, a spacer material layer on the substrate, and a composite spacer/mandrel Sidewall Image Transfer (SIT) structure on the spacer material layer, according to an embodiment of the present invention;

FIG. 2 is a cross-sectional view showing that mandrels have been selectively removed for composite SIT spacers, in accordance with an embodiment of the present invention;

FIG. 3 is a cross-sectional view that illustrates a composite SIT spacer that has been used as a mask to pattern a layer of spacer material in accordance with an embodiment of the present invention;

FIG. 4 is a cross-sectional view illustrating that the second spacer has been selectively removed with respect to the first spacer, according to an embodiment of the present invention;

figure 5 is a cross-sectional view illustrating first spacers that have been used to further trim a layer of spacer material into a plurality of gate sidewall spacers, in accordance with an embodiment of the present invention;

FIG. 6 is a cross-sectional view showing a gate sidewall space that has been buried in a dielectric according to an embodiment of the present invention;

FIG. 7 is a cross-sectional view showing a mask that has been formed on/over the area between the gate sidewall spacers where a self-aligned contact is to be formed in accordance with an embodiment of the present invention;

FIG. 8 is a cross-sectional view showing a mask that has been used to allow selective removal of dielectric from regions between gate sidewall spacers where a Replacement Metal Gate (RMG) is to be formed, resulting in a gate trench between the gate sidewall spacers, in accordance with an embodiment of the present invention;

FIG. 9 is a cross-sectional view showing the gate stack material that has been deposited into and filling the gate trench in accordance with an embodiment of the present invention;

FIG. 10 is a cross-sectional view showing gate stack material that has been polished to form different gate stacks in the gate trench, in accordance with an embodiment of the present invention;

FIG. 11 is a cross-sectional view showing a mask that has been formed to selectively cover all but one or more of the gate stacks to be removed in accordance with an embodiment of the present invention;

FIG. 12 is a cross-sectional view that illustrates an etch through a mask to remove exposed gate stacks that has been performed in accordance with an embodiment of the present invention;

FIG. 13 is a cross-sectional view showing the region between the gate sidewall spacers from which the gate stack has been removed that has been filled with insulator in accordance with an embodiment of the present invention;

FIG. 14 is a cross-sectional view showing that dielectric has been selectively removed for metal gate stacks, forming a plurality of contact trenches between the gate stacks, in accordance with an embodiment of the present invention;

fig. 15 is a cross-sectional view showing a contact that has been formed in a contact trench according to an embodiment of the present invention; and

figure 16 is a cross-sectional view illustrating a side-by-side example of a composite spacer and a single spacer, according to an embodiment of the present invention.

Detailed Description

Techniques are provided for forming self-aligned contacts using Sidewall Image Transfer (SIT) techniques using a novel replacement metal gate (or RMG) process flow, wherein gate sidewall spacers are formed first, then RMGs are formed, and finally contact metallization. Advantageously, SIT allows for patterning sub-lithographic features (i.e., features smaller than those achievable using direct patterning techniques). SIT generally involves forming one or more mandrels, forming spacers on opposing sides of the mandrels, and then removing the mandrels selective to the spacers. The underlying substrate is then patterned using spacers. It is noted that for each patterned mandrel there will be at least two spacers. Thus, SIT is generally considered to be a cavity (pitch) doubling technique.

Exemplary embodiments of the present technique are now described with reference to fig. 1-15. As shown in fig. 1, the process begins with a substrate 102 on which it is desired to form a metal gate stack and a contact that is self-aligned to the metal gate stack. The particular configuration of the substrate 102 is not a primary focus of the present technique, but it is envisioned that the substrate is a semiconductor substrate, such as a bulk silicon (Si) wafer or a silicon-on-insulator (SOI) wafer that is prepared (using standard processes) to include one or more active regions comprising a planar or non-planar (e.g., fin) channel material upon which a metal gate stack and source and drain regions will be formed, wherein (currently self-aligned) contacts will be formed.

As described above, the first stage of the process includes first forming a plurality of gate sidewall spacers. These spacers are also referred to herein as "spacer sea". The gate sidewall spacers can be formed in a number of different ways, including via a standard direct patterning process. However, according to an exemplary embodiment, gate sidewall spacers are formed using SIT. Further, in the exemplary embodiment, the spacers are formed from a suitable spacer material, such as silicon nitride (SiN), silicon carbon nitride (SiCN), silicon boron nitride carbonitride (SiBCN), silicon oxygen nitride carbonitride (SiOCN), and combinations thereof. Also, a composite SIT spacer configuration is used in this example. As will be described in detail below, the composite spacer SIT prevents rounding at the top corners of the spacer. Rounding at the top corners of the spacers can result in large variations in the width of the device structure. In contrast, the use of a composite spacer enables the formation of a spacer having a square shoulder.

Thus, as shown in fig. 1, a layer of spacer material 104 is formed on the substrate 102. As described above, suitable spacer materials include, but are not limited to, SiN, SiCN, SiBCN, and/or SiOCN. A composite spacer SIT structure is then formed on the spacer material layer 104. As shown in fig. 1, the composite spacer SIT structure includes a plurality of mandrels 106, first spacers 108 on opposite sides of the mandrels 106, and second spacers 110 on one side of the first spacers 108 opposite the mandrels 106.

The mandrels 106 may be formed on the layer of spacer material 104 by first blanket depositing a suitable mandrel material over the layer of spacer material and then patterning the mandrel material into individual mandrels. Suitable mandrel materials include, but are not limited to, amorphous silicon (Si) and amorphous carbon. The amorphous silicon film can be deposited using, for example, a physical or chemical vapor deposition process. The amorphous carbon film may be deposited, for example, using magnetron sputtering. The mandrel 106 may be patterned using standard photolithography and etching techniques. For example, a patterned hard mask (e.g., silicon nitride (SiN)) (not shown) may be formed over the mandrel material, masking the footprint and location of the mandrels 106, as is known in the art. An etch through the patterned hard mask may then be performed to pattern the material in the respective mandrels 106. Suitable etching processes include, but are not limited to, anisotropic etching processes, such as Reactive Ion Etching (RIE). After etching, any remaining portions of the mandrel hardmask may be removed.

As described below, the mandrels 106 are selectively removed for the first spacers 108 and the second spacers 110, and then the second spacers 110 are selectively removed for the first spacers. Thus, the mandrels 106, first spacers 108, and second spacers 110 are preferably all formed of different materials to allow for selective removal. According to an exemplary embodiment, the first spacers 108 are made of silicon dioxide (SiO)₂) And the second spacers 110 are formed of nitride (such as SiN), or vice versa. The selective removal of one spacer over another can then be easily achieved using an oxide or nitride etch.

The first spacers 108 may be formed by depositing a corresponding spacer material and then using standard photolithography and etching techniques to form the individual spacers 108 on opposite sides of the mandrel 106. The same process may then be used to form second spacers on the side of the first spacers 108 opposite the mandrels 106. The result is the composite spacer configuration shown in fig. 1.

Next, as shown in fig. 2, the mandrels 106 are selectively removed for the composite spacers (first/second spacers 108/110). According to an exemplary embodiment, the mandrels 106 are removed using an isotropic etching process (e.g., a selective wet etch). What remains after the removal of the mandrels is the composite SIT spacer over the layer of spacer material 104. It is noted that the use of composite SIT spacers is merely an example, and embodiments of composite SIT spacers in which SIT patterning is used with more standard single spacer/mandrel configurations are contemplated herein.

The composite SIT spacers (i.e., first spacers 108/second spacers 110) are then used as a mask to pattern the layer of spacer material 104. See fig. 3. According to an exemplary embodiment, the spacer material layer is patterned using an anisotropic etching process that stops on the substrate 102. As described above, the composite spacer prevents rounding at the top corners of the spacer, thereby enabling formation of a spacer having a square shoulder.

Then, the second spacers 110 are selectively removed with respect to the first spacers 108. See fig. 4. As mentioned above, the first and second spacers are preferably formed of different materials, such as oxide versus nitride, and vice versa. In that case, an oxide or nitride selective etch may be used to remove the second spacers 110 relative to the first spacers 108. Removing the second spacers 110 allows a second etch to be performed on the layer of spacer material 104, further thinning the spacers.

That is, as shown in fig. 5, the layer of spacer material 104 is then further trimmed into a plurality (i.e., a substantial amount) of gate sidewall spacers using first spacers 108. The gate sidewall spacers, which will now be formed from the layer of spacer material 104, are given the reference numeral 104 a.

Now, the gate sidewall spacers have been formed, and the next stage in the process is to form the RMG. To this end, the gate sidewall space is buried in the dielectric 602 (see fig. 6), and then the dielectric 602 is selectively removed from the region between the gate sidewall spacers 104a where the RMG is to be formed (see fig. 7 and 8-described below). Suitable dielectrics include, but are not limited to, SiO₂. As shown in fig. 6, after deposition, the dielectric may be planarized (e.g., using a process such as chemical mechanical polishing or CMP, where the first spacers 108 act as an etch stop layer).

To allow selective removal of the dielectric 602 from the areas between the gate sidewall spacers 104a where the RMG will be formed, a mask 702 is formed over/covering the areas between the gate sidewall spacers 104a where the self-aligned contacts will be formed. See fig. 7. According to an exemplary embodiment, the mask 702 is a nitride (e.g., SiN) hard mask. For clarity, the labels SAC (for self-aligned contacts) and gate are now used in the figures to show the region between gate sidewall spacers 104a in which the self-aligned contacts and gate, respectively, are formed.

The use of mask 702 then allows selective removal of dielectric 602 from the areas between gate sidewall spacers 104a where RMG will be formed. See fig. 8. The mask 702 will protectA dielectric 602 present in the region between the gate sidewall spacers 104a where the self-aligned contact will be formed. For example only, when dielectric 602 is SiO₂In time, the dielectric 602 may be removed from the RMG area using an oxide selective etch that stops on the substrate 102. By this process, a gate trench is effectively formed between the gate sidewall spacers 104 a. See fig. 8.

As shown in fig. 9 and 10, RMG is then formed in the gate trench. That is, as shown in fig. 9, a gate stack material 902 is deposited into and fills the gate trench. For example only, the gate stack material may include a gate dielectric and a combination of a work function layer and a fill metal layer. For example, a gate dielectric may be deposited into the gate trench, followed by a workfunction setting metal (on the gate dielectric), followed by a fill metal (on the workfunction setting metal). Suitable gate dielectrics for metal gates include, but are not limited to, high-k materials such as hafnium oxide (HfO)₂) And lanthanum oxide (La)₂O₃). As used herein, the term "high- κ" refers to a material having a relative dielectric constant κ that is much higher than the relative dielectric constant κ of silicon dioxide (e.g., the dielectric constant κ of hafnium oxide is 4, 25 relative to the dielectric constant k of silicon dioxide). Suitable work function setting metals include, but are not limited to, n-type work function setting metals such as titanium nitride (TiN) and tantalum nitride (TaN), and p-type work function setting metals such as tungsten (W). Suitable filler metals include, but are not limited to, aluminum (Al). The gate stack material is generally represented in the figure by layer 902.

As shown in fig. 10, the gate stack material 902 may be polished using a chemical and/or mechanical polishing process (e.g., CMP). The result is that a different gate stack 1002 has been formed in the gate trench.

Self-aligned contacts will be formed in the regions between gate sidewall spacers 104a on opposite sides of each gate stack 1002. Each pair of self-aligned contacts will be associated with a particular gate stack 1002 with the particular gate stack 1002 between that pair of contacts. For example, take the case where self-aligned contacts are formed to the source and drain regions on opposite sides of each gate stack 1002. In this case, the self-aligned contact/gate stack/self-aligned contact combination of adjacent regions between the gate sidewall spacers 104a will correspond to a common transistor. To achieve this configuration, every other gate stack 1002 is selectively removed. See fig. 11 and 12.

As shown in fig. 11, removal of select gate stack 1002 may be accomplished using a selective mask 1102 (e.g., a SiN hard mask) that covers all gate stacks except the gate stack to be removed. The mask 1102 may be formed using standard photolithography and etching techniques. An etch through the mask 1102 may then be performed to remove the exposed gate stacks. See fig. 12. The particular etch chemistry used may depend on the gate stack material, and may require multiple etch steps to completely remove the gate metal, gate dielectric, etc.

The regions between the gate sidewall spacers 104a from which the gate stack has been removed may then be filled with an insulator 1302, such as SiN. See fig. 13. As shown in fig. 13, polishing (e.g., using CMP) may then be performed to remove the mask 1102 and any excess insulator 1302.

Since the gate sidewall spacers have been formed (first stage of the process) and the RMG has been formed (second stage of the process), a third stage of the process is now performed to form the self-aligned metal contacts. Referring to fig. 14 and 15, as highlighted above, contacts will be formed in the regions between the gate sidewall spacers 104a on opposite sides of each gate stack 1002. Thus, the contacts will be self-aligned with the gate stack 1002.

To begin the contact formation process, dielectric 602 is first removed selectively to metal gate stack 1002. See fig. 14. By way of example only, when dielectric 602 is a dielectric such as SiO₂For the oxide of (3), a process of selectively etching the oxide may be used. By removing dielectric 602, a plurality of contact trenches are formed between gate stacks 1002. See fig. 14. Contacts 1502 are then formed in the contact trenches. According to an exemplary embodiment, the contact 1502 is formed in the contact trench from trench silicide. By way of example only, one or more silicide metals are deposited into the contact trenches. The silicide will be silicidedWhere the metal is in contact with the silicon (e.g., in the source and drain regions of the substrate 102). Suitable silicide metals include, but are not limited to, nickel (Ni) (e.g., forming nickel silicide (NiSi)). An anneal (e.g., at a temperature of about 500 degrees celsius (c) to about 800 c, and ranges therebetween) is then used to react the silicide metal with the substrate 102 to form trench silicide within the contact trench (i.e., contact 1502)). Thereafter, any unreacted silicide metal may be removed.

As described above, the use of the composite spacer SIT prevents rounding at the top corners of the spacer, thereby enabling formation of a spacer having square shoulders. This concept is further illustrated in fig. 16, which shows a side-by-side example of a composite spacer on the left and a single spacer on the right. In the case of a composite spacer, only the outer spacer would be rounded. The internal spacer advantageously has a square shoulder. In contrast, for a single spacer, rounding is done at the upper corners. Such rounding in the final spacers can undesirably cause device width variations.

Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be affected therein by one skilled in the art without departing from the scope or spirit of the invention.