阅读说明：本技术 非易失性存储器结构 (Non-volatile memory structure ) 是由 陈明晖 于 2018-08-08 设计创作，主要内容包括：一种非易失性存储器结构，包括基底与多个存储单元。多个存储单元至少包括第一存储单元、第二存储单元、第三存储单元与第四存储单元。第二存储单元与第三存储单元位于第一存储单元的一侧，且第四存储单元位于第一存储单元的另一侧。每个存储单元包括彼此分离设置在基底中的第一阱区、第一掺杂区与第二掺杂区。第一存储单元与第二存储单元共享第一阱区。第一存储单元与第三存储单元共享第一掺杂区。第一存储单元与第四存储单元共享第二掺杂区。(A non-volatile memory structure includes a substrate and a plurality of memory cells. The plurality of memory cells at least comprises a first memory cell, a second memory cell, a third memory cell and a fourth memory cell. The second storage unit and the third storage unit are positioned on one side of the first storage unit, and the fourth storage unit is positioned on the other side of the first storage unit. Each memory cell includes a first well region, a first doped region, and a second doped region disposed in the substrate apart from each other. The first memory cell and the second memory cell share the first well region. The first memory cell and the third memory cell share the first doped region. The first memory cell and the fourth memory cell share the second doped region.)

1. A non-volatile memory structure, comprising:

a substrate; and

a plurality of storage units at least comprising a first storage unit, a second storage unit, a third storage unit and a fourth storage unit, wherein the second storage unit and the third storage unit are positioned at one side of the first storage unit, the fourth storage unit is positioned at the other side of the first storage unit,

each memory cell includes a first well region, a first doped region and a second doped region disposed in the substrate apart from each other,

the first memory cell and the second memory cell share the first well region,

the first memory cell and the third memory cell share the first doped region, and

the first memory cell and the fourth memory cell share the second doped region.

2. The non-volatile memory structure of claim 1, wherein each memory cell further comprises:

a second well region disposed in the substrate, wherein the second well region and the first well region are separated from each other;

a floating gate disposed on the substrate and covering a portion of the first well region and a portion of the second well region, wherein the first doped region and the second doped region are respectively located in the second well region on one side and the other side of the floating gate; and

a dielectric layer disposed between the floating gate and the substrate.

3. The non-volatile memory structure of claim 2, wherein the first well region shared by the first memory cell and the second memory cell extends from under the floating gate of the first memory cell to under the floating gate of the second memory cell.

4. The non-volatile memory structure of claim 3, wherein the first well region intersects one side of the floating gate and the first well region does not intersect the other side of the floating gate.

5. The non-volatile memory structure of claim 2, wherein the first well region, the first doped region, and the second doped region have a first conductivity type, and the second well region has a second conductivity type.

6. The non-volatile memory structure of claim 5, wherein each memory cell further comprises a third doped region disposed in the first well region on one side of the floating gate and having the first conductivity type, and the first memory cell shares the third doped region with the second memory cell.

7. The non-volatile memory structure of claim 2, wherein the floating gate of the first memory cell is located over a different second well region than the floating gate of the second memory cell.

8. The non-volatile memory structure of claim 2, wherein the floating gate of the first memory cell, the floating gate of the third memory cell, and the floating gate of the fourth memory cell are located over the same second well region.

9. The non-volatile memory structure of claim 1, wherein the first memory cell and the second memory cell are in a staggered arrangement, and the first memory cell and the third memory cell are in a staggered arrangement.

10. The non-volatile memory structure of claim 1, wherein the first memory cell and the fourth memory cell are mirror images.

Technical Field

The present invention relates to a memory structure, and more particularly, to a non-volatile memory structure.

Background

A non-volatile memory (non-volatile memory) is widely used in personal computers and electronic devices because it can perform operations such as data storage, data reading, and data erasing many times, and has advantages such as no loss of stored data when power supply is interrupted, short data access time, and low power consumption.

However, with the increasing integration of non-volatile memory devices, how to effectively reduce the area of the memory cell and increase the device density is a continuous goal of the industry.

Disclosure of Invention

The invention provides a nonvolatile memory structure which can effectively reduce the area of a memory cell and increase the density of elements.

The invention provides a nonvolatile memory structure, which comprises a substrate and a plurality of memory units. The plurality of memory cells at least comprises a first memory cell, a second memory cell, a third memory cell and a fourth memory cell. The second storage unit and the third storage unit are positioned on one side of the first storage unit, and the fourth storage unit is positioned on the other side of the first storage unit. Each memory cell includes a first well region, a first doped region, and a second doped region disposed in the substrate apart from each other. The first memory cell and the second memory cell share the first well region. The first memory cell and the third memory cell share the first doped region. The first memory cell and the fourth memory cell share the second doped region.

According to an embodiment of the invention, in the above-mentioned nonvolatile memory structure, each memory cell may further include a second well region, a floating gate and a dielectric layer. The second well region is disposed in the substrate. The second well region and the first well region are separated from each other. The floating gate is disposed on the substrate and covers a portion of the first well region and a portion of the second well region. The first doped region and the second doped region may be located in the second well region on one side and the other side of the floating gate, respectively. The dielectric layer is arranged between the floating gate and the substrate.

According to an embodiment of the present invention, in the above-mentioned nonvolatile memory structure, the first well region shared by the first memory cell and the second memory cell may extend from below the floating gate of the first memory cell to below the floating gate of the second memory cell.

According to an embodiment of the invention, in the above-mentioned nonvolatile memory structure, the first well region may intersect with one side of the floating gate, and the first well region may not intersect with the other side of the floating gate.

According to an embodiment of the present invention, in the above-mentioned nonvolatile memory structure, the first well region, the first doped region and the second doped region may have a first conductivity type, and the second well region may have a second conductivity type.

According to an embodiment of the invention, in the above-mentioned nonvolatile memory structure, each memory cell may further include a third doped region. The third doped region is disposed in the first well region on one side of the floating gate. The third doped region may have the first conductivity type. The first memory cell and the second memory cell may share the third doped region.

According to an embodiment of the present invention, in the above-mentioned nonvolatile memory structure, the floating gate of the first memory cell and the floating gate of the second memory cell may be located above different second well regions.

According to an embodiment of the invention, in the above-mentioned nonvolatile memory structure, the floating gate of the first memory cell, the floating gate of the third memory cell and the floating gate of the fourth memory cell may be located above the same second well region.

According to an embodiment of the present invention, in the nonvolatile memory structure, the first memory cell and the second memory cell may be arranged in a staggered manner, and the first memory cell and the third memory cell may be arranged in a staggered manner.

According to an embodiment of the invention, in the above-mentioned nonvolatile memory structure, the first memory cell and the fourth memory cell may be mirror images.

Based on the above, in the non-volatile memory structure provided by the present invention, the first memory cell and the second memory cell share the first well region, the first memory cell and the third memory cell share the first doped region, and the first memory cell and the fourth memory cell share the second doped region.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a top view of a non-volatile memory structure according to an embodiment of the invention.

Fig. 2 is an enlarged view of a portion of fig. 1 at block.

FIG. 3 is a sectional view taken along line I-I 'and line II-II' of FIG. 2.

[ notation ] to show

100: non-volatile memory structure

102: substrate

104. 110: well region

106. 108, 116: doped region

112: floating gate

114: dielectric layer

118: corner

120: isolation structure

122. 124, 126: contact window

C: capacitor with a capacitor element

MC 1-MC 4: memory cell

T: transistor with a metal gate electrode

Detailed Description

FIG. 1 is a top view of a non-volatile memory structure according to an embodiment of the invention. Fig. 2 is an enlarged view of a portion of fig. 1 at block. FIG. 3 is a sectional view taken along line I-I 'and line II-II' of FIG. 2. In fig. 3, the contact window in fig. 2 is omitted for simplicity.

Referring to fig. 1 to 3, a non-volatile memory structure 100 includes a substrate 102 and a plurality of memory cells. The non-volatile memory structure 100 can be applied to a multi-time programmable (MTP) memory element or a one-time programmable (OTP) memory element. The substrate 102 may be a semiconductor substrate, such as a silicon substrate.

The plurality of memory cells at least includes a memory cell MC1, a memory cell MC2, a memory cell MC3 and a memory cell MC 4. In the present embodiment, the layout design of the nonvolatile memory structure 100 is illustrated by taking the memory cell MC1, the memory cell MC2, the memory cell MC3 and the memory cell MC4 as examples. The memory cell MC2 and the memory cell MC3 are located on one side of the memory cell MC1, and the memory cell MC4 is located on the other side of the memory cell MC 1. The memory cell MC1 and the memory cell MC2 may be in a staggered arrangement, and the memory cell MC1 and the memory cell MC3 may be in a staggered arrangement, thereby contributing to a reduction in memory cell area and an increase in device density. The memory cell MC1 and the memory cell MC4 may be mirror images.

Taking memory cell MC1 as an example, each memory cell includes well region 104, doped region 106, and doped region 108 disposed in substrate 102 separately from one another. Well region 104 may function as a control gate. The doped regions 106 and 108 may serve as one and the other of a source and a drain, respectively. The memory cell MC1 and the memory cell MC2 share the well 104, the memory cell MC1 and the memory cell MC3 share the doped region 106, and the memory cell MC1 and the memory cell MC4 share the doped region 108.

In addition, the well region 104, the doped region 106 and the doped region 108 may have the first conductivity type. Hereinafter, the first conductivity type and the second conductivity type may be one and the other of an N-type conductivity and a P-type conductivity, respectively. In the present embodiment, the first conductive type is an N-type conductive type, and the second conductive type is a P-type conductive type, but the invention is not limited thereto. In another embodiment, the first conductivity type may be a P-type conductivity type, and the second conductivity type may be a P-type conductivity type. The well 104, the doped region 106 and the doped region 108 are formed by ion implantation, for example.

In addition, taking the memory cell MC1 as an example, each memory cell may further include at least one of the well region 110, the floating gate 112, the dielectric layer 114, and the doped region 116. Well region 110 is disposed in substrate 102. Well region 110 and well region 104 are separated from each other. The well region 110 may have a second conductivity type (e.g., P-type). The well 110 is formed by ion implantation, for example.

The floating gate 112 is disposed on the substrate 102. The floating gate 112 may be used to store charge. The floating gate 112 covers a portion of the well region 104 and a portion of the well region 110, thereby reducing process damage to the well region 104 and the well region 110. The material of the floating gate 112 may be polysilicon, such as doped polysilicon or undoped polysilicon. The doped regions 106 and 108 may be located in the well 110 on one side and the other side of the floating gate 112, respectively. The floating gate 112 is formed, for example, by a combined deposition process, a photolithography process, and an etching process.

In addition, the well region 104 shared by the memory cell MC1 and the memory cell MC2 may extend from under the floating gate 112 of the memory cell MC1 to under the floating gate 112 of the memory cell MC 2. The well region 104 and one side of the floating gate 112 may intersect, and the well region 104 and the other side of the floating gate 112 may not intersect. Since the corner (corner)118 at the intersection of the well region 104 and the floating gate 112 is prone to generate a leakage path, the number of corners 118 at the intersection of the well region 104 and the floating gate 112 can be reduced without the well region 104 intersecting the other side of the floating gate 112. That is, the leakage path can be reduced to reduce the leakage. For example, in fig. 2, there are only two corners 118 where each well region 104 intersects each floating gate 112, but the invention is not limited thereto.

In addition, the floating gate 112 of the memory cell MC1 and the floating gate 112 of the memory cell MC2 may be located above different well regions 110. The floating gate 112 of the memory cell MC1, the floating gate 112 of the memory cell MC3, and the floating gate 112 of the memory cell MC4 may be located over the same well region 110.

A dielectric layer 114 is disposed between the floating gate 112 and the substrate 102. The material of the dielectric layer 114 is, for example, silicon oxide. The dielectric layer 114 is formed by, for example, thermal oxidation.

A doped region 116 is disposed in the well region 104 on one side of the floating gate 112. The doped region 116 may have a first conductivity type (e.g., N-type). The memory cell MC1 and the memory cell MC2 may share the doped region 116. The doped region 116 is formed by ion implantation, for example.

Furthermore, the non-volatile memory structure 100 may further include at least one of an isolation structure 120, a contact 122, a contact 124, and a contact 126. The isolation structures 120 may be disposed between adjacent well regions 104, between adjacent well regions 110, and between adjacent well regions 104 and 110. The material of the isolation structure 120 is, for example, silicon oxide. The isolation structure 120 is, for example, a shallow trench isolation structure.

Contact windows 122 may be electrically connected to well regions 104. In the present embodiment, the contact window 122 is electrically connected to the well 104 through the doped region 116, for example, but the invention is not limited thereto. The contact windows 124 and 126 may be electrically connected to the doped regions 106 and 108, respectively. The material of the contact windows 122, 124 and 126 is, for example, tungsten, copper or aluminum.

In each memory cell, for example, memory cell MC1, a capacitor C of a first conductivity type (e.g., N-type) may be formed by floating gate 112, dielectric layer 114 and well 104, and a transistor T of the first conductivity type (e.g., N-type) may be formed by floating gate 112, dielectric layer 114, doped region 106 and doped region 108. The floating gate 112 is connected between the capacitor C and the transistor T. The well region 104 in the capacitor C can be used as a control gate to control the transistor T to be turned on and off (on/off).

In addition, the non-volatile memory structure 100 may further have other interconnect structures electrically connected to the contact windows 122, 124 and 126. For example, the nonvolatile memory structure 100 may further include word lines, bit lines, and source lines, and the layout of the word lines, the bit lines, and the source lines may be determined by one skilled in the art according to the layout design, and therefore, the description thereof is omitted.

In addition, the memory cells in the non-volatile memory structure 100 can be programmed by hot carrier injection (hot carrier injection) or F-N tunneling (F-N tunneling) and erased by band-to-band tunneling (BTBT) or F-N tunneling.

Based on the above embodiments, in the nonvolatile memory structure 100, the memory cell MC1 and the memory cell MC2 share the well 104, the memory cell MC1 and the memory cell MC3 share the doped region 106, and the memory cell MC1 and the memory cell MC4 share the doped region 108.

Although the layout of the nonvolatile memory structure 100 is described with reference to the layout design between the memory cell MC1 and its neighboring memory cells in the above embodiment, the layout design can be applied to other memory cells in the nonvolatile memory structure 100.

In summary, in the nonvolatile memory structure of the above embodiments, the layout design between a single memory cell and the adjacent memory cells can effectively reduce the area of the memory cell and increase the device density.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.