阅读说明：本技术 半导体结构及其制造方法 (Semiconductor structure and manufacturing method thereof ) 是由 周耀辉 任小兵 刘群 金炎 王德进 于 2018-08-15 设计创作，主要内容包括：本发明涉及一种半导体结构,包括：衬底；浮栅,设于所述衬底上；硅氧化物层,覆盖所述浮栅；无掺杂多晶硅层,设于所述硅氧化物层上；介质层,设于所述无掺杂多晶硅层上；及金属层,设于所述介质层上。本发明将传统的作为SAB的SiO<Sub>2</Sub>介质替换成硅氧化物层+无掺杂多晶硅层,使得硅氧化物层在厚度较薄的情况下,仍然能够通过无掺杂多晶硅层保证良好的电子隔绝能力,从而可以兼顾填充能力与电子隔绝能力。(The invention relates to a semiconductor structure, comprising: a substrate; the floating gate is arranged on the substrate; a silicon oxide layer covering the floating gate; an undoped polysilicon layer disposed on the silicon oxide layer; the dielectric layer is arranged on the undoped polysilicon layer; and the metal layer is arranged on the dielectric layer. The invention uses the conventional SiO as SAB 2 The medium is replaced by a silicon oxide layer and an undoped polysilicon layer, so that the silicon oxide layer can still ensure good electronic isolation capability through the undoped polysilicon layer under the condition of a thin thickness, and the filling capability and the electronic isolation capability can be considered at the same time.)

1. A semiconductor structure, comprising:

a substrate;

the floating gate is arranged on the substrate;

a silicon oxide layer covering the floating gate;

an undoped polysilicon layer disposed on the silicon oxide layer;

the dielectric layer is arranged on the undoped polysilicon layer; and

and the metal layer is arranged on the dielectric layer.

2. The semiconductor structure of claim 1, wherein the silicon oxide layer has a thickness of

3. The semiconductor structure of claim 1, wherein the undoped polysilicon layer has a thickness of

4. The semiconductor structure of claim 1, further comprising a contact hole disposed on a side surface of the floating gate, wherein a metal plug is disposed in the contact hole.

5. The semiconductor structure of claim 4, further comprising:

the metal silicide layer is formed on the surface of the substrate, and the bottom of the metal plug is in contact with the metal silicide layer; and

and the contact hole etching stop layer is arranged between the undoped polysilicon layer and the silicon oxide layer.

6. The semiconductor structure of any of claims 1-5, wherein the semiconductor structure is an embedded one-time programmable structure.

7. A method of fabricating a semiconductor structure, comprising:

forming a floating gate on a substrate;

forming a silicon oxide layer on the floating gate to serve as a metal silicide blocking layer;

forming an undoped polysilicon layer on the silicon oxide layer;

forming a dielectric layer on the undoped polysilicon layer; and

and forming a metal layer on the dielectric layer.

8. The method of claim 7, further comprising forming a contact hole on a side of the floating gate after the step of forming a dielectric layer on the undoped polysilicon layer and before the step of forming a metal layer on the dielectric layer.

9. The method of manufacturing a semiconductor structure according to claim 7, further comprising:

forming a metal contact, including forming a metal silicide layer on the surface of the substrate;

and forming a contact hole etching stop layer on the metal silicide layer.

10. The method of claim 7, wherein the step of forming an undoped polysilicon layer over the silicon oxide layer is a low pressure chemical vapor deposition of undoped polysilicon.

Technical Field

The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure.

Background

An Embedded one-time programmable (Embedded OTP) Feature is a semiconductor device structure widely used, and has the main advantages of compatibility with a CMOS process, no need of an additional photomask or a special process, short development time, and suitability for promoting efficient development of derivative products meeting market requirements on a mature process platform.

As semiconductor Critical Dimensions (CD) shrink (scaling down) to 0.11 μm and below, such device structures encounter more process challenges. The most significant process challenge comes from the small distance between gates (e.g., floating gates) resulting in SiO as a metal Silicide Area Block (SAB)₂The ability of the dielectric to fill (gap fill) is not compatible with the ability to isolate injected electrons in the floating gate. To ensure SiO as SAB₂The medium has better filling, the layer is SiO₂The dielectric must not be too thick, which results in poor isolation of electrons injected in the floating gate.

Disclosure of Invention

In view of the above, it is desirable to provide a semiconductor structure that can achieve both fill capability and electrical isolation capability.

A semiconductor structure, comprising: a substrate; the floating gate is arranged on the substrate; a silicon oxide layer covering the floating gate; an undoped polysilicon layer disposed on the silicon oxide layer; the dielectric layer is arranged on the undoped polysilicon layer; and the metal layer is arranged on the dielectric layer.

In one embodiment, the silicon oxide layer has a thickness of

In one embodiment, the thickness of the undoped polysilicon layer is

In one embodiment, the floating gate structure further comprises a contact hole arranged on the side face of the floating gate, and a metal plug is arranged in the contact hole.

In one embodiment, the metal plug further comprises a metal silicide layer formed on the surface of the substrate, and the bottom of the metal plug is in contact with the metal silicide layer; and a contact hole etching stop layer arranged between the undoped polysilicon layer and the silicon oxide layer.

In one embodiment, the semiconductor structure is an embedded one-time programmable structure.

It is also desirable to provide a method of fabricating a semiconductor structure.

A method of fabricating a semiconductor structure, comprising: forming a floating gate on a substrate; forming a silicon oxide layer on the floating gate to serve as a metal silicide blocking layer; forming an undoped polysilicon layer on the silicon oxide layer; forming a dielectric layer on the undoped polysilicon layer; and forming a metal layer on the dielectric layer.

In one embodiment, after the step of forming a dielectric layer on the undoped polysilicon layer and before the step of forming a metal layer on the dielectric layer, a step of forming a contact hole on the side surface of the floating gate is further included.

In one embodiment, the method further comprises the following steps: forming a metal contact, including forming a metal silicide layer on the surface of the substrate; and forming a contact hole etching stop layer on the metal silicide layer.

In one embodiment, the step of forming an undoped polysilicon layer on the silicon oxide layer is a low pressure chemical vapor deposition of undoped polysilicon.

The semiconductor structure is formed by using SiO as SAB₂The dielectric is replaced with a silicon oxide layer + an undoped polysilicon layer. The reason for the poor electron-blocking ability of the conventional SAB is the formation of SiO by deposition₂Polar bonds are easy to introduce into the medium, so that the silicon oxide layer is still enabled to ensure good electronic isolation capability (the undoped polysilicon layer isolates electron flow between the floating gate and the metal layer) under the condition of thin thickness (the thinner silicon oxide layer can ensure that the silicon oxide layer and the undoped polysilicon layer have better filling) by the undoped polysilicon layer by arranging the undoped polysilicon layer on the silicon oxide layer and utilizing the relatively compact structure and the better electronic isolation characteristic of the undoped polysilicon layer.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure in one embodiment;

FIG. 2 is a flow chart of a method of fabricating a semiconductor structure in one embodiment.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

As used herein, the term semiconductor is used in the art to distinguish between P-type and N-type impurities, and for example, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

Fig. 1 is a schematic diagram of a semiconductor structure in one embodiment, which includes a substrate (not shown in fig. 1), a floating gate 10, a silicon oxide layer 20, an undoped polysilicon layer 30, a dielectric layer 40, and a metal layer 50. The floating gate 10 is disposed on the substrate, the silicon oxide layer 20 covers the floating gate 10, the undoped polysilicon layer 30 is disposed on the silicon oxide layer 20, the dielectric layer 40 is disposed on the undoped polysilicon layer 30, and the metal layer 50 is disposed on the dielectric layer 40. The structure shown in fig. 1 is left-right symmetric, so only one side structure is labeled.

The semiconductor structure is formed by using SiO as SAB₂The dielectric is replaced with a silicon oxide layer + an undoped polysilicon layer. The reason for the poor electron-blocking ability of the conventional SAB is the formation of SiO by deposition₂Poor medium compactness, SiO₂In which polar bonds are easily introduced. Therefore, by arranging the undoped polysilicon layer on the silicon oxide layer, the silicon oxide layer can still ensure good electronic isolation capability through the undoped polysilicon layer under the condition of thin thickness (the thinner silicon oxide layer can ensure that the silicon oxide layer and the undoped polysilicon layer have better filling) by utilizing the relatively compact structure and the better electronic isolation characteristic of the undoped polysilicon layer. That is, the flow of electrons between the floating gate and the metal layer (as indicated by the vertical dashed arrows in fig. 1) is isolated by the undoped polysilicon layer.

In one embodiment, the floating gate 10 is made of polysilicon. In one embodiment, a gate oxide layer is also formed between the floating gate 10 and the substrate.

In one embodiment, the semiconductor structure is further provided with contact holes at the sides of the floating gate 10, the contact holes being filled with metal plugs 60 to electrically connect the metal layer 50 with the substrate at the bottom of the contact holes.

In one embodiment, the silicon oxide layer 20 serves as a metal silicide blocking layer (SAB), and the semiconductor structure is further formed with metal silicide layers on the surface of the substrate in the active region (e.g., metal silicide layers on the surface of the source region and the surface of the drain region), and the metal plugs 60 at corresponding positions are in contact with the metal silicide layers.

In one embodiment, the thickness of the silicon oxide layer 20 is

In one embodiment, by depositionThe thick silicon oxide forms a silicon oxide layer 20. In a conventional technique, SiO is used as SAB to ensure the electron isolation capability of the dielectric₂The medium needs to be deposited

Left and right. The thinner silicon oxide layer 20 enables the undoped polysilicon layer 30 to be formed on a structure with a smaller aspect ratio, thereby ensuring that the undoped polysilicon layer 30 can be well filled, and not easily forming voids (void), thereby avoiding negative effects of the voids on device performance. On the other hand, good filling of the undoped polysilicon layer 30 also improves the lateral escape of injected electrons in the floating gate 10 (as indicated by the lateral dashed arrows in fig. 1).

In one embodiment, a contact hole etch stop layer 22 is also formed between the undoped polysilicon layer 30 and the silicon oxide layer 20. In one embodiment, before the contact hole etching, a metal silicide layer (or substrate), a contact hole etching stop layer 22, an undoped polysilicon layer 30, and a dielectric layer 40 are sequentially stacked at a position where the contact hole needs to be formed from bottom to top. When the contact hole is etched, the patterned mask layer is used as a mask to etch the dielectric layer 40; by proper choice of etchant, the etching stops at the undoped polysilicon layer 30 at the location of the contact hole. The etchant is then replaced and the undoped polysilicon layer 30 continues to be etched at the contact hole location, stopping on the contact hole etch stop layer 22. The etchant is again replaced and the contact etch stop layer 22 is etched through, stopping on the silicide/polysilicon layer (depending on the location of the contact hole). The patterned masking layer is then removed, using methods known to those skilled in the art.

In one embodiment, the thickness of the undoped polysilicon layer 30 is

In one embodiment, by Low Pressure Chemical Vapor Deposition (LPCVD)

The thick undoped polysilicon layer, together with the silicon oxide layer 20, serves as a metal silicide barrier layer, and the deposition temperature is about 500 ℃.

In one embodiment, the substrate is a semiconductor substrate, and the material thereof may be undoped monocrystalline silicon, impurity-doped monocrystalline silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. In the embodiment shown in fig. 1, the substrate is formed from single crystal silicon.

In one embodiment, dielectric layer 40 is an interlayer dielectric (ILD). The interlayer dielectric may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed using a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron.

In one embodiment, the semiconductor structure is an embedded one-time programmable structure.

The application also provides a manufacturing method of the semiconductor structure. FIG. 2 is a flow diagram of a method for fabricating a semiconductor structure in one embodiment, comprising:

s210, forming a floating gate on the substrate.

In one embodiment, the floating gate may be formed by photolithography and etching of polysilicon after the polysilicon is deposited on the substrate.

In one embodiment, the substrate is a semiconductor substrate, and the material thereof may be undoped monocrystalline silicon, impurity-doped monocrystalline silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. In the embodiment shown in fig. 1, the substrate is formed from single crystal silicon.

And S220, forming a silicon oxide layer on the floating gate to be used as a metal silicide blocking layer.

In one embodiment, by deposition

The thick silicon oxide forms a silicon oxide layer. The deposition may be followed by photolithography and etching of the silicon oxide layer to form a metal silicide barrier layer. Self-aligned metal silicide (salicide) is a relatively simple and convenient contact metallization process, but in the fabrication process of a semiconductor device, some regions require salicide process and some regions require non-self-aligned metal silicide (non-salicide) process, and for devices requiring non-salicide process, the characteristics of the salicide are utilized to cover the regions requiring non-salicide with a material that does not react with metal. Such a material for covering a non-salicide device is referred to as a salicide block film (SAB).

S230, an undoped polysilicon layer is formed on the silicon oxide layer.

In one embodiment, by Low Pressure Chemical Vapor Deposition (LPCVD)

Thick undoped polysilicon, as a metal silicide barrier layer with the silicon oxide layer 20, is depositedThe product temperature is about 500 ℃.

And S240, forming a dielectric layer on the undoped polysilicon layer.

In one embodiment, an interlayer dielectric (ILD) is deposited over the undoped polysilicon layer. The interlayer dielectric may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed using a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron.

And S250, forming a metal layer on the dielectric layer.

A metal layer is formed as a metal interconnect.

In one embodiment, the steps between S220 and S230 further include a step of forming a metal silicide layer on the surface of the substrate. In one embodiment, a method of forming a metal silicide layer includes the steps of: first, a metal or other metal substitute, which may include nickel (nickel), cobalt (cobalt), and platinum (platinum) or a combination thereof, is deposited to form a metal layer. The substrate is then heated to cause silicidation of the metal layer and the underlying silicon layer to form a metal silicide, and an etchant is then used that attacks the metal layer but does not attack the metal silicide to remove the unreacted metal layer. In one embodiment, heating the substrate may specifically use a Rapid Thermal Anneal (RTA) process. A metal silicide layer may be formed on the surface of the source region and the surface of the drain region.

In one embodiment, the method further comprises the step of forming a contact hole etching stop layer on the metal silicide layer. In one embodiment, the contact hole etch stop layer is made of silicon oxide and may have a thickness of

Left and right.

In one embodiment, between steps S240 and S250, a step of forming a contact hole is further included. The contact hole may be formed in plural, at least a part of the contact hole being formed at a side of the floating gate.

In one embodiment, the method for forming the contact hole by etching comprises the following steps: first, a patterned mask layer (e.g., a patterned photoresist layer) is formed on the surface of the dielectric layer, the patterned mask layer defining the pattern, location, etc. of each contact hole to be formed.

Then, etching the interlayer medium by taking the patterned mask layer as a mask; the etching is stopped at the undoped polysilicon layer at the position of the contact hole by reasonably selecting the etchant. And then, replacing the etchant, and continuously etching the undoped polysilicon layer at the position of the contact hole, wherein the etching is stopped on the contact hole etching stop layer. The etchant is replaced again and the contact hole etch stop layer is etched through, stopping on the silicide/polysilicon layer (depending on the location of the contact hole). The patterned masking layer is then removed, using methods known to those skilled in the art.

And finally, filling the contact hole with a conductive material, and forming a metal plug in the contact hole. Wherein the conductive material may be any suitable conductive material known to those skilled in the art, including but not limited to metallic materials; wherein, the metal material can comprise one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W and Al.

The semiconductor structure and the manufacturing method thereof are particularly suitable for embedded one-time programmable structures with the Critical Dimension (CD) below 0.11 micrometer.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.