Bonded semiconductor device with processor and static random access memory and method of forming the same
阅读说明:本技术 具有处理器和静态随机存取存储器的键合半导体器件及其形成方法 (Bonded semiconductor device with processor and static random access memory and method of forming the same ) 是由 刘峻 于 2019-09-11 设计创作,主要内容包括:公开了半导体器件的实施例及其制造方法。在示例中,一种半导体器件,包括:第一半导体结构,包括处理器和第一键合层,所述第一键合层包括多个第一键合接触部。所述半导体器件还包括第二半导体结构,所述第二半导体结构包括静态随机存取存储器(SRAM)单元的阵列和第二键合层,所述第二键合层包括多个第二键合接触部。所述半导体器件还包括键合界面,所述键合界面在所述第一键合层和所述第二键合层之间。所述第一键合接触部在所述键合界面处与所述第二键合接触部接触。(Embodiments of a semiconductor device and methods of fabricating the same are disclosed. In an example, a semiconductor device includes: a first semiconductor structure comprising a processor and a first bonding layer comprising a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of Static Random Access Memory (SRAM) cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contact is in contact with the second bonding contact at the bonding interface.)
1. A semiconductor device, comprising:
a first semiconductor structure comprising a processor and a first bonding layer, the first bonding layer comprising a plurality of first bonding contacts;
a second semiconductor structure comprising an array of Static Random Access Memory (SRAM) cells and a second bonding layer comprising a plurality of second bonding contacts; and
a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contact is in contact with the second bonding contact at the bonding interface.
2. The semiconductor device of claim 1, wherein the first semiconductor structure does not include an SRAM cell and the second semiconductor structure does not include a processor.
3. The semiconductor device of claim 1 or 2, wherein the first semiconductor structure comprises:
a substrate;
the processor on the substrate; and
the first bonding layer over the processor.
4. The semiconductor device of claim 3, wherein the second semiconductor structure comprises:
the second bonding layer over the first bonding layer;
an array of the SRAM cells over the second bonding layer; and
a semiconductor layer over and in contact with the array of SRAM cells.
5. The semiconductor device of claim 4, further comprising a pad-out interconnect layer over the semiconductor layer.
6. The semiconductor device of claim 4 or 5, wherein the semiconductor layer comprises single crystal silicon.
7. The semiconductor device of claim 1 or 2, wherein the second semiconductor structure comprises:
a substrate;
an array of the SRAM cells on the substrate; and
the second bonding layer over the array of SRAM cells.
8. The semiconductor device of claim 7, wherein the first semiconductor structure comprises:
the first bonding layer over the second bonding layer;
the processor over the first bonding layer; and
a semiconductor layer over and in contact with the processor.
9. The semiconductor device of claim 8, further comprising a pad-out interconnect layer over the semiconductor layer.
10. The semiconductor device of claim 8 or 9, wherein the semiconductor layer comprises single crystal silicon.
11. The semiconductor device of any one of claims 1-10, wherein the first semiconductor structure further comprises peripheral circuitry of the array of SRAM cells.
12. The semiconductor device of any one of claims 1-11, wherein the first semiconductor structure further comprises an interface circuit.
13. The semiconductor device of any one of claims 1-12, wherein the processor comprises a plurality of cores.
14. The semiconductor device of any one of claims 1-13, wherein the first semiconductor structure comprises a first interconnect layer vertically between the first bonding layer and the processor, and the second semiconductor structure comprises a second interconnect layer vertically between the second bonding layer and the array of SRAM cells.
15. The semiconductor device of claim 14, wherein the processor is electrically connected to the array of SRAM cells through the first and second interconnect layers and the first and second bonding contacts.
16. The semiconductor device of claim 15, wherein a vertical distance between the processor and the array of SRAM cells is less than 1 mm.
17. A method for forming a semiconductor device, comprising:
forming a plurality of first semiconductor structures on a first wafer, wherein at least one of the first semiconductor structures comprises a processor and a first bonding layer comprising a plurality of first bonding contacts;
forming a plurality of second semiconductor structures on a second wafer, wherein at least one of the second semiconductor structures comprises an array of Static Random Access Memory (SRAM) cells and a second bonding layer comprising a plurality of second bonding contacts;
bonding the first and second wafers in a face-to-face manner such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures, wherein the first bonding contact of the first semiconductor structure is in contact with the second bonding contact of the second semiconductor structure at a bonding interface; and
dicing the bonded first and second wafers into a plurality of dies, wherein at least one of the dies includes the bonded first and second semiconductor structures.
18. The method of claim 17, wherein forming the plurality of first semiconductor structures comprises:
forming the processor on the first wafer;
forming a first interconnect layer over the processor; and
forming the first bonding layer over the first interconnect layer.
19. The method of claim 18, wherein forming the processor comprises forming a plurality of transistors on the first wafer.
20. The method of claim 18 or 19, wherein forming the plurality of first semiconductor structures further comprises forming peripheral circuitry of the array of SRAM cells on the first wafer.
21. The method of any of claims 18-20, wherein forming the plurality of first semiconductor structures further comprises forming interface circuitry on the first wafer.
22. The method of any of claims 17-21, wherein forming the plurality of second semiconductor structures comprises:
forming an array of the SRAM cells on the second wafer;
forming a second interconnect layer over the array of SRAM cells; and
forming the second bonding layer over the second interconnect layer.
23. The method of claim 22, wherein forming the array of SRAM cells comprises forming a plurality of transistors on the second wafer.
24. The method of any of claims 17-23, wherein the second semiconductor structure is over the first semiconductor structure after the bonding.
25. The method of claim 24, further comprising, after said bonding and before said cutting:
thinning the second wafer to form a semiconductor layer; and
forming a pad-out interconnect layer over the semiconductor layer.
26. The method of any of claims 17-23, wherein the first semiconductor structure is over the second semiconductor structure after the bonding.
27. The method of claim 26, further comprising, after said bonding and before said cutting:
thinning the first wafer to form a semiconductor layer; and
forming a pad-out interconnect layer over the semiconductor layer.
28. The method of any one of claims 17-27, wherein the bonding comprises hybrid bonding.
29. A method for forming a semiconductor device, comprising:
forming a plurality of first semiconductor structures on a first wafer, wherein at least one of the first semiconductor structures comprises a processor and a first bonding layer comprising a plurality of first bonding contacts;
dicing the first wafer into a plurality of first dies such that at least one of the first dies includes the at least one of the first semiconductor structures;
forming a plurality of second semiconductor structures on a second wafer, wherein at least one of the second semiconductor structures comprises an array of Static Random Access Memory (SRAM) cells and a second bonding layer comprising a plurality of second bonding contacts;
dicing the second wafer into a plurality of second dies such that at least one of the second dies includes the at least one of the second semiconductor structures; and
bonding the first die and the second die in a face-to-face manner such that the first semiconductor structure is bonded to the second semiconductor structure, wherein the first bonding contact of the first semiconductor structure is in contact with the second bonding contact of the second semiconductor structure at a bonding interface.
30. The method of claim 29, wherein forming the plurality of first semiconductor structures comprises:
forming the processor on the first wafer;
forming a first interconnect layer over the processor; and
forming the first bonding layer over the first interconnect layer.
31. The method of claim 30, wherein forming the processor comprises forming a plurality of transistors on the first wafer.
32. The method of claim 30 or 31, wherein forming the plurality of first semiconductor structures further comprises forming peripheral circuitry of the array of SRAM cells on the first wafer.
33. The method of any of claims 30-32, wherein forming the plurality of first semiconductor structures further comprises forming interface circuitry on the first wafer.
34. The method of any of claims 29-32, wherein forming the plurality of second semiconductor structures comprises:
forming an array of the SRAM cells on the second wafer;
forming a second interconnect layer over the array of SRAM cells; and
forming the second bonding layer over the second interconnect layer.
35. The method of claim 34, wherein forming the array of SRAM cells comprises forming a plurality of transistors on the second wafer.
36. The method of any of claims 29-35, wherein the second semiconductor structure is over the first semiconductor structure after the bonding.
37. The method of claim 36, further comprising:
thinning the second wafer after the bonding to form a semiconductor layer; and
forming a pad-out interconnect layer over the semiconductor layer.
38. The method of any of claims 29-35, wherein the first semiconductor structure is over the second semiconductor structure after the bonding.
39. The method of claim 38, further comprising:
thinning the first wafer after the bonding to form a semiconductor layer; and
forming a pad-out interconnect layer over the semiconductor layer.
40. The method of any one of claims 29-39, wherein the bonding comprises hybrid bonding.
Technical Field
Embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the same.
Background
In modern microprocessors, including Central Processing Units (CPUs) and Graphics Processing Units (GPUs), cache size plays an increasingly important role for processor performance enhancement. A cache is a smaller, faster memory, closer to the processor core (e.g., a distance on the order of millimeters to a few centimeters), that stores a copy of data from a common main memory location. Most processors have different independent caches, including instruction and data caches, with the data cache typically organized into more levels of cache levels (e.g., L1, L2, L3, L4, etc.). Caches are typically formed from dense arrays of Static Random Access Memory (SRAM) cells.
Disclosure of Invention
Embodiments of a semiconductor device and methods of fabricating the same are disclosed herein.
In one example, a semiconductor device includes: a first semiconductor structure comprising a processor and a first bonding layer comprising a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of SRAM cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contact is in contact with the second bonding contact at the bonding interface.
In another example, a method for forming a semiconductor device is disclosed. A plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor and a first bonding layer including a plurality of first bonding contacts. A plurality of second semiconductor structures is formed on the second wafer. At least one of the second semiconductor structures includes an array of SRAM cells and a second bonding layer including a plurality of second bonding contacts. Bonding the first wafer and the second wafer in a face-to-face manner such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contact of the first semiconductor structure is in contact with the second bonding contact of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into a plurality of dies. At least one of the dies includes bonded first and second semiconductor structures.
In yet another example, a method for forming a semiconductor device is disclosed. A plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor and a first bonding layer including a plurality of first bonding contacts. Dicing the first wafer into a plurality of first dies such that at least one of the first dies includes the at least one of the first semiconductor structures. A plurality of second semiconductor structures is formed on the second wafer. At least one of the second semiconductor structures includes an array of SRAM cells and a second bonding layer including a plurality of second bonding contacts. Dicing the second wafer into a plurality of second dies such that at least one of the second dies includes the at least one of the second semiconductor structures. Bonding the first die and the second die in a face-to-face manner such that the first semiconductor structure is bonded to the second semiconductor structure. The first bonding contact of the first semiconductor structure is in contact with the second bonding contact of the second semiconductor structure at a bonding interface.
Drawings
The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.
Fig. 1A illustrates a schematic view of a cross-section of an exemplary semiconductor device, in accordance with some embodiments.
Fig. 1B illustrates a schematic view of a cross-section of another exemplary semiconductor device, in accordance with some embodiments.
Fig. 2A illustrates a schematic plan view of an exemplary semiconductor structure having a processor, peripheral circuitry, and interface circuitry, in accordance with some embodiments.
Fig. 2B illustrates a schematic plan view of an exemplary semiconductor structure having an SRAM, in accordance with some embodiments.
Fig. 3A illustrates a schematic plan view of an exemplary semiconductor structure having a processor and interface circuitry, in accordance with some embodiments.
Fig. 3B illustrates a schematic plan view of an exemplary semiconductor structure having an SRAM and peripheral circuitry, in accordance with some embodiments.
Fig. 4 illustrates a cross-section of an exemplary semiconductor device, in accordance with some embodiments.
Fig. 5 illustrates a cross-section of another exemplary semiconductor device, in accordance with some embodiments.
Fig. 6A and 6B illustrate a fabrication process for forming an exemplary semiconductor structure with a processor and other logic circuitry, in accordance with some embodiments.
Fig. 7A and 7B illustrate a fabrication process for forming an exemplary semiconductor structure with an SRAM, in accordance with some embodiments.
Fig. 8A and 8B illustrate a fabrication process for forming an exemplary semiconductor device, according to some embodiments.
Figures 9A-9C illustrate a fabrication process for bonding and dicing (dicing) an exemplary semiconductor structure, according to some embodiments.
Fig. 10A-10C illustrate a fabrication process for cutting and bonding an exemplary semiconductor structure, according to some embodiments.
Fig. 11 is a flow chart of an exemplary method for forming a semiconductor device according to some embodiments.
Fig. 12 is a flow chart of another exemplary method for forming a semiconductor device according to some embodiments.
Embodiments of the present disclosure will be described with reference to the accompanying drawings.
Detailed Description
Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without parting from the spirit and scope of the disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.
It should be noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, and/or characteristic in connection with other embodiments whether or not explicitly described.
In general, terms may be understood, at least in part, according to usage in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may still be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but may instead, depending at least in part on the context, allow for the presence of other factors not necessarily explicitly described.
It will be readily understood that the meanings of "on … …", "above … …", and "above … …" in this disclosure should be interpreted in the broadest manner such that "on … …" means not only "directly on … … (something), but also includes the meaning of" on … … (something) with intervening features or layers therebetween, and "above … …" or "above … …" means not only "above … … (something)" or "above … … (something)" but may also include the meaning of "above … … (something) or" above … … (something) without intervening features or layers therebetween (i.e., directly on something).
Furthermore, spatially relative terms, such as "below … …," "below … …," "lower," "above … …," "upper," and the like, may be used for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, the term "substrate" refers to a material to which a subsequent layer of material is to be added. The substrate itself may be patterned. The material added atop the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be composed of a non-conductive material such as glass, plastic, or sapphire wafers.
As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a smaller extent than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of the continuous structure having a thickness less than the thickness of the homogeneous or heterogeneous continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (where interconnect lines, and/or via contacts are formed) and one or more dielectric layers.
As used herein, the term "about" indicates a value of a given amount that may vary based on the particular technology node associated with the subject semiconductor device. The term "about" can indicate that a given amount of a value can vary, for example, within 10-30% of the value (e.g., ± 10%, ± 20%, or ± 30% of the value), based on the particular technology node.
As used herein, a "wafer" is a block of semiconductor material in and/or on which semiconductor devices are built and may undergo various fabrication processes before being separated into dies.
As modern processors (also referred to as "microprocessors") evolve to higher generations, cache size plays an increasingly important role for processor performance enhancement. In some cases, the cache typically formed by sensing high speed SRAM cells may occupy half or even more of the chip space in a microprocessor chip. Furthermore, the resistance-capacitance (RC) delay from the cache to the processor core may become significant for reduced performance. Therefore, both interconnect RC delay and SRAM yield dominate microprocessor performance and yield. However, as the chip size of microprocessors becomes larger and larger, on the order of a few centimeters, the RC delay from the SRAM cache to the processor core can become significant for reduced performance.
Various embodiments according to the present disclosure provide a semiconductor device with a processor and SRAM cache integrated on a bonded chip to achieve better cache performance (faster data transfer with higher efficiency), wider data bandwidth, and faster memory interface speeds. The semiconductor devices disclosed herein may include a first semiconductor structure having a processor (e.g., having multiple processor cores) and a second semiconductor structure having an SRAM (e.g., as a cache) that is bonded to the first semiconductor structure with a large number of short-range vertical metal interconnects, rather than peripherally distributed long-range metal wires, or even conventional through-silicon vias (TSVs). Since the SRAM is located directly above or below the processor core, the interconnection distance between the processor core and the SRAM is shortened, for example, from the centimeter level to the micrometer level, thereby significantly reducing the RC delay and chip/board size and increasing the data transmission speed. Furthermore, shorter fabrication cycle times with higher yields can be achieved due to less interaction from the fabrication process of the processor wafer and the SRAM wafer and known good hybrid bonding yields.
Fig. 1A illustrates a schematic view of a cross-section of an
The processor may be a special purpose processor including, but not limited to, a CPU, a GPU, a Digital Signal Processor (DSP), a Tensor Processing Unit (TPU), a Visual Processing Unit (VPU), a Neural Processing Unit (NPU), a Synergistic Processing Unit (SPU), a Physical Processing Unit (PPU), and an Image Signal Processor (ISP). The processor may also be a system on a chip (SoC) that combines multiple dedicated processors, such as an application processor, a baseband processor, and so forth. In some embodiments where
The processor may include: one or more processing units (also referred to as "processor cores" or "cores"), each of which reads and executes instructions; and one or more caches formed of high-speed memory such as SRAM. In some embodiments, the processors in the
In addition to processors, other processing units (also referred to as "logic circuits") may also be formed in the
In some embodiments, the
The
As shown in fig. 1A, the
It should be understood that the relative positions of the stacked first and
In some embodiments, the
Fig. 2A illustrates a schematic plan view of an
Fig. 2B illustrates a schematic plan view of an exemplary semiconductor structure 201 having an
It should be understood that the layout of the
It should also be understood that some or all of the peripheral circuitry of SRAM 212 (e.g.,
Fig. 4 illustrates a cross-section of an exemplary semiconductor device 400 according to some embodiments. As one example of the
The first semiconductor structure 402 of the semiconductor device 400 may include a device layer 410 over a substrate 408. Notably, the x-axis and y-axis are added in fig. 4 to further illustrate the spatial relationship of components in the semiconductor device 400. The substrate 408 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (lateral direction or width direction). As used herein, whether a component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of a semiconductor device (e.g., semiconductor device 400) is determined in the y-direction relative to a substrate (e.g., substrate 408) of the semiconductor device when the substrate is located in the lowest plane of the semiconductor device in the y-direction (vertical direction or thickness direction). The same concepts are applied throughout this disclosure to describe spatial relationships.
In some embodiments, the device layer 410 includes a processor 412 on the substrate 408 and other logic 414 on the substrate 408 and external to the processor 412. In some embodiments, the other logic circuitry 414 includes interface circuitry for sending and receiving signals to and from the semiconductor device 400, as described in detail above. In some embodiments, the other logic circuitry 414 includes some or all of the peripheral circuitry for controlling and sensing the SRAM of the semiconductor device 400, as described in detail above. In some embodiments, processor 412 includes a plurality of transistors 418 forming any suitable special purpose processor core and/or SoC core, as described in detail above. In some embodiments, the transistors 418 also form other logic circuitry 414, such as any suitable I/O circuitry or bus circuitry for sending and receiving signals to and from the semiconductor device 400, and/or any suitable digital, analog, and/or mixed-signal control and sensing circuitry for facilitating operation of the SRAM, including but not limited to input/output buffers, decoders (e.g., row and column decoders), and sense amplifiers.
The transistor 418 may be formed "on" the substrate 408, with all or a portion of the transistor 418 formed in the substrate 408 (e.g., below a top surface of the substrate 408) and/or directly on the substrate 408. Isolation regions (e.g., Shallow Trench Isolations (STIs)) and doped regions (e.g., source and drain regions of the transistor 418) may also be formed in the substrate 408. According to some embodiments, the transistor 418 is high speed, with advanced logic processes (e.g., technology nodes of 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, etc.).
In some embodiments, the first semiconductor structure 402 of the semiconductor device 400 also includes an interconnect layer 420 above the device layer 410 to transmit electrical signals to and from the processor 412 (and other logic 414, if present). The interconnect layer 420 may include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and vertical interconnect access (via) contacts. As used herein, the term "interconnect" may broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer 420 may further include one or more inter-layer dielectric (ILD) layers (also referred to as "inter-metal dielectric (IMD) layers") in which interconnect lines and via contacts may be formed. That is, the interconnect layer 420 may include interconnect lines and via contacts in multiple ILD layers. The interconnect lines and via contacts in the interconnect layer 420 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layer in interconnect layer 420 may comprise a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof. In some embodiments, devices in device layer 410 are electrically connected to each other through interconnects in interconnect layer 420. For example, other logic 414 may be electrically connected to the processor 412 through the interconnect layer 420.
As shown in fig. 4, the first semiconductor structure 402 of the semiconductor device 400 may further include a bonding layer 422 at the bonding interface 406 and above the interconnect layer 420 and the device layer 410 (including the processor 412). Bonding layer 422 may include a plurality of bonding contacts 424 and a dielectric that electrically isolates bonding contacts 424. Bonding contact 424 may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining regions of bonding layer 422 may be formed with a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contact 424 and surrounding dielectric in the bonding layer 422 may be used for hybrid bonding.
Similarly, as shown in fig. 4, the second semiconductor structure 404 of the semiconductor device 400 may further include a bonding layer 426 at the bonding interface 406 and over the bonding layer 422 of the first semiconductor structure 402. The bonding layer 426 may include a plurality of bonding contacts 428 and a dielectric that electrically isolates the bonding contacts 428. The bonding contacts 428 may comprise a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining regions of bonding layer 426 may be formed with a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 428 and surrounding dielectric in the bonding layer 426 may be used for hybrid bonding. According to some embodiments, the bonding contact 428 contacts the bonding contact 424 at the bonding interface 406.
As described above, the second semiconductor structure 404 may be bonded on top of the first semiconductor structure 402 at the bonding interface 406 in a face-to-face manner. In some embodiments, bonding interface 406 is disposed between bonding layers 422 and 426 as a result of a hybrid bond (also referred to as a "hybrid metal/dielectric bond"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can achieve both a metal-metal bond and a dielectric-dielectric bond. In some embodiments, bonding interface 406 is where bonding layers 422 and 426 meet and bond. In practice, bonding interface 406 may be a layer having a thickness that includes a top surface of bonding layer 422 of first semiconductor structure 402 and a bottom surface of bonding layer 426 of second semiconductor structure 404.
In some embodiments, the second semiconductor structure 404 of the semiconductor device 400 further includes an interconnect layer 430 over the bonding layer 426 to transmit electrical signals. The interconnect layer 430 may include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in interconnect layer 430 also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 430 may also include one or more ILD layers in which interconnect lines and via contacts may be formed. The interconnect lines and via contacts in interconnect layer 430 may comprise a conductive material including, but not limited to, W, Co, Cu, Al, suicide, or any combination thereof. The ILD layer in interconnect layer 430 may comprise a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof.
The second semiconductor structure 404 of the semiconductor device 400 may also include an array of SRAM cells 432 above the interconnect layer 430 and the bonding layer 426. An array of SRAM cells 432 may be used, for example, as a cache and/or data buffer for semiconductor device 400. For example, an array of SRAM cells 432 may be used as an internal instruction cache and/or data cache for processor 412. In some embodiments, each SRAM cell 432 includes a plurality of transistors 434. In some embodiments, the SRAM cell 432 is a 6T cell, which is made up of four transistors 434 for storing one bit of data and two transistors 434 for controlling access to the data. It should be appreciated that the SRAM cell 432 may be any suitable configuration, such as more or less than six transistors (e.g., more or less transistors per bit). In some embodiments, transistor 434 is formed "on" semiconductor layer 440, wherein all or a portion of transistor 434 is formed in semiconductor layer 440 and/or directly on semiconductor layer 440. Isolation regions (e.g., Shallow Trench Isolations (STIs)) and doped regions (e.g., source and drain regions of transistor 434) may also be formed in semiconductor layer 440. In some embodiments, two access transistors 434 (e.g., transistors 434 that control access to data) are controlled by a word line, and four storage transistors 434 (e.g., transistors 434 that store a bit of data) are coupled to a bit line and controlled by the two access transistors 434.
In some embodiments, the second semiconductor structure 404 further includes a semiconductor layer 440 disposed over and in contact with the array of SRAM cells 432. Semiconductor layer 440 may be a thinned substrate with transistor 434 formed thereon. In some embodiments, semiconductor layer 440 comprises monocrystalline silicon. In some embodiments, semiconductor layer 440 may comprise polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable material. Semiconductor layer 440 may also include isolation regions and doped regions (e.g., as the source and drain of transistor 434).
As shown in fig. 4, the second semiconductor structure 404 of the semiconductor device 400 may further include a pad-out interconnect layer 444 over the semiconductor layer 440. The pad-out interconnect layer 444 may include interconnects, e.g., contact pads 446, in one or more ILD layers. Pad-out interconnect layer 444 and interconnect layer 430 may be formed on opposite sides of semiconductor layer 440. In some embodiments, the interconnects in the pad-out interconnect layer 444 may transmit electrical signals between the semiconductor device 400 and external circuitry, for example, for pad-out purposes. In some embodiments, second semiconductor structure 404 further includes one or more contacts 448 extending through semiconductor layer 440 to electrically connect pad-out interconnect layer 444 and interconnect layers 430 and 420. As a result, the processor 412 and the array of SRAM cells 432 (and other logic 414, if present) may be electrically connected to external circuitry through contacts 448 and pad-out interconnect layer 444.
In addition, the processor 412 (and other logic 414, if any) may be electrically connected to an array of SRAM cells 432 through interconnect layers 430 and 420 and bond contacts 428 and 424. By vertically integrating the array of processors 412 and SRAM cells 432, the interconnect distance can be significantly reduced compared to laterally arranging the array of processors 412 and SRAM cells 432 in the same plane of a microprocessor chip (which has a chip size in the order of centimeters). According to some embodiments, the vertical distance between the processor 412 and the array of SRAM cells 432 is less than 1 mm. In one example, the vertical distance between the processor 412 and the array of SRAM cells 432 is between 1 μm and 1mm (e.g., 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 150mm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, 750 μm, 800 μm, 850 μm, 900 μm, 950 μm, 1mm, any range bounded by any of these values at the bottom end, or any range defined by any two of these values).
Fig. 5 illustrates a cross-section of another
The second semiconductor structure 504 of the
In some embodiments, the second semiconductor structure 504 of the
As shown in fig. 5, the
The
In some embodiments,
In some embodiments, the
As shown in fig. 5, the
In addition, processor 540 (and
Fig. 6A and 6B illustrate a fabrication process for forming an exemplary semiconductor structure with a processor and other logic circuitry, in accordance with some embodiments. Fig. 7A and 7B illustrate a fabrication process for forming an exemplary semiconductor structure with an SRAM, in accordance with some embodiments. Fig. 8A and 8B illustrate a fabrication process for forming an exemplary semiconductor device, according to some embodiments. Fig. 9A-9C illustrate a fabrication process for bonding and dicing an exemplary semiconductor structure, according to some embodiments. Fig. 10A-10C illustrate a fabrication process for cutting and bonding an exemplary semiconductor structure, according to some embodiments. Fig. 11 is a flow diagram of an
As depicted in fig. 6A and 6B, a first semiconductor structure is formed, the first semiconductor structure comprising: a processor; other logic circuits; and a first bonding layer comprising a plurality of first bonding contacts. As depicted in fig. 7A and 7B, a second semiconductor structure is formed, the second semiconductor structure comprising: an array of SRAM cells; and a second bonding layer comprising a plurality of second bonding contacts. As depicted in fig. 8A and 8B, the first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner such that the first bonding contact is in contact with the second bonding contact at a bonding interface.
Referring to fig. 11, a
As shown in fig. 9A, a plurality of
As shown in fig. 6A, a plurality of
The
The
The
As shown in fig. 9A, a plurality of
As shown in fig. 7A, a plurality of
The
The
The
As shown in fig. 9B, the
As shown in fig. 8A, the
The
As shown in fig. 8B, the substrate on top of the bonded chip (e.g.,
The
The
In lieu of the packaging scheme based on wafer level bonding before dicing as described above with respect to fig. 9A-9C and 11, fig. 10A-10C and 12 illustrate another packaging scheme based on die level bonding after dicing, in accordance with some embodiments.
The
The
The
The
As shown in fig. 8B, the substrate on top of the bonded chip (e.g.,
The
According to one aspect of the present disclosure, a semiconductor device includes: a first semiconductor structure comprising a processor and a first bonding layer comprising a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of SRAM cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contact is in contact with the second bonding contact at the bonding interface.
In some embodiments, the first semiconductor structure does not include an SRAM cell and the second semiconductor structure does not include a processor.
In some embodiments, the first semiconductor structure comprises: a substrate; the processor on the substrate; and the first bonding layer over the array of processors and the SRAM cells.
In some embodiments, the second semiconductor structure comprises: the second bonding layer over the first bonding layer; an array of the SRAM cells over the second bonding layer; and a semiconductor layer over and in contact with the array of SRAM cells.
In some embodiments, the semiconductor device further comprises a pad-out interconnect layer over the semiconductor layer. In some embodiments, the semiconductor layer comprises single crystal silicon.
In some embodiments, the second semiconductor structure comprises: a substrate; an array of the SRAM cells on the substrate; and the second bonding layer over the array of SRAM cells.
In some embodiments, the first semiconductor structure comprises: the first bonding layer over the second bonding layer; the processor over the first bonding layer; and a semiconductor layer over and in contact with the processor.
In some embodiments, the semiconductor device further comprises a pad-out interconnect layer over the semiconductor layer. In some embodiments, the semiconductor layer comprises single crystal silicon.
In some embodiments, the first semiconductor structure also includes peripheral circuitry of the array of SRAM cells. In some embodiments, the first semiconductor structure further comprises an interface circuit. In some embodiments, the processor includes a plurality of cores.
In some embodiments, the first semiconductor structure includes a first interconnect layer vertically between the first bonding layer and the processor, and the second semiconductor structure includes a second interconnect layer vertically between the second bonding layer and the array of SRAM cells.
In some embodiments, the processor is electrically connected to the array of SRAM cells through the first and second interconnect layers and the first and second bonding contacts.
In some embodiments, a vertical distance between the processor and the array of SRAM cells is less than 1 mm.
In accordance with another aspect of the present disclosure, a method for forming a semiconductor device is disclosed. A plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor and a first bonding layer including a plurality of first bonding contacts. A plurality of second semiconductor structures is formed on the second wafer. At least one of the second semiconductor structures includes an array of SRAM cells and a second bonding layer including a plurality of second bonding contacts. Bonding the first wafer and the second wafer in a face-to-face manner such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contact of the first semiconductor structure is in contact with the second bonding contact of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into a plurality of dies. At least one of the dies includes bonded first and second semiconductor structures.
In some embodiments, to form the plurality of first semiconductor structures, the processor is formed on the first wafer, a first interconnect layer is formed over the processor, and the first bonding layer is formed over the first interconnect layer. In some embodiments, to form the processor, a plurality of transistors are formed on the first wafer.
In some embodiments, to form the plurality of first semiconductor structures, peripheral circuitry of the array of SRAM cells is formed on the first wafer. In some embodiments, to form the plurality of first semiconductor structures, interface circuitry is formed on the first wafer.
In some embodiments, to form the plurality of second semiconductor structures, the array of SRAM cells is formed on the second wafer, a second interconnect layer is formed over the array of SRAM cells, and the second bonding layer is formed over the second interconnect layer.
In some embodiments, to form the array of SRAM cells, a plurality of transistors are formed on the second wafer.
In some embodiments, the second semiconductor structure is over the first semiconductor structure after the bonding. In some embodiments, after the bonding and before the dicing, the second wafer is thinned to form a semiconductor layer, and a pad-out interconnect layer is formed over the semiconductor layer.
In some embodiments, the first semiconductor structure is over the second semiconductor structure after the bonding. In some embodiments, thinning the first wafer after the bonding and before the dicing to form a semiconductor layer, and forming a pad-out interconnect layer over the semiconductor layer.
In some embodiments, the bonding comprises hybrid bonding.
According to yet another aspect of the present disclosure, a method for forming a semiconductor device is disclosed. A plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor and a first bonding layer including a plurality of first bonding contacts. Dicing the first wafer into a plurality of first dies such that at least one of the first dies includes the at least one of the first semiconductor structures. A plurality of second semiconductor structures is formed on the second wafer. At least one of the second semiconductor structures includes an array of SRAM cells and a second bonding layer including a plurality of second bonding contacts. Dicing the second wafer into a plurality of second dies such that at least one of the second dies includes the at least one of the second semiconductor structures. Bonding the first die and the second die in a face-to-face manner such that the first semiconductor structure is bonded to the second semiconductor structure. The first bonding contact of the first semiconductor structure is in contact with the second bonding contact of the second semiconductor structure at a bonding interface.
In some embodiments, to form the plurality of first semiconductor structures, the processor is formed on the first wafer, a first interconnect layer is formed over the processor, and the first bonding layer is formed over the first interconnect layer. In some embodiments, to form the processor, a plurality of transistors are formed on the first wafer.
In some embodiments, to form the plurality of first semiconductor structures, peripheral circuitry of the array of SRAM cells is formed on the first wafer. In some embodiments, to form the plurality of first semiconductor structures, interface circuitry is formed on the first wafer.
In some embodiments, to form the plurality of second semiconductor structures, the array of SRAM cells is formed on the second wafer, a second interconnect layer is formed over the array of SRAM cells, and the second bonding layer is formed over the second interconnect layer.
In some embodiments, to form the array of SRAM cells, a plurality of transistors are formed on the second wafer.
In some embodiments, the second semiconductor structure is over the first semiconductor structure after the bonding. In some embodiments, the second wafer is thinned after the bonding to form a semiconductor layer, and a pad-out interconnect layer is formed over the semiconductor layer.
In some embodiments, the first semiconductor structure is over the second semiconductor structure after the bonding. In some embodiments, thinning the first wafer to form a semiconductor layer after the bonding, and forming a pad-out interconnect layer over the semiconductor layer.
In some embodiments, the bonding comprises hybrid bonding.
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