阅读说明：本技术 存储器装置和控制存储器装置的方法
(Memory device and method of controlling the same
) 是由 藤原英弘
陈炎辉 于 2019-07-31 设计创作，主要内容包括：本申请实施例涉及存储器装置和控制存储器装置的方法。一种存储器装置包含：存储器单元阵列,其具有多个存储器单元,其中所述多个存储器单元中的每一个包含第一端口；第一控制电路,其安置于所述存储器单元阵列的第一侧上且经布置以电连接到所述多个第一端口；以及第二控制电路,其安置于所述存储器单元阵列的第二侧上且经布置以电连接到所述多个第一端口；其中所述存储器单元阵列的所述第二侧与所述第一侧相对。(Embodiments of the present application relate to a memory device and a method of controlling the memory device. A memory device comprising: a memory cell array having a plurality of memory cells, wherein each of the plurality of memory cells includes a first port; first control circuitry disposed on a first side of the array of memory cells and arranged to be electrically connected to the plurality of first ports; and second control circuitry disposed on a second side of the array of memory cells and arranged to be electrically connected to the plurality of first ports; wherein the second side of the memory cell array is opposite the first side.)
1. A memory device, comprising:
a memory cell array having a plurality of memory cells, wherein each of the plurality of memory cells includes a first port;
first control circuitry disposed on a first side of the array of memory cells and arranged to be electrically connected to the plurality of first ports; and
second control circuitry disposed on a second side of the array of memory cells and arranged to be electrically connected to the plurality of first ports;
wherein the second side of the memory cell array is opposite the first side.
Technical Field
Embodiments of the present application relate to a memory device and a method of controlling the memory device.
Background
Semiconductor memories are electronic data storage devices implemented on semiconductor-based integrated circuits. Semiconductor memories are fabricated in many different types and technologies. Semiconductor memories have much faster access times than other types of data storage technologies. For example, bytes of data can typically be written to or read from semiconductor memory in nanoseconds, while the access time of a rotating storage device (such as a hard disk) is in the millisecond range. For these and other reasons, semiconductor memory is used as the primary storage mechanism for computer memory to hold data that the computer is currently operating on, among other uses.
Static Random Access Memory (SRAM) is commonly used in integrated circuits. Embedded SRAMs are particularly popular in high speed communications, image processing, and system on a chip (SOC) applications. SRAM cells have the advantageous feature of retaining data without requiring refresh. Typically, an SRAM cell includes two pass gate transistors through which a bit can be read from or written to the SRAM cell. This type of SRAM cell is referred to as a single-port SRAM cell. Another type of SRAM cell is referred to as a dual port SRAM cell, which includes four pass gate transistors.
Disclosure of Invention
Embodiments of the present application relate to a memory device, comprising: a memory cell array having a plurality of memory cells, wherein each of the plurality of memory cells includes a first port; first control circuitry disposed on a first side of the array of memory cells and arranged to be electrically connected to the plurality of first ports; and second control circuitry disposed on a second side of the array of memory cells and arranged to be electrically connected to the plurality of first ports; wherein the second side of the memory cell array is opposite the first side.
Embodiments of the present application relate to a memory device, comprising: a memory cell array having a plurality of memory cells, wherein each of the plurality of memory cells includes a first port and a second port; first control circuitry disposed on a first side of the array of memory cells and arranged to be electrically connected to the plurality of first ports; and second control circuitry disposed on the first side of the array of memory cells and arranged to be electrically connected to the plurality of second ports; wherein the plurality of first ports is different from the plurality of second ports.
Embodiments of the present application relate to a method of controlling a memory device, comprising: precharging a first node of a first bit line to a first voltage level during a read operation, wherein the first bit line extends from a first side of an array of memory cells in the memory device to a second side of the array of memory cells, the second side of the array of memory cells being opposite the first side, and the first bit line is electrically connected to a plurality of memory cells in the array of memory cells; precharging a first node of a second bit line to a second voltage level during the read operation, wherein the second bit line extends from the first side of the memory cell array to the second side of the memory cell array, and the second bit line is electrically connected to the plurality of memory cells in the memory cell array; precharging a second node of the first bit line to the first voltage level during the read operation; and precharging a second node of the second bit line to the second voltage level during the read operation.
Drawings
Aspects of embodiments of the present invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 is a diagram illustrating a memory device according to some embodiments.
FIG. 2 is a schematic diagram illustrating a memory cell according to some embodiments.
FIG. 3 is a schematic diagram illustrating a portion of the memory device of FIG. 1, according to some embodiments.
FIG. 4 is a schematic diagram illustrating a portion of the memory device of FIG. 1, according to some embodiments.
FIG. 5 is a schematic diagram illustrating a portion of the memory device of FIG. 1, according to some embodiments.
FIG. 6 is a timing diagram illustrating signal waveforms of a memory device during a read operation, according to some embodiments.
FIG. 7 is a timing diagram illustrating signal waveforms of a memory device during a write operation, according to some embodiments.
FIG. 8 is a flow chart illustrating a method of reading a memory device, according to some embodiments.
FIG. 9 is a flow chart illustrating a method of writing to a memory device, according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Embodiments of the invention are discussed in detail below. It should be appreciated that many of the applicable inventive concepts provided by the embodiments of the present invention can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of embodiments of the invention.
Furthermore, spatially relative terms, such as "below," "above," "upper," "lower," "left," "right," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Also, as used herein, the term "about" generally refers to within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" means within an acceptable standard error of the mean when considered by a person of ordinary skill. Except in the operating/working examples, or unless otherwise expressly specified, all numerical ranges, amounts, values and percentages (e.g., those for amounts of materials, durations, temperatures, operating conditions, ratios of amounts, and the like disclosed herein) are to be understood as modified in all instances by the term "about. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the examples of the invention and the attached claims are approximations that may vary as desired. Each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from one end point to another end point or between two end points. Unless otherwise specified, all ranges disclosed herein are inclusive of the endpoints.
The following disclosure describes aspects of Static Random Access Memory (SRAM). In particular, embodiments of the present invention describe different embodiments relating to SRAM write operations. For ease of illustration, certain SRAM circuit elements and control logic are disclosed to facilitate description of the different embodiments. One of ordinary skill in the art will appreciate that the SRAM also contains other circuit elements and control logic. These other circuit elements and control logic are within the spirit and scope of embodiments of the present invention.
In addition, the dual port SRAM cell includes a first port and a second port. The first port may be configured as a read port, and the read port includes a read data line configured to carry data read from the memory cell. The second port may be configured as a write port, and the write port includes a write data line configured to carry data to be written to the memory cell. In some configurations, the write data line is precharged and/or maintained at a predetermined voltage level when the write data line is not being used to write to the memory cell. The write data line is also coupled to the memory cell in response to the activated write word line when the write word line is activated to access another memory cell of the same row.
FIG. 1 is a diagram illustrating a memory device 100 according to some embodiments. The memory device 100 may be an SRAM device. Memory device 100 includes an array of memory cells 102, a first control circuit 104, a second control circuit 106, a third control circuit 108, and a fourth control circuit 110. According to some embodiments, the top view shape of the memory cell array 102 may be rectangular or square. However, this is not a limitation of the embodiments of the present invention. The top view shape of the memory cell array 102 can be any regular or irregular shape. For example, the shape may be a regular hexagon or an irregular hexagon. Memory cell array 102 includes a plurality of memory cells 102_11-102_ mn arranged in a two-dimensional array. According to some embodiments, the parameter "m" (or "n") is an integer ranging from 8 to 512. However, this is not a limitation of the embodiments of the present invention. The integer "m" (or "n") may be greater than 512, such as 1024.
FIG. 2 is a schematic diagram illustrating a memory cell 200 according to some embodiments. The memory cell 200 may be a memory cell in the memory cell array 102. The memory cell 200 may be a dual port SRAM cell. For example, an SRAM cell may be configured as an "8T" circuit topology, where "T" is an abbreviation for "transistor". As one of ordinary skill in the art will appreciate, SRAM cells can have different circuit topologies. According to some embodiments, the memory cell 200 includes eight transistors M1-M8, where transistors M1 and M3 are p-channel field effect transistors and transistors M2, M4, and M5-M8 are n-channel field effect transistors. The transistors M1-M4 are configured as latches, cross latches, or flip-flop structures. The transistor M5 is configured as a switch between node N1 on the first bit line 202 and node N2 of the latch. The transistor M6 is configured as a switch between a node N3 on the second bit line 204 and the second node N4 of the latch. The gates of transistors M5 and M6 are electrically connected to the first word line 206. According to some embodiments, second bit line 204 is the complement of first bit line 202. Transistor M7 is configured as a switch between node N5 on third bit line 208 and node N2 of the latch. The transistor M8 is configured as a switch between node N6 on the fourth bit line 210 and node N4 of the latch. The gates of transistors M7 and M8 are electrically connected to the second word line 212. According to some embodiments, the fourth bit line 210 is the complement of the third bit line 208.
In addition, nodes N1 and N3 are configured as a first port of memory cell 200, and nodes N5 and N7 are configured as a second port of memory cell 200. However, this is not a limitation of the embodiments of the present invention. The first port and the second port may be configured as a read port or a write port of the memory cell 200.
According to some embodiments, the first bit line 202, the second bit line 204, the third bit line 206, and the fourth bit line 208 are four relatively long conductive lines extending from the bottom side to the top side of the memory cell array 102 so as to connect corresponding nodes of all memory cells in the same column of the memory cell array 102. Accordingly, first bit line 202, second bit line 204, third bit line 206, and fourth bit line 208 may have a relatively large number of parasitic elements, such as parasitic resistors, capacitors, and/or inductors, that may affect the cycle time and/or write time of memory cell 200. For simplicity, in fig. 2, the first, second, third and fourth resistors R1, R2, R3 and R4 on the first, second, third and fourth bit lines 202, 204, 206 and 208 are used to represent parasitic resistors of the first, second, third and fourth bit lines 202, 204, 206 and 208, respectively.
Referring again to fig. 1, the first control circuitry 104 and the fourth control circuitry 110 are disposed on a first side of the memory cell array 102, and the second control circuitry 106 and the third control circuitry 108 are disposed on a second side of the memory cell array 102 opposite the first side. Second control circuitry 106 is disposed between the memory cell array 102 and third control circuitry 108, and fourth control circuitry 110 is disposed between the memory cell array 102 and the first control circuitry 104. According to some embodiments, first control circuitry 104 and fourth control circuitry 110 are disposed on a bottom side of memory cell array 102, and second control circuitry 106 and third control circuitry 108 are disposed on a top side of memory cell array 102. However, this is not a limitation of the embodiments of the present invention. The first control circuitry 104 and the fourth control circuitry 110 may be disposed on the right side of the memory cell array 102, and the second control circuitry 106 and the third control circuitry 108 may be disposed on the left side of the memory cell array 102.
According to some embodiments, the first control circuitry 104 and the second control circuitry 106 are arranged to control the first ports of the memory cells 102_11-102_1n of the first column via a first bit line 112, a second bit line 114, and at least one conductive line 116. The first control circuitry 104 is arranged to control the second control circuitry 106 via at least one conductive line 116. The third control circuitry 108 and the fourth control circuitry 110 are arranged to control the second ports of the memory cells 102_11-102_1n of the first column via a third bit line 118, a fourth bit line 120 and at least one conductive line 122. The third control circuitry 108 is arranged to control the fourth control circuitry 110 via at least one conductive line 122.
Similarly, the first control circuit 104 and the second control circuit 106 are also arranged to control the first ports of the other columns of memory cells 102_11-102_1n via two bit lines and one conductive line, and the third control circuit 108 and the fourth control circuit 110 are also arranged to control the second ports of the other columns of memory cells 102_11-102_1n via two bit lines and one conductive line. For example, the first control circuitry 104 and the second control circuitry 106 are arranged to control a first port of the last column of memory cells 102_ m1-102_ mn via a first bit line 124, a second bit line 126, and at least one conductive line 128. The third control circuitry 108 and the fourth control circuitry 110 are arranged to control the second ports of the memory cells 102_11-102_1n of the last column via a third bit line 130, a fourth bit line 132 and at least one conductive line 134.
FIG. 3 is a schematic diagram illustrating a portion 300 of the memory device 100, according to some embodiments. Portion 300 of memory device 100 includes memory cell array 302, a portion of first control circuitry 104 (i.e., control circuitry 304), a portion of second control circuitry 106 (i.e., control circuitry 306), a portion of third control circuitry 108 (i.e., control circuitry 308), and a portion of fourth control circuitry 110 (i.e., control circuitry 310). For purposes of description, memory cell array 302 includes only memory cell 302_11, which is located in the upper left corner of memory cell array 302. The configuration of memory cell 302_11 is similar to memory cell 200, and therefore a detailed description is omitted here for the sake of brevity. Memory cell 302_11 includes first ports (i.e., Na and Nb) connected to first bit line 312 and second bit line 314, respectively, and second ports (i.e., Nc and Nd) connected to third bit line 318 and fourth bit line 320, respectively. The first bit line 312 and the second bit line 314 are arranged to extend from the control circuitry 304 to the control circuitry 306, and the third bit line 318 and the fourth bit line 320 are arranged to extend from the control circuitry 308 to the control circuitry 310.
Control circuitry 304 includes first precharge and equalization circuitry 3042, write drivers 3044, first control logic 3046, latch circuitry 3048, second control logic 3050, second precharge and equalization circuitry 3052, and a sense amplifier 3054, in accordance with some embodiments.
The first precharge and equalization circuit 3042 includes three p-channel transistors Ma, Mb, and Mc, where the p-channel transistors Ma and Mb are configured as prechargers and the p-channel transistor Mc is configured as an equalizer. The first precharge and equalization circuit 3042 is controlled by a precharge control signal YA. When the p-channel transistors Ma, Mb, and Mc are on, the p-channel transistors Ma and Mb are arranged to charge voltages on nodes Ne and Nf on the first and second bit lines 312 and 314, respectively, to the supply voltage level Vdd, and the p-channel transistor Mc is arranged to equalize voltages on the nodes Ne and Nf.
The write driver 3044 includes two n-channel transistors Md and Me. The write driver 3044 is controlled by first control logic 3046. The first control logic 3046 includes two NOR gates 3046a and 3046 b. Each of the nor gates 3046a and 3046b has three input terminals. The first terminals of the nor gates 3046a and 3046b are arranged to receive first write data WT and second write data WC, where the first write data WT may be complementary to the second write data WC. Second terminals of the nor gates 3046a and 3046b are coupled to the precharge control signal YA. The third terminals of the nor gates 3046a and 3046b are coupled to the write enable signal WE.
The latch circuit 3048 includes two p-channel transistors Mi and Mj. The p-channel transistors Mi and Mj are arranged to latch the voltage on one of the first bit line 312 and the second bit line 314 to the supply voltage level Vdd.
The second control logic 3050 includes a NAND (NAND) gate 3050a and two p-channel transistors Mk and Ml. The p-channel transistors Mk and Ml are controlled by the output of the nand gate 3050 a. The p-channel transistors Mk and Ml are configured as two switches connected between the first and second bit lines 312 and 314 and the second precharge and equalization circuit 3052. The nand gate 3050a has two input terminals, with a first input terminal coupled to the precharge control signal YA and a second input terminal coupled to the sense amplifier activation signal SAE.
The second precharge and equalization circuit 3052 includes three p-channel transistors Mf, Mg, and Mh, where the p-channel transistors Mf and Mg are configured as prechargers and the p-channel transistor Mh is configured as an equalizer. The second precharge and equalization circuit 3052 is controlled by the read enable signal REB. The operation of the second precharge and equalization circuit 3052 is similar to the first precharge and equalization circuit 3042, and thus a detailed description is omitted here for the sake of brevity.
Sense amplifier 3054 is a differential amplifier having two input terminals coupled to first bit line 312 and second bit line 314, respectively. The sense amplifier 3054 is controlled by the sense amplifier activation signal SAE for outputting a differential output signal according to the differential input signal.
According to some embodiments, control circuit 306 includes three p-channel transistors Mm, Mn, and Mo, where p-channel transistors Mm and Mn are configured as a pre-charger and p-channel transistor Mo is configured as an equalizer. The control circuit 306 is controlled by the precharge control signal YA. When the p-channel transistors Mm, Mn and Mo are turned on, the p-channel transistors Mm and Mn are arranged to charge the voltages on the nodes Ng and Nh on the first and second bit lines 312 and 314, respectively, to the supply voltage level Vdd, and the p-channel transistor Mo is arranged to equalize the voltages on the nodes Ng and Nh.
According to some embodiments, control circuitry 306 is a replica of first precharge and equalization circuitry 3042, with control circuitry 306 disposed on a top side of memory cell array 302 and first precharge and equalization circuitry 3042 disposed on a bottom side of memory cell array 302. Thus, the conductive lines 316 are arranged to extend from the bottom side to the top side of the memory cell array 402 for transmitting the precharge control signal YA to the control circuitry 306.
During a read operation of memory cell 302_11, first precharge and equalization circuit 3042 precharges and equalizes the voltages on nodes Ne and Nf on first bit line 312 and second bit line 314 to the supply voltage level Vdd. Ideally, the voltages on nodes Na and Nb on the first bit line 312 and the second bit line 314 should momentarily reach the supply voltage level Vdd. However, due to parasitic elements of the first and second bit lines 312 and 314, the voltages on the nodes Na and Nb on the first and second bit lines 312 and 314 cannot instantaneously reach the supply voltage level Vdd. To accelerate the precharge and equalize operation, another precharge and equalize circuit (i.e., control circuit 306) is disposed on the opposite side of the first precharge and equalize circuit 3042 to precharge the voltages on nodes Ng and Nh to the supply voltage level Vdd during a read operation of memory cell 302_ 11. During a read operation of memory cell 302_11, first precharge and equalization circuit 3042 precharges the voltages on nodes Ne and Nf to supply voltage level Vdd on the bottom side of memory cell array 302 while control circuit 306 precharges the voltages on nodes Ng and Nh to supply voltage level Vdd on the top side of memory cell array 302. Accordingly, the voltages on the nodes Na and Nb connected to the first port of the memory cell 302_11 may reach the supply voltage level Vdd in a relatively short time. Thus, the cycle time of the memory cell 302_11 can be reduced.
According to some embodiments, control circuitry 308, control circuitry 310, and conductive lines 322 may be similar to control circuitry 304, control circuitry 306, and conductive lines 316, respectively, and therefore a detailed description is omitted herein for the sake of brevity.
FIG. 4 is a schematic diagram illustrating a portion 400 of the memory device 100, according to some embodiments. Portion 400 of memory device 100 includes memory cell array 402, a portion of first control circuitry 104 (i.e., control circuitry 404), a portion of second control circuitry 106 (i.e., control circuitry 406), a portion of third control circuitry 108 (i.e., control circuitry 408), and a portion of fourth control circuitry 110 (i.e., control circuitry 410). For purposes of description, memory cell array 402 includes only memory cell 402_11, which is located in the upper left corner of memory cell array 402. The configuration of memory cell 402_11 is similar to memory cell 200, and therefore a detailed description is omitted here for the sake of brevity. Memory cell 402_11 includes first ports (i.e., Na 'and Nb') connected to first bit line 412 and second bit line 414, respectively, and second ports (i.e., Nc 'and Nd') connected to third bit line 418 and fourth bit line 420, respectively. The first bit line 412 and the second bit line 414 are arranged to extend from the control circuit 404 to the control circuit 406, and the third bit line 418 and the fourth bit line 420 are arranged to extend from the control circuit 408 to the control circuit 410.
According to some embodiments, the control circuitry 404 includes at least a write driver 4044 and control logic 4046. The write driver 4044 includes two n-channel transistors Md 'and Me'. The write driver 4044 is controlled by control logic 4046. The control logic 4046 includes two nor gates 4046a and 4046 b. Each of the nor gates 4046a and 4046b has three input terminals. The first terminals of the nor gates 4046a and 4046b are arranged to receive first write data WT and second write data WC, where the first write data WT may be complementary to the second write data WC. The second terminals of the nor gates 4046a and 4046b are coupled to the precharge control signal YA. The third terminals of the nor gates 4046a and 4046b are coupled to the write enable signal WE. It should be noted that the control circuit 404 is similar to the control circuit 304, and thus a detailed description of other circuits in the control circuit 404 is omitted here for the sake of brevity.
The control circuit 406 includes two n-channel transistors Mp 'and Mq', where the n-channel transistors Mp 'and Mq' are configured as a write driver. The write driver is controlled by control logic 4046. Thus, the write driver is controlled by the precharge control signal YA, the write enable signal WE, the first write data WT, and the second write data WC.
According to some embodiments, control circuitry 406 is a copy of write drivers 4044, with control circuitry 406 disposed on a top side of memory cell array 402 and write drivers 4044 disposed on a bottom side of memory cell array 402. Thus, a first conductive line 416a is arranged to extend from the bottom side to the top side of the memory cell array 402 for connecting the gate terminal of the n-channel transistor Mp 'to the gate terminal of the n-channel transistor Md', and a second conductive line 416b is arranged to extend from the bottom side to the top side of the memory cell array 402 for connecting the gate terminal of the n-channel transistor Mq 'to the gate terminal of the n-channel transistor Me'.
During a write operation of memory cell 402_11, write driver 4044 is arranged to write data into memory cell 402_11 by outputting a first voltage level (e.g., a high voltage level) and a second voltage level (e.g., a low voltage level) to nodes Ne 'and Nf' of first bit line 412 and second bit line 414, respectively. However, due to parasitic elements of the first and second bit lines 412, 414, the voltages on the nodes Na 'and Nb' on the first and second bit lines 412, 414 cannot instantaneously reach the high and low voltage levels, respectively. To speed up the write operation, another write driver (i.e., control circuitry 406) is disposed on the opposite side of write driver 4044 to drive the voltages on nodes Ng 'and Nh' to the first and second voltage levels, respectively, during the write operation of memory cell 402_ 11. During a write operation of memory cell 402_11, write driver 4044 drives the voltages on nodes Ne 'and Nf' to the first and second voltage levels, respectively, on the bottom side of memory cell array 402, while control circuitry 406 drives the voltages on nodes Ng 'and Nh' to the first and second voltage levels, respectively, on the top side of memory cell array 402. Accordingly, the voltages on the nodes Na 'and Nb' connected to the write port of the memory cell 402_11 may reach the first voltage level and the second voltage level, respectively, in a relatively short time. Therefore, the write time of the memory cell 402_11 can be reduced.
According to some embodiments, the control circuitry 408, the control circuitry 410, and the conductive lines 422a and 422b may be similar to the control circuitry 404, the control circuitry 406, and the conductive lines 416a and 416b, respectively, and thus a detailed description is omitted herein for brevity.
FIG. 5 is a schematic diagram illustrating a portion 500 of the memory device 100, according to some embodiments. Portion 500 of memory device 100 includes memory cell array 502, a portion of first control circuitry 104 (i.e., control circuitry 504), a portion of second control circuitry 106 (i.e., control circuitry 506), a portion of third control circuitry 108 (i.e., control circuitry 508), and a portion of fourth control circuitry 110 (i.e., control circuitry 510). For purposes of description, memory cell array 502 includes only memory cell 502_11, which is located in the upper left corner of memory cell array 502. The configuration of the memory cell 502_11 is similar to the memory cell 200, and thus a detailed description is omitted here for the sake of brevity. Memory cell 502_11 includes first ports (i.e., Na "and Nb") connected to first bit line 512 and second bit line 514, respectively, and second ports (i.e., Nc "and Nd") connected to third bit line 520 and fourth bit line 522, respectively. First bit line 512 and second bit line 514 are arranged to extend from control circuit 504 to control circuit 506, and third bit line 520 and fourth bit line 522 are arranged to extend from control circuit 508 to control circuit 510.
According to some embodiments, the control circuitry 504 includes at least precharge and equalization circuitry 5042, write drivers 5044, and control logic 5046.
The precharge and equalization circuit 5042 includes three p-channel transistors Ma ", Mb", and Mc ", where the p-channel transistors Ma" and Mb "are configured as prechargers and the p-channel transistor Mc" is configured as an equalizer. The precharge and equalization circuit 5042 is controlled by the precharge control signal YA. When the p-channel transistors Ma ", Mb", and Mc "are on, the p-channel transistors Ma" and Mb "are arranged to charge the voltages on the nodes Ne 1" and Nf1 "on the first and second bit lines 512 and 514, respectively, to the supply voltage level Vdd, and the p-channel transistor Mc" is arranged to equalize the voltages on the nodes Ne1 "and Nf 1".
The write driver 5044 includes two n-channel transistors Md "and Me". The write driver 5044 is controlled by control logic 5046. The control logic 5046 includes two NOR gates 5046a and 5046 b. Each of the nor gates 5046a and 5046b has three input terminals. The first terminals of the nor gates 5046a and 5046b are arranged to receive first write data WT and second write data WC, wherein the first write data WT may be complementary to the second write data WC. Second terminals of the nor gates 5046a and 5046b are coupled to the precharge control signal YA. The third terminals of the NOR gates 5046a and 5046b are coupled to the write enable signal WE. It should be noted that control circuit 504 is similar to control circuit 304, and thus a detailed description of other circuits in control circuit 504 is omitted herein for the sake of brevity.
According to some embodiments, the control circuit 506 includes a precharge and equalization circuit 5062 and a write driver 5064.
The precharge and equalization circuit 5062 includes three p-channel transistors Mm ", Mn", and Mo ", where the p-channel transistors Mm" and Mn "are configured as prechargers and the p-channel transistor Mo" is configured as an equalizer. The precharge and equalization circuit 5062 is a replica of the precharge and equalization circuit 5042, with the precharge and equalization circuit 5062 disposed on a top side of the memory cell array 502 and the precharge and equalization circuit 5042 disposed on a bottom side of the memory cell array 502. Thus, the conductive lines 516 are arranged to extend from the bottom side to the top side of the memory cell array 502 for transmitting the precharge control signal YA to the precharge and equalization circuit 5062.
During a read operation of memory cell 502_11, precharge and equalize circuit 5042 precharges the voltages on nodes Ne1 "and Nf 1" to supply voltage level Vdd on the bottom side of memory cell array 502, while precharge and equalize circuit 5062 precharges the voltages on nodes Ng1 "and Nh 1" to supply voltage level Vdd on the top side of memory cell array 502. Accordingly, the voltages on the nodes Na "and Nb" connected to the first port of the memory cell 502_11 may reach the supply voltage level Vdd in a relatively short time. Thus, the cycle time of the memory cell 502_11 can be reduced. The operation of the precharge and equalization circuit 5062 is similar to that of the control circuit 306, and therefore a detailed description is omitted herein for the sake of brevity.
In addition, the write driver 5064 includes two n-channel transistors Mp "and Mq". The write driver is controlled by control logic 5046. Thus, the write driver 5064 is controlled by the precharge control signal YA, the write enable signal WE, the first write data WT, and the second write data WC.
According to some embodiments, write driver 5064 is a replica of write driver 5044, where write driver 5064 is disposed on a top side of memory cell array 502 and write driver 5044 is disposed on a bottom side of memory cell array 502. Thus, a first conductive line 518a is arranged to extend from the bottom side to the top side of the memory cell array 502 for connecting the gate terminal of the n-channel transistor Mp "to the gate terminal of the n-channel transistor Md", and a second conductive line 518b is arranged to extend from the bottom side to the top side of the memory cell array 502 for connecting the gate terminal of the n-channel transistor Mq "to the gate terminal of the n-channel transistor Me".
During a write operation of memory cell 502_11, write driver 5044 drives voltages on nodes Ne2 "and Nf 2" to the first and second voltage levels, respectively, on a bottom side of memory cell array 502, while write driver 5064 drives voltages on nodes Ng2 "and Nh 2" to the first and second voltage levels, respectively, on a top side of memory cell array 502. Accordingly, the voltages on nodes Na "and Nb" connected to the second port of memory cell 502_11 may reach the first voltage level and the second voltage level, respectively, in a relatively short time. Therefore, the write time of the memory cell 502_11 can be reduced. The operation of the write driver 5064 is similar to the control circuit 406, and thus a detailed description is omitted herein for the sake of brevity.
According to some embodiments, control circuitry 508, control circuitry 510, and conductive lines 524, 526a, and 526b may be similar to control circuitry 504, control circuitry 506, and conductive lines 516, 518a, and 518b, respectively, and therefore a detailed description is omitted herein for the sake of brevity.
FIG. 6 is a timing diagram illustrating signal waveforms of a memory device during a read operation, according to some embodiments. The waveforms may be a precharge control signal YA, a read enable signal REB, a sense amplifier activation signal SAE, a bit line signal BL, and an output signal OUT of the memory device 300 or 500 during a read operation. When the memory device enters a read operation for reading data of the memory cells, the voltage levels of the precharge control signal YA and the read enable signal REB are changed from, for example, a low voltage level and a high voltage level to, for example, a high voltage level and a low voltage level, respectively, at time t 1. When the voltage levels of the precharge control signal YA and the read enable signal REB are a high voltage level and a low voltage level, respectively, the control circuit 306 and the first precharge and equalization circuit 3042 precharge the voltage level at the bit line (i.e., the nodes Na and Nb, Ng and Nh, Ne and Nf) to, for example, a high voltage level, i.e., the voltage level of the bit line signal BL at time t 1. After time t1, depending on the data stored in the memory cell, the voltage level of one bit line (e.g., nodes Na, Ng, and Ne) gradually decreases to reach a low voltage level, and the voltage levels of the other bit lines (e.g., nodes Nb, Nh, and Nf) remain unchanged. At time t2, the voltage level of the sense amplifier activation signal SAE changes from, for example, a low voltage level to a high voltage level to sense the voltage level on the bit line. At time t2, the voltage level of one output terminal of the sense amplifier 3054 (i.e., the output signal OUT) changes from the current voltage level to a low voltage level, and the voltage level of the other output terminal of the sense amplifier 3054 (i.e., the output signal OUT) remains unchanged. It should be noted that during the time interval between times t1 and t2, sense amplifier 3054 may be a voltage follower that follows the voltage level on the bitline. During the time interval between times t2 and t3, the sense amplifier 3054 may output the output signal OUT to the follower circuit. At time t3, the voltage levels of the precharge control signal YA and the read enable signal REB are changed from the high voltage level and the low voltage level to the low voltage level and the high voltage level, respectively, to stop the read operation. In addition, at time t4, the voltage level of the sense amplifier activation signal SAE is changed from the high voltage level to the low voltage level to disable the sense amplifier 3054.
FIG. 7 is a timing diagram illustrating signal waveforms of a memory device during a write operation, according to some embodiments. The waveforms may be a precharge control signal YA, a write enable signal WE, a bit line signal BL, and memory cell data Da for the memory cells of memory device 400 or 500 during a read operation. When the memory device enters a write operation for writing data to the memory cells, the voltage levels of the precharge control signal YA and the write enable signal WE change from, for example, a low voltage level to, for example, a high voltage level at time t 1'. When the voltage levels of the precharge control signal YA and the write enable signal WE are high voltage levels, the control circuit 406 and the write driver 4044 drive the voltage levels at the bit lines (i.e., nodes Ng 'and Nh', Ne 'and Nf') to, for example, high and low voltage levels, respectively, depending on the data to be stored into the memory. For example, during the interval between times t1 'and t2', the voltage levels of nodes Ng 'and Ne' gradually reach a low voltage level, and the voltage levels of nodes Nh 'and Nf' remain unchanged. At time t2', the voltage levels of nodes Ng ' and Ne ' reach a low voltage level. At time t3', memory cell data Da is stored into the memory cell, i.e., the logic state of the memory cell changes at time t 3'. At time t4', the voltage levels of the precharge control signal YA and the write enable signal WE are changed from the high voltage level to the low voltage level to stop the read operation. In addition, at time t4', the voltage level at the bit line changes to a high voltage level.
FIG. 8 is a flow chart illustrating a method 800 of reading a memory device, according to some embodiments. The method 800 may be applied in a read operation of the memory device 300 or 500. Accordingly, the operations of method 800 are described based on fig. 3. Method 800 includes operations 802 and 810. In operation 802, a first node (e.g., Ne) of a first bit line (e.g., 312) and a first node (e.g., Nf) of a second bit line (e.g., 314) are precharged to a first voltage level and a second voltage level, respectively. The first node of the first bit line and the first node of the second bit line are disposed on a first side of the memory cell array. In operation 804, a second node (e.g., Ng) of the first bit line and a second node (e.g., Nh) of the second bit line are precharged to the first voltage level and the second voltage level, respectively. The second node of the first bit line and the second node of the second bit line are disposed on a second side of the array of memory cells opposite the first side. In operation 806, a first voltage level on a first node of the first bit line and a second voltage level on a first node of the second bit line are equalized. In operation 808, a first voltage level on the second node of the first bit line and a second voltage level on the second node of the second bit line are equalized. In operation 810, data stored in a memory cell having a port connected to a first bit line and a second bit line is output.
FIG. 9 is a flow chart illustrating a method 900 of writing to a memory device, according to some embodiments. The method 900 may be applied in a write operation of the memory device 400 or 500. Accordingly, the operations of method 900 are described based on fig. 4. The method 900 includes operations 902-906. In operation 902, a first node (e.g., Ne ') of a first bit line (e.g., 412) and a first node (e.g., Nf') of a second bit line (e.g., 414) are charged to a first voltage level and a second voltage level, respectively. The first node of the first bit line and the first node of the second bit line are disposed on a first side of the memory cell array. In operation 904, a second node (e.g., Ng ') of the first bit line and a second node (e.g., Nh') of the second bit line are charged to a first voltage level and a second voltage level, respectively. The second node of the first bit line and the second node of the second bit line are disposed on a second side of the array of memory cells opposite the first side. In operation 906, data is written into a memory cell having a port connected to a first bit line and a second bit line.
Briefly, in embodiments of the present invention, the write time and cycle time of a memory cell can be reduced when the bit lines of the memory cell are simultaneously controlled by a control circuit disposed on one side of the memory cell array and a feedback control circuit disposed on the opposite side of the memory cell array.
According to some embodiments, a memory device is provided. The memory device includes a memory cell array, a first control circuit, and a second control circuit. The memory cell array has a plurality of memory cells, wherein each of the plurality of memory cells includes a first port. The first control circuitry is disposed on a first side of the memory cell array and arranged to be electrically connected to the plurality of first ports. Second control circuitry is disposed on a second side of the array of memory cells and arranged to be electrically connected to the plurality of first ports. The second side of the memory cell array is opposite the first side.
According to some embodiments, a memory device is provided. The memory device includes a memory cell array, a first control circuit, and a second control circuit. The memory cell array has a plurality of memory cells, wherein each of the plurality of memory cells includes a first port and a second port. The first control circuitry is disposed on a first side of the memory cell array and arranged to be electrically connected to the plurality of first ports. The second control circuitry is disposed on a first side of the memory cell array and arranged to be electrically connected to the plurality of second ports. The plurality of first ports is different from the plurality of second ports.
According to some embodiments, a method of controlling a memory device is provided. The method comprises the following steps: precharging a first node of a first bit line to a first voltage level during a read operation, wherein the first bit line extends from a first side of an array of memory cells in the memory device to a second side of the array of memory cells, the second side of the array of memory cells being opposite the first side, and the first bit line is electrically connected to a plurality of memory cells in the array of memory cells; precharging a first node of a second bit line to a second voltage level during a read operation, wherein the second bit line extends from a first side of the memory cell array to a second side of the memory cell array, and the second bit line is electrically connected to the plurality of memory cells in the memory cell array; precharging a second node of the first bit line to a first voltage level during a read operation; and precharging a second node of the second bit line to a second voltage level during a read operation.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or obtaining the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the embodiments of the present disclosure.
