阅读说明：本技术 基于gpio管脚实现mido从机功能的方法及终端 (Method and terminal for realizing MIDO slave function based on GPIO pin ) 是由 杨超 吴闽华 孟庆晓 梁栋 戴瑜 于 2019-09-19 设计创作，主要内容包括：本发明公开了基于GPIO管脚实现MIDO从机功能的方法及终端,所述方法包括：设置GPIO1为时钟信号,并设置GPIO2为数据信号；主机MCU发送所述时钟信号给从机CPU,所述数据信号在所述主机MCU和所述从机CPU之间进行双线传递；当所述主机MCU读取所述从机CPU的数据时,所述数据信号由所述从机CPU控制,当所述主机MCU写所述从机CPU的数据时,所述数据信号由所述主机MCU控制。本发明通过GPIO管脚,实现了MIDO从机功能,可以被MDIO主机访问。(The invention discloses a method and a terminal for realizing an MIDO slave machine function based on a GPIO pin, wherein the method comprises the following steps: setting GPIO1 as a clock signal and GPIO2 as a data signal; the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in a two-wire way between the host MCU and the slave CPU; when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU. The invention realizes the function of the MIDO slave machine through the GPIO pin and can be accessed by the MDIO host machine.)

1. A method for realizing an MIDO slave function based on a GPIO pin is characterized by comprising the following steps:

setting GPIO1 as a clock signal and GPIO2 as a data signal;

the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in a two-wire way between the host MCU and the slave CPU;

when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU.

2. The method for implementing MIDO slave functions based on GPIO pins as claimed in claim 1, wherein the method for implementing MIDO slave functions based on GPIO pins further comprises:

when the host MCU pulls the clock signal to high level, the slave CPU sends out interruption through the GPIO1, the slave CPU enters an interruption processing program, and the level of the MDIO pin of the GPIO2 is read and stored in the interruption processing program.

3. The method for realizing MIDO slave functions based on GPIO pins as claimed in claim 1, wherein the setting GPIO1 as clock signal and GPIO2 as data signal further comprises:

setting GPIO1 as an input function, setting GPIO2 as an input-output function, and setting GPIO1 as an edge interrupt attribute;

mounting a GPIO1 interrupt processing function;

the number of the receiving bits is 0, and the number of the sending bits is 0;

the GPIO1 interrupt is enabled, setting the MDIO device address to 0x 08.

4. The method for realizing MIDO slave functions based on GPIO pins as claimed in claim 3, wherein the interrupt processing function is used for processing read and write requests sent by the host MCU;

when the host MCU writes the slave CPU, the level of the clock signal is read in the interrupt processing function, one bit is read in each interrupt, and 5 bits are read as a device address and a 5-bit register internal address according to a protocol PHY address.

5. The method for realizing MIDO slave function based on GPIO pin as claimed in claim 3, wherein two states are predefined, idle state and busy state respectively;

the idle state indicates that no request is currently available, the bus is empty, and 32 synchronous frames are waited;

the busy status indicates that the current status has entered the MIDO timing.

6. The method for implementing MIDO slave functions based on GPIO pins as claimed in claim 5, wherein the method for implementing MIDO slave functions based on GPIO pins further comprises:

when entering the entrance of the interrupt processing function, judging whether the current state is an idle state;

when the receiver is in an idle state, reading the level of the GPIO2 to a receiving buffer, receiving the bit number, and judging whether the bit number is 46;

if yes, judging whether a 32-bit synchronous frame, 2 starting bits, 2 operation codes and 2 bit reading and writing bits exist, if no, enabling the whole state machine to enter an idle state, if yes, enabling the whole state machine to enter a busy state, receiving the bit length to be 0, and sending the bit length to be 0.

7. The method for implementing the MIDO slave function based on the GPIO pin as claimed in claim 6, wherein the determining whether the current state is an idle state further comprises:

when the mobile terminal is not in an idle state, entering a read operation or a write operation;

the read operation is: writing the register value of the address A into the GPIO2 according to bits, adding 1 to the sending bit length, entering the final state into an idle state, and receiving the bit length of 0;

the write operation is: reading the high-low level value of the GPIO2 to a receiving buffer, adding 1 to the number of receiving bits, writing the 16-bit data of the receiving buffer into the register address A, entering the final state into an idle state, and receiving the bit length of 0.

8. A system for realizing MIDO slave function based on GPIO pin is characterized in that the system comprises: a host MCU and a slave CPU;

the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in a two-wire way between the host MCU and the slave CPU; when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU.

9. A terminal, characterized in that the terminal comprises: memory, a processor and a program stored on the memory and operable on the processor for implementing a MIDO slave function based on GPIO pins, the program for implementing a MIDO slave function based on GPIO pins implementing the steps of the method for implementing a MIDO slave function based on GPIO pins as claimed in any one of claims 1-7 when executed by the processor.

10. A storage medium, characterized in that the storage medium stores a program for implementing a mio slave function based on a GPIO pin, and the program for implementing a mio slave function based on a GPIO pin implements the steps of the method for implementing a mio slave function based on a GPIO pin as claimed in any one of claims 1 to 7 when being executed by a processor.

Technical Field

The invention relates to the technical field of computer application, in particular to a method, a terminal and a storage medium for realizing an MIDO slave machine function based on a GPIO pin.

Background

The MDIO (Management Data Input/Output) interface is a very simple serial interface with only two wires, and is generally used for connecting physical layer chips of network ports. The MDIO is also divided into a master device and a slave device, the master device initiates an MDIO time sequence, and the slave device receives the MDIO time sequence and makes a certain response. Most CPUs with network ports support the MDIO host function, GPIO (general purpose input/output ports are short, namely STM32 controllable pins, the GPIO pins of the STM32 chip are connected with external equipment, so that the functions of external communication, control and data acquisition are realized) is used for simulating the MIDO time sequence, and the MDIO protocol is realized by software. The driving of the MDIO host mode by the GPIO is very simple, mature and very much used.

If the function of the MDIO slave is to be realized on the current general CPU and accessed by the MDIO host, hardware support is generally required, or a CPLD (Complex Programmable Logic Device) is used to realize a protocol, and it is difficult to realize the function of the mio slave by software.

Accordingly, the prior art is yet to be improved and developed.

Disclosure of Invention

The invention mainly aims to provide a method, a terminal and a storage medium for realizing an MIDO slave machine function based on a GPIO pin, and aims to solve the problem that the MIDO slave machine function cannot be realized through software in the prior art.

In order to achieve the above object, the present invention provides a method for implementing an MIDO slave function based on a GPIO pin, wherein the method for implementing the MIDO slave function based on the GPIO pin comprises the following steps:

setting GPIO1 as a clock signal and GPIO2 as a data signal;

the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in a two-wire way between the host MCU and the slave CPU;

when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU.

Optionally, the method for implementing a mid slave function based on a GPIO pin further includes:

when the host MCU pulls the clock signal to high level, the slave CPU sends out interruption through the GPIO1, the slave CPU enters an interruption processing program, and the level of the MDIO pin of the GPIO2 is read and stored in the interruption processing program.

Optionally, the method for implementing a MIDO slave function based on a GPIO pin, where setting GPIO1 as a clock signal and GPIO2 as a data signal, further includes:

setting GPIO1 as an input function, setting GPIO2 as an input-output function, and setting GPIO1 as an edge interrupt attribute;

mounting a GPIO1 interrupt processing function;

the number of the receiving bits is 0, and the number of the sending bits is 0;

the GPIO1 interrupt is enabled, setting the MDIO device address to 0x 08.

Optionally, the method for implementing the function of the MIDO slave computer based on the GPIO pin, wherein the interrupt processing function is used for processing a read-write request sent by the host MCU;

when the host MCU writes the slave CPU, the level of the clock signal is read in the interrupt processing function, one bit is read in each interrupt, and 5 bits are read as a device address and a 5-bit register internal address according to a protocol PHY address.

Optionally, the method for implementing the function of the mio slave based on the GPIO pin, wherein two states are predefined, that is, an idle state and a busy state, respectively;

the idle state indicates that no request is currently available, the bus is empty, and 32 synchronous frames are waited;

the busy status indicates that the current status has entered the MIDO timing.

Optionally, the method for implementing a mid slave function based on a GPIO pin further includes:

when entering the entrance of the interrupt processing function, judging whether the current state is an idle state;

when the receiver is in an idle state, reading the level of the GPIO2 to a receiving buffer, receiving the bit number, and judging whether the bit number is 46;

if yes, judging whether a 32-bit synchronous frame, 2 starting bits, 2 operation codes and 2 bit reading and writing bits exist, if no, enabling the whole state machine to enter an idle state, if yes, enabling the whole state machine to enter a busy state, receiving the bit length to be 0, and sending the bit length to be 0.

Optionally, the method for implementing a function of the mio slave based on the GPIO pin, wherein the determining whether the current state is an idle state further includes:

when the mobile terminal is not in an idle state, entering a read operation or a write operation;

the read operation is: writing the register value of the address A into the GPIO2 according to bits, adding 1 to the sending bit length, entering the final state into an idle state, and receiving the bit length of 0;

the write operation is: reading the high-low level value of the GPIO2 to a receiving buffer, adding 1 to the number of receiving bits, writing the 16-bit data of the receiving buffer into the register address A, entering the final state into an idle state, and receiving the bit length of 0.

In addition, in order to achieve the above object, the present invention further provides a system for implementing a function of a mio slave based on a GPIO pin, wherein the system includes: a host MCU and a slave CPU;

the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in a two-wire way between the host MCU and the slave CPU; when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU.

In addition, to achieve the above object, the present invention further provides a terminal, wherein the terminal includes: the method comprises the steps of realizing the MIDO slave function based on the GPIO pin, wherein the method comprises the following steps of storing a program for realizing the MIDO slave function based on the GPIO pin, storing the program on the memory, and running on the processor.

In addition, in order to achieve the above object, the present invention further provides a storage medium, wherein the storage medium stores a program for implementing a mio slave function based on a GPIO pin, and the program for implementing a mio slave function based on a GPIO pin implements the steps of the method for implementing a mio slave function based on a GPIO pin as described above when being executed by a processor.

The invention sets GPIO1 as clock signal and GPIO2 as data signal; the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in a two-wire way between the host MCU and the slave CPU; when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU. The invention realizes the function of the MIDO slave machine through the GPIO pin and can be accessed by the MDIO host machine.

Drawings

FIG. 1 is a flow chart of the preferred embodiment of the method for realizing the MIDO slave function based on the GPIO pin of the invention;

FIG. 2 is a functional schematic diagram of a preferred embodiment of the system for implementing the MIDO slave function based on the GPIO pin according to the present invention;

FIG. 3 is a schematic flow chart of an initialization stage in the method for implementing the MIDO slave function based on the GPIO pin according to the present invention;

FIG. 4 is a schematic diagram of the state judgment and execution process in the method for implementing the function of the MIDO slave based on the GPIO pin according to the present invention;

FIG. 5 is a diagram illustrating an operating environment of a terminal according to a preferred embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

As shown in fig. 1 and 2, the method for implementing an midao slave function based on a GPIO pin according to a preferred embodiment of the present invention includes the following steps:

step S10, setting GPIO1 as a clock signal (MDC signal) and GPIO2 as a data signal (MDIO signal);

step S20, the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in two lines between the host MCU and the slave CPU;

and step S30, when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU.

Further, the GPIO1 pin of the selected MDC can support sending an interrupt to the slave CPU, and the interrupt type can be set as an edge starting; once the host MCU pulls up the MDC to be effective, the GPIO1 of the slave CPU sends an interrupt to the CPU, the slave CPU enters an interrupt processing program, and then the level of the GPIO2 MDIO pin is read in the interrupt processing program, wherein the high level represents data 1, and the low level represents data 0; and storing each read bit into a variable, and performing corresponding processing according to the time sequence requirement of the MDIO protocol.

As shown in the following table (data frame structure of MDIO interface), the format of MDIO protocol is as follows:

wherein, the specific meanings of each domain are as follows:

PRE: frame sync code, in which state the MAC will drive the MDIO to send 32 consecutive "1" s to the PHY device for synchronous communication of the device, but this field is not necessary, and for efficiency, some MDIO operations of the PHY device do not have this field,

ST: the start of frame flag, MAC outputs a "01" bit to inform the PHY that a framing operation is starting.

OP: the frame operation code, bit "01" indicates that the frame is a write operation request, and bit "10" indicates that the frame is a read operation request.

PHY AD: the PHY device address is 5 bits wide, each PHY device compares its own address with the 5 bits, if matching, the subsequent operation is responded, if not, the subsequent operation is ignored, and the 5 bits determine that one MDIO interface can only support the configuration of 32 PHY chips at most.

REG AD: PHY register address, 5 bit wide; the PHY is a physical layer interface, each PHY interface comprises 32 16-bit registers, the first 16 registers (corresponding to addresses 5'b00000 to 5' b11111) are registers that the 802.3 protocol must have, and the last 16 registers are registers that can be designated by the manufacturer. Typically the contents of the first 16 registers of different PHY chips should be consistent.

TA: state transition field, 2 bits in total. If the bit is read, the 1 st bit is sent out high impedance state by the MDIO module, and the 2 nd bit is set to be 0 by the PHY chip to the MDIO signal. If the operation is write operation, the MDIO signal is controlled by the MDIO module to continuously output two bits of '10'.

DATA: register data field of frame, total 16 bits. If the operation is a read operation, the serial data is sent to the MDIO module by the PHY, and if the operation is a write operation, the serial data is sent to the PHY by the MDIO module.

IDLE: idle state after the end of the frame. The MDIO is now driven passively, in a high-impedance state, but is typically pulled high by a pull-up resistor.

Furthermore, the whole process of the method for realizing the function of the MIDO slave machine based on the GPIO pin is divided into three parts, namely an initialization stage, a read operation and a write operation. The initialization process is shown in fig. 3, and specifically includes:

s1: setting GPIO1 as an input function;

s2: setting GPIO2 as an input/output function;

s3: setting GPIO1 as an edge interrupt attribute;

s4: mounting a GPIO1 interrupt processing function GPIO1_ irs ();

s5: the number of the receiving bits is 0, and the number of the sending bits is 0;

s6: enable GPIO1 interrupts;

s7: the MDIO device address is set to 0x 08.

The core part is an interrupt processing function gpio1_ irs (), which is used for processing read-write requests sent by the host MCU, if the host MCU is about to write to the slave CPU, the level of MDC is read in the gpio1_ irs (), one bit (bit, which is the minimum unit of information and is the information contained in one bit of binary number or the required information amount of 1 specially specified in 2 options) is read in each interrupt, and 5 bits are read as the device address according to the protocol PHY address, followed by the internal address of the 5-bit register.

Further, as shown in fig. 4, two states, namely an idle state and a busy state, are predefined; the idle state indicates that no request is currently available, the bus is empty, and 32 synchronous frames are waited; the busy status indicates that the current status has entered the MIDO timing.

Specifically, when entering an entry of the interrupt processing function GPIO1_ irs (), it is determined whether a current state is an idle state (N indicates no, and yes in the other case), when in the idle state, a GPIO2 level is read to a reception buffer, and a bit number L is received as L +1, it is determined whether the bit number is 46, when not, an exit of GPIO1_ irs () is entered, when yes, it is determined whether bits [0-31] are all 1, bits [32-33] are 0b01, when no, the current state is controlled to continue in the idle state, and a bit length is received as 0, a transmission bit length is 0, when yes, it is determined whether bits [36-41] are device address 0x08, when no, the current state is controlled to continue in the idle state, and a bit length is received as 0, a transmission bit length is 0, and when yes, the register address A is equal to bits [42-46], the operation code O is equal to bits [34-35], the current state is controlled to be busy, the receiving bit length is equal to 0, the sending bit length is equal to 0, and whether the operation code is equal to 01 or not is judged; after the judgment is started, when the mobile terminal is not in an idle state, similarly, judging whether the operation code is 01 or not; entering a write operation when the current time is positive, and entering a read operation when the current time is negative; and (3) writing: reading a high-low level value of GPIO2 to a receiving buffer, adding 1 to the receiving bit number, judging whether the receiving bit number L is equal to 16, if not, entering an outlet of GPIO1_ irs (), if so, writing 16-bit data of the receiving buffer into a register address A, finally entering an idle state, receiving the bit length of 0, and then entering an outlet of GPIO1_ irs (); and (3) reading: writing the register value of the address a into the GPIO2 in bit-by-bit manner, adding 1 to the transmission bit length, determining whether the transmission bit number L is 16, if not, entering the exit of GPIO1_ irs (), if yes, entering the final state into the idle state, and receiving the bit length of 0.

The slave CPU is continuously interrupted at 46, reads 46 bits of data, and respectively judges whether the data is a synchronous frame with 32 bits, 2 starting bits, 2 operation codes and 2 bit read-write bits; as long as there is a judgment error, the whole state machine enters an idle transition state and continues to read 46 bits.

If the operation is a read operation, writing one bit into the GPIO2 MDIO by each interrupt in the content of the address A in continuous 16 interrupts, and continuing to enter an idle state after the operation is finished; if the operation is write operation, in the continuous 16 interrupts, each interrupt reads a bit from the GPIO2 MDIO, the bits are spliced into 16-bit data and then written into the A address register, and the idle state is continuously entered after the completion.

Further, as shown in fig. 2, the present invention further provides a system for implementing the function of the mio slave based on the GPIO pin, wherein the system includes: a host MCU and a slave CPU; setting GPIO1 to be a clock signal (MDC signal) and GPIO2 to be a data signal (MDIO signal); the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in a two-wire way between the host MCU and the slave CPU; when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU.

Further, as shown in fig. 5, based on the above method for implementing the function of the mio slave based on the GPIO pin, the present invention also provides a terminal, which includes a processor 10, a memory 20 and a display 30. Fig. 5 shows only some of the components of the terminal, but it is to be understood that not all of the shown components are required to be implemented, and that more or fewer components may be implemented instead.

The memory 20 may in some embodiments be an internal storage unit of the terminal, such as a hard disk or a memory of the terminal. The memory 20 may also be an external storage device of the terminal in other embodiments, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the terminal. Further, the memory 20 may also include both an internal storage unit and an external storage device of the terminal. The memory 20 is used for storing application software installed in the terminal and various types of data, such as program codes of the installation terminal. The memory 20 may also be used to temporarily store data that has been output or is to be output. In an embodiment, the memory 20 stores a program 40 for implementing a mio slave function based on a GPIO pin, and the program 40 for implementing a mio slave function based on a GPIO pin can be executed by the processor 10, so as to implement the method for implementing a mio slave function based on a GPIO pin in the present application.

The processor 10 may be a Central Processing Unit (CPU), a microprocessor or other data Processing chip in some embodiments, and is configured to execute program codes stored in the memory 20 or process data, for example, execute the method for implementing the mio slave function based on the GPIO pin.

The display 30 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch panel, or the like in some embodiments. The display 30 is used for displaying information at the terminal and for displaying a visual user interface. The components 10-30 of the terminal communicate with each other via a system bus.

In one embodiment, the following steps are implemented when the processor 10 executes the program 40 for implementing the MIDO slave function based on the GPIO pin in the memory 20:

setting GPIO1 as a clock signal and GPIO2 as a data signal;

the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in a two-wire way between the host MCU and the slave CPU;

when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU.

The method for realizing the MIDO slave function based on the GPIO pin further comprises the following steps:

when the host MCU pulls the clock signal to high level, the slave CPU sends out interruption through the GPIO1, the slave CPU enters an interruption processing program, and the level of the MDIO pin of the GPIO2 is read and stored in the interruption processing program.

The setting of the GPIO1 as a clock signal and the GPIO2 as a data signal previously further includes:

setting GPIO1 as an input function, setting GPIO2 as an input-output function, and setting GPIO1 as an edge interrupt attribute;

mounting a GPIO1 interrupt processing function;

the number of the receiving bits is 0, and the number of the sending bits is 0;

the GPIO1 interrupt is enabled, setting the MDIO device address to 0x 08.

The interrupt processing function is used for processing the read-write request sent by the host MCU;

when the host MCU writes the slave CPU, the level of the clock signal is read in the interrupt processing function, one bit is read in each interrupt, and 5 bits are read as a device address and a 5-bit register internal address according to a protocol PHY address.

Predefining two states, namely an idle state and a busy state respectively;

the idle state indicates that no request is currently available, the bus is empty, and 32 synchronous frames are waited;

the busy status indicates that the current status has entered the MIDO timing.

The method for realizing the MIDO slave function based on the GPIO pin further comprises the following steps:

when entering the entrance of the interrupt processing function, judging whether the current state is an idle state;

when the receiver is in an idle state, reading the level of the GPIO2 to a receiving buffer, receiving the bit number, and judging whether the bit number is 46;

if yes, judging whether a 32-bit synchronous frame, 2 starting bits, 2 operation codes and 2 bit reading and writing bits exist, if no, enabling the whole state machine to enter an idle state, if yes, enabling the whole state machine to enter a busy state, receiving the bit length to be 0, and sending the bit length to be 0.

The judging whether the current state is an idle state further comprises:

when the mobile terminal is not in an idle state, entering a read operation or a write operation;

the read operation is: writing the register value of the address A into the GPIO2 according to bits, adding 1 to the sending bit length, entering the final state into an idle state, and receiving the bit length of 0;

the write operation is: reading the high-low level value of the GPIO2 to a receiving buffer, adding 1 to the number of receiving bits, writing the 16-bit data of the receiving buffer into the register address A, entering the final state into an idle state, and receiving the bit length of 0.

Further, the present invention also provides a storage medium, wherein the storage medium stores a program for implementing the function of the mio slave based on the GPIO pin, and the program for implementing the function of the mio slave based on the GPIO pin implements the steps of the method for implementing the function of the mio slave based on the GPIO pin when being executed by a processor.

In summary, the present invention provides a method and a terminal for implementing the function of an MIDO slave based on a GPIO pin, wherein the method comprises: setting GPIO1 as a clock signal and GPIO2 as a data signal; the host MCU sends the clock signal to the slave CPU, and the data signal is transmitted in a two-wire way between the host MCU and the slave CPU; when the host MCU reads the data of the slave CPU, the data signal is controlled by the slave CPU, and when the host MCU writes the data of the slave CPU, the data signal is controlled by the host MCU. The invention realizes the function of the MIDO slave machine through the GPIO pin and can be accessed by the MDIO host machine.

Of course, it will be understood by those skilled in the art that all or part of the processes of the methods of the above embodiments may be implemented by a computer program instructing relevant hardware (such as a processor, a controller, etc.), and the program may be stored in a computer readable storage medium, and when executed, the program may include the processes of the above method embodiments. The storage medium may be a memory, a magnetic disk, an optical disk, etc.

It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.