阅读说明：本技术 Sram电路及其操作方法 (SRAM circuit and operation method thereof ) 是由 藤原英弘 戴承隽 林志宇 陈炎辉 野口纮希 于 2019-07-16 设计创作，主要内容包括：静态随机存取存储器(SRAM)电路可以将存储器阵列中的列位线分组为位线的子集,并且为位线的每个子集提供y地址信号输入。额外地或可选地,存储器单元的阵列中的每行可操作地连接到多条字线。本发明的实施例还涉及SRAM电路的操作方法。(Static Random Access Memory (SRAM) circuitry may group column bit lines in a memory array into subsets of bit lines and provide a y address signal input for each subset of bit lines. Additionally or alternatively, each row in the array of memory cells is operatively connected to a plurality of word lines. Embodiments of the present invention also relate to methods of operating SRAM circuits.)

1. A Static Random Access Memory (SRAM) circuit, comprising:

a row of memory cells in a memory array, the row comprising a plurality of memory cells;

a first word line operatively connected to a first subset of memory cells of the plurality of memory cells; and

a second word line operably connected to a second subset of different memory cells of the plurality of memory cells.

2. The static random access memory circuit of claim 1, wherein the first subset of memory cells and the second subset of different memory cells include all of the plurality of memory cells.

3. The static random access memory circuit of claim 1, wherein the first subset of memory cells is interposed between memory cells in the second subset of different memory cells.

4. The static random access memory circuit of claim 3, wherein:

the first subset of memory cells comprises a first memory cell;

the second subset of the different memory cells includes a second memory cell immediately adjacent to the first memory cell;

a first access transistor in the first memory cell is operably connected to the first word line;

a second access transistor in the first memory cell is operably connected to the second word line;

a first access transistor in the second memory cell is operably connected to the second word line; and is

A second access transistor in the second memory cell is operably connected to the first word line.

5. The static random access memory circuit of claim 3, wherein:

the first subset of memory cells comprises a first memory cell;

the second subset of the different memory cells includes a second memory cell immediately adjacent to the first memory cell;

a first access transistor in the first memory cell is operably connected to the first word line;

a second access transistor in the first memory cell is operably connected to the first word line;

a first access transistor in the second memory cell is operably connected to the second word line; and is

A second access transistor in the second memory cell is operably connected to the second word line.

6. The static random access memory circuit of claim 1, further comprising:

at least one x-decoder circuit operably connected to the first word line and the second word line; and

column select circuitry operatively connected to a portion of the memory cells in the row.

7. The static random access memory circuit of claim 1, wherein each memory cell comprises a six transistor memory cell.

8. The static random access memory circuit of claim 1, wherein the static random access memory circuit comprises a single-port static random access memory circuit.

9. A Static Random Access Memory (SRAM) circuit, comprising:

a plurality of memory cells arranged in rows and columns and organized into a plurality of blocks of memory cells, wherein each block comprises a subset of the memory cells, each subset of the memory cells comprising one or more rows and two or more columns;

a plurality of column select circuits, wherein each column select circuit of the plurality of column select circuits is operatively connected to a respective block of the memory cells;

a plurality of y decoder circuits, wherein each y decoder circuit of the plurality of y decoder circuits is operatively connected to a respective column select circuit;

a first word line operatively connected to each row; and

a second word line operatively connected to each row.

10. A method of operating a Static Random Access Memory (SRAM) circuit comprising an array of memory cells, a first word line and a second word line operatively connected to each row in the array, and a plurality of bit lines operatively connected to the array of memory cells, the method comprising:

activating a first word line operably connected to a first row of memory cells in the array to select only a subset of selected memory cells in the first row of memory cells;

activating a bit line of the plurality of bit lines to access a memory cell of the subset of the selected memory cells; and

performing a read operation or a write operation on memory cells accessed in the subset of the selected memory cells.

Technical Field

Embodiments of the invention relate to SRAM circuits and methods of operating the same.

Background

Different types of memory circuits are used in electronic devices for various purposes. Read Only Memory (ROM) and Random Access Memory (RAM) are two such types of memory circuits. The ROM circuit allows data to be read from the ROM circuit but not written to the ROM circuit, and retains its stored data when the power is turned off. Thus, ROM circuits are commonly used to store programs that are executed when an electronic device is turned on.

Unlike a ROM circuit, a RAM circuit allows data to be written to and read from selected memory cells in the RAM circuit. One type of RAM circuit is a Static Random Access Memory (SRAM) circuit. A typical SRAM circuit includes an array of addressable memory cells arranged in columns and rows. In some cases, memory cells in a row may be accessed faster than memory cells in a column. For example, only one access cycle may be required to access memory cells in a row because one word line is enabled or activated to access the memory cells. However, many access cycles may be required to access the memory cells in a column because multiple word lines must be activated to access the memory cells. Multiple access cycles may also be required when a matrix of memory cells in the array (e.g., an 8 x 8 matrix) is accessed and the data in the matrix is located in a different row of the memory array.

Furthermore, in some electronic devices, the design and operation of memory circuits may adversely affect the throughput of the computing system. Processor speed has improved significantly over time, while memory transfer rate improvement is limited. As a result, the processor may spend a significant amount of time idle waiting to retrieve data from memory.

Disclosure of Invention

An embodiment of the present invention provides a Static Random Access Memory (SRAM) circuit, including: a row of memory cells in a memory array, the row comprising a plurality of memory cells; a first word line operatively connected to a first subset of memory cells of the plurality of memory cells; and a second word line operatively connected to a second subset of different ones of the plurality of memory cells.

Another embodiment of the present invention provides a Static Random Access Memory (SRAM) circuit, including: a plurality of memory cells arranged in rows and columns and organized into a plurality of blocks of memory cells, wherein each block comprises a subset of the memory cells, each subset of the memory cells comprising one or more rows and two or more columns; a plurality of column select circuits, wherein each column select circuit of the plurality of column select circuits is operatively connected to a respective block of the memory cells; a plurality of y decoder circuits, wherein each y decoder circuit of the plurality of y decoder circuits is operatively connected to a respective column select circuit; a first word line operatively connected to each row; and a second word line operatively connected to each row.

Yet another embodiment of the present invention provides a method of operating a Static Random Access Memory (SRAM) circuit including an array of memory cells, a first word line and a second word line operatively connected to each row in the array, and a plurality of bit lines operatively connected to the array of memory cells, the method comprising: activating a first word line operably connected to a first row of memory cells in the array to select only a subset of selected memory cells in the first row of memory cells; activating a bit line of the plurality of bit lines to access a memory cell of the subset of the selected memory cells; and performing a read operation or a write operation on memory cells accessed in the subset of the selected memory cells.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 illustrates a block diagram of portions of a static random access memory circuit, in accordance with some embodiments;

FIG. 2 depicts a schematic diagram of a first example of two memory cells suitable for use in the SRAM circuit shown in FIG. 1, in accordance with some embodiments;

FIG. 3 illustrates an example first word line connection pattern between two word lines and a row of memory cells for the embodiment shown in FIG. 2;

FIG. 4 depicts a schematic diagram of a second example of two memory cells suitable for use in the SRAM circuit shown in FIG. 1, in accordance with some embodiments;

FIG. 5 illustrates an example second word line connection pattern between two word lines and a row of memory cells for the embodiment shown in FIG. 4;

FIG. 6 depicts a schematic diagram of a third example of an SRAM circuit, according to some embodiments; and

FIG. 7 illustrates a flow diagram of an example method of operating an SRAM circuit, in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatial relational terms, such as "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. Spatial relationship terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such.

Embodiments described herein disclose a Static Random Access Memory (SRAM) circuit that provides simultaneous independent activation of wordlines and/or simultaneous independent activation of bitlines. This allows for the simultaneous selection of memory cells in multiple rows and columns for read and/or write operations. The SRAM circuit includes y address signal inputs for two or more subsets of columns in an array of memory cells (e.g., two or more blocks of memory cells). In some embodiments, every 2ⁿThe bit lines provide y address signal inputs, where n is equal to or greater than 1. For example, a y address signal input may be provided for 2, 4, 8, 16, 32, or 64 bit lines.

Additionally or alternatively, the SRAM circuit includes a plurality of word lines operatively connected to each row of memory cells in the SRAM circuit. For example, a pair of word lines may be connected to each row. The connection between the access transistor and the first and second word lines in each memory cell varies within each row. For example, the first and second access transistors in one memory cell in a row may be connected to one word line, and the first and second access transistors in another memory cell in the row may be connected to another word line. Alternatively, in one memory cell in a row, a first access transistor may be connected to a first word line, and a second access transistor in the memory cell may be connected to a second word line. In another memory cell in the row, the connection between the first and second access transistors may be reversed. The first access transistor may be connected to the second word line, and the second access transistor may be connected to the first word line.

Embodiments of the SRAM circuit support segment free data access. In addition, the memory cells may be accessed row by row (e.g., horizontal direction) and column by column (e.g., vertical direction). In some cases, such flexible data access may reduce the time that the processor is idle and waiting to retrieve data from memory. In addition, flexible data access may be used in a variety of applications, including but not limited to imaging process applications including convolutional neural networks.

FIG. 1 illustrates a block diagram of portions of a static random access memory circuit, in accordance with some embodiments. In the illustrated embodiment, the SRAM circuit 100 includes memory cells 102 arranged in rows and columns to form a memory array 104. The SRAM circuit 100 may include any suitable number of rows and columns. For example, an SRAM circuit includes R rows and C columns, where R is an integer greater than or equal to 1 and C is a number greater than or equal to 2.

Memory cells 102 may be logically and/or physically organized into M blocks 106A, 106B, 106M (collectively, blocks 106) of memory cells 102, where M is greater than or equal to 1. Any suitable number of memory cells 102 are included in block 106. In some cases, the number of memory cells 102 in block 106 is from 2ⁱDetermining, wherein i is a number greater than or equal to 1. For example, the block 106 may be implemented as an 8 × 8 block of memory cells (e.g., where n ═ 6 and 2⁶64 memory cells arranged in 8 rows and 8 columns) or 16 x 16 block memory cells (e.g., where n is 8 and 2⁸256 memory cells arranged in 16 rows and 16 columns). Although fig. 1 depicts three blocks 106 of memory cells 102, embodiments may include any suitable number of blocks 106 of memory cells 102, any suitable number of memory cells 102, and any suitable number of memory cells 102 in each block 106.

Each block 106 is operatively connected to column select circuitry 108A, 108B. One example of column select circuitry 108 is a multiplexer. Each column select circuit 108 is operatively connected to a y decoder circuit 110A, 110B. Each y-decoder circuit 110 receives a y- address signal 112A, 112B, and generates a y- select signal 114A, 114B, and 114M (collectively, y-address signals 112 and y-select signals 114) for a respective column select circuit 108. Each column select circuit 108 selects a column ("bit line") in the block (an exemplary bit line is represented by 116) based on a y select signal 114 and a digit line pair signal 118A, 118B.

In the illustrated embodiment, each row of memory cells in the memory array 104 is operatively connected to a first word line and a second word line (the first word lines are collectively 120 and the second word lines are collectively 122). The number of first word lines corresponds to R, i.e. the number of rows. Similarly, the number of second word lines corresponds to R. Thus, in one non-limiting example, the total number of word lines operatively connected to the memory array can correspond to 2 xR. In other embodiments, the memory cells in a row may be operably connected to three or more word lines.

An x-decoder circuit 124 is operatively connected to the first and second word lines 120, 122. Although only one x-decoder circuit is shown in fig. 1, other embodiments may include multiple x-decoder circuits, each operatively connected to a subset of word lines. Thus, x-decoder circuit 124 represents one or more x-decoder circuits.

The x-decoder circuit 124 receives a first x-address signal 126 and generates a first x-select signal on the selected first word line 120. The x-decoder circuit 124 receives a second x-address signal 128 and generates a second x-select signal on the selected second word line 122. For each selected first word line 120 and corresponding selected bit line 116, a first memory cell 102 in block 106 is selected for access (e.g., a read or write operation). Similarly, for each selected second word line 122 and corresponding selected bit line 116, a second memory cell 102 in the block 106 is selected for access (e.g., a read or write operation). The second memory unit 102 may be in the same block (e.g., blocks 106A, 106B,..., 106M) or in a different block than the first memory unit 102.

In some aspects, the SRAM circuit 100 includes y address signal inputs for a subset of the columns or bit lines in the memory array. For example, in FIG. 1, y address signal lines 112A, 112B, and 112M are provided for respective blocks 106A, 106B, and 106M, where each block 106A, 106B, and 106M includes a sub-set of bit lines 116And (4) collecting. In some embodiments, each block includes 2ⁿA bit line, wherein n is equal to or greater than 1. This allows multiple bit lines 116 to be selected and activated independently and simultaneously.

In addition, each row in the SRAM circuit 100 is operatively connected to a plurality of word lines (e.g., word lines 120, 122). The word lines 120, 122 may be independently and simultaneously selected and activated. When combined with independent and simultaneous activation of the plurality of bit lines 116, a plurality of memory cells 102 in the memory array 104 may be accessed for write operations or read operations (the plurality of memory cells 102 may be in the same or different blocks (e.g., blocks 106A, 106B, 106A).

FIG. 2 depicts a schematic diagram of a first example of two memory cells suitable for use in the SRAM circuit shown in FIG. 1, in accordance with some embodiments. Each memory cell 200, 202 is shown as a six transistor (6T) memory cell, but other embodiments are not limited to this configuration. For example, each memory cell 200, 202 may be a four transistor (4T) memory cell. In the illustrated embodiment, the first word line WL [0] and the second word line WL [1] correspond to the first and second word lines 120, 122 in FIG. 1, the memory cells 200, 202 correspond to the memory cell 102, and the bit lines 210, 216, 222, 228 correspond to the bit line 116 in FIG. 1.

Each memory cell 200, 202 includes a first cross-coupled inverter 204 operatively connected to a second cross-coupled inverter 206. The first cross-coupled inverter 204 is connected to a first access transistor T0 and the second cross-coupled inverter 206 is connected to a second access transistor T1. In the illustrated embodiment, each cross-coupled inverter 204, 206 includes a P-type metal oxide semiconductor (PMOS) transistor (e.g., P0 and P1) operatively connected to an NMOS transistor (e.g., N0 and N1). A source terminal of the PMOS transistor is operatively connected to the supply voltage and a drain terminal of the PMOS transistor is operatively connected to a drain terminal of the NMOS transistor. The source terminal of the NMOS transistor is operatively connected to a reference voltage. The gate terminal of the PMOS transistor P1 is operatively connected to the drain terminal of the NMOS transistor N0. Similarly, the gate terminal of the PMOS transistor P0 is operatively connected to the drain terminal of the NMOS transistor N1. The cross-coupled inverters 204, 206 form a memory cell having two stable states for representing 0 and 1.

The access transistors T0, T1 control access to the memory cells during read and write operations. The two access transistors T0, T1 enable reading or writing of the bit from the memory cells 200, 202. This type of SRAM memory cell is referred to as a single-port memory cell, and the SRAM circuit is referred to as a single-port SRAM circuit. Other embodiments are not limited to this implementation. For example, the memory cells 200, 202 may be dual port SRAM memory cells.

In the illustrated embodiment, the access transistors T0, T1 are NMOS transistors. In the first memory cell 200, the gate of the first access transistor T0 is operably connected to a second word line WL [1] at node 208. The source of the first access transistor T0 is operatively connected to the bit line 210 at node 212. And the drain of the first access transistor T0 is operatively connected to the drain of the NMOS transistor N0. With respect to the second access transistor T1 in the first memory cell 200, the gate of the second access transistor T1 is operatively connected to the first word line WL [0] at node 214. The drain of the second access transistor T1 is operatively connected to the drain of the NMOS transistor N1, and the source of the second access transistor T1 is operatively connected to the bit line 216 at node 218.

In second memory cell 202, the gate of first access transistor T0 is operably connected to a first word line WL [0] at node 220. The source of the first access transistor T0 is operatively connected to the bit line 222 at node 224, and the drain of the first access transistor T0 is operatively connected to the drain of the NMOS transistor N0. With respect to the second access transistor T1 in the second memory cell 202, the gate of the second access transistor T1 is operatively connected to a second word line WL [1] at node 226. The drain of the second access transistor T1 is operatively connected to the drain of the NMOS transistor N1, and the source of the second access transistor T1 is operatively connected to the bit line 228 at node 230.

In the embodiment of FIG. 2, the gates of the access transistors T0, T1 in each memory cell 200, 202 are selectively connected to either the first or second word lines WL [0], WL [1 ]. In each row in a block or memory array (e.g., block 106 or memory array 104 in FIG. 1), the gate of the first access transistor T0 in memory cell 200 is connected to the second word line WL [1], and in the immediately adjacent memory cell 202, the gate of the first access transistor T0 is connected to the first word line WL [0 ]. Similarly, in the same row, the gate of the second access transistor T1 in the first memory cell 200 is connected to the first word line WL [0], and the gate of the second access transistor T1 in the second memory cell 202 is connected to the second word line WL [1 ]. In one embodiment, memory cell 200 is in an even column and memory cell 202 is in an odd column. In another embodiment, memory cell 200 is in an odd column and memory cell 202 is in an even column.

FIG. 3 shows an example first word line connection pattern between two word lines and a row of memory cells for the embodiment shown in FIG. 2. Row 300 is a row in a block or a row in a memory array (e.g., block 106 or memory array 104 in fig. 1). The connection between the first and second access transistors T0, T1 and the first and second word lines WL [0], WL [1] in the memory cells 220, 202 varies within the row 300 of memory cells 200, 202.

In the non-limiting example of fig. 3, row 300 includes eight memory cells 200, 202. In this row 300, the gates of the first set of second access transistors T1 in a memory cell 200 are connected to a first word line WL [0], and the first set of first access transistors T0 in the same memory cell 200 are connected to a second word line WL [1 ]. In the memory cells 202 immediately adjacent to the memory cell 200 (e.g., the memory cell 202 is interposed between the memory cells 200), the gates of the second set of second access transistors T1 are connected to the second word line WL [1], and the gates of the second set of first access transistors T0 in the same memory cell 202 are connected to the first word line WL [0 ].

Thus, in a first word line connection pattern, the gate of one access transistor in a memory cell is connected to one word line and the gate of another access transistor in the same memory cell is connected to another word line, and the word line connections alternate every other memory cell 200, 202 in row 300. The first word line connection pattern may extend throughout the row 300, or the rows 300 in at least one block (e.g., block 106 in fig. 1) may have different word line connection patterns. For example, a row 300 in one block may have a first word line connection pattern shown in FIG. 2, while the word line connection patterns in another block may be different, except that the gates of the first set of second access transistors T1 in a memory cell 200 may be connected to a second word line WL [1], the gates of the first set of first access transistors T0 in the same memory cell 200 may be connected to a first word line WL [0], the gates of the second set of second access transistors T1 in a memory cell 202 are connected to a first word line WL [0], and the gates of the second set of first access transistors T0 in the same memory cell 202 may be connected to a second word line WL [1 ].

Additionally or alternatively, each row in the memory array may have a first word line connection pattern, or the word line connection patterns may be different for at least one row in the memory array. For example, a row in a memory array may have a first word line connection pattern shown in fig. 2. Another row in the memory array may have a different word line connection pattern. In a non-limiting example, different word line connection patterns may connect the gates of the first set of second access transistors T1 in a memory cell 200 to a second word line WL [1], the gates of the first set of first access transistors T0 in the same memory cell 200 to a first word line WL [0], the gates of the second set of second access transistors T1 in a memory cell 202 to the first word line WL [0], and the gates of the second set of first access transistors T0 in the same memory cell 202 to the second word line WL [1 ].

FIG. 4 depicts a schematic diagram of a second example of two memory cells suitable for use in the SRAM circuit shown in FIG. 1, in accordance with some embodiments. Each memory cell 400, 402 is shown as a six transistor (6T) memory cell, but other embodiments are not limited to this configuration. In the illustrated embodiment, the first word line WL [0] and the second word line WL [1] correspond to the first and second word lines 120, 122 in FIG. 1, and the memory cells 400, 402 correspond to the memory cell 102.

The first and second memory cells 400, 402 are the same as the first and second memory cells 200, 202 in FIG. 2, except for the connections between the first and second word lines WL [0], WL [1] and the gates of the first and second access transistors T0, T1. In the first memory cell 400, the gates of the first and second access transistors T0, T1 are operably connected to a first word line WL [0] at nodes 404, 406, respectively. In the immediately adjacent second memory cell 402, the gates of the first and second access transistors T0, T1 are operably connected to a second word line WL [1] at nodes 408, 410, respectively. In one embodiment, memory cell 400 is in an even column and memory cell 402 is in an odd column. In another embodiment, memory cell 400 is in an odd column and memory cell 402 is in an even column.

FIG. 5 illustrates an example second word line connection pattern between two word lines and a row of memory cells for the embodiment shown in FIG. 4. Row 500 is a row in a block or a row in a memory array (e.g., block 106 or memory array 104 in fig. 1). The connection between the first and second access transistors T0, T1 and the first and second word lines WL [0], WL [1] in the memory cells 400, 402 varies within the row 500 of memory cells 400, 402.

In the non-limiting example of FIG. 5, row 500 includes eight memory cells. In this row 500, the gates of the first set of first access transistors T0 and the gates of the first set of second access transistors T1 in memory cells 400 are connected to a first word line WL [0 ]. In the memory cell 402 next to the memory cell 400 (the memory cell 402 is interposed between the memory cells 400), the gates of the second group first access transistors T0 and the gates of the second group second access transistors T1 are connected to the second word line WL [1 ]. Thus, in the second word line connection pattern, the gates of the two access transistors T0, T1 in the memory cell 400 are connected to one word line (the same word line), and the gates of the two access transistors T0, T1 in the memory cell 402 are connected to the other word line. The connections between the access transistors T0, T1 and the word lines WL [0], WL [1] in the memory cells 400, 402 alternate for every other memory cell 400, 402 in the row 500.

The second word line connection pattern may extend across the entire row 500, or the memory cells in at least one block (e.g., block 106 in fig. 1) may have different connection patterns. For example, a second word line connection pattern may be implemented in a first block associated with row 500, while a different word line connection pattern is used in a second block associated with row 500. For example, the word line connection pattern may be different in the second block, the word line connection pattern being inverted (e.g., the gates of the two access transistors in the first memory cell 400 are connected to the second word line WL [1], and the gates of the two access transistors in the second memory cell 402 are connected to the first word line WL [0 ]). Alternatively, the gates of the access transistors in a second block (e.g., block 106 in FIG. 1) may be connected to word lines WL [0], WL [1] according to a first word line connection pattern.

Additionally or alternatively, each row in the memory array may have a second word line connection pattern, or the connection pattern may be different for at least one row in the memory array. For example, one row in the memory array may have a second word line connection pattern (fig. 4), and another row in the memory array may have a different word line connection pattern (e.g., the first word line connection pattern shown in fig. 2).

Other word line connection patterns may be used in other embodiments. For example, the first word line connection pattern shown in FIG. 2 may be modified such that the connections between the gates of the access transistors T0, T1 and the word lines WL [0], WL [1] may alternate every two memory cells. In another example, the second word line connection pattern shown in FIG. 4 may be modified such that the connections between the gates of the access transistors T0, T1 and the word lines WL [0], WL [1] may alternate every two memory cells. Any word line connection pattern that changes the connection between the word line and the access transistors across the rows and enables independent access to the memory cells may be used.

FIG. 6 depicts a schematic diagram of a third example of an SRAM circuit, according to some embodiments. FIG. 6 is similar to FIG. 1, but shows the connections between the memory cells and the word lines in more detail. In the illustrated embodiment, word lines AWL [0] and AWL [1] correspond to second word line 122 in FIG. 1, and word lines BWL [0] and BWL [1] correspond to first word line 120.

The SRAM circuit 600 is depicted as having M blocks 106A, 106B, ·, 106M (collectively referred to as blocks 106) of memory cells 102 in the memory array 104. The memory array 104 includes any suitable number of rows and columns. In the illustrated embodiment, each block 106 includes two rows 602, 604 of memory cells 102 and four columns 606, 608, 610, 612 of memory cells 102, for a total of eight memory cells 102 in each block 106.

The x-decoder circuit 124 is operably connected to word lines AWL [0], BWL [0], AWL [1], BWL [1 ]. A first pair of wordlines AWL [0], BWL [0] are operably connected to row 602, and a second pair of wordlines AWL [1], BWL [1] are operably connected to row 604. With respect to row 602, a first pair of word lines AWL [0], BWL [0] are operably connected to alternating memory cells. For example, word line AWL [0] is operably connected to memory cells 614, 616, and word line BWL [0] is operably connected to memory cells 618, 622.

With respect to row 604, a second pair of word lines AWL [1], BWL [1] are operably connected to alternate memory cells. For example, word line AWL [1] is operably connected to memory cells 622, 624, and word line BWL [1] is operably connected to memory cells 626, 628. In a non-limiting embodiment, the first pair of word lines AWL [0], BWL [0] and the second pair of word lines AWL [1], BWL [1] are operably connected to memory cells 614, 616, 618, 620, 622, 624, 626, 628 according to a second word line connection pattern shown in FIG. 4.

Since the word line connections in FIG. 6 correspond to the second word line pattern shown in FIG. 4, activating one word line (e.g., word line AWL [0]) that is operably connected to a row enables or activates the gates of the first and second access transistors (e.g., first access transistor T0 and second access transistor T1 in FIGS. 4 and 5) in the first subset of memory cells 102 in the row. For example, when wordline AWL [0] is activated, memory cells 614, 616 are selected, while activating another wordline (e.g., BWL [0]) that is operably connected to the same row (e.g., row 602) activates the gates of the first and second access transistors in the second subset of memory cells 102 in the same row. When combined, the first and second subsets of memory cells include all of the memory cells in a row (e.g., row 602). Alternatively, activating a word line operatively connected to a first row (e.g., row 602) activates the gates of the first and second access transistors in the subset of memory cells in the first row, while activating a second word line operatively connected to a second row (e.g., row 604) activates the gates of the first and second access transistors in the subset of memory cells in the second row.

Example embodiments of accessing a selected memory cell 102 in a memory array 104 are now described. In fig. 6, the activation of the word and bit lines is represented by the thick word and bit lines. The x-decoder circuit 124 receives a first x-address signal to activate wordline BWL [0], and the x-decoder circuit 124 receives a second x-address signal to activate wordline AWL [1 ]. y-decoder circuit 110A receives the first y address signal to generate a first y select signal on line 114A. Column select circuit 108A activates bit line 630 based on y-select signal 114A and digit line pair signal 118A. Based on the activation of word line AWL [1] and bit line 630, memory cell 622 is selected and accessed for a read or write operation.

Continuing with the non-limiting example, y-decoder circuit 110B receives a second y-address signal to generate a second y-select signal on line 114B. Column select circuit 108B activates second bit line 632 based on y-select signal 114B and digit line pair signal 118B. Based on the activation of wordline BWL [0] and bitline 632, memory cell 634 is selected and accessed for a read or write operation.

y-decoder circuit 110M may receive the third y-address signal to generate a third y-select signal on line 114M. Column select circuit 108M activates bit line 636 based on y-select signal 114M and digit line pair signal 118M. Memory cell 638 is selected and accessed for a read or write operation based on the activation of wordline BWL [0] and bitline 636.

In FIG. 6, additional or different memory cells 102 may be selected and accessed by independently activating select word lines and bit lines. For example, based on activation of word line AWL [0] and bit line 642, memory cell 640 is selected and accessed for a read or write operation.

Embodiments described herein can select different subsets of memory cells based on which word lines are activated. For example, in FIG. 6, when the word line AWL [0] is activated, memory cells 614, 616, 640, 644, 646, 648 are selected and form a subset of the selected memory cells. Additionally or alternatively, when word line BWL [1] is asserted, memory cells 626, 628, 650, 652, 654, 656 are selected and constitute a subset of the selected memory cells. Thus, depending on which word lines are activated, multiple subsets of selected memory cells may be selected, with the subsets being located in the same row or in different rows.

In addition, when activating one or more word lines, embodiments may access different subsets of memory cells for read or write operations based on which bit lines are asserted. For example, in FIG. 6, when word line AWL [0] is activated and bit lines 630, 658 are asserted, memory cells 614, 648 are accessed for a read or write operation, and memory cells 614, 648 form a subset of the accessed memory cells. In addition, when word line BWL [1] is asserted and bit lines 630, 632 are asserted, memory cells 622, 652 are accessed for a read or write operation. Memory cells 622, 652 constitute a subset of the accessed memory cells.

Alternatively, when word line BWL [1] is asserted and bit lines 658, 660 are asserted, memory cells 626, 648 are accessed for a read or write operation and form a subset of the accessed memory cells. Thus, depending on which word lines and which bit lines are activated, the subset of memory cells accessed is: (1) in the same row and operatively connected to the same set of column output circuits (e.g., the column output circuits associated with column select circuit 108A); (2) column output circuits in the same row and operatively connected to different groups (e.g., column output circuits associated with column select circuits 108A and 108B); (3) in different rows and operatively connected to the same set of column output circuits; and/or (4) in different rows and operatively connected to different sets of column output circuits. When one or more bit lines are asserted and then one or more word lines are activated, independent access to one or more subsets of the accessed memory cells for read or write operations may also be performed.

FIG. 7 illustrates a flow diagram of an example method of operating an SRAM circuit, in accordance with some embodiments. First, as shown in block 700, a plurality of word lines are independently activated. Multiple word lines may be operably connected to the same row or different rows in the memory array.

Next, as indicated at block 702, the plurality of bit lines are independently activated. The bit lines may be associated with memory cells of the same or different blocks (e.g., block 106 in FIG. 1). Based on the activation of the plurality of word lines and the plurality of bit lines, certain memory cells in the memory array are selected and accessed for a read or write operation at block 704.

Embodiments disclosed herein provide SRAM circuits that can access memory cells in the same and/or different blocks of memory cells by simultaneously and independently activating select word lines and simultaneously and independently activating select bit lines. The select memory cells are located in different columns and may be in the same row or in different rows. This results in an SRAM circuit that is more flexible in addressing and accessing memory cells. In some cases, it reduces the time required to access multiple memory cells.

Although the blocks shown in fig. 7 are shown in a particular order, in other embodiments, the order of the blocks may be arranged differently. For example, block 704 may be performed before blocks 700 and 702. Alternatively, blocks 700 and 704 may be performed before block 702.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

A Static Random Access Memory (SRAM) circuit includes a row of memory cells in a memory array, where the row includes a plurality of memory cells. The first word line is operatively connected to a first subset of memory cells of the plurality of memory cells. The second word line is operably connected to a second subset of different ones of the plurality of memory cells. In one embodiment, the first subset of memory cells and the second subset of memory cells include all memory cells in the row.

In the above static random access memory circuit, wherein the first subset of memory cells and the second subset of different memory cells include all of the plurality of memory cells.

In the above static random access memory circuit, wherein the first subset of memory cells is interposed between memory cells in the second subset of different memory cells.

In the above static random access memory circuit, wherein the first subset of memory cells is interposed between memory cells in the second subset of different memory cells, wherein: the first subset of memory cells comprises a first memory cell; the second subset of the different memory cells includes a second memory cell immediately adjacent to the first memory cell; a first access transistor in the first memory cell is operably connected to the first word line; a second access transistor in the first memory cell is operably connected to the second word line; a first access transistor in the second memory cell is operably connected to the second word line; and a second access transistor in the second memory cell is operably connected to the first word line.

In the above static random access memory circuit, wherein the first subset of memory cells is interposed between memory cells in the second subset of different memory cells, wherein: the first subset of memory cells comprises a first memory cell; the second subset of the different memory cells includes a second memory cell immediately adjacent to the first memory cell; a first access transistor in the first memory cell is operably connected to the first word line; a second access transistor in the first memory cell is operably connected to the first word line; a first access transistor in the second memory cell is operably connected to the second word line; and a second access transistor in the second memory cell is operably connected to the second word line.

In the above static random access memory circuit, further comprising: at least one x-decoder circuit operably connected to the first word line and the second word line; and column select circuitry operatively connected to a portion of the memory cells in the row.

In the above static random access memory circuit, wherein each memory cell comprises a six transistor memory cell.

In the above sram circuit, the sram circuit may comprise a single-port sram circuit.

A Static Random Access Memory (SRAM) circuit includes a plurality of memory cells arranged in rows and columns and grouped into a plurality of blocks of memory cells, where each block includes a subset of the memory cells. In some aspects, each subset of memory cells includes one or more rows and two or more columns. The SRAM circuit further includes a plurality of column select circuits, wherein each column select circuit is operatively connected to a respective block of memory cells. The SRAM circuit also includes a plurality of y-decoder circuits, where each y-decoder circuit is operatively connected to a respective column select circuit, and to the first word line and the second word line of each row.

In the above static random access memory circuit, further comprising one or more x-decoder circuits operatively connected to the first word line and the second word line.

In the above static random access memory circuit, wherein the connections between the first and second word lines and the memory cells in the respective rows vary along the respective rows.

In the above static random access memory circuit, wherein the connections between the first and second word lines and the memory cells in respective rows vary along the respective rows, wherein each row comprises a first memory cell and a second memory cell immediately adjacent to the first memory cell.

In the above static random access memory circuit, wherein connections between the first and second word lines and the memory cells in respective rows vary along the respective rows, wherein each row includes a first memory cell and a second memory cell immediately adjacent to the first memory cell, wherein each of the first and second memory cells includes a first access transistor and a second access transistor, and: the first access transistor in the first memory cell is operably connected to the first word line; the second access transistor in the first memory cell is operably connected to the second word line; the first access transistor in the second memory cell is operably connected to the second word line; and the second access transistor in the second memory cell is operably connected to the first word line.

In the above static random access memory circuit, wherein connections between the first and second word lines and the memory cells in respective rows vary along the respective rows, wherein each row includes a first memory cell and a second memory cell immediately adjacent to the first memory cell, wherein each of the first and second memory cells includes a first access transistor and a second access transistor, and: the first access transistor in the first memory cell is operably connected to the first word line; the second access transistor in the first memory cell is operably connected to the first word line; the first access transistor in the second memory cell is operably connected to the second word line; and the second access transistor in the second memory cell is operably connected to the second word line.

In the above static random access memory circuit, further comprising one or more x-decoder circuits operatively connected to the first word line and the second word line, wherein each memory cell comprises a six transistor memory cell.

In the above static random access memory circuit, further comprising one or more x-decoder circuits operatively connected to the first word line and the second word line, wherein the static random access memory circuit comprises a single-port static random access memory circuit.

A Static Random Access Memory (SRAM) circuit may include an array of memory cells, wherein a first word line and a second word line are operatively connected to each row in the array, and a plurality of bit lines are operatively connected to the array of memory cells. A method of operating a static random access memory circuit includes activating a first word line operatively connected to a first row of memory cells in an array to select only a subset of selected memory cells in the first row of memory cells, and activating a bit line of a plurality of bit lines to access memory cells in the subset of selected memory cells. A read operation or a write operation is then performed on the memory cells accessed in the subset of the selected memory cells.

In the above method, wherein: the bit line comprises a first bit line; the memory cells accessed in the subset of the selected memory cells include a first memory cell accessed in the subset of the selected memory cells; and the method further comprises: activating a second bit line of the plurality of bit lines to access a second memory cell of the subset of the selected memory cells; and performing a read operation or a write operation on the second memory cell.

In the above method, wherein: the bit line comprises a first bit line; the memory cells accessed in the subset of the selected memory cells include a first memory cell accessed in the subset of the selected memory cells; and the method further comprises: activating a second bit line of the plurality of bit lines to access a second memory cell of the subset of the selected memory cells; and performing a read operation or a write operation on the second memory cell, wherein each of the first and second memory cells includes a first access transistor and a second access transistor, and: activating the first word line activates a first gate of the first access transistor and a second gate of the second access transistor in the first memory cell; and activating the second word line activates the first gate of the first access transistor and the second gate of the second access transistor in the second memory cell.

In the above method, wherein: the bit line comprises a first bit line; the memory cells accessed in the subset of the selected memory cells include a first memory cell accessed in the subset of the selected memory cells; and the method further comprises: activating a second bit line of the plurality of bit lines to access a second memory cell of the subset of the selected memory cells; and performing a read operation or a write operation on the second memory cell, wherein each of the first and second memory cells includes a first access transistor and a second access transistor, and: activating the first word line activates a first gate of the first access transistor in the first memory cell and a second gate of the second access transistor in the second memory cell; and activating the second word line activates the second gate of the second access transistor in the first memory cell and the first gate of the first access transistor in the second memory cell.