阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 大部功 小屋茂树 梅本康成 筒井孝幸 于 2019-06-28 设计创作，主要内容包括：本发明提供在安装到外部基板时能够抑制电连接不良的产生的半导体装置。半导体装置具有：半导体基板；多个第一双极晶体管,设置于半导体基板的第一主面侧,在与第一主面垂直的方向上,在发射层与发射极之间具有第一高度；至少一个以上的第二双极晶体管,设置于半导体基板的第一主面侧,在与第一主面垂直的方向上,在发射层与发射极之间具有比第一高度高的第二高度；以及第一凸块,遍布多个第一双极晶体管和至少一个以上的第二双极晶体管而配置。(A semiconductor device includes a semiconductor substrate, a plurality of th bipolar transistors provided on a th main surface side of the semiconductor substrate and having a th height between an emitter layer and an emitter in a direction perpendicular to a 0 th main surface, at least or more second bipolar transistors provided on a th main surface side of the semiconductor substrate and having a second height between the emitter layer and the emitter higher than the th height in a direction perpendicular to a th main surface, and th bumps arranged over the plurality of th bipolar transistors and the at least or more second bipolar transistors.)

A semiconductor device of the kind 1, , having:

a semiconductor substrate;

a plurality of th bipolar transistors, which are disposed on the th main surface side of the semiconductor substrate and have a th height between the emitter layer and the emitter in a direction perpendicular to the th main surface;

at least or more second bipolar transistors arranged on the main surface side of the semiconductor substrate and having a second height between the emitter layer and the emitter layer higher than the height in a direction perpendicular to the main surface, and

the th bump is disposed over a plurality of the th bipolar transistors and at least of the second bipolar transistors.

2. The semiconductor device according to claim 1, wherein:

a plurality of third bipolar transistors provided on the th main surface side of the semiconductor substrate and having the second height between the emitter layer and the emitter in a direction perpendicular to the th main surface, and

and second bumps disposed over the plurality of third bipolar transistors.

3. The semiconductor device according to claim 2,

the th bipolar transistor is disposed between the second bipolar transistor and the third bipolar transistor in a direction parallel to the th main surface of the semiconductor substrate.

4. The semiconductor device according to claim 2 or 3,

the third bipolar transistor is a heterojunction bipolar transistor.

5. The semiconductor device according to any of claims 2 to 4, wherein,

the second bump is a pillar bump.

6. The semiconductor device according to any of claims 2 to 5, wherein,

the third bipolar transistor has a resistive layer between the emitter layer and the emitter.

7. The semiconductor device according to claim 6,

the resistive layer of the third bipolar transistor contains AlGaAs as a main component.

8. The semiconductor device according to any of claims 2 to 7, wherein,

the bases of the th bipolar transistors are electrically connected to a common th base interconnection, the collectors of the th bipolar transistors are electrically connected to a common th collector interconnection,

at least of bases and collectors of the second bipolar transistor are not connected to the th base interconnection and the th collector interconnection.

9. The semiconductor device according to any of claims 2 to 8, wherein,

emitters of the th bipolar transistors and the second bipolar transistors are electrically connected to a common emitter wire ,

emitters of the plurality of third bipolar transistors are electrically connected to a common second emitter wiring,

the th bump is disposed on the th emitter wire along the th emitter wire,

the second bump is provided above the second emitter wiring along the second emitter wiring.

10. The semiconductor device according to claim 1,

having a plurality of the above-mentioned second bipolar transistors,

the plurality of th bipolar transistors and the plurality of second bipolar transistors are alternately arranged in a direction parallel to the th main surface of the semiconductor substrate.

11. The semiconductor device according to claim 10,

the bases of the th bipolar transistors are electrically connected to a common th base interconnection, the collectors of the th bipolar transistors are electrically connected to a common th collector interconnection,

the bases of the second bipolar transistors are electrically connected to a common second base interconnection, and the collectors of the second bipolar transistors are electrically connected to a common second collector interconnection.

12. The semiconductor device according to any of claims 1 to 11, wherein,

the th bipolar transistor and the second bipolar transistor are heterojunction bipolar transistors.

13. The semiconductor device according to any of claims 1 to 12, wherein,

the th bump is a pillar bump.

14. The semiconductor device according to any of claims 1 to 13, wherein,

the second bipolar transistor has a resistive layer between the emitter layer and the emitter.

15. The semiconductor device according to claim 14,

the resistive layer of the second bipolar transistor contains AlGaAs as a main component.

Technical Field

The present invention relates to a semiconductor device.

Background

Patent document 1 describes a semiconductor device in which a th bipolar transistor and a second bipolar transistor are provided on the same semiconductor substrate, a plurality of unit transistors constituting a th bipolar transistor do not have an emitter ballast resistor layer, and a plurality of unit transistors constituting the second bipolar transistor have an emitter ballast resistor layer.

Patent document 1: japanese patent laid-open publication No. 2017-220584

In the semiconductor device of patent document 1, the height between the rear surface of the semiconductor substrate and the emitter wiring (upper surface of the emitter) of the th bipolar transistor is different from the height between the rear surface of the semiconductor substrate and the emitter wiring (upper surface of the emitter) of the second bipolar transistor, and therefore, in the case where bumps are provided for the th bipolar transistor and the second bipolar transistor, respectively, and the semiconductor device is mounted on the module substrate via the bumps, there is a possibility that a connection failure occurs.

Disclosure of Invention

The invention provides a semiconductor device capable of suppressing occurrence of poor electrical connection when mounted on an external substrate.

The semiconductor device includes a semiconductor substrate, a plurality of bipolar transistors provided on a 0 th main surface side of the semiconductor substrate and having a th height between an emitter layer and an emitter in a direction perpendicular to the 1 th main surface, at least or more second bipolar transistors provided on the th main surface side of the semiconductor substrate and having a second height between the emitter layer and the emitter higher than the th height in a direction perpendicular to the th main surface, and an th bump provided over the plurality of bipolar transistors and at least or more second bipolar transistors.

Effects of the invention

According to the semiconductor device of the present invention, when mounted on an external substrate, occurrence of electrical connection failure can be suppressed.

Drawings

Fig. 1 is a plan view of a semiconductor device according to embodiment .

Fig. 2 is a sectional view taken along line II-II' of fig. 1.

Fig. 3 is a cross-sectional view of an th bipolar transistor.

Fig. 4 is a cross-sectional view of a second bipolar transistor.

Fig. 5 is an equivalent circuit diagram of the th transistor group.

Fig. 6 is an equivalent circuit diagram of the second transistor group.

Fig. 7 is an explanatory diagram for explaining a method of manufacturing the semiconductor device according to embodiment .

Fig. 8 is a plan view of a semiconductor device according to a modification of embodiment .

Fig. 9 is a sectional view taken along line IX-IX' of fig. 8.

Fig. 10 is an equivalent circuit diagram of a th transistor group according to a th modification example of the th embodiment.

Fig. 11 is a plan view of a semiconductor device according to a second modification example of embodiment .

Fig. 12 is a plan view of a semiconductor device according to a third modification example of embodiment .

Fig. 13 is a plan view of a semiconductor device according to a fourth modification example of the embodiment.

Fig. 14 is a plan view of a semiconductor device according to a fifth modification example of the embodiment.

Fig. 15 is a plan view of a semiconductor device according to a sixth modification example of the embodiment.

Fig. 16 is a plan view of the semiconductor device according to the second embodiment.

Fig. 17 is a sectional view taken along line XVII-XVII' of fig. 16.

Fig. 18 is an equivalent circuit diagram of the semiconductor device according to the second embodiment.

Fig. 19 is a cross-sectional view of the semiconductor device according to the third embodiment.

Fig. 20 is a sectional view of a power amplifier module according to the fourth embodiment.

Fig. 21 is a block diagram showing a configuration of a power amplifier module according to the fourth embodiment.

Detailed Description

In the following, embodiments of a semiconductor device according to the present invention will be described in detail with reference to the drawings, and the present invention is not limited to the embodiments, and it goes without saying that each embodiment is an example, and partial replacement or combination of the configurations shown in the different embodiments can be performed.

(embodiment )

Fig. 1 is a plan view of a semiconductor device according to an th embodiment, fig. 2 is a sectional view taken along line II-II' of fig. 1, fig. 3 is a sectional view of a th bipolar transistor, fig. 4 is a sectional view of a second bipolar transistor, fig. 5 is an equivalent circuit diagram of a th transistor group, fig. 6 is an equivalent circuit diagram of the second transistor group, and fig. 1 shows a detailed configuration of each bipolar transistor, and schematically shows a positional relationship of each bipolar transistor.

As shown in fig. 1, the semiconductor device 100 includes a semiconductor substrate 1, an th transistor group Qa, a second transistor group Qb, a th bump 61, and a second bump 62.

In the following description, the direction in the plane parallel to the th main surface S1 of the semiconductor substrate 1 is referred to as the X direction, a direction orthogonal to the X direction in the plane parallel to the th main surface S1 is referred to as the Y direction, and a direction orthogonal to each of the X direction and the Y direction is referred to as the Z direction.

As shown in fig. 1, the semiconductor substrate 1 has a substantially rectangular shape in a plan view when viewed from the Z direction, and as shown in fig. 2, the semiconductor substrate 1 has an th main surface S1 and a second main surface S2 facing the th main surface S1, the longitudinal direction of the semiconductor substrate 1 is arranged along the X direction, the short side direction is arranged along the Y direction, and the direction perpendicular to the th main surface S1 is the Z direction, and the semiconductor substrate 1 is made of, for example, semi-insulating gallium arsenide (GaAs).

As shown in fig. 1 and 2, the th transistor group Qa and the second transistor group Qb are provided on the th main surface S1 side of the semiconductor substrate 1, the th transistor group Qa and the second transistor group Qb are adjacently disposed with a space in the X direction, the th transistor group Qa has a plurality of th bipolar transistors 20 and a plurality of second bipolar transistors 30, the second transistor group Qb has a plurality of third bipolar transistors 40, that is, the plurality of th bipolar transistors 20, a plurality of second bipolar transistors 30, and a plurality of third bipolar transistors 40 are provided on the st main surface S1 side of the semiconductor substrate 1.

The th Bipolar Transistor 20, the second Bipolar Transistor 30, and the third Bipolar Transistor 40 are Heterojunction-type Bipolar transistors (HBTs), respectively, and in fig. 1, the second Bipolar Transistor 30 and the third Bipolar Transistor 40 are indicated by hatching so as to be distinguished from the th Bipolar Transistor 20.

The th bipolar transistor 20, the second bipolar transistor 30, and the third bipolar transistor 40 are also referred to as unit transistors, respectively, the th bipolar transistor 20 is electrically connected in parallel to constitute the th transistor group Qa. at least sides of the collector and base of the second bipolar transistor 30 are not connected to the th bipolar transistor 20 and do not function as a transistor, the plurality of third bipolar transistors 40 are electrically connected in parallel to constitute the second transistor Qb., and the unit transistor is defined as the smallest transistor constituting the th transistor group Qa or the second transistor group Qb.

In this embodiment, the -numbered -transistor group Qa includes 6 of the th bipolar transistors 20 and 3 of the second bipolar transistors 30, and in the -numbered transistor group Qa, the 3 second bipolar transistors 30 are disposed apart at both ends and at the center in the X direction, and the -numbered bipolar transistors 20 are disposed between the adjacent second bipolar transistors 30 in the X direction.

In this embodiment, the second transistor group Qb has 6 third bipolar transistors 40. In the second transistor group Qb, the plurality of third bipolar transistors 40 are arranged side by side in the X direction. However, the number and arrangement of the third bipolar transistors 40 may be changed as appropriate.

The th bump 61 is disposed throughout the plurality of th bipolar transistors 20 and the plurality of second bipolar transistors 30 the second bump 62 is disposed throughout the plurality of third bipolar transistors 40.

As shown in fig. 2, an isolation region 50 is provided between the th transistor group Qa and the second transistor group Qb in the semiconductor substrate 1 and the subcollector layer 2, the isolation region 50 is a region where the semiconductor substrate 1 and portion of the subcollector layer 2 are insulated by ion implantation, and the th transistor group Qa and the second transistor group Qb are electrically isolated by the isolation region 50.

The th bipolar transistor 20 is a transistor without the emitter ballast resistor 88 the second bipolar transistor 30 and the third bipolar transistor 40 are transistors with the emitter ballast resistor 88.

Specifically, as shown in fig. 3, the th bipolar transistor 20 includes a sub-collector layer 2, a collector layer 3, a base layer 4, an emitter layer 5, a th contact layer 6, various electrodes, and wiring, the sub-collector layer 2, the collector layer 3, the base layer 4, the emitter layer 5, and a th contact layer 6 are laminated in this order on the semiconductor substrate 1.

The subcollector layer 2 is provided on the th main surface S1 of the semiconductor substrate 1, the collector layer 3 is provided on the subcollector layer 2, the subcollector layer 2 and the collector layer 3 function as collectors of the th bipolar transistor 20, the subcollector layer 2 and the collector layer 3 are n-type semiconductors containing GaAs as a main component, for example, the subcollector layer 2 may have a Si doping concentration of about 5 × 10¹⁸cm^－3The film thickness was about 600 nm. The collector layer 3 can be doped with Si at a concentration of about 1X 10¹⁶cm^－3The film thickness was about 1000 nm.

The base layer 4 is disposed on the collector layer 3. The base layer 4 is, for example, a p-type semiconductor containing GaAs as a main component. The base layer 4 can be C doped to a concentration of about 5 x 10¹⁹cm^－3The film thickness was about 96 nm.

The emission layer 5 is disposed on the base layer 4. The emitter layer 5 is an n-type semiconductor containing InGaP as a main component, for example. The emitter layer 5 can be InP with a molar ratio of about 0.48 and a Si doping concentration of about 4X 10¹⁷cm^－3The film thickness was about 35 nm.

The th contact layer 6 is disposed on the emitter layer 5. the th contact layer 6 is, for example, an n-type semiconductor containing GaAs as a main component. the th contact layer 6 can be made of Si with a doping concentration of about 5X 10¹⁸cm^－3The film thickness was about 50 nm.

The 2 collectors 15 are provided on the sub-collector layer 2, and are provided so as to sandwich the collector layer 3 in the X direction. The collector 15 is AuGe (thickness of about 60nm)/Ni (thickness of about 10nm)/Au (thickness of about 200 nm). Further, "/" indicates a laminated structure. For example, AuGe/Ni/Au represents a structure in which Ni is stacked on AuGe and Au is stacked on Ni.

In the present embodiment, the collectors 15 are shared by the th bipolar transistors 20 adjacent to each other, in other words, as shown in fig. 2, collectors 15 are provided between the th bipolar transistors 20 adjacent to each other, collectors 15 are electrically connected to each of the th bipolar transistors 20 adjacent to each other, whereby the number of electrodes and wirings of the th transistor group Qa can be reduced as compared with the case where 2 collectors 15 are provided for each th bipolar transistor 20.

As shown in FIG. 3, 2 bases 16 are disposed on the base layer 4. in a plan view, th contact layers 6 are disposed between the 2 bases 16. the bases 16 are, for example, Pt (film thickness about 20nm)/Ti (film thickness about 50nm)/Pt (film thickness about 50nm)/Au (film thickness about 200 nm).

The emitter 17 is disposed on the th contact layer 6. the emitter 17 is, for example, Mo (film thickness about 10nm)/Ti (film thickness about 5nm)/Pt (film thickness about 30nm)/Au (film thickness about 200 nm).

The protective film 57 is provided so as to cover the sub-collector layer 2, the collector layer 3, the base layer 4, the emitter layer 5, the th contact layer 6, and various electrodes, the collector connecting wiring 51a and the emitter connecting wiring 52a are provided on the protective film 57, the collector connecting wiring 51a is connected to the collector 15 through a through hole provided in the protective film 57, and the emitter connecting wiring 52a is connected to the emitter 17 through a through hole provided in the protective film 57.

An interlayer insulating film 58 is provided on a protective film 57 covering the collector connecting wiring 51a and the emitter connecting wiring 52a, an th emitter wiring 53a is provided on the interlayer insulating film 58, and an th emitter wiring 53a is connected to the emitter connecting wiring 52a through hole provided in the interlayer insulating film 58, whereby the th emitter wiring 53a is electrically connected to the emitter 17 through the emitter connecting wiring 52 a.

The protective film 57 and the interlayer insulating film 58 are, for example, sin, and the collector connecting wiring 51a, the emitter connecting wiring 52a, and the -th emitter wiring 53a are, for example, Au.

The th bump 61 is disposed on the th emitter line 53a through the lower metal layer 56a, the th bump 61 is a Cu pillar bump and is formed by an electric field plating method, the th bump 61 may be made of another metal material such as Au, and the lower metal layer 56a is, for example, Ti/Cu and is a plating seed electrode when forming the th bump 61.

Fig. 4 shows a layer structure of the second bipolar transistor 30. Note that the layer structure of the third bipolar transistor 40 is the same as that of the second bipolar transistor 30, and the description about the layer structure of the second bipolar transistor 30 can also be applied to the third bipolar transistor 40.

As shown in fig. 4, in the second bipolar transistor 30, similarly to the th bipolar transistor 20, the subcollector layer 2, the collector layer 3, the base layer 4, the emitter layer 5, the th contact layer 6, the collector 15, the base 16, and the collector connecting wiring 51a are provided on the th main surface S1 of the semiconductor substrate 1, and the channel stopper layer 7, the isolation layer 8, the emitter ballast resistor 88, the second contact layer 12, the third contact layer 13, and the fourth contact layer 14 are stacked in this order between the th contact layer 6 and the emitter 17.

The channel stopper layer 7 is provided on the th contact layer 6, the channel stopper layer 7 is an n-type semiconductor containing, for example, InGaP as a main component, the channel stopper layer 7 can be formed of InP with a molar ratio of about 0.48 and a Si doping concentration of about 5X 10¹⁸cm^－3The film thickness was about 3 nm.

The isolation layer 8 is disposed on the channel stopper layer 7. The spacer 8 is an n-type semiconductor containing GaAs as a main component, for example. The spacer layer 8 can be doped with Si to a concentration of about 3 x 10¹⁷cm^－3The film thickness was about 100 nm.

The emitter ballast resistor 88 has th, 10, and 11 th emitter ballast resistor layers 9, th, 10, and 11 laminated in this order on the isolation layer 8, and th, 10, and 11 th emitter ballast resistor layers are n-type semiconductors containing AlGaAs as a main component, respectively.

The th emitter ballast resistor layer 9 can be doped with Si at a concentration of about 1X 10¹⁷cm^－3Specifically, the AlAs molar ratio is 0 at the interface between the th emitter ballast resistor layer 9 and the spacer layer 8, and is about 0.33 at the interface between the th emitter ballast resistor layer 9 and the second emitter ballast resistor layer 10, and the AlAs molar ratio of the th emitter ballast resistor layer 9 is linearly changed.

The second emitter ballast resistor layer 10 can have an AlAs molar ratio of about 0.33 and a Si doping concentration of about 1 × 10¹⁷cm^－3The film thickness was about 200 nm.

The third emitter ballast resistor layer 11 can be doped with Si at a concentration of about 1 × 10¹⁷cm^－3Specifically, the AlAs molar ratio of the third emitter ballast resistor layer 11 is about 0.33 at the interface where the third emitter ballast resistor layer 11 meets the second contact layer 10, and is 0 at the interface where the third emitter ballast resistor layer 11 meets the second contact layer 12, the AlAs molar ratio of the third emitter ballast resistor layer 11 is linearly changed, and the emitter ballast resistor 88 has a higher specific resistance than the -th contact layer 6.The emitter ballast resistor 88 is not limited to being formed of 3 layers, and may be formed of, for example, 1 layer of the second emitter ballast resistor layer 10.

The second contact layer 12, the third contact layer 13, and the fourth contact layer 14 are laminated in this order on the third emitter ballast resistance layer 11. The second contact layer 12 is, for example, an n-type semiconductor containing GaAs as a main component. The second contact layer 12 can be doped with Si at a concentration of about 5X 10¹⁸cm^－3The film thickness was about 50 nm.

The third contact layer 13 is an n-type semiconductor containing InGaAs as a main component, for example. The third contact layer 13 can be doped with Si at a concentration of about 5X 10¹⁸cm^－3The film thickness was about 50 nm. The molar ratio of InAs in the third contact layer 13 increases as it approaches the fourth contact layer 14. Specifically, the molar ratio of InAs is 0 at the interface where the third contact layer 13 and the second contact layer 12 contact each other, and is about 0.5 at the interface where the third contact layer 13 and the fourth contact layer 14 contact each other. The InAs molar ratio of the third contact layer 13 is formed to vary linearly.

The fourth contact layer 14 is an n-type semiconductor containing InGaAs as a main component, for example. The fourth contact layer 14 can be InAs molar ratio of about 0.5, with a Si doping concentration of about 1 × 10¹⁹cm^－3The film thickness was about 50 nm.

The emitter 17 is disposed on the fourth contact layer 14. The protective film 57 is provided to cover the layers from the sub-collector layer 2 to the fourth contact layer 14 and the collector electrode 15, the base electrode 16, and the emitter electrode 17.

In the second bipolar transistor 30, as in the th bipolar transistor 20, the th emitter interconnection 53a is provided on the interlayer insulating film 58, the th emitter interconnection 53a is connected to the emitter connecting interconnection 52a via a through hole provided in the interlayer insulating film 58, and thus the th emitter interconnection 53a is electrically connected to the emitter 17 of the second bipolar transistor 30 via the emitter connecting interconnection 52 a.

As shown in fig. 3, the distance in the Z direction between the upper surface of the emitter layer 5 and the lower surface of the emitter 17 in the th bipolar transistor 20 is defined as the height hea, as shown in fig. 4, the distance in the Z direction between the upper surface of the emitter layer 5 and the lower surface of the emitter 17 in the second bipolar transistor 30 is defined as the second height heb, the second height HEb is higher than the height HEa, and the third bipolar transistor 40 also has the same second height HEb as the second bipolar transistor 30.

As shown in FIG. 2, in the th transistor group Qa, a plurality of th bipolar transistors 20 having a th height HEa and a plurality of second bipolar transistors 30 having a second height HEb are arranged in the X direction, th emitter wirings 53a are provided over the plurality of th bipolar transistors 20 and the plurality of second bipolar transistors 30 and are electrically connected to the respective emitters 17.

The th bump 61 is provided over the plurality of th bipolar transistors 20 and the plurality of second bipolar transistors 30 on the upper side of the th emitter wiring 53a the th bump 61 is provided along the th emitter wiring 53a, and has irregularities corresponding to a difference between the heights of the plurality of th bipolar transistors 20 and the heights of the plurality of second bipolar transistors 30.

Here, assuming that the distance in the Z direction between the second main surface S2 and the uppermost surface of the bump 61 is the maximum height Ha., in this embodiment, a passivation film 59 covering at least the side surfaces of the 0 th transistor group Qa is provided, and the bump 61 is also provided in a region partially overlapping with of the passivation film 59, in fig. 2, a distance between the upper surface of a portion of the bump 61 partially overlapping with of the passivation film 59 and the second main surface S2 is the maximum height Ha と, but when the passivation film 59 is not provided above the emitter wiring 53a, a distance between the upper surface of a portion of the bump 61 overlapping with the second bipolar transistor 30 and the second main surface S2 is the maximum height Ha.

In the second transistor group Qb, a plurality of third bipolar transistors 40 having a second height HEb are arranged in the X direction. The second emitter wiring 53b is provided over the plurality of third bipolar transistors 40, and is electrically connected to the emitters 17 of the third bipolar transistors 40 via the emitter connection wiring 52 b.

Second bump 62 is provided on the upper side of second emitter wiring 53b with lower metal layer 56b interposed therebetween, and is provided over a plurality of third bipolar transistors 40, second bump 62 is provided along second emitter wiring 53b, second bump 62 is a Cu pillar bump made of the same metal material as that of bump 61, and is formed by an electric field plating method, and second bump 62 may be made of another metal material such as Au.

Here, assuming that the distance in the Z direction between the second main surface S2 and the uppermost surface of the second bump 62 is the second maximum height Hb., in the present embodiment, the passivation film 59 is provided so as to cover at least the side surface of the second transistor group Qb, and the second bump 62 is also provided in a region overlapping with of the passivation film 59, in fig. 2, a second maximum height Hb. is provided between the upper surface of the portion of the second bump 62 overlapping with the portion of the passivation film 59 and the second main surface S2, but when the passivation film 59 is not provided on the upper side of the second emitter wiring 53b, a second maximum height Hb is provided between the upper surface of the portion of the second bump 62 overlapping with the third bipolar transistor 40 and the second main surface S2.

In the present embodiment, the th transistor group Qa has the plurality of th bipolar transistors 20 and the plurality of second bipolar transistors 30, and therefore, the 1 th maximum height Ha of the 0 th transistor group Qa and the second maximum height Hb of the second transistor group Qb are equal to each other, and therefore, when the semiconductor device 100 is mounted with the 2 th bump 61 and the second bump 62 facing the external substrate, at least a portion of the 3 th bump 61 having the th maximum height Ha is electrically connected, that is, at least a portion of the st bump 61 overlapping with the second bipolar transistor 30 is electrically connected to the external substrate, and the th bipolar transistor 20 having the th height HEa is electrically connected to the external substrate via the bump 61, and therefore, the semiconductor device 100 can suppress the occurrence of poor electrical connection when mounted to the external substrate, as compared to the case where the th transistor group Qa is constituted by only the plurality of th bipolar transistors 20 having the th height HEa.

As shown in fig. 5, in the th transistor group Qa, the bases (bases 16) of the th bipolar transistor 20 are connected to a common th base wiring 54a via a capacitor 86, the th base wiring 54a is connected to a base high-frequency input terminal 81a, the capacitor 86 is a capacitive element for cutting off a dc component, the bases (bases 16) of the th bipolar transistor 20 are connected to a common th base bias wiring 55a via a base ballast resistor 87, the th base bias wiring 55a is connected to a base bias terminal 82a, and the bases of the second bipolar transistor 30 are not connected to the th base wiring 54a and the th base bias wiring 55 a.

The emitters (emitters 17) of the th bipolar transistor 20 and the emitters (emitters 17) of the second bipolar transistor 30 are connected to the common emitter wiring line a and grounded.

The collector (collector 15) of the th bipolar transistor 20 is connected to a common th collector line 51c, the th collector line 51c is connected to the collector high-frequency output terminal 83a and the collector bias terminal 84a, and the collector (collector 15) of the second bipolar transistor 30 is not connected to the th collector line 51 c.

With this configuration, the plurality of th bipolar transistors 20 amplify the high-frequency signal input from the base high-frequency input terminal 81a and output the amplified signal to the collector high-frequency output terminal 83a, and the second bipolar transistor 30 is not connected to the base high-frequency input terminal 81a and the collector high-frequency output terminal 83a and does not operate as a transistor, and further, at least of the base and the collector of the second bipolar transistor 30 is not connected to the th base wiring 54a and the th collector wiring 51c, so the second bipolar transistor 30 does not operate and does not generate heat, and therefore the second bipolar transistor 30 is used as a space and can expect an effect of dispersing thermal deviation, which means that the difference δ between the heat of the transistors at the center and both ends is small, or that the second bipolar transistor 30 does not operate, and therefore, the effect of reducing the thermal resistance of the th transistor group Qa can be expected.

As shown in fig. 6, in the second transistor group Qb, each base (base 16) of the third bipolar transistor 40 is connected to a common second base wiring 54 b. The second base wiring 54b is connected to the base high-frequency input terminal 81b via a capacitor 85. The capacitor 85 is a capacitive element for cutting off a direct current component. Further, the bases (bases 16) of the third bipolar transistors 40 are connected to a common second base bias wiring 55 b. The second base bias wiring 55b is connected to the base bias terminal 82 b.

The emitters (emitters 17) of the third bipolar transistor 40 are connected to the common second emitter wiring 53b and grounded. Each collector (collector 15) of the third bipolar transistor 40 is connected to a common second collector wiring 51 d. Second collector wiring 51 is connected to collector high-frequency output terminal 83b and collector bias terminal 84 b.

With such a configuration, the plurality of third bipolar transistors 40 amplify the high-frequency signal input from the base high-frequency input terminal 81b and output the amplified signal to the collector high-frequency output terminal 83 b.

With the above configuration, in the semiconductor device 100, the plurality of th bipolar transistors 20 each having no emitter ballast resistor 88 and the third bipolar transistor 40 each having an emitter ballast resistor 88 are mounted on the same semiconductor substrate 1, the semiconductor device 100 can suppress breakdown of the transistors while securing the amplification characteristics of the transistors by switching the transistors (the th transistor group Qa or the second transistor group Qb) which operate in accordance with the collector voltage, specifically, the th bipolar transistor 20 having no emitter ballast resistor 88 is operated when the collector voltage ratio is low (for example, about 6V or less), and the third bipolar transistor 40 having the emitter ballast resistor 88 is operated when the collector voltage ratio is high (for example, about 6V or more), whereby the semiconductor device 100 maintains high power adding efficiency at both the time of low output power and the time of high output power and reliability is improved.

In addition, by providing the emitter ballast resistor 88 on the same semiconductor substrate 1 as the third bipolar transistor 40, it is possible to suppress occurrence of a problem such as partial thermal runaway due to a difference between the plurality of third bipolar transistors 40, as compared with a case where the emitter ballast resistor is provided outside the semiconductor device 100, and specifically, in the second transistor group Qb, the amount of current flowing through each third bipolar transistor 40 is not uniform, and the current concentrates on the third bipolar transistor 40 in the portion , in such a case, even if the emitter ballast resistor is provided outside the semiconductor device 100, the amount of current in the entire second transistor group Qb is suppressed, and the amount of current in the third bipolar transistor 40 in the portion cannot be effectively suppressed, and in addition , in the present embodiment, the emitter ballast resistor 88 is provided inside the semiconductor device 100 in each third bipolar transistor 40, and therefore, a large current that concentrates on the third bipolar transistor 40 in the portion can be effectively suppressed.

(method of manufacturing semiconductor device)

Fig. 7 is an explanatory view for explaining a method of manufacturing the semiconductor device according to embodiment , and as shown in fig. 7, a plurality of th bipolar transistors 20, a plurality of second bipolar transistors 30, and a plurality of third bipolar transistors 40 are formed on the th main surface S1 of the semiconductor substrate 1 (step ST 1).

Since a specific manufacturing method of forming the -th bipolar transistor 20 without the emitter ballast resistor 88, the second bipolar transistor 30 with the emitter ballast resistor 88, and the third bipolar transistor 40 on the same semiconductor substrate 1 is described in patent document 1, the description of patent document 1 is included in the present embodiment and omitted.

The passivation film 59 is provided over the th transistor group Qa and the second transistor group Qb, and an opening 59a is formed by photolithography and etching, and the th emitter wiring 53a and the second emitter wiring 53b are exposed in the opening 59 a.

Next, lower metal layer 56 and resist 71 are formed (step ST 2). lower metal layer 56 is formed by, for example, sputtering, lower metal layer 56 covers passivation film 59 and opening 59a and is formed on the surfaces of emitter wiring 53a and second emitter wiring 53 b. resist 71 is exposed and developed using a photomask after a resist layer is formed on the entire surface of lower metal layer 56, whereby resist 71 is provided in a region overlapping passivation film 59 and opening 71a is provided in a region overlapping emitter wiring 53a and second emitter wiring 53 b.

Next, th bumps 61 and second bumps 62 are formed by plating (step ST3), the th bumps 61 are formed over the plurality of th bipolar transistors 20 and the plurality of second bipolar transistors 30 are formed on the upper side of the th emitter wiring 53a, the second bumps 62 are formed over the plurality of third bipolar transistors 40 on the upper side of the second emitter wiring 53b, the plurality of th bumps 61 and second bumps 62 are formed by the same process, therefore, the height of the th bumps 61 is substantially equal to the height of the second bumps 62, further, the height of the th bumps 61 is the distance from the surface of the th emitter wiring 53a to the surface of the th bumps 61 in the Z direction, and the height of the second bumps 62 is the distance from the surface of the second emitter wiring 53b to the surface of the second bumps 62 in the Z direction.

In the -th bump 61, the height of the -th bump 61 provided in the upper portion of the -th bipolar transistor 20 and the height of the -th bump 61 provided in the upper portion of the second bipolar transistor 30 are substantially equal to each other, and the height of the -th bump 61 provided in the upper portion of the second bipolar transistor 30 and the height of the second bump 62 provided in the upper portion of the third bipolar transistor 40 are substantially equal to each other.

Next, the resist 71 is removed by etching, and the lower metal layer 56 of the portion where the -th bump 61 and the second bump 62 are not provided is removed by etching (step ST 4). by the above-described steps, the semiconductor device 100 is formed such that the -th maximum height Ha of the -th transistor group Qa is equal to the second maximum height Hb of the second transistor group Qb, and the manufacturing method shown in fig. 7 is merely examples, and the manufacturing method of the semiconductor device 100 is not limited thereto.

(modification of the embodiment )

Fig. 8 is a plan view of a semiconductor device according to a modification of the th embodiment, fig. 9 is a cross-sectional view taken along the line IX-IX' in fig. 8, fig. 10 is an equivalent circuit diagram of a th transistor group according to a modification of the th embodiment, and in a modification of the th embodiment, a configuration in which the th transistor group Qa is arranged differently from the th embodiment will be described.

As shown in fig. 8 and 9, in the semiconductor device 100A, the th transistor group Qa includes 6 th bipolar transistors 20 and 2 second bipolar transistors 30, the 6 th th bipolar transistors 20 are disposed between the 2 second bipolar transistors 30 in the X direction, and of the 2 second bipolar transistors 30, the -side second bipolar transistor 30 is disposed at a position farther from the second transistor group Qb than the -side bipolar transistor 20, and the -side second bipolar transistor 30 is disposed at a position closer to the second transistor group Qb than the -side bipolar transistor 20.

As shown in fig. 10, the th bipolar transistor 20 is connected to the th base interconnection 54a, the th base bias interconnection 55a, the th emitter interconnection 53a, and the th collector interconnection 51c, and functions as a transistor, the base of the second bipolar transistor 30 is not connected to the th base interconnection 54a and the th base bias interconnection 55a, respectively, and the collector of the second bipolar transistor 30 is not connected to the collector interconnection 51c, respectively, so that the second bipolar transistor 30 does not function as a transistor.

In the semiconductor device 100A of the present modification, the number of second bipolar transistors 30 is smaller than that in the th embodiment, and therefore, the th transistor group Qa can be downsized.

(second modification of embodiment )

Fig. 11 is a plan view of a semiconductor device according to a second modification example of the th embodiment, and a configuration in which second bipolar transistors 30 are provided in the second modification example of the th embodiment, unlike the th embodiment, will be described.

As shown in fig. 11, the second bipolar transistor 30 is provided at a position farther from the second transistor group Qb than the plurality of -th bipolar transistors 20 in the X direction, in other words, the plurality of -th bipolar transistors 20 are arranged between the second bipolar transistor 30 and the third bipolar transistor 40, and thus the -th transistor group Qa is not limited to the configuration having the plurality of second bipolar transistors 30, and may have at least or more second bipolar transistors 30, and in the semiconductor device 100B of the present modification, the maximum height Ha is equal to the second maximum height Hb even when second bipolar transistors 30 are provided.

( third modification of the embodiment)

Fig. 12 is a plan view of a semiconductor device according to a third modification example of the th embodiment, and in the third modification example of the th embodiment, a description is given of a configuration in which second bipolar transistors 30 are located at different positions, unlike the second modification example of the th embodiment.

As shown in fig. 12, in the semiconductor device 100B, second bipolar transistors 30 are located at the center in the X direction of the transistor group Qa, the second bipolar transistors 30 are provided between the th bipolar transistors 20 and the th bipolar transistors 20, 3 th bipolar transistors 20 are provided between the second bipolar transistors 30 and the second transistor group Qb, and 3 th bipolar transistors 20 are provided at a position farther from the second transistor group Qb than the second bipolar transistors 30.

The number of -th bipolar transistors 20 arranged on the side of the second bipolar transistor 30 may be different from the number of -th bipolar transistors 20 arranged on the side of the second bipolar transistor, the number of -th bipolar transistors 20 arranged between the second bipolar transistor 30 and the second transistor group Qb is preferably larger than the number of -th bipolar transistors 20 arranged at a position farther from the second transistor group Qb than the second bipolar transistor 30, and thus, the distance between the second bipolar transistor 30 having the maximum height Ha of the transistor group Qa and the second transistor group Qb is increased, so that the semiconductor device 100C can be stably mounted on an external substrate.

( fourth modification of the embodiment)

Fig. 13 is a plan view of a semiconductor device according to a fourth modification example of the th embodiment, and in a fourth modification example of the th embodiment, a description is given of a configuration in which each of the th transistor group Qa and the second transistor group Qb has a plurality of transistor rows, unlike the th embodiment.

As shown in fig. 13, the th transistor group Qa has a th transistor row Qas and a second transistor row Qat, the th transistor row Qas and the second transistor row Qat are disposed adjacently in the Y direction, the th transistor row Qas and the second transistor row Qat have a plurality of th bipolar transistors 20 and a plurality of second bipolar transistors 30 arranged in the X direction, respectively, and 3 th bipolar transistors 20 are disposed between 2 second bipolar transistors 30 in each of the th transistor row Qas and the second transistor row Qat.

The th bipolar transistor 20 of the th transistor array Qas and the second transistor array Qat is electrically connected to a common 0 th emitter line 53a, 1 th base line 54a, 2 th base bias line 55a, and th collector line 51c (see fig. 5), and the second bipolar transistors 30 of the th transistor array Qa., the th transistor array Qas, and the second transistor array Qat are configured such that at least the side of the base or the collector is not connected to the th base line 54a, the th base bias line 55a, and the th collector line 51 c.

The second transistor group Qb has an th transistor column Qbs and a second transistor column qbt. the th transistor column Qbs and the second transistor column Qbt are arranged adjacently in the Y direction, the th transistor column Qbs of the second transistor group Qb is arranged adjacently in the X direction to the th transistor column Qas of the th transistor group Qa, the second transistor column Qbt of the second transistor group Qb is arranged adjacently in the X direction to the second transistor column Qat of the th transistor group Qa, and the th transistor column Qbs and the second transistor column Qbt each have a plurality of third bipolar transistors 40 arranged in the X direction.

Even in the case where the semiconductor device 100D according to this modification includes the same number of transistors as in the th embodiment or a larger number of transistors than in the th embodiment, the lengths in the X direction of the th transistor group Qa and the second transistor group Qb can be shortened.

( fifth modification of the embodiment)

Fig. 14 is a plan view of a semiconductor device according to a fifth modification example of the embodiment , and in a fifth modification example of the embodiment , a description will be given of a configuration in which the -th transistor row Qas and the second transistor row Qat of the -th transistor group Qa have second bipolar transistors 30, respectively, unlike the fourth modification example of the .

As shown in fig. 14, in the semiconductor device 100E, the th transistor row Qas has a plurality of th bipolar transistors 20 and 0 second bipolar transistors 30. the second bipolar transistors 30 are provided at a position farther from the th transistor row Qbs of the second transistor group Qb than the plurality of th bipolar transistors 20 in the X direction, in other words, a plurality of th bipolar transistors 20 are arranged between the second bipolar transistors 30 and the th transistor row Qbs of the second transistor group Qb in the X direction, the second transistor row Qat is the same as the th transistor row Qas, in other words, in the th transistor row Qas and the second transistor row Qat, a plurality of th bipolar transistors 20 are arranged adjacent in the Y direction, and a plurality of second bipolar transistors 30 are arranged adjacent in the Y direction.

( sixth modification of the embodiment)

Fig. 15 is a plan view of a semiconductor device according to a sixth modification example of the embodiment , and in the sixth modification example of the embodiment , a description will be given of a configuration in which the th transistor array Qas and the second transistor array Qat of the th transistor group Qa have different arrangements, unlike the fifth modification example of the .

As shown in fig. 15, in the semiconductor device 100F, the th transistor row Qas has the same configuration as that in fig. 14, in the second transistor row Qat, second bipolar transistors 30 are disposed closer to the th transistor row Qbs of the second transistor group Qb than the 0 th bipolar transistors 20 in the X direction, in other words, second bipolar transistors 30 are disposed between the th transistor row Qbs and the th bipolar transistors 20 of the second transistor group Qb in the X direction, the second bipolar transistors 30 of the th transistor row Qas are disposed adjacent to the th bipolar transistors 20 of the second transistor row Qat in the Y direction, and the second bipolar transistors 30 of the second transistor row Qat and the th bipolar transistors 20 of the th transistor row Qas are disposed adjacent to each other in the Y direction.

As described above, the semiconductor devices 100, 100A to 100F according to the present embodiment include the semiconductor substrate 1, the plurality of -th bipolar transistors 20, the second bipolar transistors 30 of at least and more, and the 0 bumps 61, the 1-th bipolar transistor 20 is provided on the side of the second 2 main surface S1 of the semiconductor substrate 1, the second bipolar transistor 30 is provided on the side of the -th main surface S1 of the semiconductor substrate 1 with the -th height hea between the emitter layer 5 and the emitter 17 in the direction perpendicular to the -th main surface S1, and the plurality of -th bipolar transistors 20 and the second bipolar transistors 30 of at least are provided over the second bumps 61, the second height heb being higher than the -th height HEa between the emitter layer 5 and the emitter 17 in the direction perpendicular to the -th main surface S1.

Thus, when the bump 61 is opposed to the external substrate and the semiconductor device 100 is mounted, at least the portion of the bump 61 overlapping the second bipolar transistor 30 is electrically connected to the external substrate, whereby the th bipolar transistor 20 having the th height HEa is electrically connected to the external substrate via the bump 61, and therefore, the occurrence of an electrical connection failure can be suppressed when the semiconductor device 100 is mounted on the external substrate.

The semiconductor devices 100 and 100A to 100F according to the present embodiment each include the third bipolar transistor 40 and the second bump 62, the third bipolar transistor 40 is provided on the th main surface S1 side of the semiconductor substrate 1, and the second bump 62 is disposed over the plurality of third bipolar transistors 40 with the second height heb between the emitter layer 5 and the emitter 17 in the direction perpendicular to the th main surface S1.

Thus, the third bipolar transistor 40 has the same maximum height as the second bipolar transistor 30, and the semiconductor device 100 can suppress the occurrence of electrical connection failure when mounted on an external substrate, as compared with the case where the transistor group Qa is configured only by the plurality of -th bipolar transistors 20 having the -th height HEa.

In the semiconductor devices 100 and 100A to 100F according to the present embodiment, the -th bipolar transistor 20 is disposed between the second bipolar transistor 30 and the third bipolar transistor 40 in the direction (X direction) parallel to the -th main surface S1 of the semiconductor substrate 1.

Accordingly, the distance between the second bipolar transistor 30 having the th maximum height Ha of the th transistor group Qa and the third bipolar transistor 40 of the second transistor group Qb is increased, and therefore the semiconductor device 100C can be stably mounted on an external substrate.

In the semiconductor devices 100 and 100A to 100F according to the present embodiment, the th bipolar transistor 20, the second bipolar transistor 30, and the third bipolar transistor 40 are heterojunction bipolar transistors.

Thus, the th transistor group Qa and the second transistor group Qb function as amplifier elements, and are excellent in power addition efficiency and linearity.

In the semiconductor devices 100 and 100A to 100F of the present embodiment, the -th bump 61 and the second bump 62 are pillar bumps.

Thus, the semiconductor device 100 is mounted on the external substrate by flip-chip mounting, and the connection pads of the external substrate and the stud bumps can be connected well.

In the semiconductor devices 100, 100A to 100F according to the present embodiment, the third bipolar transistor 40 has a resistive layer (emitter ballast resistor 88) between the emitter layer 5 and the emitter 17.

Thus, the th transistor group Qa is formed by the th bipolar transistor 20 having no resistive layer, and the second transistor group Qb is formed by the third bipolar transistor 40 having a resistive layer, the semiconductor device 100 can be operated by switching the th transistor group Qa and the second transistor group Qb in accordance with the collector voltage, and therefore, the semiconductor device 100 can maintain high power addition efficiency at both the time of low output power and the time of high output power.

In the semiconductor devices 100, 100A to 100F according to the present embodiment, the second bipolar transistor 30 has a resistive layer (emitter ballast resistor 88) between the emitter layer 5 and the emitter 17.

Thus, the maximum height Ha of the th transistor group Qa can be formed to be the same height as the second maximum height Hb of the second transistor group Qb.

In the semiconductor devices 100, 100A to 100F of the present embodiment, the resistive layers of the second bipolar transistor 30 and the third bipolar transistor 40 have AlGaAs as a main component.

This allows the resistance value of the resistive layer of the third bipolar transistor 40 to be set to a desired value. The resistive layers of the second bipolar transistor 30 and the third bipolar transistor 40 can be formed in the same process, and the second height HEb of the second bipolar transistor 30 can be formed to be the same as the second height HEb of the third bipolar transistor 40.

In the semiconductor devices 100, 100A to 100F according to the present embodiment, the bases 16 of the th bipolar transistors 20 are electrically connected to the common th base interconnection 54a, the collectors 15 of the th bipolar transistors 20 are electrically connected to the common th collector interconnection 51c, and at least sides of the base 16 and the collector 15 of the second bipolar transistor 30 are not connected to the th base interconnection 54a and the th collector interconnection 51 c.

Thus, in the th transistor group Qa, the th bipolar transistors 20 function as transistors, and the second bipolar transistor 30 does not function as a transistor.

In the semiconductor devices 100 and 100A to 100F according to the present embodiment, the emitters 17 of the th bipolar transistor 20 and the second bipolar transistor 30 are electrically connected to the common emitter line 53a, the emitters 17 of the third bipolar transistors 40 are electrically connected to the common second emitter line 53b, the th bump 61 is provided on the th emitter line 53a along the th emitter line 53a, and the second bump 62 is provided on the second emitter line 53b along the second emitter line 53 b.

Accordingly, irregularities corresponding to the th height HEa of the th bipolar transistor 20 and the second height HEb of the second bipolar transistor 30 are formed in the th bump 61. the portion of the th bump 61 where the second bipolar transistor 30 is disposed has the th maximum height Ha., and thus the th maximum height Ha of the first transistor group Qa and the second maximum height Hb of the second transistor group Qb are equal to each other.

(second embodiment)

Fig. 16 is a plan view of the semiconductor device according to the second embodiment, fig. 17 is a cross-sectional view taken along line XVII-XVII' in fig. 16, fig. 18 is an equivalent circuit diagram of the semiconductor device according to the second embodiment, and a configuration in which bumps 63 are provided in the transistor group Qa and the second transistor group Qb, unlike the embodiment, will be described in the second embodiment.

As shown in fig. 16, the plurality of th bipolar transistors 20 and the plurality of second bipolar transistors 30 are alternately arranged in the X direction parallel to the th main surface S1 of the semiconductor substrate 1, the th transistor group Qa has the plurality of th bipolar transistors 20, and the second transistor group Qb has the plurality of second bipolar transistors 30.

As shown in fig. 17, the emitter wiring 53, the lower metal layer 56, and the bump 63 are provided over the plurality of th bipolar transistors 20 and the plurality of second bipolar transistors 30, the emitter wiring 53 is electrically connected to the emitters 17 of the plurality of th bipolar transistors 20 and the emitters 17 of the plurality of second bipolar transistors 30, the lower metal layer 56 is provided on the emitter wiring 53, the bump 63 is provided on the lower metal layer 56, and the bump 63 is provided on the upper side of the emitter wiring 53 along the emitter wiring 53.

The isolation region 50 is disposed between the th bipolar transistor 20 and the second bipolar transistor 30, respectively, the collector 15 is disposed corresponding to each of the th bipolar transistor 20 and the second bipolar transistor 30, in other words, the collector 15 is not shared by the th bipolar transistor 20 and the second bipolar transistor 30.

As shown in fig. 18, the emitters (emitters 17) of the th bipolar transistor 20 and the emitters (emitters 17) of the second bipolar transistor 30 are connected to the common emitter wiring 53 and grounded.

In the th transistor group Qa, the bases (bases 16) of the th bipolar transistors 20 are connected to a common th base interconnection 54a via a capacitor 86, the bases (bases 16) of the th bipolar transistors 20 are connected to a common th base bias interconnection 55a via a base ballast resistor 87, and the collectors (collectors 15) of the th bipolar transistors 20 are connected to a common th collector interconnection 51 c.

In the second transistor group Qb, the bases (bases 16) of the plurality of second bipolar transistors 30 are connected to a common second base wiring 54 b. The second base wiring 54b is connected to the base high-frequency input terminal 81b via a capacitor 85. The bases (bases 16) of the second bipolar transistors 30 are connected to a common second base bias wiring 55 b. Each collector (collector 15) of the second bipolar transistor 30 is connected to a common second collector wiring 51 d.

With this configuration, the plurality of bipolar transistors 20 constituting the th transistor group Qa amplify the high-frequency signal input from the base high-frequency input terminal 81a and output the amplified signal to the collector high-frequency output terminal 83a, and the second bipolar transistor 30 constituting the second transistor group Qb amplifies the high-frequency signal input from the base high-frequency input terminal 81b and outputs the amplified signal to the collector high-frequency output terminal 83 b.

As described above, in the semiconductor device 100G of the present embodiment, the plurality of bipolar transistors 20 constituting the th transistor group Qa and the plurality of second bipolar transistors 30 constituting the second transistor group Qb are alternately provided, and the common bump 63 is provided over the plurality of th bipolar transistors 20 and the plurality of second bipolar transistors 30.

In the semiconductor device 100G of the present embodiment, the height from the second main surface S2 to the uppermost surface of the bump 63 on the transistor group Qa and the height from the second main surface S2 to the uppermost surface of the bump 63 on the second transistor group Qb are different from each other in this case, when the semiconductor device 100G is mounted on an external substrate, the transistor group Qa and the second transistor group Qb are electrically connected to the external substrate via the common bump 63.

(third embodiment)

Fig. 19 is a cross-sectional view of a semiconductor device according to a third embodiment, and a structure in which solder layers 65a and 65b are provided on a th bump 61 and a second bump 62, respectively, will be described in the third embodiment, unlike the th embodiment and the second embodiment.

As shown in fig. 19, the solder layer 65a extends over the plurality of th bipolar transistors 20 and the plurality of second bipolar transistors 30 are provided on the th bump 61, and the solder layer 65b extends over the plurality of third bipolar transistors 40 and is provided on the second bump 62, whereby, when the semiconductor device 100H is mounted on an external substrate, the solder layers 65a, 65b are mounted so as to be in contact with the connection pads of the external substrate, and the th bump 61 and the second bump 62 are bonded to the connection pads via the solder layers 65a, 65b by solder reflow processing or the like.

The configuration of the present embodiment can be applied to the semiconductor devices 100 and 100A to 100G of the th embodiment and the second embodiment.

(fourth embodiment)

Fig. 20 is a sectional view of a power amplifier module according to the fourth embodiment. Fig. 21 is a block diagram showing a configuration of a power amplifier module according to the fourth embodiment. The power amplifier module 200 includes a module substrate 210, a semiconductor device 100, and a resin layer 240.

The module substrate 210 includes -th lands 220, through vias 211, second lands 212, and wiring provided in an inner layer of the substrate, the -th lands 220 are terminals for mounting the semiconductor device 100, the second lands 212 are terminals to which a reference potential is supplied, and the -th lands 220 and the second lands 212 are connected by the plurality of through vias 211.

The semiconductor device 100 is Flip-chip mounted on the module substrate 210, the th bump 61 and the second bump 62 are connected to the th pad 220 via solder 230, respectively, whereby the th transistor group Qa and the second transistor group Qb are electrically connected to the module substrate 210, and the resin layer 240 is provided on the module substrate 210 covering the semiconductor device 100.

As shown in fig. 21, the power amplifier module 200 has an th signal chain Sc1 and a second signal chain Sc 2.

A th signal chain Sc1 is a path through which a th high frequency signal flows, and has a th input terminal 91a, a th input matching circuit 93a, a th primary amplification circuit 96a, a th interstage matching circuit 94a, a th output stage amplification circuit 97a, a th output matching circuit 95a, and a th output terminal 92 a. a th input matching circuit 93a is a circuit that matches the impedance of the input side of the th primary amplification circuit 96 a. the 82639 interstage matching circuit 94a is a circuit that matches the impedance between the output side of the th primary amplification circuit 96a and the input side of the 592 th output stage amplification circuit 97 a. the th output matching circuit 95a is a circuit that matches the impedance of the output side of the th output stage amplification circuit 97 a. the th input matching circuit 93a, the th interstage matching circuit 94a, and the th output matching circuit 95a are constituted by respective high frequency signal input matching circuits, such as a and a th input and output amplification circuit a, and is constituted by respective high frequency signal input matching circuits a and a , and a is constituted by a, respectively.

The second signal chain Sc2 is a path through which a second high-frequency signal flows, and has a second input terminal 91b, a second input matching circuit 93b, a second primary amplification circuit 96b, a second inter-stage matching circuit 94b, a second output stage amplification circuit 97b, a second output matching circuit 95b, and a second output terminal 92 b. the second input matching circuit 93b, the second inter-stage matching circuit 94b, and the second output matching circuit 95b are circuits having the same functions as the input matching circuit 93a, the inter-stage matching circuit 94a, and the output matching circuit 95a, respectively.

The th signal chain Sc1 and the second signal chain Sc2 are not electrically operated at the same time but are operated separately in time, that is, the second signal chain Sc2 is electrically stopped during the period when the th signal chain Sc1 is electrically operated, the th signal chain Sc1 is electrically stopped during the period when the second signal chain Sc2 is electrically operated, and thus the th signal chain Sc1 or the second signal chain Sc2 is operated according to each of the low output power and the high output power, and a good power addition efficiency can be maintained.

Description of the reference numerals

1 semiconductor substrate 1 …, 2 … sub-collector layer, 3 … collector layer, 4 … base layer, 5 … emitter layer, 9 … first emitter ballast layer, 10 … second emitter ballast layer, 11 … third emitter ballast layer, 15 … collector, 16 … base, 17 … emitter, 20 … second … bipolar transistor, 30 … second bipolar transistor, 40 … third bipolar transistor, 51a … collector connecting wiring, 51c … first main surface … collector wiring, 51d … second collector wiring, 52a, 52b, emitter connecting wiring, 53 … emitter wiring, 53a … first … emitter wiring, 53b … second emitter wiring, 54a … first base wiring, 54b … second base wiring, … first … bump, 62 … second bump, 63 bump 88 emitter wiring, … emitter wiring, 36100 power amplifier semiconductor device …, … power amplifier circuit …, … maximum height …, … Haqqqhb power amplifier circuit ….