阅读说明：本技术 一种提高转换速度的电平转换电路及电子设备 (level conversion circuit for increasing conversion speed and electronic equipment ) 是由 刘丽 苗小雨 于 2019-10-18 设计创作，主要内容包括：本发明涉及电子电路技术领域,尤其涉及一种高速电平转换电路及电子设备。一种高速电平转换电路及电子设备,包括：两个NMOS管组成的下拉电路,用于在输入电压后下拉电压至零电平；一个反相器将输入电压进行反相；一个恒定阻值的电阻R,一个恒定电流的电流源I,用于产生一个恒定电压,当输入电平为低电平时,经过反相器反相后的电压与该恒定电压值相同；一个PMOS管,用于将电压上拉至高电平；一个电容C,借助电容的耦合作用使经过NMOS管后的输出电压快速变换。该电路相比现有技术具有结构简单、并且能显著的提升转换速度的优点。(The invention relates to the technical field of electronic circuits, in particular to high-speed level conversion circuits and electronic equipment, wherein each high-speed level conversion circuit comprises a pull-down circuit consisting of two NMOS (N-channel metal oxide semiconductor) tubes, a inverter, resistors R with constant resistance, current sources I with constant current, and used for generating constant voltages, when the input level is low, the voltage after inversion of the inverter is the same as the constant voltage, PMOS tubes used for pulling the voltage to high, and capacitors C used for rapidly converting the output voltage after passing through the NMOS tubes by virtue of the coupling effect of the capacitors.)

1, level conversion circuit for increasing conversion speed, wherein the level conversion circuit comprises an input signal terminal, an output signal terminal, an inverter, a NMOS transistor, a second NMOS transistor, a constant current source, an impedance, a capacitor, and a PMOS transistor;

the gate of the NMOS transistor is connected to the input signal terminal, the source is grounded, and the drain is connected to the terminal of the impedance through the constant current source;

the grid electrode of the second NMOS transistor is connected with the input signal through the reverser, the source electrode of the second NMOS transistor is grounded, and the drain electrode of the second NMOS transistor is connected with the source electrode of the PMOS transistor in common and is simultaneously connected to the output signal end;

the th end of the impedance is connected with the gate of the PMOS transistor in common, and the th end of the impedance is also connected to the gate of the second NMOS transistor through the capacitor;

the second end of the impedance and the drain of the PMOS transistor are connected to high level;

when the input signal of the input signal end is low level signal, the output signal end outputs low level;

when the input signal of the input signal end is high level signal, the output signal end outputs high level.

2. The circuit of claim 1, wherein the low level of the output signal terminal is zero level when the input signal terminal input signal is low level signal, and the high level of the output signal terminal output is high level when the input signal terminal input signal is high level signal.

3. The circuit of claim 1, wherein the impedance resistor is R, the constant current source current is I, the th high level voltage is V, the voltage at the gate of the second NMOS transistor is VL when the input is low, and VL R I and V-R I are voltages capable of turning on the PMOS transistor.

4. The circuit of claim 1, wherein the impedance is a constant impedance that does not vary with current.

5. The circuit of claim 1, wherein the low level signal inputted from the input signal terminal is a ground voltage level.

6. The circuit of claim 1, wherein the high level signal inputted from the input signal terminal is a signal with a voltage greater than or equal to 1.5V.

7. The circuit of claim 1, wherein the channel width ratio of the NMOS transistor to the second NMOS transistor is 1: 1.

8. The improved slew rate level shifter of claim 1 wherein the channel width ratio of the PMOS transistor to the NMOS transistor is anywhere from 2.5 to 3 to .

9. The circuit of claim 1, wherein the channel width ratio of the PMOS transistor to the second NMOS transistor is any ratio between 2.5 and 3.

10, electronic equipment, characterized in that level shifting is performed using the level shifting circuit of any of claims 1-9 and .

Technical Field

The present invention relates to the field of electronic circuit technology, and in particular, to high-speed level shift circuits and electronic devices.

Background

In the design and development of electronic circuits, with the introduction of low-voltage logic, the problem of inconsistent input/output logic often occurs inside a system, so that the complexity of system design is increased. For example, when a 1.5V digital circuit communicates with an analog circuit operating at 3.3V, the problem of the conversion of two levels needs to be solved first, which requires a level conversion circuit.

FIG. 1 shows a level shifting structure commonly used at present, as shown IN FIG. 1, the circuit includes 2 PMOS transistors P1 and P2, two NMOS transistors N1 and N2, and inverters INV. P1 and P2 constituting a pull-up circuit, and N1 and N2 constituting a pull-down circuit, when the input is low, N1 is turned off, N2 is turned on, the B point voltage is pulled down to zero level, Vout outputs zero level, when the input is high, N1 is turned on, the A point voltage is pulled down to zero level, P2 is turned on, the B point voltage is pulled up to 5V, Vout outputs 5V, but when the input is low, Vout output is zero level, which acts on P1 IN reverse, causing P1 to be turned on, the A point voltage is pulled up to 5V, when the IN input is high, N1 is turned on, the A point voltage is pulled down to zero level, P1 competes with N2, when A point voltage is pulled down to zero level, which affects , and the speed of the shift is changed over time.

Disclosure of Invention

The invention provides new level conversion structure circuits aiming at the problem of slow circuit conversion speed, and the new circuit structure comprises a pull-down circuit consisting of two NMOS tubes, a resistor R with constant resistance values, a current source I with constant currents, a capacitor C and a capacitor C, wherein the pull-down circuit is used for pulling down the voltage to a zero level after the input voltage, the resistor R with inverters are used for inverting the input voltage, the resistor R with constant resistance values is used for generating constant voltages, when the input voltage is a low level, the voltage after the inversion of the inverters is the same as the constant voltage value, the PMOS tubes are used for pulling the voltage to a high level, and the capacitors C are used for quickly converting the output voltage after the NMOS tubes by means of the coupling effect of the capacitors.

The circuit has the advantages of simple structure and capability of obviously improving the conversion speed.

Drawings

FIG. 1 is a level shifting architecture that is currently in common use;

FIG. 2 is level shifting structures provided by the present invention;

FIG. 3 is a comparison waveform of simulation of the present invention and the prior art.

Detailed Description

As described in the background section, in the prior art, the circuit conversion speed is slow due to the competition relationship between PMOS and NMOS in the level conversion process, and the invention provides level conversion circuits to improve the conversion speed.

In embodiments, the level shifter circuit comprises an input signal terminal, an output signal terminal, an inverter, a NMOS transistor, a second NMOS transistor, a constant current source, an impedance, a capacitor, and a PMOS transistor, wherein the NMOS transistor has a gate connected to the input signal terminal, a source connected to ground, and a drain connected to the terminal of the impedance via the constant current source, the second NMOS transistor has a gate connected to the input signal terminal through the inverter, a source connected to ground, a drain connected to the source of the PMOS transistor in common and to the output signal terminal, the impedance terminal is connected to the gate of the PMOS transistor in common, the impedance terminal is further connected to the gate of the second NMOS transistor through the capacitor, and the impedance second terminal and the drain of the PMOS transistor are connected to a high level.

The output signal end outputs low level when the input signal of the input signal end is low level signal, and outputs high level when the input signal of the input signal end is high level signal.

In the embodiment, the constant power supply and the constant impedance generate constant voltage, and the constant power supply and the constant impedance are matched with the capacitor, so that the output voltage after passing through the NMOS tube is quickly converted, and the technical effect of remarkably improving the conversion speed can be achieved.

In embodiments, the output signal terminal outputs a low level of zero when the input signal is low level signal, and outputs a high level of high level when the input signal is high level signal.

In , the constant current source current is I, the th high level voltage is V, the voltage at the gate of the second NMOS transistor is VL when the input is low, and VL-R I and V-R I are voltages that can turn on the PMOS transistor.

In embodiments, the impedance is a constant impedance that does not vary with current.

In embodiments, the low level signal inputted from the input signal terminal is a ground voltage level.

In embodiments, the high level signal inputted from the input signal terminal is a signal with a voltage greater than or equal to 1.5V.

In embodiments, the channel width ratio of the NMOS transistor to the second NMOS transistor is 1: 1.

In embodiments, the channel width ratio of the PMOS transistor to the NMOS transistor is any ratio between 2.5 and 3.

In embodiments, the channel width ratio of the PMOS transistor to the second NMOS transistor is any ratio between 2.5 and 3.

To further illustrate the level shifter of the present invention, specific working examples thereof are given in conjunction with fig. 2.

As shown IN fig. 2, when the input signal IN is at zero level and at high level 5V, the NMOS transistor N1 is turned off, the voltage at point D is at 5V, P1 is turned off, the voltage at point E is at high level VL, N2 is turned on, the voltage at point B is pulled down to zero level, and Vout output is at zero level, and when the input signal IN is at 1.5V, point E is at zero level, the voltage at point E is changed to VL, N1 is turned on, and the values of R and I are set so that I x R becomes VL, the voltage at point D can be instantaneously changed to 5 VL due to the coupling effect of the capacitor C, point P1 is turned on, point B is pulled up to 5V, and the voltage at point E is at zero level, and N2 is turned off, so Vout output is at 5V.

Fig. 3 is a comparison diagram of two simulated waveforms of the prior art embodiment shown IN fig. 1 and the present application embodiment shown IN fig. 2, the three waveforms are, from top to bottom, the th waveform, the second waveform and the third waveform, the st waveform represents the input IN, the second waveform represents the output Vout of the circuit structure of fig. 2, and the third waveform represents the output Vout of the circuit structure of fig. 1.

In another embodiments, the level shift circuit disclosed in the present invention can also be applied to electronic devices to implement a level shift function.

The above description is only an alternative embodiment of the present disclosure and is not intended to limit the embodiments of the present disclosure, and various modifications and changes may be made to the embodiments of the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, combination and the like made within the spirit and principle of the embodiments of the present disclosure should be included in the scope of protection of the embodiments of the present disclosure.