Memory system and method for accessing memory system
阅读说明：本技术 存储器系统以及用于访问存储器系统的方法 (Memory system and method for accessing memory system ) 是由 蒋逸波 严钢 R·X·金 金立之 尤立中 于 2019-06-19 设计创作，主要内容包括：本申请提供了一种存储器系统及用于访问存储器系统的方法,存储器系统包括：第一多个存储器组；第二多个本地控制器,每个本地控制器耦接在一个或多个存储器组与存储器控制器之间；存储器控制器被配置为从第一多个片选CS信号中向目标本地控制器提供目标访问CS信号,目标访问CS信号允许对耦接到目标本地控制器的第一多个存储器组中的目标存储器组进行目标访问,并且存储器控制器还被配置为晚于目标访问CS信号向第二多个本地控制器提供命令地址CA信号,CA信号用于寻址并访问目标存储器组中的多个存储单元。(The present application provides a memory system and a method for accessing the memory system, the memory system including: a first plurality of memory banks; a second plurality of local controllers, each local controller coupled between one or more memory banks and a memory controller; the memory controller is configured to provide a target access CS signal from the first plurality of chip select CS signals to a target local controller, the target access CS signal allowing target access to a target memory bank of the first plurality of memory banks coupled to the target local controller, and the memory controller is further configured to provide a command address CA signal to the second plurality of local controllers later than the target access CS signal, the CA signal for addressing and accessing a plurality of memory cells in the target memory bank.)
1. A memory system, comprising:
a first plurality of memory banks, each of the memory banks having a plurality of memory cells;
a second plurality of local controllers, each coupled between one or more of the first plurality of memory banks and a memory controller;
the memory controller is configured to provide a target access CS signal from a first plurality of chip select CS signals to a target local controller of the second plurality of local controllers, the target access CS signal allowing target access to a target memory bank of the first plurality of memory banks coupled to the target local controller, and the memory controller is further configured to provide a command address, CA, signal to the second plurality of local controllers later than the target access CS signal, the command address signal for addressing and accessing a plurality of memory cells of the target memory bank; and
wherein the target local controller is configured to generate a target CA on-die termination (ODT) instruction in response to receiving the target access CS signal, the target CA ODT instruction to turn on a target CA ODT at a CA input of the target local controller at least for a period of time that the CA signal is received from the memory controller.
2. The memory system of claim 1, wherein each local controller is coupled to two memory banks of the first plurality of memory banks, and wherein the target local controller is configured to generate the target CA ODT instruction when either or both of the two memory banks are allowed for target access.
3. The memory system of claim 1, wherein the target local controller receives the CA signal N clock cycles later than the target access CS signal to allow the target CAODT instruction to be generated before receiving the CA signal, where N is a positive integer.
4. The memory system of claim 3, wherein N is a programmable value.
5. The memory system of claim 1, wherein the target CA ODT instruction turns on the target CA ODT at the CA input of the target local controller from a setup time before receiving a CA signal until a hold time after receiving a CA signal.
6. The memory system of claim 1, wherein the memory controller is further configured to provide non-target local controllers of the second plurality of local controllers with non-target access CS signals of the first plurality of CS signals that inhibit target access to all non-target memory banks of the first plurality of memory banks coupled to the non-target local controllers;
wherein the non-target local controller is configured to generate a non-target CA ODT instruction in response to receiving the non-target access CS signal, the non-target CA ODT instruction to turn on a non-target CA ODT at a CA input of a non-target local controller at least for a period of time that the CA signal is received from the memory controller.
7. The memory system of claim 1, wherein the memory system comprises the memory controller.
8. The memory system of claim 1, further comprising a second plurality of Registered Clock Drivers (RCDs), and wherein each of the second plurality of local controllers is integrated in one of the second plurality of RCDs.
9. The memory system of claim 1, wherein each of the second plurality of local controllers is integrated into one of the first plurality of memory banks.
10. A memory controller for a memory system, the memory system comprising a first plurality of memory banks each having a plurality of memory cells and a second plurality of local controllers, each local controller coupled between one or more of the first plurality of memory banks and the memory controller, wherein the memory controller is configured to perform the steps of:
providing a target local controller of the second plurality of local controllers with a target access CS signal of a first plurality of CS signals, the target access CS signal allowing target access to a target memory bank of the first plurality of memory banks coupled to the target local controller; and
providing CA signals to the second plurality of local controllers later than the target access CS signals, the CA signals for addressing and accessing a plurality of memory cells in the target memory bank.
11. The memory controller of claim 10, wherein the CA signal is provided to the target local controller N clock cycles later than the target access CA signal to allow the target local controller to generate a target CA ODT instruction that turns on the target CA ODT at a CA input of the target local controller at least a period of time that the CA signal is received, where N is a positive integer.
12. A method for accessing a memory system by a memory controller, the memory system comprising a first plurality of memory banks and a second plurality of local controllers, wherein each memory bank has a plurality of memory cells, each local controller being coupled between one or more memory banks of the first plurality of memory banks and the memory controller, the method comprising:
providing a target access CS signal from the memory controller to a target local controller of the second plurality of local controllers from a first plurality of chip select CS signals, the target access CS signal allowing target access to a target memory bank of the first plurality of memory banks coupled to the target local controller;
in response to the target local controller receiving the target access CS signal, generating, by the target local controller, a target CA ODT instruction that turns on a target CA ODT at a CA input of the target local controller; and
providing command address, CA, signals from the memory controller to the second plurality of local controllers, later than the target access CS signals, the CA signals for addressing and accessing a plurality of memory cells in the target memory bank;
wherein the target CA ODT at the CA input of the target local controller is turned on by the target CA ODT instruction at least for a period of time that the CA signal is received from the memory controller.
13. The method of claim 12, wherein each local controller is coupled to two memory banks of the first plurality of memory banks, and wherein the target CA ODT instruction is generated by the target local controller when either or both of the two memory banks are allowed for target access.
14. The method of claim 12, wherein the CA signal is provided from the memory controller to the second plurality of local controllers N clock cycles later than the target access CS signal to allow the target CA ODT instruction to be generated by the target local controller before receiving the CA signal, where N is a positive integer.
15. The method of claim 14, wherein N is a programmable value.
16. The method of claim 12, wherein the target CA ODT at the CA input of the target local controller is turned on by the target CA ODT instruction from a setup time before the target local controller receives a CA signal until a hold time after the target local controller receives the CA signal.
17. The method of claim 12, further comprising:
providing, from the memory controller to a non-target local controller of the second plurality of local controllers, a non-target access CS signal of the first plurality of CS signals that inhibits target access to all non-target memory banks of the first plurality of memory banks coupled to the non-target local controller; and
in response to the non-target local controller receiving the non-target access CS signal, generating, by the non-target local controller, a non-target CA ODT instruction that turns on non-target CA ODT at a CA input of the non-target local controller at least for a period of time that the non-target local controller receives the CA signal.
18. The method of claim 12, wherein the memory system further comprises a second plurality of Registered Clock Driver (RCDs), and wherein each of the second plurality of local controllers is integrated into one of the second plurality of RCDs.
19. The method of claim 12, wherein each of the second plurality of local controllers is integrated into one of the first plurality of memory banks.
Technical Field
The present application relates to memory technology, and more particularly, to a memory system and a method for accessing a memory system.
Background
On-Die Termination (ODT) technology is a technology in which a Termination resistor is provided On a semiconductor chip, wherein the Termination resistor is used for impedance matching On a transmission line. ODT can reduce signal reflections caused by the transmission of signals along stubs (stub lines) that connect the memory controller to devices on the memory card, such as Dynamic Random Access (DRAM) memory modules, thereby reducing unwanted noise introduced on these signals.
With the ever-increasing operating frequency of memory systems, ODT technology has been used in memory modules such as DDR5 synchronous dram (sdram) modules. For example, an ODT termination resistance may be selectively coupled to a command/address (CA) bus line to turn termination of the CA bus line on or off to improve signal integrity thereof.
However, there is a need to further improve existing memory systems.
Disclosure of Invention
It is an object of the present application to provide a dynamic ODT mechanism for a memory system for improving the performance of receiving CA signals.
In one aspect of the present application, there is provided a memory system including: a first plurality of memory banks, each of the memory banks having a plurality of memory cells; a second plurality of local controllers, each coupled between one or more of the first plurality of memory banks and a memory controller; the memory controller is configured to provide a target access CS signal from a first plurality of chip select CS signals to a target local controller of the second plurality of local controllers, the target access CS signal allowing target access to a target memory bank of the first plurality of memory banks coupled to the target local controller, and the memory controller is further configured to provide a command address, CA, signal to the second plurality of local controllers later than the target access CS signal, the command address signal for addressing and accessing a plurality of memory cells of the target memory bank; and wherein the target local controller is configured to generate a target CA on-die termination, ODT, instruction in response to receiving the target access CS signal, the target CA ODT instruction to turn on a target CAODT at a CA input of the target local controller at least for a period of time that the CA signal is received from the memory controller.
In some embodiments, each local controller is coupled to two memory banks of the first plurality of memory banks, and the target local controller is configured to generate the target CA ODT instruction when either or both of the two memory banks are allowed for target access.
In some embodiments, the target local controller receives the CA signal N clock cycles later than the target access CS signal to allow the target CA ODT instruction to be generated before receiving the CA signal, where N is a positive integer.
In some embodiments, N is a programmable value.
In some embodiments, the target CA ODT instruction turns on the target CA ODT at the CA input of the target local controller from a setup time before receiving a CA signal until a hold time after receiving a CA signal.
In some embodiments, the memory controller is further configured to provide a non-target access CS signal of the first plurality of CS signals to a non-target local controller of the second plurality of local controllers, the non-target access CS signal to inhibit target access to all non-target memory banks of the first plurality of memory banks coupled to the non-target local controller; wherein the non-target local controller is configured to generate a non-target CA ODT instruction in response to receiving the non-target access CS signal, the non-target CA ODT instruction to turn on a non-target CA ODT at a CA input of a non-target local controller at least for a period of time that the CA signal is received from the memory controller.
In some embodiments, the memory system includes the memory controller.
In some embodiments, the memory system further comprises a second plurality of registered clock drivers RCDs, and each of the second plurality of local controllers is integrated in one of the second plurality of RCDs.
In some embodiments, each of the second plurality of local controllers is integrated in one of the first plurality of memory banks.
In another aspect of the present application, there is also provided a memory controller for a memory system, the memory system comprising a first plurality of memory banks and a second plurality of local controllers, wherein each memory bank has a plurality of memory cells, each local controller being coupled between one or more memory banks of the first plurality of memory banks and the memory controller, wherein the memory controller is configured to perform the steps of: providing a target local controller of the second plurality of local controllers with a target access CS signal of a first plurality of CS signals, the target access CS signal allowing target access to a target memory bank of the first plurality of memory banks coupled to the target local controller; and providing CA signals to the second plurality of local controllers later than the target access CS signals, the CA signals for addressing and accessing a plurality of memory cells in the target memory bank.
In yet another aspect of the present application, there is also provided a method for accessing a memory system by a memory controller, the memory system comprising a first plurality of memory banks, each memory bank having a plurality of memory cells, and a second plurality of local controllers, each local controller coupled between one or more memory banks of the first plurality of memory banks and the memory controller; the method comprises the following steps: providing a target access CS signal from the memory controller to a target local controller of the second plurality of local controllers from a first plurality of chip select CS signals, the target access CS signal allowing target access to a target memory bank of the first plurality of memory banks coupled to the target local controller; in response to the target local controller receiving the target access CS signal, generating, by the target local controller, a target CA ODT instruction that turns on a target CA ODT at a CA input of the target local controller; and providing, from the memory controller to the second plurality of local controllers, CA signals later than the target access CS signals, the CA signals for addressing and accessing a plurality of memory cells in the target memory bank; wherein the target CA ODT at the CA input of the target local controller is turned on by the target CA ODT instruction at least for a period of time that the CA signal is received from the memory controller.
The foregoing is a summary of the application that may be simplified, generalized, and details omitted, and thus it should be understood by those skilled in the art that this section is illustrative only and is not intended to limit the scope of the application in any way. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
Drawings
The above-described and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is appreciated that these drawings depict only several embodiments of the disclosure and are therefore not to be considered limiting of its scope. The present disclosure will be described more clearly and in detail by using the accompanying drawings.
FIG. 1 is a memory system 100 according to one embodiment of the present application;
FIG. 2 is a
FIG. 3 illustrates an exemplary timing diagram of signals on a portion of the signal lines/buses of the memory system of FIG. 1 according to the method of FIG. 2;
FIG. 4 illustrates another exemplary timing diagram of signals on a portion of the signal lines/buses of the memory system of FIG. 1 according to the method of FIG. 2.
Detailed Description
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, like reference numerals generally refer to like parts throughout the various views unless the context dictates otherwise. The illustrative embodiments described in the detailed description, drawings, and claims are not intended to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter of the present application. It will be understood that aspects of the present disclosure, as generally described in the present disclosure and illustrated in the figures herein, may be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which form part of the present disclosure.
FIG. 1 illustrates a memory system 100 according to one embodiment of the present application. The memory system 100 may be coupled to a memory controller 102, such as a central processor unit, to interact with data with the memory controller 102. In particular, memory controller 102 may access memory system 100, for example, by providing write instructions for writing data into memory system 100 or providing read instructions for reading data from memory system 100. In some embodiments, the memory system 100 may be a memory system conforming to the JEDEC double data rate synchronous dynamic random access memory (DDR SDRAM) standard, including, for example: JEDEC DDR2, DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5, or any other DDR standard.
As shown in FIG. 1, in one embodiment, the memory system 100 includes a plurality of DIMM memory modules, such as DIMM memory modules 104-0 and 104-1, which when operated will store data therein. It is understood that the number of DIMM memory modules may be greater than 2 in other embodiments. In addition, each DIMM memory module may include at least one DRAM memory bank (rank) and a local controller, such as a Registering Clock Driver (RCD), coupled between the at least one DRAM memory bank and the memory controller 102. For example, memory module 104-0 includes DRAM memory banks 108-0 and 108-1, and RCD 106-0. It is understood that in other embodiments, the number of DRAM memory banks included in a memory module may be other positive integers other than 2. Memory module 104-1 includes DRAM memory banks 108-2 and 108-3 and RCD 106-1. In the embodiments of the present application, a local controller refers to control logic or circuitry on a memory module, such as those provided on a printed circuit board of the memory module, which interacts with the memory controller through a memory interface. In some embodiments, the local controller may or may not be integrated in the RCD. In some other embodiments, the local controller may be integrated with the memory bank so that the memory controller 102 may directly access the memory bank without buffering access commands and/or other control instructions via the RCD. The present application is specifically described below with reference to an exemplary memory system 100 having a local controller integrated in a memory module as shown in fig. 1, but such description is merely exemplary and should not be taken as limiting the scope of the present application.
Specifically, memory controller 102 is coupled to the RCDs (RCDs 106-0 and 106-1 in the embodiment shown in FIG. 1) via a DCA bus that is used to provide command/address (CA) signals indicative of specific access operations (e.g., write, read, select, deselect, etc.) to the memory bank and a DCK _ t clock bus that is used to provide clock signals used to synchronize the CA signals and other signals provided to RCDs 106-0 and 106-1. The RCDs 106-0 and 106-1 each have a CA input coupled to the DCA bus for receiving a CA signal. RCDs 106-0 and 106-1 may forward the received CA and clock signals to memory banks 108-0 through 108-3 via their respective QCA _ n and QCK _ t signal lines to instruct memory banks 108-0 through 108-3 how to operate. It will be appreciated that the clock signal may be conveyed via the DCK _ t bus and then via the QCK _ t signal line, while in some other embodiments the clock signal may take the form of a differential signal and may be conveyed via separate bus and signal lines.
In addition, the memory controller 102 is also coupled to the RCDs (RCD 106-0 and RCD 106-1 in the embodiment shown in FIG. 1) via respective DCSi _ n (DCS 0_ n through DCS3_ n in the embodiment shown in FIG. 1) signal lines for providing Chip Select (CS) signals to the RCDs, i being a positive integer. The CS signal may enable or disable target access to a particular one of the plurality of memory groups. For example, the RCD106-0 is coupled to the memory controller 102 via DCS0_ n and DCS1_ n signal lines. The RCDs 106-0 and 106-1 may also forward the received CS signals to the memory banks 108-0 through 108-3 via respective QCSi _ n signal lines (in the embodiment shown in FIG. 1, QCS0_ n through QCS3_ n). Each memory group is controlled by the CS signal on a corresponding QCSi _ n signal line coupled to the RCD output on that QCSi _ n signal line. During operation, the memory bank that is allowed target access by the memory controller 102 via the corresponding RCD is referred to as a target memory bank, the corresponding CS signal is referred to as a target access CS signal, and the RCD coupled to the target memory bank is referred to as a target RCD. It can be seen that in the embodiment shown in fig. 1, each RCD is coupled to two memory banks. Accordingly, when any one or both of the memory banks coupled to the same RCD are allowed for target access by the corresponding CS signal, the RCD is the target RCD. On the other hand, a memory bank disabled by a memory controller for a target access via a corresponding RCD may be referred to as a non-target memory bank, and a corresponding CS signal may be referred to as a non-target access CS signal. Accordingly, when two memory banks coupled to an RCD are each disabled for target access by a corresponding CS signal, the RCD may be referred to as a non-target RCD.
All of the memory banks 108-0 through 108-3 are also coupled to the memory controller 102 via a bi-directional DQ/DQS data bus over which data may be written to a target memory bank during write operations indicated by a target RCD and read from the target memory bank to the memory controller 102 during read operations indicated by the target RCD. The JEDEC standards, including DDR SDRAM (JESD79-4B) standard disclosed in 6 months 2017, DDR4 registered clock driver-DDR 4RCD01(JESD82-31) standard disclosed in 8 months 2016, double data rate with low power consumption 4(JESD209-4B) standard disclosed in 2 months 2017, and the like, provide more details regarding access operations to memory systems that conform to the DDR standard, and are hereby incorporated by reference in their entirety.
Since data communications between the memory modules 104-0 and 104-1 and the memory master controller 102 may operate at very high operating frequencies, e.g., 2400MHz or higher, ODT may be applied to the signal buses (e.g., the DCA bus and the DQ/DQS bus) between the memory modules 104-0 and 104-1 and the memory controller 102 to improve signal integrity and reduce signal reflections on these buses. The inventors of the present application have discovered that conventional static ODT techniques for CA buses do not work well in these access operations. Thus, a novel dynamic ODT technique for CA buses is provided herein, which may be implemented, for example, in memory system 100 shown in fig. 1.
FIG. 2 illustrates a
Hereinafter, the
Specifically, at
At
In some embodiments, a dynamic ODT mechanism may also be applied to an RCD when a group of memory coupled to the RCD receives a non-target access CS signal. Specifically, when the RCD receives a non-target access CS signal, the RCD's decoder may decode the non-target access CS signal into a non-target CA ODT instruction for turning on the non-target CA ODT for its CA input. Both the target CA ODT and the non-target CA ODT are ODT technologies for the CA bus lines, differing in the resistance values of the termination resistors that are switched for termination.
TABLE I complete combination of DSC0_ n and DSC1_ n codes
Table I shows the complete combination of DCS0_ n and DCS1_ n encodings for the memory system shown in FIG. 1. The DCS0_ n and DCS1_ n signal lines are both coupled to the RCD106-0 shown in FIG. 1. And the memory system may be one that conforms to the DDR5 standard and other future DDR standards, where the CS signal is a two clock cycle wide signal and active low. The CA signal may also be a two clock cycle wide signal and each signal line of the CA bus transfers 1 bit of data during each clock cycle, as shown in fig. 3. For a memory system without an RCD for buffering the CA signal, i.e., the memory modules of the memory system are directly accessed by the memory controller, each memory module may have a CA [13:0] bus with 14 signal lines, and thus a total of up to 28 bits may be transferred over the CA [13:0] bus during each two clock cycles. Up to 28 bits of data constitute the data access instructions and access addresses required for the data access operation. In addition, the CS signal and CA signal, both two clock cycles wide, may be respectively aligned to the clock signal provided at the CK _ t bus to pass the necessary chip select instructions, data access instructions, access addresses, etc. to the memory module. For a memory system with RCDs, as shown in FIG. 1, the RCDs may have a DCA [6:0] bus for receiving CA signals from the memory controller, and a QCA [13:0] bus for outputting buffered CA signals. Accordingly, the CA signal may carry 4 bits on each signal line of the DCA [6:0] bus during every two clock cycles (i.e., two bits per clock cycle, one bit in the upper half cycle and another bit in the lower half cycle) to ensure that at most 28 bits in total may be output to the corresponding memory bank via the QCA [13:0] bus of the RCD. Furthermore, for the LPDDR5 memory system that uses a single clock cycle CA signal to carry CA instructions and no RCD to buffer the CA signal, each signal line of the CA [6:0] bus coupled to a memory module of the memory system may transfer two bits of data per clock cycle, i.e., one bit on the first half of the clock cycle and another bit on the second half of the clock cycle, so that a total of up to 14 bits may be transferred via the CA [6:0] bus per clock cycle (see FIG. 4). It should be noted that the number of signal lines included in the CA bus (DCA/QCA) does not affect the scope of the present application.
As shown in Table I, the CS signal is illegal when a value of "10" is received on either or both of the DCS0_ n or DCS1_ n signal lines for two consecutive clock cycles. In addition, a target access to memory bank 108-1 will be performed upon receiving a value of "01" on the DCS1_ n signal line for two consecutive clock cycles; and when the value "01" is received on the DCS0_ n signal line for two consecutive clock cycles, a target access to memory bank 108-0 will be performed. In this case, the target CA ODT may be turned on for RCD 106-0. Further, when the values "00" or "11" are received on both the DCS0_ n and DCS1_ n signal lines for two consecutive clock cycles, a non-targeted access to memory banks 108-0 and 108-1 will be performed. Accordingly, a non-target CA ODT may be turned on for RCD 106-0.
Still referring to FIGS. 1 and 2, at
As before, upon receiving the target access CS signal, the target RCD requires a period of time to generate the target CA ODT command by decoding the target access CS signal or otherwise. If a CA signal is transmitted from the memory controller to a target RCD simultaneously with a target access CS signal, the target CA ODT may not operate at least at the moment the target RCD starts receiving the CA signal, and may introduce unwanted noise in the received CA signal. Thus, at
As such, the target RCD should always receive the CA signal no earlier than the target CA ODT of the target RCD is turned on. In addition, the target CA ODT should be maintained for at least the period of time during which the CA signal is being received by the target RCD. In some preferred embodiments, the target CA ODT command may turn on the target CA ODT for the target RCD at a setup time before the RCD receives the CA signal and until a hold time after the reception of the CA signal. Accordingly, the target CA ODT may be held stable throughout the reception of the CA signals.
As before, an RCD may receive a non-target access CS signal at all its DSCi _ n inputs, and accordingly, the RCD is a non-target RCD. For non-target RCDs, the non-target CA ODT may be turned on at its CA input. In some embodiments, the non-target CA ODT may be set to a default ODT that will be switched to the target CA ODT only upon receiving a target access CS signal. The CA ODT is set to a non-target CA ODT except that the target CA ODT is turned on for receiving CA signals.
In the embodiment shown in fig. 3, the target access CS signal and the non-target access CS signal are each two clock cycles wide, which conforms to, for example, the DDR5 standard. FIG. 4 illustrates a timing diagram of signals on a portion of a signal line/bus of a memory system that conforms to the LPDDR5 standard. Specifically, the target access and non-target access CS signals are signals that are one clock cycle wide and active high. The CA signal is also transmitted within one clock cycle. The target CA ODT and non-target CA ODT settings for this memory system are similar to those for a memory system that conforms to the DDR5 standard and are not described in detail herein.
It should be noted that although in the above detailed description some steps of the method for accessing the memory system are mentioned, as well as several modules or sub-modules of the memory system, such partitioning is merely exemplary and not mandatory. Indeed, according to embodiments of the application, the features and functions of two or more modules described above may be embodied in one module. Conversely, the features and functions of one module described above may be further divided into embodiments by a plurality of modules.
Other variations to the disclosed embodiments can be understood and effected by those skilled in the art from a study of the specification, the disclosure, the drawings, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the words "a" or "an" do not exclude a plurality. In the practical application of the present application, one element may perform the functions of several technical features recited in the claims. Any reference signs in the claims shall not be construed as limiting the scope.