阅读说明：本技术 存储系统和存储控制装置 (Storage system and storage control device ) 是由 吴聿旻 于 2018-06-29 设计创作，主要内容包括：本申请提供一种存储系统和存储控制装置,该存储系统包括：第一时钟装置,用于生成第一时钟信号并将该第一时钟信号发送至第一存储控制装置和第二存储控制装置；第一存储控制装置,用于接收该第一时钟信号并将该第一时钟信号发送至存储装置；第二存储控制装置,用于接收该第一时钟信号并将该第一时钟信号发送至存储装置；存储装置,用于从该第一存储控制装置和第二存储控制装置接收该第一时钟信号；根据该第一时钟信号进行数据读写。以此避免因针失效引起的时钟信号无法正常传输信号导致的丢盘。(The application provides a storage system and a storage control apparatus, the storage system including: a first clock means for generating a first clock signal and transmitting the first clock signal to the first memory control means and the second memory control means; a first memory control device for receiving the first clock signal and sending the first clock signal to a memory device; the second storage control device is used for receiving the first clock signal and sending the first clock signal to the storage device; a memory device for receiving the first clock signal from the first memory control device and the second memory control device; and reading and writing data according to the first clock signal. Therefore, the problem that the clock signal cannot normally transmit signals due to the failure of the pin is avoided.)

1. A storage system, comprising: the storage system comprises a first clock device, a first storage control device, a second storage control device and a storage device, wherein the first clock device is connected with the first storage control device, the first clock device is connected with the second storage control device, the first storage control device is connected with the storage device, and the second storage control device is connected with the storage device;

the first clock device is used for generating a first clock signal and sending the first clock signal to the first storage control device and the second storage control device;

the first storage control device is used for receiving the first clock signal and sending the first clock signal to the storage device;

the second storage control device is used for receiving the first clock signal and sending the first clock signal to the storage device;

the storage device is used for receiving the first clock signal from the first storage control device and the second storage control device; and reading and writing data according to the first clock signal.

2. The storage system of claim 1, wherein the storage system further comprises: the second clock device is connected with the first storage control device, and the second clock device is connected with the second storage control device;

the second clock device is used for generating a second clock signal and sending the second clock signal to the first storage control device and the second storage control device;

the first storage control device is further configured to receive the second clock signal and send the second clock signal to the storage device;

the second storage control device is further configured to receive the second clock signal and send the second clock signal to the storage device;

the storage device is used for receiving the second clock signal from the first storage control device and the second storage control device; and reading and writing data according to the second clock signal.

3. The memory system of claim 2, wherein the second clock means is coupled to the first clock means;

the first clock device is further configured to send the generated first clock signal to the second clock device;

the second clock device is further configured to forward the received first clock signal to the first storage control device and the second storage control device; sending the generated second clock signal to the first clock device;

the first clock device is further configured to forward the received second clock signal to the first memory control device and the second memory control device.

4. The memory system of claim 3, wherein the first clock means includes a first port and a second port, and the second clock means includes a third port and a fourth port, wherein the first port is coupled to the third port and the second port is coupled to the fourth port,

the first clock device is further configured to send the first clock signal to the second clock device through the first port or the second port;

the second clock device is further configured to send the second clock signal to the first clock device through the third port or the fourth port.

5. The storage system according to claim 3 or 4,

the first memory control device is further used for carrying out phase locking and multi-cycle slow phase shifting on the second clock signal under the condition that a clock signal source is determined to be switched from the first clock device to the second clock device;

the second memory control device is further configured to perform phase locking and multi-cycle slow phase shifting on the second clock signal when it is determined that the clock signal source is switched from the first clock device to the second clock device.

6. The method according to any one of claims 3 to 5,

the storage device is further configured to perform phase locking and multi-cycle slow phase shifting on the second clock signal when it is determined that the clock signal source is switched from the first clock device to the second clock device.

7. The method according to any one of claims 3 to 6,

the second clock device is further configured to perform phase locking and multi-cycle slow phase shifting on the second clock signal when it is determined that the clock signal source is switched from the first clock device to the second clock device.

8. The method according to any one of claims 1 to 7,

the storage device is further configured to send first warning information to the first storage control device when a clock signal cannot be received from the first storage control device, where the first warning information is used to indicate that the storage device cannot receive the clock signal from the first storage control device;

the storage device is further configured to send second warning information to the second storage control device when the clock signal cannot be received from the second storage control device, where the second warning information is used to indicate that the storage device cannot receive the clock signal from the second storage control device.

9. A storage control device, characterized in that the storage control device comprises a first port, a second port and a switching unit,

the first port is used for connecting a first clock device in the storage system;

the second port is used for connecting a second clock device in the storage system;

the switch unit is used for controlling the clock signal received from the first clock device through the first port or the clock signal received from the second clock device through the second port.

10. The storage control apparatus of claim 1,

the memory control device further comprises a processing unit, wherein the processing unit is used for carrying out phase locking and multi-cycle slow phase shifting on the received clock signal under the condition that the clock signal source is determined to be switched from the first clock device to the second clock device.

Technical Field

The present application relates to the field of storage technologies, and more particularly, to a storage system and a storage control apparatus.

Background

In order to ensure the reliability of the storage device, the storage device is provided with 2 ports (ports), wherein the 2 ports are respectively connected with 2 controllers, and the 2 controllers are independently decoupled. If one of the 2 ports of a storage device fails, the corresponding controller will mark the storage device as failed. This phenomenon may be referred to as lost discs. The number of read and write channels of the memory device is changed from 2 to 1. This affects the read and write performance of the memory device.

Taking the example of a storage device using the SFF-8639 interface, the storage device has two ports, port a (port a) and port b (port b), respectively. The memory device may be connected to controller a through port a and to controller B through port B. The pins corresponding to the clock signal of port B are shorter and more densely arranged than the pins corresponding to the clock signal of port a. Therefore, the pin corresponding to the clock signal of the port B is prone to fail (e.g., oxidation or contamination adhering to multiple pins) and thus the clock signal cannot be transmitted normally. The reading and writing of data in a memory device is clock signal dependent. Taking writing data as an example, the controller B may send a write operation command for one clock cycle, send a write address for five clock cycles, and send data to be written into the storage device to the storage device. The memory device determines a clock period based on the clock signal. Once the clock signal of the port B cannot be transmitted normally, the memory device cannot read and write data according to the clock signal. Thus, if the clock signal of port B is not transmitted properly, controller B will mark the memory device as faulty. Therefore, the read-write channel of the storage device is changed from a dual channel to a single channel, thereby seriously affecting the read-write performance of the storage device.

Therefore, how to avoid missing the disk caused by the clock signal unable to normally transmit due to the pin failure.

Disclosure of Invention

The application provides a storage system and a storage control device, which can avoid lost disks caused by the fact that clock signals cannot be normally transmitted due to pin failure.

In a first aspect, the present application provides a storage system comprising: the storage system comprises a first clock device, a first storage control device, a second storage control device and a storage device, wherein the first clock device is connected with the first storage control device, the first clock device is connected with the second storage control device, the first storage control device is connected with the storage device, and the second storage control device is connected with the storage device; the first clock device is used for generating a first clock signal and sending the first clock signal to the first storage control device and the second storage control device; the first storage control device is used for receiving the first clock signal and sending the first clock signal to the storage device; the second storage control device is used for receiving the first clock signal and sending the first clock signal to the storage device; the storage device is used for receiving the first clock signal from the first storage control device and the second storage control device; the storage device is also used for reading and writing data according to the first clock signal. The technical scheme can avoid the problem of lost disks caused by the fact that clock signals cannot be normally transmitted due to pin failure.

In one possible implementation manner, the storage system further includes: a second clock device, wherein the second clock device is connected to the first memory control device, and the second clock device is connected to the second memory control device; the second clock device is used for generating a second clock signal and sending the second clock signal to the first storage control device and the second storage control device; the first storage control device is also used for receiving the second clock signal and sending the second clock signal to the storage device; the second storage control device is also used for receiving the second clock signal and sending the second clock signal to the storage device; the memory device is used for receiving the second clock signal from the first memory control device and the second memory control device; the storage device is also used for reading and writing data according to the second clock signal. According to the technical scheme, the storage device can still acquire the clock signal under the condition that one clock device fails or a bus and/or a port for transmitting the clock signal fails.

In another possible implementation, the second clock means is connected to the first clock means; the first clock device is further used for sending the generated first clock signal to the second clock device; the second clock device is also used for forwarding the received first clock signal to the first storage control device and the second storage control device; the second clock device is also used for sending the generated second clock signal to the first clock device; the first clock means is further configured to forward the received second clock signal to the first memory control means and the second memory control means. Based on the above technical solution, if the second memory control device cannot directly receive the second clock signal from the second clock device, the second memory control device can still receive the second clock signal forwarded by the first clock device.

In another possible implementation manner, in a third possible implementation manner of the first aspect, the first clock device includes a first port and a second port, and the second clock device includes a third port and a fourth port, where the first port is connected to the third port, and the second port is connected to the fourth port, and the first clock device is specifically configured to send the first clock signal to the second clock device through the first port or the second port; the second clock device is specifically configured to send the second clock signal to the first clock device through the third port or the fourth port. In this way, the first clock device may transmit the first clock signal to the second clock device through the second port even if the first port, the third port, or a bus for connecting the first port and the third port fails. The second clock means is also able to receive the first clock signal via the fourth port. Similarly, the first clock device may transmit the first clock signal to the second clock device through the first port even if the second port, the fourth port, or a bus connecting the second port and the fourth port fails. The second clock device may also receive the first clock signal through a third port. Accordingly, even if the first port, the third port, or a bus for connecting the first port and the third port malfunctions, the second clock device can transmit the second clock signal to the first clock device through the fourth port. The first clock device is also capable of receiving the first clock signal through the second port. Similarly, the second clock device may transmit the second clock signal to the first clock device through the third port even if the second port, the fourth port, or a bus for connecting the second port and the fourth port fails. The first clock device may also receive the second clock signal through the first port.

In another possible implementation manner, the first memory control device is further configured to perform phase locking and multi-cycle slow phase shifting on the second clock signal when the clock signal source is determined to be switched from the first clock device to the second clock device; the second memory control device is further configured to perform phase locking and multi-cycle slow phase shifting on the second clock signal when it is determined that the clock signal source is switched from the first clock device to the second clock device. Therefore, the consistency of the overall jitter of the clock at any moment is ensured, and the switching reliability of the clock signal source is improved.

In another possible implementation manner, the storage device is further configured to perform phase locking and multi-cycle slow phase shifting on the second clock signal when the clock signal source is determined to be switched from the first clock device to the second clock device. Therefore, the consistency of the overall jitter of the clock at any moment is ensured, and the switching reliability of the clock signal source is improved.

In another possible implementation manner, the second clock device is further configured to perform phase locking and multi-cycle slow phase shifting on the second clock signal when the clock signal source is determined to be switched from the first clock device to the second clock device. Therefore, the consistency of the overall jitter of the clock at any moment is ensured, and the switching reliability of the clock signal source is improved.

In another possible implementation manner, the storage device is further configured to send first warning information to the first storage control device in a case where the clock signal cannot be received from the first storage control device, where the first warning information is used to indicate that the storage device cannot receive the clock signal from the first storage control device; the memory device is further configured to send second warning information to the second memory control device when the clock signal cannot be received from the second memory control device, where the second warning information is used to indicate that the memory device cannot receive the clock signal from the second memory control device. Therefore, the user can be informed of the failure of the port of the storage device in time.

In a second aspect, the present application provides a storage control apparatus, which includes a first port, a second port, and a switch unit, wherein the first port is used for connecting a first clock apparatus in a storage system; the second port is used for connecting a second clock device in the memory system; the switch unit is used for controlling the clock signal received from the first clock device through the first port or the clock signal received from the second clock device through the second port. The memory control device can acquire clock signals from different clock devices. In this way, in the case where a clock signal cannot be acquired from one clock device, a clock signal can be acquired from another clock device.

In a possible implementation manner, the memory control device further includes a processing unit, and the processing unit is configured to perform phase locking and multi-cycle slow phase shifting on the received clock signal when the clock signal source is determined to be switched from the first clock device to the second clock device. Therefore, the consistency of the overall jitter of the clock at any moment is ensured, and the switching reliability of the clock signal source is improved.

Drawings

Fig. 1 is a schematic structural block diagram of a storage system according to an embodiment of the present invention.

Fig. 2 is a schematic structural block diagram of another storage system provided by the embodiment of the present invention.

Fig. 3 is a schematic structural block diagram of another storage system provided by the embodiment of the present invention.

Fig. 4 is a schematic structural block diagram of another storage system provided by the embodiment of the invention.

Fig. 5 is a schematic connection diagram of a first clock device and a second clock device according to an embodiment of the present invention.

Detailed Description

The technical solution of the present invention will be described with reference to the accompanying drawings. To help those skilled in the art to better understand the technical solution of the present invention, some concepts related to the present application will be first introduced.

The storage system referred to in the embodiments of the present invention may be a built-in storage system or a plug-in storage system. The built-in storage system may also be referred to as built-in storage, internal storage, or the like. A built-in storage system is a storage system inside a computer device. The computer device may directly access the built-in storage system, read data stored in the built-in storage system, or write data to the built-in storage system. The plug-in storage system can also be called as plug-in storage, external storage and the like. The computer equipment can be connected with the plug-in storage system in a wired or wireless mode to read data stored in the plug-in storage system or write the data into the plug-in storage system.

The computer device referred to in the embodiments of the present invention refers to a device having a built-in storage system or capable of accessing a plug-in storage system, for example, a desktop computer, a notebook computer, a mobile phone, a tablet computer, a server, and the like.

Clock devices (e.g., first clock device, second clock device) referred to in the embodiments of the present invention may also be referred to as clock boards, clock sources, clock circuits, etc. The clock device can generate a clock signal, and the memory device in the memory system can read and write data according to the clock signal generated by the clock device. The memory control device in the memory system may also generate the operation instruction according to the clock signal.

The memory control devices (e.g., the first memory control device and the second memory control device) referred to in the embodiments of the present invention may also be referred to as a memory controller, a memory control circuit, a memory control chip, or the like. The storage control device may control a storage device in the storage system. For example, the storage control apparatus may generate a read operation command, a write operation command, and the like, and transmit the generated operation command to the storage apparatus. The storage device can perform corresponding operation on the stored data according to the received operation command. The storage control device is also responsible for sending the clock signal generated by the clock device to the storage device so that the storage device can read and write data according to the clock signal.

The storage apparatus in the embodiment of the present invention may also be referred to as a storage device, for example, a Solid State Drive (SSD). The memory device in the embodiment of the invention comprises two ports. For example, the storage device referred to in the embodiment of the present invention may be a storage device having an SFF-8639 interface. The SFF-8639 interface may also be referred to as the U.2 interface. Two ports of the storage device may be connected to two controllers, respectively. Each of the two ports may include a plurality of pins, and the functions of the different pins may be different. For example, some pins are used to receive clock signals sent by the corresponding controller, and other pins are used to receive control signals sent by the controller. The two controllers can respectively control the storage device to complete the read-write operation of data.

The bus referred to in the embodiments of the present invention is a generic term of a common path capable of connecting two devices and transmitting a signal between the two devices. A bus is used to connect the ports of two devices so that signals are transmitted between the two devices. The signal generated by the transmitting end is transmitted to the receiving end through the bus through the port of the transmitting end, and the receiving end receives the signal transmitted by the transmitting end through the port of the receiving end. The port can realize the transceiving function of signals. Further, the devices in the port for implementing the transmit function may also be referred to as transmit ports, output ports, and the like. The devices in a port that are used to implement a receive function may also be referred to as receive ports, input ports, etc.

Fig. 1 is a schematic structural block diagram of a storage system provided according to an embodiment of the present invention. As shown in fig. 1, the system 100 includes: a first clock device 110, a first storage control device 120, a second storage control device 130, and a storage device 140. As shown in FIG. 1, the first clock device 110 is connected to the first storage control device 120, the first clock device 110 is connected to the second storage control device 130, the first storage control device 120 is connected to the storage device 140, and the second storage control device 130 is connected to the storage device 140.

The first clock device 110 is configured to generate a first clock signal and send the first clock signal to the first memory control device 120 and the second memory control device 130. The first clock signal generated by the first clock device 110 can guarantee the basic clock phase jitter requirements of the memory device 140.

The first memory control device 120 is configured to receive the first clock signal and send the first clock signal to the memory device 140.

The second memory control device 130 is configured to receive the first clock signal and send the first clock signal to the memory device 140.

The memory device 140 is used for receiving the first clock signal from the first memory control device 120 and the memory control device 130.

The memory device 140 is further configured to read and write according to the first clock signal.

The first storage control device 120, the second storage control device 130, and the storage device 140 are connected in the same manner as in the related art. Specifically, two ports (not shown), port a and port B, of the storage device 140 are connected to the first storage control device 120 and the second storage control device 130, respectively. More specifically, port A of the storage device 140 may be used to connect to the first storage control device 120. Port B of the storage device 140 may be used to connect to a second storage control device 130. The first memory control device 120 may send the first clock signal to port a of the memory device 140 through an output port (not shown) of the first memory control device 120. The second storage control device 130 may transmit the first clock signal to the port B of the storage device 140 through an output port (not shown) of the second storage control device 130. In other words, the memory device 140 may obtain the first clock signal transmitted by the first memory control device 120 and the first clock signal transmitted by the second memory control device 130 through the port a and the port B, respectively. The memory device 140 can read and write data using the first clock signal. More specifically, the memory device 140 may receive the first clock signal through a pin of the port a for acquiring the clock signal (hereinafter, referred to as a clock pin). Meanwhile, the memory device 140 may receive the first clock signal through a clock pin of the port B.

Based on the system shown in fig. 1, the memory device 140 may obtain the same clock signal from different ports and give the clock signal to read and write data. In this case, if one of the two ports of the memory device 140 has a failed clock pin, the memory device 140 may still receive the first clock signal through the non-failed pin. In other words, even if the clock pin in one port of the memory device 140 fails, the memory device 140 can still obtain the clock signal through the clock pin of the other port, so as to ensure that the memory device 140 can normally read and write data.

The clock signal received by the memory device in the system shown in fig. 1 may provide redundancy safeguards. Thus, clock switching at the memory device level may be achieved. That is, if one pin of the memory device for receiving the clock signal fails, the memory device can read and write data using the clock signal received by the other pin for receiving the clock signal. Therefore, the reliability of the system is improved.

Further, the storage device 140 may also send first warning information to the first storage control device 120 in a case where the clock signal cannot be received from the first storage control device 120, where the first warning information indicates that the storage device 140 cannot receive the clock signal from the first storage control device 120; the storage device 140 may also send second warning information to the second storage control device 130 in case the clock signal cannot be received from the second storage control device 130, the second warning information indicating that the storage device 140 cannot receive the clock signal from the second storage control device 130. After the storage control device receives the alarm information, the storage control device can prompt the user that the storage device is in failure.

Fig. 2 is a schematic block diagram of another storage system provided in accordance with an embodiment of the present invention. As shown in fig. 2, the storage system 200 includes: a first clock means 210, a second clock means 220, a first memory control means 230, a second memory control means 240 and a memory means 250. As shown in fig. 2, the first clock unit 210 is connected to the first memory control unit 230, the first clock unit 210 is connected to the second memory control unit 240, the first memory control unit 230 is connected to the memory unit 250, the second memory control unit 240 is connected to the memory unit 250, the second clock unit 220 is connected to the first memory control unit 230, and the second clock unit is connected to the second memory control unit 240.

In the system 200 shown in FIG. 2, one of the first clock device 210 and the second clock device 220 serves as a clock signal source for providing a clock signal to the memory device 250. Assume that the first clock device 210 first provides a signal to the memory device as a clock signal source. In this case, the first clock device 210 may generate a first clock signal and transmit the first clock signal to the first and second memory control devices 230 and 240. The first memory control device 230 receives the first clock signal and sends the first clock signal to the memory device 250. The second memory control device 240 receives the first clock signal and sends the first clock signal to the memory device 250.

In some cases, the first clock device 210 may not be able to continue to provide a clock signal to the memory device 250 as a clock signal source. For example, the first clock device 210 fails and cannot continue to provide the first clock signal. For another example, a failure of a bus and/or a port between the first clock device 210 and the first memory control device 230 for transmitting the first clock signal may result in the first memory control device 230 failing to receive the first clock signal. For another example, a failure of a bus and/or a port between the first clock device 210 and the second memory control device 240 for transmitting the first clock signal may result in the second memory control device 240 failing to receive the first clock signal. In the event that it is determined that the first clock device 210 is unable to provide a clock signal as a source of the clock signal to the memory device 250, the source of the clock signal may be switched from the first clock device 210 to the second clock device 220.

Optionally, in some embodiments, the switching of the clock signal source from the first clock device 210 to the second clock device 220 may be determined even though the first clock device 210 is still capable of providing a clock signal to the memory device 250. For example, the operation periods of the two clock devices may be set in advance. The memory device 250 is clocked by the first clock device for a first period of time and the memory device 250 is clocked by the second clock device 220 for a second period of time.

Alternatively, in some embodiments, the second clock device 220 generates and sends a second clock signal to the first storage control device 230 and the second storage control device 240 upon determining that the clock signal source is switched from the first clock device 210 to the second clock device 220. First memory control 230 receives the second clock signal and sends the second clock signal to memory device 250. The second memory control device 240 receives the second clock signal and sends the second clock signal to the memory device 250. The memory device 250 reads and writes data according to the received clock signal. Specifically, if the storage device 250 receives the first clock signal, the storage device reads and writes data according to the first clock signal; if the memory device 250 receives the second clock signal, the memory device 250 reads and writes data according to the second clock signal.

Alternatively, in some embodiments, the first storage control device 230 or the second storage control device 240 may determine that the clock signal source is switched from the first clock device 210 to the second clock device 220. Specifically, if the first storage control device 230 cannot receive the first clock signal from the first clock device 210, the first storage control device 230 may determine to switch the clock signal source from the first clock device 210 to the second clock device 220. The first storage control device 230 may send a switch indication message to the second clock device 220, in case it is determined that the clock signal source is switched from the first clock device 210 to the second clock device 220, the switch indication message indicating that the clock signal source is switched from the first clock device 210 to the second clock device 220. The second clock means 220 determines that the clock signal source is switched from the first clock means 210 to the second clock means 220 and generates the second clock signal in case the indication message is received. Similarly, if the second storage control device 240 cannot receive the first clock signal from the first clock device 210, the second storage control device 240 may determine to switch the clock signal source from the first clock device 210 to the second clock device 220. The second storage control device 240 may send a switch indication message to the second clock device 220, in case it is determined that the clock signal source is switched from the first clock device 210 to the second clock device 220, the switch indication message indicating that the clock signal source is switched from the first clock device 210 to the second clock device 220. The second clock means 220 determines that the clock signal source is switched from the first clock means 210 to the second clock means 220 and generates the second clock signal in case the indication message is received.

Alternatively, in other embodiments, second clock device 220 may begin generating the second clock signal only upon determining that the clock signal source is switched from first clock device 210 to second clock device 220. In other words, the second clock device 220 may not generate the clock signal if it is not determined that the clock signal source is switched. In this case, at a certain time, the first control device 230 and the second clock control device 240 can receive the clock signal from only one clock device. Specifically, if the clock signal source is not switched, the first control device 230 and the second control device 240 may receive the first clock signal from the first clock device 210. If the first control device 230 and/or the second control device 240 cannot receive the first clock signal, the clock signal source is switched from the first clock device 210 to the second clock device 220. In this case, the first and second control devices 240 receive the second clock signal from the second clock device 220.

Alternatively, in some embodiments, the first clock device 210 and the second clock device 220 may generate respective clock signals simultaneously, and the first memory control device 230 and the second memory control device 240 receive the clock signals from one of the two clock devices (i.e., the first clock device 210 and the second clock device 220). In other words, if the first clock device 210 does not have a failure that cannot generate the clock signal, the first clock device 210 always generates the first clock signal; if the second clock device 220 does not have a failure that cannot generate the clock signal, the second clock device 220 always generates the second clock signal. The first memory control device 230 and the second memory control device 240 select one of the two clock devices to receive the clock signal. In other words, the clock means selected by the first memory control means 230 and the second memory control means 240 are the same. For example, the first memory control device 230 and the second memory control device 240 may first select to receive the first clock signal from the first clock device 210. The first storage control device 230 and the second storage control device 240 then determine that the clock signal source switched from the first clock device to the second clock device. In this case, the first memory control device 230 and the second memory control device 240 receive the second clock signal from the second clock device 220. How to determine to switch the clock signal source from the first clock device to the second clock device can be seen from the above description, and is not described herein again. In other words, at a certain moment in time, the first storage control device 230 and the second storage control device 240 may actively select a clock signal source that receives a clock signal.

Based on the system shown in fig. 2, the memory device 250 may obtain the same clock signal from different ports and give the clock signal to read and write data. In this case, if the clock pin of one of the two ports of the memory device 140 fails, the memory device 250 may still receive the clock signal through the non-failed pin. In other words, even if the clock pin in one port of the memory device 250 fails, the memory device 250 can still obtain the clock signal through the clock pin in the other port, so as to ensure that the memory device 250 can normally read and write data. Further, if the first memory control device 230 and/or the second memory control device 240 cannot obtain the first clock signal from the first clock device 210, the first memory control device 230 and the second memory control device 240 may still obtain the second clock signal from the second clock device 220 and send the obtained clock signal to the memory device 250. This ensures that the memory device 250 can still acquire a clock signal in the event of a failure of one clock device or a failure of the bus and/or port used to transmit the clock signal.

The clock signal received by the memory devices in the system shown in fig. 2 may provide redundancy safeguards. Thus, clock switching at the memory device level may be achieved. That is, if one pin of the memory device for receiving the clock signal fails, the memory device can read and write data using the clock signal received by the other pin for receiving the clock signal. Therefore, the reliability of the system is improved.

In addition, the system shown in FIG. 2 provides redundant clock signal sources. Thus, the system shown in FIG. 2 may also implement clock switching of the clock signal source stage. That is, if one clock signal source providing a clock signal fails, the system may switch the clock signal source to another clock device. Therefore, the reliability of the system is further improved.

In the traditional storage system, because a clock device distributed uniformly is not arranged, and two storage control devices need to be replaced independently, the self clock of the storage control device in the design is only provided for the self controller. In the system of FIG. 2, a unified clock device is used to provide the clock source, and the clocks between the two memory control devices are coupled. Meanwhile, the storage control device can still ensure independent online replacement due to the fact that the unified redundant clock device exists independently of the storage control device.

Optionally, in some embodiments, the second clock device 220 may also perform phase locking and multi-cycle slow phase shifting on the second clock signal when the clock signal source is switched from the first clock device 210 to the second clock device 220. More specifically, the second clock device 220 may include a clock signal generation unit and a processing unit. The processing unit may perform the functions of phase locking and multi-cycle slow phase shifting of the second clock signal when the clock signal source is switched from the first clock device 210 to the second clock device 220. A clock source is used for generating the second clock signal. The processing unit may be implemented by a processor, which may be a Digital Signal Processor (DSP). Therefore, the consistency of the overall jitter of the clock at any moment is ensured, and the switching reliability of the clock signal source is improved.

Specifically, when a clock signal is switched from the first clock signal to the second clock signal, the phases of the first clock signal and the second clock signal may be different. The phase change of the clock signal can affect the reading and writing of data. Therefore, in order to improve the reliability of the switching of the clock signal source, it is necessary to lock the phase (i.e., phase lock) and to adjust the phase of the second clock signal to be the same as the phase of the first clock signal. The process of adjusting the phase of the second clock signal to coincide with the phase of the first clock signal is called phase shifting. In order to ensure the consistency of the overall jitter of the clock at any time, the phase shift is slowly realized by multiple cycles. In other words, the phase of the second signal may be adjusted using a plurality of clock cycles, each cycle only partially adjusting the phase of the second clock signal.

Optionally, in some embodiments, the first memory control device 230 may further perform phase locking and multi-cycle slow phase shifting on the second clock signal in case that it is determined that the clock signal source is switched from the first clock device 210 to the second clock device 220; the second memory control device 230 may also phase lock and multi-cycle slow phase shift the second clock signal upon determining that the clock signal source is switched from the first clock device 210 to the second clock device 220. More specifically, the first storage control device 230 may include a processing unit. The processing unit may perform the functions of phase locking and multi-cycle slow phase shifting of the second clock signal when the clock signal source is switched from the first clock device 210 to the second clock device 220. A clock source is used for generating the second clock signal. The processing unit may be implemented by a processor, which may be a Digital Signal Processor (DSP). The second storage control device 240 may include a processing unit. The processing unit may perform the functions of phase locking and multi-cycle slow phase shifting of the second clock signal when the clock signal source is switched from the first clock device 210 to the second clock device 220. A clock source is used for generating the second clock signal. The processing unit may be implemented by a processor, which may be a Digital Signal Processor (DSP). Therefore, the consistency of the overall jitter of the clock at any moment is ensured, and the switching reliability of the clock signal source is improved.

Optionally, in some embodiments, memory device 250 may also phase lock and multi-cycle slow phase shift the second clock signal upon determining that the clock signal source is switched from first clock device 210 to second clock device 220. More specifically, the storage device 250 may include a processing unit. The processing unit may perform the functions of phase locking and multi-cycle slow phase shifting of the second clock signal when the clock signal source is switched from the first clock device 210 to the second clock device 220. A clock source is used for generating the second clock signal. The processing unit may be implemented by a processor, which may be a Digital Signal Processor (DSP). Therefore, the consistency of the overall jitter of the clock at any moment is ensured, and the switching reliability of the clock signal source is improved.

Optionally, in some embodiments, the storage device 250 may also send an alert message to the first storage control device 230 and an alert message to the second storage control device 240. The specific manner of sending the warning information and the content of the warning information may refer to the embodiment shown in fig. 1, and thus, details are not described herein.

Fig. 3 is a schematic block diagram of another memory system provided in accordance with an embodiment of the present invention. As shown in fig. 3, the storage system 300 includes: a first clock device 310, a second clock device 320, a first memory control device 330, a second memory control device 340, and a memory device 350. As shown in fig. 3, the first clock device 310 is connected to the first memory control device 330, the first clock device 310 is connected to the second memory control device 340, the first memory control device 330 is connected to the memory device 350, the second memory control device 340 is connected to the memory device 350, the second clock device 320 is connected to the first memory control device 330, and the second clock device is connected to the second memory control device 340.

The memory system 300 in fig. 3 differs from the memory system 200 shown in fig. 2 in that the memory system 300 is capable of transmitting the respective generated clock signals to each other by the first clock device 310 and the second clock device 320. The first clock means 310 is capable of performing all the functions of the first clock means 210. The second clock means 320 is capable of performing the full functionality of the second clock means 220. The first storage control device 330 is capable of implementing all functions of the first storage control device 230. The second storage control device 340 is capable of implementing all functions of the second storage control device 240. Storage device 350 is capable of performing all of the functions of storage device 250. Therefore, in describing the storage system 300 shown in FIG. 3, the same functions of the storage system 200 will not be described again. Only the functions that the storage system 300 can additionally implement are described herein.

The first clock device 310 may transmit the generated first clock signal to the second clock device 320.

The second clock device 320 may transmit the first clock signal to the first memory control device 330 and the second memory control device 340.

The second clock device 320 may also send the generated second clock signal to the first clock device 310.

The first clock device 310 may transmit the received second clock signal to the first memory control device 330 and the second memory control device 340.

Alternatively, in some embodiments, the first clock signal received by the first storage control device 330 may be sent directly to the first storage control device by the first clock device 310. Alternatively, in other embodiments, the first clock signal received by the first memory control device 330 may be forwarded by the second clock device 320. Thus, if the first memory control device 330 cannot directly receive the first clock signal from the first clock device 310, the first memory control device 330 may still receive the first clock signal forwarded by the second clock device 320. In other words, if the bus and/or port between the first clock device 310 and the first memory control device 330 for transmitting the first clock signal fails, the first memory control device 330 can still obtain the first clock signal from the second clock device 320.

Alternatively, in some embodiments, the first clock signal received by the second storage control device 340 may be sent directly to the first storage control device by the first clock device 310. Alternatively, in other embodiments, the first clock signal received by the second memory control device 340 may be forwarded by the second clock device 320. Thus, if the second memory control device 340 cannot receive the first clock signal directly from the first clock device 310, the second memory control device 340 may still receive the first clock signal forwarded by the second clock device 320. In other words, if the bus and/or port between the first clock device 310 and the second memory control device 340 for transmitting the first clock signal fails, the second memory control device 340 can still obtain the first clock signal from the second clock device 320.

Alternatively, in some embodiments, the second clock signal received by the first memory control device 330 may be sent directly to the first memory control device by the second clock device 320. Alternatively, in other embodiments, the second clock signal received by the first memory control device 330 may be forwarded by the first clock device 310. Thus, if the first memory control device 330 cannot receive the second clock signal directly from the second clock device, the first memory control device 330 may still receive the second clock signal forwarded by the first clock device 310. In other words, if the bus and/or port between the second clock device 320 and the first memory control device 330 for transmitting the second clock signal fails, the first memory control device 330 can still obtain the second clock signal from the first clock device 310.

Alternatively, in some embodiments, the second clock signal received by the second memory control device 340 may be sent directly to the second memory control device by the second clock device 320. Alternatively, in other embodiments, the second clock signal received by the second memory control device 340 may be forwarded by the first clock device 310. Thus, if the second memory control device 340 cannot receive the second clock signal directly from the second clock device, the second memory control device 340 may still receive the second clock signal forwarded by the first clock device 310. In other words, if the bus and/or port between the second clock device 320 and the second memory control device 340 for transmitting the second clock signal fails, the second memory control device 340 can still obtain the second clock signal from the first clock device 310.

The clock signal received by the memory device in the system shown in fig. 3 may provide redundancy guarantees. Thus, clock switching at the memory device level may be achieved. That is, if one pin of the memory device for receiving the clock signal fails, the memory device can read and write data using the clock signal received by the other pin for receiving the clock signal. Therefore, the reliability of the system is improved.

In addition, the system shown in FIG. 3 provides redundant assurance of the clock signal source. Thus, the system shown in FIG. 3 may also implement clock switching of the clock signal source stage. That is, if one clock signal source providing a clock signal fails, the system may switch the clock signal source to another clock device. Therefore, the reliability of the system is further improved.

Furthermore, the clock signal acquired by the memory control device in the system shown in fig. 3 may also provide redundancy. Thus, the system shown in FIG. 3 may also implement clock switching at the storage control device level. That is, if the memory controller cannot receive the first clock signal directly from the first clock device, the memory controller may receive the first clock signal forwarded by the second clock device. The memory controller may receive the second clock signal forwarded by the first clock device if the memory controller cannot receive the second clock signal directly from the second clock device. Therefore, the reliability of the system is further improved.

Fig. 4 is a schematic block diagram of another memory system provided in accordance with an embodiment of the present invention. As shown in fig. 4, the storage system 400 includes: a first clock device 410, a second clock device 420, a first memory control device 430, a second memory control device 440, and a memory device 450. As shown in fig. 4, the first clock device 410 is connected to the first memory control device 430, the first clock device 410 is connected to the second memory control device 440, the first memory control device 430 is connected to the memory device 450, the second memory control device 440 is connected to the memory device 450, the second clock device 420 is connected to the first memory control device 430, and the second clock device is connected to the second memory control device 440.

Memory system 300 in fig. 3 differs from memory system 400 shown in fig. 4 in that two buses for transmitting the respectively generated clock signals are included between first clock device 410 and second clock device 420 of memory system 400. The first clock means 310 is capable of performing all the functions of the first clock means 410. The second clock means 320 is capable of performing the full functionality of the second clock means 420. The first storage control device 330 can implement the entire functions of the first storage control device 430. The second storage control device 340 is capable of implementing all functions of the second storage control device 440. Memory device 350 is capable of performing all the functions of memory device 450. Therefore, in describing the memory system 400 shown in fig. 4, the same functions of the memory system 300 will not be described. Only the functions that the storage system 400 can additionally implement are described herein.

The first clock device 410 comprises a first port and a second port, the second clock device 420 comprises a third port and a fourth port, wherein the first port is connected to the third port, the second port is connected to the fourth port, and the first clock device 410 is specifically configured to transmit the first clock signal to the second clock device 420 through the first port or the second port; the second clock device 420 is specifically configured to send the second clock signal to the first clock device 410 through the third port or the fourth port. In this way, the first clock device 410 may transmit the first clock signal to the second clock device 420 through the second port even if the first port, the third port, or a bus for connecting the first port and the third port fails. The second clock means 420 is also able to receive the first clock signal via the fourth port. Similarly, the first clock device 410 may transmit the first clock signal to the second clock device 420 through the first port even if the second port, the fourth port, or a bus for connecting the second port and the fourth port fails. The second clock device 420 may also receive the first clock signal through a third port. Accordingly, even if the first port, the third port, or the bus for connecting the first port and the third port malfunctions, the second clock device 420 may transmit the second clock signal to the first clock device 410 through the fourth port. The first clock device 410 is also capable of receiving the first clock signal through the second port. Similarly, the second clock device 420 may transmit the second clock signal to the first clock device 410 through the third port even if the second port, the fourth port, or a bus for connecting the second port and the fourth port fails. The first clock device 410 may also receive the second clock signal through the first port.

The system shown in fig. 4 can implement clock switching at the level of the memory device, clock switching at the level of the clock signal source, and clock switching at the level of the memory control device. Further, there are redundant paths between two clock devices in the system shown in FIG. 4 for transmitting clock signals. If one of the paths fails, a clock signal may be transmitted through the other path. Therefore, the reliability of the system is further improved.

Further, each of the devices (i.e., the first clock device, the second clock device, the first storage control device, the second storage control device, and the storage device) in the systems of FIGS. 1-4 can support hot-plugging. If one device fails, the failed device can be directly replaced without powering off.

Further, the clock means and the memory control means in the systems of fig. 2 to 4 are present in pairs. Therefore, if one clock device fails or one storage control device fails, data held in the storage device can still be read and written normally.

Fig. 5 is a schematic diagram of the connection of the first clock device and the second clock device of the embodiment shown in fig. 4. As shown in fig. 5, the first clock device 410 includes a clock source unit 411 and a switching unit 412, and the second clock device 420 includes a clock unit 421 and a switching unit 422. The switch unit 412 shown in fig. 4 includes a stationary contact 413, a stationary contact 414, and a movable contact 415, and the switch unit 422 includes a stationary contact 423, a stationary contact 424, and a movable contact 425. The stationary contact 413 is connected to the clock unit 421, and the second clock signal generated by the clock unit 421 may be transmitted to the stationary contact 413. The stationary contact 414 is connected to the clock unit 411, and the first clock signal generated by the clock unit 411 may be transmitted to the stationary contact 414. The stationary contact 423 is connected to the clock unit 421, and the second clock signal generated by the clock unit 421 may be transmitted to the stationary contact 423. The stationary contact 424 is connected to the clock unit 411, and the first clock signal generated by the clock unit 411 may be transmitted to the stationary contact 424.

It is to be understood that fig. 5 describes the switch unit using the fixed contact and the movable contact only to more intuitively embody the switching of the clock signal source. It is known to the person skilled in the art that in a practical implementation the steps performed by the switching unit comprising the movable contacts and the stationary contacts may be implemented in other ways. For example, the source of the clock signal may be selected by software means. As another example, the clock signal source may be selected by way of a logic control circuit. The embodiment of the present invention does not specifically limit how the switch unit is implemented.

If a clock signal source is provided by the first clock device 410, the movable contact 415 in the switch unit 412 is connected to the stationary contact 414 and the movable contact 425 in the switch unit 422 is connected to the stationary contact 424. Thus, the clock signals output by the first clock means 410 and the second clock means 412 are both the first clock signal generated by the clock unit 411.

If a clock signal source is provided by the second clock means 420, the movable contact 415 in the switch unit 412 is connected to the stationary contact 413 and the movable contact 425 in the switch unit 422 is connected to the stationary contact 423. Thus, the clock signals output by the first clock device 410 and the second clock device 412 are the second clock signal generated by the clock unit 421.

It can be seen that the switch unit 412 and the switch unit 422 are switched in reciprocal linkage. In other words, if switch 412 is switched to the left (i.e., movable contact 415 is connected to stationary contact 413), then switch 422 must be switched to the right (i.e., movable contact 425 is connected to stationary contact 423); if switch 412 is switched to the right (i.e., moving contact 415 is connected to stationary contact 414), then switch 422 must be switched to the left (i.e., moving contact 425 is connected to stationary contact 424).

Furthermore, the first clock device 410 further comprises a processing unit (not shown in the figure) for performing phase locking and multi-cycle slow phase shifting in case of switching of the clock source signal. For example, in case the clock signal source is switched from the clock unit 411 to the clock unit 421, the processing unit is configured to perform phase locking and multi-cycle slow phase shifting on the second clock signal generated by the clock unit 421. As another example, in the case where the clock signal source is switched from the clock unit 421 to the clock unit 411, the processing unit is configured to perform phase locking and multi-cycle slow phase shifting on the first clock signal generated by the clock unit 411.

Similarly, the second clock device 420 further comprises a processing unit (not shown in the figure) for performing phase locking and multi-cycle slow phase shifting in case of switching of the clock source signal. For example, in case the clock signal source is switched from the clock unit 411 to the clock unit 421, the processing unit is configured to perform phase locking and multi-cycle slow phase shifting on the second clock signal generated by the clock unit 421. As another example, in the case where the clock signal source is switched from the clock unit 421 to the clock unit 411, the processing unit is configured to perform phase locking and multi-cycle slow phase shifting on the first clock signal generated by the clock unit 411.

It should be understood that "first" and "second" in the embodiments of the present invention are only for convenience of describing the technical solutions of the present application, and are not limited. For example, assuming that a memory system includes a clock device a and a clock device B, in some cases, the clock device a may be the first clock device and the clock device B may be the second clock device in the above embodiments, and in other cases, the clock device a may be the second clock device and the clock device B may be the first clock device in the above embodiments.

The storage control apparatus in the embodiment of the present invention may also be referred to as a storage controller. The memory control device includes a first port for connection to a first clock device and a second port for connection to a second clock device. The memory control device further comprises a switch unit for controlling the clock signal received from the first clock device through the first port or the clock signal received from the second clock device through the second port. The memory control device further comprises a processing unit which may be configured to perform phase locking and multi-cycle slow phase shifting in case it is determined that the clock signal source is switched from the first clock means to the second clock means. The processing unit may also be used for control of the storage means. The storage control device may further comprise an interface for connecting with a storage device.

It is to be understood that, in the embodiments of the present invention, the clock signal source is switched from the first clock device to the second clock device, which means that the clock signal finally sent to the storage device is changed from the first clock signal generated by the first clock device to the second clock signal generated by the second clock device. The fact that the memory control device receives the same clock signal from a different source (e.g., from directly receiving the first clock signal sent by the first clock device to receiving the first clock signal forwarded by the second clock device) is not a clock signal source switch as referred to in the embodiments of the present invention.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded or executed on a computer, cause the flow or functions according to embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more collections of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium may be a Solid State Drive (SSD).

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.