阅读说明：本技术 一种具测试接地功能的陶瓷电容器 (Ceramic capacitor with grounding test function ) 是由 黄景林 黄景明 于 2019-08-30 设计创作，主要内容包括：本发明涉及电子领域,提供一种具测试接地功能的陶瓷电容器,其包括第一引脚和第二引脚、第一陶瓷电容芯片和第二陶瓷电容芯片、导电连接件、测试接地连接段以及绝缘层。绝缘层用于将第一引脚、第一陶瓷电容芯片、导电连接件、第二陶瓷电容芯片、以及第二引脚包封住；所述第一陶瓷电容芯片和所述第二陶瓷电容芯片在平面中通过所述导电连接件左右连接,所述中间导电段相对于所述第一段和所述第二段向上隆起。本发明在使用时,陶瓷电容器只需要占据一个安装位即可实现两个电容器串联的效果。在提高电路线路的安全的同时,也以紧凑的结构避免了对电路板安装位置的消耗。增加了测试接地连接段,使得本发明具有测试、接地功能,且可作为单个电容使用。(The invention relates to the field of electronics, and provides a ceramic capacitor with a test grounding function. The insulating layer is used for encapsulating the first pin, the first ceramic capacitor chip, the conductive connecting piece, the second ceramic capacitor chip and the second pin; the first ceramic capacitor chip and the second ceramic capacitor chip are connected left and right in a plane through the conductive connecting piece, and the middle conductive section is upwards raised relative to the first section and the second section. When the invention is used, the ceramic capacitor only needs to occupy one mounting position to realize the effect of connecting two capacitors in series. The safety of the circuit line is improved, and the consumption of the installation position of the circuit board is avoided by a compact structure. The test grounding connection section is added, so that the invention has the functions of test and grounding and can be used as a single capacitor.)

1. A ceramic capacitor with a test grounding function, comprising:

the first pin and the second pin respectively comprise a connecting end and a pin end opposite to the connecting end;

the first ceramic capacitor chip and the second ceramic capacitor chip comprise a first surface and a second surface which are coated with metal films respectively and are opposite, and a ceramic dielectric layer between the first surface and the second surface;

the conductive connecting piece comprises a first section, a second section opposite to the first section, and a middle conductive section for connecting the first section and the second section;

the test grounding connection section is connected to the conductive connecting piece;

the insulating layer is used for encapsulating the first pin, the first ceramic capacitor chip, the conductive connecting piece, the second ceramic capacitor chip and the second pin; the pin end of the first pin is far away from the connecting end of the first pin and extends out of the shell; the pin end of the second pin is far away from the connecting end of the second pin and extends out of the insulating layer; the pin end of the first pin and the pin end of the second pin are positioned at the corner of the insulating layer at the far end relative to the test grounding connection section;

the connecting end of the first pin is connected with the first surface of the first ceramic capacitor chip; the second surface of the first ceramic capacitor chip is connected with the first section of the conductive connecting piece; the second section of the conductive connecting piece is connected with the second surface of the second ceramic capacitor chip; the first surface of the second ceramic capacitor chip is connected with the connecting end of the second pin;

the first ceramic capacitor chip and the second ceramic capacitor chip are connected left and right in a plane through the conductive connecting piece, and the middle conductive section is upwards raised relative to the first section and the second section.

2. The ceramic capacitor of claim 1, wherein the insulating layer is an epoxy insulating layer.

3. The ceramic capacitor of claim 1 wherein said first and second legs further comprise a fold between said leg end and said connection end, said fold forming an insulating enclosure by a fold configuration.

4. The ceramic capacitor according to claim 1, wherein the height of the intermediate conductive segment that is raised upward with respect to the first segment and the second segment is 0.3mm to 3 mm.

5. The ceramic capacitor of claim 1, wherein the pin end of the first pin and the pin end of the second pin are located at corners of the insulating layer distal to the test ground connection.

Technical Field

The invention relates to the field of electronics, in particular to a ceramic capacitor with a grounding test function.

Background

A ceramic capacitor is a capacitor having a ceramic as a dielectric. Generally, a ceramic capacitor includes a ceramic capacitor chip, two leads, and an insulating layer that encapsulates the aforementioned components. The ceramic capacitor usually works in a high-voltage environment, and the alternating-current working voltage of the ceramic capacitor can reach more than 10KV, or the direct-current working voltage of the ceramic capacitor can reach more than 40 KV. In such an operating environment, a short circuit of the line due to a capacitor failure would cause an unpredictable risk. For this reason, in the prior art, in order to improve safety, two capacitors are connected in series in a circuit. In this way, in the event that one of the capacitors fails while the other capacitor is still operating properly, the occurrence of a short circuit can be avoided. However, this approach requires at least two capacitor mounting locations to be reserved in the circuit. When the circuit board is integrated and the installation space of the components is reduced, it is obviously a deviation from the trend, which is not favorable for the development of circuit integration.

Disclosure of Invention

In order to solve the technical problems in the background art, the invention provides a ceramic capacitor with a grounding test function. The test ceramic capacitor is equivalent to two or more capacitors in series. When the capacitor is used, the effect of connecting two capacitors in series can be realized only by occupying one mounting position. The safety of the circuit line is improved, and the consumption of the installation position of the circuit board is avoided by a compact structure.

More specifically, the present invention is realized by:

a ceramic capacitor with a test ground function, comprising:

the first pin and the second pin respectively comprise a connecting end and a pin end opposite to the connecting end;

the first ceramic capacitor chip and the second ceramic capacitor chip comprise a first surface and a second surface which are coated with metal films respectively and are opposite, and a ceramic dielectric layer between the first surface and the second surface;

the conductive connecting piece comprises a first section, a second section opposite to the first section, and a middle conductive section for connecting the first section and the second section;

the test grounding connection section is connected to the conductive connecting piece;

the insulating layer is used for encapsulating the first pin, the first ceramic capacitor chip, the conductive connecting piece, the second ceramic capacitor chip and the second pin; the pin end of the first pin is far away from the connecting end of the first pin and extends out of the shell; the pin end of the second pin is far away from the connecting end of the second pin and extends out of the insulating layer; the pin end of the first pin and the pin end of the second pin are positioned at the corner of the insulating layer at the far end relative to the test grounding connection section;

the connecting end of the first pin is connected with the first surface of the first ceramic capacitor chip; the second surface of the first ceramic capacitor chip is connected with the first section of the conductive connecting piece; the second section of the conductive connecting piece is connected with the second surface of the second ceramic capacitor chip; the first surface of the second ceramic capacitor chip is connected with the connecting end of the second pin;

the first ceramic capacitor chip and the second ceramic capacitor chip are connected left and right in a plane through the conductive connecting piece, and the middle conductive section is upwards raised relative to the first section and the second section.

Further, the insulating layer is an epoxy resin insulating layer.

Furthermore, the first pin and the second pin further comprise a folding section between the pin end and the connecting end, and the folding section forms an insulating packaging space through a folding line structure.

Further, the height of the middle conductive segment which is raised upwards relative to the first segment and the second segment is 0.3 mm-3 mm.

Further, the pin end of the first pin and the pin end of the second pin are located at corners of the insulating layer far from the test ground connection section.

The invention has the advantage that two ceramic capacitor chips are connected in series and integrated into a single capacitor. In the use process, the effect of connecting two capacitors in series can be realized only by occupying one mounting position. The circuit line safety is improved, and the consumption of the installation position of the circuit board is avoided by a compact structure. Meanwhile, the two ceramic capacitor chips connected in series are transversely arranged and connected through the conductive connecting piece, so that a certain distance is formed between the two ceramic capacitor chips, the stability and the reliability of the whole capacitor are improved, and the space occupation in the vertical direction is reduced. Because the ceramic capacitor chip is transversely arranged, the whole capacitor is basically only the thickness of the ceramic capacitor chip in the longitudinal space, and the design advantage of a surface mount type is more facilitated. Meanwhile, a plurality of series capacitors are integrated on a transverse plane, so that the operation of once inserting is greatly improved and the installation efficiency is improved when the capacitor is used. The ceramic capacitor chips which are transversely arranged enlarge the connection distance between the two ceramic capacitor chips to a certain extent, and the influence of high temperature generated after one ceramic capacitor chip is broken down on the other ceramic capacitor chip is avoided.

However, after the series connection and integration insulating layer is packaged, when defective products appear, the specific location of the defective problems of the products is difficult to be searched. Therefore, the test grounding connection section is added, the two capacitors can be independently tested and checked through the test grounding connection section, and specific problems can be conveniently found, so that the processing flow is improved, and the yield is improved. Likewise, the test ground connection segment can also be used as a ground, further increasing safety. In addition, when the test grounding connection section is connected with the first pin or the second pin, the invention can be used as a conventional single capacitor. The pin ends of the first pin and the second pin are respectively positioned at the corner of the insulating layer opposite to the far end of the test grounding connecting section, so that the distance between the two pin ends and the test grounding connecting section is maximized, and the test effect is better.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts. Specifically, the method comprises the following steps:

FIG. 1 is a schematic structural view of a ceramic capacitor according to an embodiment of the present invention;

FIG. 2 is a front view of a ceramic capacitor according to an embodiment of the present invention;

FIG. 3 is a top view of a ceramic capacitor according to an embodiment of the present invention;

FIG. 4 is a bottom view of a ceramic capacitor according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a lead of a ceramic capacitor according to an embodiment of the present invention;

fig. 6 is a schematic view showing a structure in which a test ground connection section of a ceramic capacitor is wrapped with an insulating layer according to still another embodiment of the present invention.

Icon:

11-a first pin; 111-a pin end of a first pin; 112-the connection end of the first pin; 113 — fold of first pin; 12-a second pin; 121-a pin end of the second pin; 122 — a connection end of a second pin; 123-fold of second pin; 13-a first ceramic capacitor chip; 131-a first surface of a first ceramic capacitor chip; 132-a second surface of the first ceramic capacitor chip; 14-a second ceramic capacitor chip; 141-a first surface of a second ceramic capacitor chip; 142-a second surface of a second ceramic capacitor chip; 15-conductive connections; 151-first section; 152-a second section; 153-intermediate conductive segments; 16-an insulating layer; 17-test ground connection segment.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

In the description of the present invention, it is to be understood that the terms, "longitudinal," "upper," "lower," "front," "rear," "left," "right," "top," "bottom," "inner," "outer," etc., indicate orientations or positional relationships based on those illustrated in the drawings, and are used merely for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

As shown in fig. 1 to 6, the ceramic capacitor with a test ground function provided by the present invention includes a first lead 11, a second lead 12, a first ceramic capacitor chip 13, a second ceramic capacitor chip 14, a conductive connection member 15 and an insulating layer 16. The first and second leads 11 and 12 include a connection terminal and a pin terminal opposite to the connection terminal, respectively. The first ceramic capacitor chip 13 and the second ceramic capacitor chip 14 include a first surface and a second surface which are respectively coated with a metal thin film and are opposite to each other, and a ceramic dielectric layer interposed between the first surface and the second surface. The conductive connecting member 15 includes a first segment 151 and a second segment 152 opposite to the first segment 151, an intermediate conductive segment 153 connecting the first segment 151 and the second segment 152; the insulating layer 16 is used for encapsulating the first pin 11, the first ceramic capacitor chip 13, the conductive connecting piece 15, the second ceramic capacitor chip 14 and the second pin 12; the pin end 111 of the first pin is remote from the connection end 112 of the first pin and extends outside the housing; the pin end 121 of the second pin is remote from the connection end 122 of the second pin and extends outside the insulating layer 16. Wherein the connection end 112 of the first lead is connected with the first surface 131 of the first ceramic capacitor chip; the second surface 132 of the first ceramic capacitor chip is connected to the first segment 151 of the conductive connection member 15; the second segment 152 of the conductive connector 15 is connected to the second surface 142 of the second ceramic capacitor chip; the first surface 141 of the second ceramic capacitor chip is connected to the connection terminal 122 of the second lead. The first ceramic capacitor chip 13 and the second ceramic capacitor chip 14 are connected left and right in a plane through the conductive connecting piece 15, and the plane is a description of being arranged up and down relative to the ceramic capacitor chips and is not limited; the middle conductive segment 153 is upwardly bulged with respect to the first segment 151 and the second segment 152 so that the conductive connection member 15 forms an insulation filling space with the first ceramic capacitor chip 13 and the second ceramic capacitor chip 14.

The ceramic capacitor chips which are transversely arranged enlarge the connection distance between the two ceramic capacitor chips to a certain extent, and the influence of high temperature generated after one ceramic capacitor chip is broken down on the other ceramic capacitor chip is avoided. In the illustration of the present embodiment, the ceramic capacitor chip is arranged in the left-right lateral direction. But in other embodiments may be arranged in tandem. The transverse arrangement in the present invention is understood to mean a parallel arrangement in a transverse plane, and is not limited to right and left or front and back.

The capacitor chip illustrated in the drawings is circular, but the shape of the capacitor chip is not particularly limited in the present invention. In theory, a square or other regular or irregular capacitor chip can also be used as the capacitor chip not described in the invention, as long as the effect of the capacitor chip can be achieved. Preferably, as described in the invention, a circular capacitor chip may be employed.

In some embodiments, the metal film may be a silver electrode layer. This is not limited in this specification, and in other embodiments, the metal thin film may be other conductive electrode layers, such as a copper electrode layer. In some embodiments, the insulating layer 16 is a package that is coated with a thermoplastic or thermosetting resin by painting, dipping, spraying, etc. to cover the entire outer surface of the capacitor element as a protective coating or insulating layer 16. The insulating layer 16 may be an epoxy insulating layer.

In some embodiments, as shown in fig. 1, a test ground connection segment 17 is connected to the conductive connection 15.

As shown in fig. 6, the pin end 111 of the first pin and the pin end 121 of the second pin are located at the corner of the insulating layer 16 opposite to the far end of the test ground connection section 17, so that the distance between the two pin ends and the test ground connection section 17 is maximized to achieve better test effect.

As shown in fig. 6, during initial assembly or factory quality inspection, the test ground connection section 17 may extend along the test ground connection section 17 on the housing to the outside of the insulating layer 16, and at this time, the conduction test may be performed through the test ground connection section 17 extending to the outside of the insulating layer 16.

In some embodiments, the first segment 151 of the conductive connection 15 is fixedly connected to the second surface 132 of the first ceramic capacitor chip by solder, and the second segment 152 is fixedly connected to the second surface 142 of the second ceramic capacitor chip by solder.

In some embodiments, as shown in fig. 5, the first lead 11 and the second lead 12 further include a folded section between the plug end and the connection end, so that the leads avoid the edge of the ceramic capacitor and avoid the occurrence of a discharge phenomenon, and the folded section 113 of the first lead and the folded section 123 of the second lead form an insulating encapsulation space through a folded line structure. Preferably, the height of the middle conductive segment 153 that is raised upward with respect to the first segment 151 and the second segment 152 is 0.3mm to 3 mm. More preferably, the height of the middle conductive segment 153 that is raised upward with respect to the first segment 151 and the second segment 152 is 2mm to 2.8 mm. In this embodiment, the height of the middle conductive segment 153 that is raised upward relative to the first segment 151 and the second segment 152 is 2.5mm, and the middle conductive segment is raised upward to form a filling space, so that the insulating layer 16 can better enter the filling space, and discharge between the middle conductive segment 153 and the ceramic capacitor chip can be prevented.

In order to facilitate understanding of the present embodiment, the insulating layer 16 in fig. 2 is shown as a transparent layer, so as to more specifically understand the relationship between the insulating layer 16 and the internal components such as the ceramic capacitor chip. It is understood that in practice the insulating layer 16 may be a non-transparentized encapsulant material.

In the embodiment shown in fig. 1-6, the prong end 111 of the first prong and the prong end 121 of the second prong are bent inward facing each other. In the embodiment shown in fig. 6, the pin end 111 of the first pin and the pin end 121 of the second pin may be bent outward away from each other. It can be understood that the bending mode of the pin end can be changed according to the specific use scene.

It should be noted that in the above embodiments, only the case where two ceramic capacitor chips are included in the lateral plane is explained. But in other embodiments, combinations of three or even more ceramic capacitor chips may be included. The connection method between the ceramic capacitor chips is the same as the connection scheme described in the above embodiments, and therefore, the description thereof is omitted.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.