阅读说明：本技术 使用晶片到晶片接合的具有共享控制电路的三维（3d）闪存存储器 (Three-dimensional (3D) flash memory with shared control circuitry using wafer-to-wafer bonding ) 是由 R·法斯托 K·哈斯纳特 P·马吉 O·容格罗特 于 2019-05-17 设计创作，主要内容包括：本文公开了使用晶片到晶片接合的具有共享CMOS电路的三维(3D)闪存存储器。晶片到晶片接合用于形成三维(3D)存储器部件,例如在一个管芯上具有共享控制电路以访问多个管芯上的阵列的3D NAND闪存存储器。在一个示例中,非易失性存储装置包括第一管芯,该第一管芯包括非易失性存储单元的3D阵列和CMOS(互补金属氧化物半导体)电路。第二管芯与第一管芯垂直堆叠并接合,该第二管芯包括非易失性存储单元的第二3D阵列。第一管芯的CMOS电路的至少一部分用于访问第一管芯的非易失性存储单元的第一3D阵列和第二管芯的非易失性存储单元的第二3D阵列。(Three-dimensional (3D) flash memory with shared CMOS circuitry using wafer-to-wafer bonding is disclosed herein. Wafer-to-wafer bonding is used to form three-dimensional (3D) memory components, such as 3D NAND flash memory having shared control circuitry on one die to access arrays on multiple dies. In one example, a non-volatile memory device includes a first die that includes a 3D array of non-volatile memory cells and CMOS (complementary metal oxide semiconductor) circuitry. A second die is vertically stacked and bonded with the first die, the second die including a second 3D array of non-volatile memory cells. At least a portion of the CMOS circuitry of the first die is used to access a first 3D array of non-volatile memory cells of the first die and a second 3D array of non-volatile memory cells of the second die.)

1. A non-volatile storage device, comprising:

a first die comprising a first three-dimensional (3D) array of non-volatile memory cells and CMOS (complementary metal oxide semiconductor) circuitry; and

a second die vertically stacked and bonded with the first die, the second die including a second 3D array of non-volatile memory cells, at least a portion of the CMOS circuitry of the first die being used to access the first 3D array of non-volatile memory cells of the first die and the second 3D array of non-volatile memory cells of the second die.

2. The non-volatile storage apparatus of claim 1, wherein:

the CMOS circuitry of the first die is disposed between the first 3D array of non-volatile memory cells and the second 3D array of non-volatile memory cells.

3. The non-volatile storage apparatus of claim 2, wherein:

the second die also includes second CMOS circuitry for accessing the first 3D array and the second 3D array of non-volatile memory cells.

4. The non-volatile storage apparatus of claim 3, wherein:

a portion of a shared CMOS circuit is included in the first CMOS circuit of the first die and a remaining portion of the shared CMOS circuit is included in the second CMOS circuit of the second die, the shared CMOS circuit including one or more of a charge pump, a static page buffer, an IO, control logic, and a string driver.

5. The non-volatile storage apparatus of claim 3, wherein:

shared string driver circuitry for accessing the first 3D array and the second 3D array of non-volatile memory cells; and

a portion of the string driver circuits for the first 3D array and the second 3D array of non-volatile memory cells are included in the CMOS circuit of the first die and a remaining portion of string driver circuits are included in the second CMOS circuit of the second die.

6. The non-volatile storage apparatus of claim 4, wherein:

the portion of the shared CMOS circuit on the first die includes a first type of transistor and the remaining portion of the shared CMOS circuit on the second die includes a second type of transistor.

7. The non-volatile storage apparatus of claim 6, wherein:

the first class of transistors includes high voltage transistors and the second class of transistors includes low voltage transistors.

8. The non-volatile storage apparatus of claim 1, further comprising:

a third die vertically stacked and bonded with the first die or the second die, the third die including a third 3D array of non-volatile memory cells, the CMOS circuitry of the first die to access the third 3D array of non-volatile memory cells.

9. The non-volatile storage apparatus of claim 3, wherein:

the layers of the first die are arranged in reverse order relative to the second die;

conductive contacts of the CMOS circuit of the first die are bonded with conductive contacts of the second CMOS circuit of the second die.

10. The non-volatile storage apparatus of claim 3, further comprising:

a bond pad between a conductive contact of the first CMOS circuit and a conductive contact of the second CMOS circuit.

11. A system, comprising:

a processor; and

a non-volatile storage device coupled with the processor, the storage device comprising:

a first die comprising a first three-dimensional (3D) array of non-volatile memory cells and CMOS (complementary metal oxide semiconductor) circuitry for accessing the first 3D array of non-volatile memory cells; and

a second die vertically stacked and bonded with the first die, the second die including a second 3D array of non-volatile memory cells, the CMOS circuitry of the first die to access the second 3D array of non-volatile memory cells of the second die.

12. The system of claim 11, wherein:

the CMOS circuitry of the first die is disposed between the first 3D array of non-volatile memory cells and the second 3D array of non-volatile memory cells.

13. The system of claim 12, wherein:

the second die also includes second CMOS circuitry for accessing the first 3D array and the second 3D array of non-volatile memory cells.

14. The system of claim 13, wherein:

a portion of a shared CMOS circuit is included in the first CMOS circuit of the first die and a remaining portion of the shared CMOS circuit is included in the second CMOS circuit of the second die, the shared CMOS circuit including one or more of a charge pump, a static page buffer, an IO, control logic, and a string driver.

15. The system of claim 13, wherein:

shared string driver circuitry for accessing the first 3D array and the second 3D array of non-volatile memory cells; and

a portion of the string driver circuits for the first 3D array and the second 3D array of non-volatile memory cells are included in the CMOS circuit of the first die and a remaining portion of string driver circuits are included in the second CMOS circuit of the second die.

16. The system of claim 14, wherein:

the portion of the shared CMOS circuit on the first die includes a first type of transistor and the remaining portion of the shared CMOS circuit on the second die includes a second type of transistor.

17. The system of claim 16, wherein:

the first class of transistors includes high voltage transistors and the second class of transistors includes low voltage transistors.

18. The system of claim 11, further comprising:

a third die vertically stacked and bonded with the first die or the second die, the third die including a third 3D array of non-volatile memory cells, the CMOS circuitry of the first die to access the third 3D array of non-volatile memory cells.

19. A three-dimensional (3D) NAND memory device, comprising:

a first die comprising a first three-dimensional (3D) array of non-volatile NAND memory cells and control circuitry; and

a second die vertically stacked and bonded with the first die, the second die including a second 3D array of non-volatile NAND memory cells, at least a portion of the control circuitry of the first die being used to access the first 3D array of non-volatile NAND memory cells of the first die and the second 3D array of non-volatile NAND memory cells of the second die.

20. The three-dimensional (3D) NAND memory device of claim 19, wherein:

the control circuitry of the first die is disposed between the first 3D array of non-volatile NAND memory cells and the second 3D array of non-volatile NAND memory cells.

Technical Field

The present description relates generally to three-dimensional (3D) memories and storage devices, and more particularly, to forming 3D flash memories with shared CMOS circuitry using wafer-to-wafer bonding.

Background

Flash memory storage, such as NAND flash memory, is a non-volatile storage medium. The nonvolatile storage refers to storage having a certain state even if power of the device is interrupted. Flash memory may be used as memory (e.g., system memory) or as a storage device. There is a trend across systems on the mobile side, the client side, and the enterprise sector to use flash memory for storage (e.g., such as Solid State Drives (SSDs)). One type of NAND flash memory is three-dimensional (3D) NAND flash memory, in which vertical NAND strings make up a memory array. Although 3D NAND flash memory arrays can store more bits than two-dimensional (2D) NAND in a given area, there has been an interest in denser, faster, and more energy efficient data storage.

Drawings

The following description includes a discussion of illustrative figures having implementations of embodiments of the invention that are presented by way of example. The drawings should be understood by way of example and not by way of limitation. As used herein, references to one or more "embodiments" or "examples" should be understood to describe a particular feature, structure, and/or characteristic included in at least one embodiment of the invention. Thus, phrases such as "in one embodiment" or "in an example" appearing herein describe various embodiments and implementations of the invention, and do not necessarily all refer to the same embodiment. However, they are also not necessarily mutually exclusive.

Fig. 1A shows a cross section of an example of a 3D flash memory storage component with shared CMOS circuitry formed using wafer bonding.

Fig. 1B shows a cross section of an example of a 3D flash memory storage component with shared CMOS circuitry formed using wafer bonding.

Fig. 2A shows a cross-section of an example of a 3D flash memory storage component with two wafers bonded substrate-to-substrate.

Fig. 2B shows a cross-section of an example of a 3D flash memory storage component with two dies with top metal to top metal bonding.

Fig. 3A illustrates an example of a technique for stack bonding 3D flash memory die in a package.

Fig. 3B illustrates an example of a technique for stack bonding 3D flash memory die in a package.

Fig. 4A shows a top view of a chip plan showing CMOS circuitry for accessing a 3D flash memory array.

Fig. 4B shows a top view of a chip plan view showing shared CMOS circuitry for accessing a 3D flash memory array using wafer-to-wafer bonding.

Fig. 5 is a flow chart of an example of a method of forming a 3D flash memory storage component having a shared CMOS circuit and a plurality of dies bonded together via wafer-to-wafer bonding.

Fig. 6A, 6B, 6C, and 6D show examples of 3D flash memory components with shared CMOS circuitry in various processing stages.

Fig. 7 shows an example of a block diagram of a flash memory device in which wafer bonding and sharing of CMOS circuitry may be implemented.

Fig. 8 provides an exemplary depiction of a computing system in which wafer bonding and sharing CMOS circuitry may be implemented.

The following description of certain details and implementations, including the description of the figures that may depict some or all of the embodiments described below, and discusses other possible embodiments or implementations of the inventive concepts presented herein.

Detailed Description

Techniques for forming three-dimensional (3D) memory components with shared control circuitry using wafer-to-wafer bonding are described herein.

One type of 3D memory is 3D flash memory, which may also be referred to as 3D flash storage. One example of a 3D flash memory is a 3D NAND (non-AND) flash memory. The 3D memory includes one or more arrays of memory cells and control circuitry for accessing the memory cells. Typically, the control circuitry for accessing the 3D flash memory array comprises CMOS (complementary metal oxide semiconductor) circuitry. The control or CMOS circuitry may also be referred to as "periphery". A typical 3D flash memory device includes one or more arrays and separate CMOS circuitry for controlling each array. CMOS circuitry is generally considered overhead, which reduces the area available for memory cells.

In contrast to conventional 3D flash memory, the 3D flash memory components described herein include shared CMOS circuitry. The shared CMOS circuitry controls or enables access to the memory array on multiple dies. In one example, multiple wafers are processed individually. At least one of the wafers includes shared CMOS circuitry. The wafers are vertically stacked and bonded together. Interconnects couple the shared CMOS circuitry with the arrays on two or more wafers. Only one wafer in the stack or multiple wafers in the stack may include shared CMOS circuitry for accessing the array on the multiple wafers. In one example, the plurality of wafers each include shared CMOS circuitry. In one example where both dies include shared CMOS circuitry, a portion (e.g., half) of the string driver circuitry is located in the CMOS circuitry of one die and the remainder of the string driver circuitry is located in the CMOS circuitry of the other die. In one such example, string driver circuits located on two dies are used to access the arrays on both dies. Other types of CMOS circuitry may be separated and shared between multiple wafers, or shared and located on only one of the wafers.

Thus, wafer-to-wafer bonding is used to connect the peripheral regions of two or more dies together so that the same peripheral area and power can be shared over more than one die. Sharing the same peripheral circuitry across multiple dies results in reduced die area and reduced power. This means lower cost per Gigabyte (GB) and lower power for the same performance.

Fig. 1A shows a cross section of an example of a 3D flash memory storage component with shared CMOS circuitry formed using wafer bonding. The component in fig. 1A includes two dies 200A and 200B bonded together. Bonding the two dies 200A and 200B together may be accomplished by bonding together a wafer including the dies and then dicing the wafer. Each of the two dies 200A and 200B includes a flash memory array and CMOS circuitry for controlling and accessing the array.

Referring to die 200B, the memory array includes memory cells (e.g., memory cells formed at pillars 256B) and conductive access lines that enable access to the memory cells (e.g., bit line 264B (which is out of the page in fig. 1A), word line 220B, SGS (select gate source) 252B, SGD (select gate drain) 260B). In the illustrated example, source plate 250B is located between pillar 256B and conductive interconnect 226B. Between the CMOS circuitry and the array, each die includes conductive interconnects to couple the array with the CMOS circuitry. For example, referring to die 200B, interconnect 226B couples CMOS circuit 201B with array 203B. In the illustrated example, a poly (polysilicon) layer 236B is between the conductive interconnect 226B and the CMOS circuitry. The additional conductive layers (e.g., 212B, 218B and vias 202B, 204B, 206B, 208B, 224B, 262B, and 266B) enable coupling the array to CMOS circuitry or coupling the CMOS circuitry to other circuitry external to the memory component. In the illustrated example, the vias are coupled with word line 220B in a staggered or stepped configuration. Die 200A also includes array 203A and interconnects 226A, which may be the same as or similar to those of die 200B. In the example shown in fig. 1A, the features of die 200A are flipped or mirrored relative to die 200B.

In the example shown in FIG. 1A, arrays 203A and 203B are 3D flash memory arrays. Arrays 203A and 203B may be constructed using three-dimensional (3D) circuitry such that the memory cells are constructed on top of a substrate. Such 3D circuit technology may use the substrate as a mechanical base for the memory array without using the substrate itself for the circuitry of the memory array. In other examples, portions of the array may be formed in the substrate. The array may include any type of 3D memory, such as floating gate flash memory, charge trapping (e.g., replacement gate) flash memory, phase change memory, resistive memory, ovonic memory, ferroelectric transistor random access memory (FeTRAM), nanowire memory, or any other 3D memory. In one example, the 3D flash memory array is a stacked NAND flash memory array that stacks a plurality of floating gate or charge trapping flash memory cells in a vertical stack that is wired in a NAND (non-AND) manner. In another example, the 3D flash memory array includes NOR (non-OR) memory cells.

In the example shown in FIG. 1A, arrays 203A and 203B include pillars that form memory cells, such as NAND flash memory cells. Fig. 1A shows two stacked layers on each die, where each stacked layer includes multiple levels (layers). However, other examples may include arrays having one stack or more than two stacks. In examples where the memory cell includes a floating gate transistor, the cell may be programmed by charging the floating gate of the memory cell. The floating gate typically comprises a conductive or semiconductor material. In examples where the memory cell includes charge trapping, the memory cell can be programmed by storing charge in the charge trapping. Charge traps typically comprise an insulating material (e.g., silicon nitride or another insulating material capable of storing charge). Other memory cell technologies for implementing the storage of data may also be used.

Below the array 203B is a control circuit 201B. In one example, the control circuit 201B includes CMOS circuitry (and is therefore referred to as "CMOS under array" or CuA). In one such example, CMOS circuitry is first formed in substrate 240B, conductive interconnects are then formed over CMOS circuitry 201B, and then array 203B is built on top of interconnects 226B and CMOS circuitry 201B. CMOS circuitry may also be formed alongside the memory array. In one such example, a portion of the substrate is used to build the array and another portion of the substrate is used to build a CMOS circuit adjacent to the array, and there is an interconnect between the CMOS circuit and the array. One advantage of forming the CMOS circuitry under the array rather than beside the array is that the overall chip area is reduced. In another example, the CMOS circuitry may be located partially under the array and partially beside the array. Whether the control circuitry is below or beside the array, the control circuitry may be referred to as "peripheral".

Control circuitry 201A and 201B includes circuitry for controlling access to arrays 203A and 203B. The control circuits 201A and 201B include one or more of the following: address decoders, line drivers, sense amplifiers, charge pumps, state machines, buffers, or various other types of circuits. The control circuits 201A and 201B typically include transistors. In one example, the control circuits 201A and 201B include n-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), p-channel MOSFETs, or both. Control circuits 201A and 201B may also include multiple routes 248A and 248B, respectively. Control circuits 201A and 201B are coupled to the access lines using vias to allow electrical communication between control circuits 201A and 201B and the access lines to enable access to the memory cells. The conductive access lines, conductive interconnects, and vias are formed of conductive (e.g., metal) or semiconductive materials to enable electrical coupling between the components.

The 3D flash memory storage component in fig. 1A includes a second die 200A underlying die 200B and bonded to die 200B. Thus, unlike conventional 3D flash memory storage components that include a single die, multiple dies (each having multiple layers or tiers) are stacked and bonded together. The dies 200A and 200B are bonded together by a wafer-to-wafer bonding process. In the example shown in fig. 1A, one of the wafers is flipped prior to bonding such that CMOS circuit 201A of die 200A faces CMOS circuit 201B of die 200B. Note that even though CMOS circuitry 201A appears "above" the array as shown in fig. 1A, wafer 200A may still be considered a CMOS (cua) implementation below the array because the array is formed above the CMOS circuitry before the wafer is flipped. The CMOS circuit 201B of die 200B and the CMOS circuit 201A of die 200A are electrically coupled together by a wafer-to-wafer bonding process. In the illustrated example, a wafer bond pad 242 is included between the two dies 200A and 200B. In the example shown in fig. 1A, a wafer bond pad is applied to each wafer (e.g., the bond pads are applied to the wafer including die 200A and the wafer including die 200B), and the wafers are bonded together at wafer bond pad 242. In one such example, any space between wafers (e.g., between bond pads in the x-direction and between wafers in the y-direction) may be air or filled with a filler material such as an insulator to provide structural support.

Although the illustrated example includes bond pads 242 between dies 200A and 200B, the bond pads may or may not be used to bond wafers. In an example without bond pads, any conductive surface exposed at the bottom of one wafer may be bonded to a conductive surface exposed at the top of another wafer. For example, the exposed conductive interconnect surfaces (e.g., surfaces 251A and 251B) of each wafer may be bonded together. Thus, the bond may include a "via-to-via" or "metal-to-metal" bond without an intervening bond pad. Very good alignment of the die (e.g., alignment of conductive interconnect surface 251A with surface 251B) enables bonding of the wafer without bond pads. In examples with bond pads, smaller bond pads (e.g., smaller in the x and z directions) than conventional bond pads enable CMOS circuitry to be coupled to each of the dies 200A and 200B. Bond pads used for wafer-to-wafer bonding are smaller than standard bond pads because there are many signals to bond. Smaller pads are challenging because alignment requirements are very stringent. In one example, the bond pad has a dimension that is about the contact dimension. In one such example, bond pad 242 has a width of 0.5 microns or less compared to a conventional bond pad having a width of 10 microns or more.

Stacking and bonding the dies together may enable sharing of the control circuitry in various ways to reduce the area occupied by the control circuitry, improve performance, and/or reduce power consumption. As a result of the electrical connection by the bonded contacts (via bond pads 242 in the illustrated example), the peripheral regions of the top and bottom wafers can be shared and the duplicate circuitry removed. Removing duplicate circuitry helps to fit the peripheral circuitry under the array and reduces the power consumed by the CMOS circuitry. One or more of the dies may include control circuitry. In the example shown in FIG. 1A, both arrays 200A and 200B include control circuitry. In the case where both dies include control circuitry, at least one die includes shared circuitry; however, multiple (up to all) dies may include shared circuitry. Sharing circuitry may involve splitting the circuitry across the dies (e.g., including half of the string driver on one die and half of the string driver on the other die) or forming one type of control circuitry on one of the dies and a different type of control circuitry on the other die (e.g., a string driver on one of the dies and a page buffer on the other die, or any other division of control circuitry). In one example, top die 200B includes a charge pump, a static page buffer, half of a string driver, and IO. The bottom die 200A includes control logic, a static page buffer, half of a string driver, and pads. The electrical connections through the bond pads enable both dies to access the CMOS on both wafers.

In one example, different classes of transistors (e.g., High Voltage (HV) transistors or Low Voltage (LV) transistors) are placed on two different wafers. Forming different classes of transistors on different wafers may reduce cost by forming more expensive classes of transistors (e.g., HV transistors) on only one (or less than all) of the wafers. In one example, the charge pump, string driver, and voltage regulator use high voltage transistors with thick gate oxides. Logic circuits, data path circuits, and static page buffers use high-speed, low-voltage devices with thin gate oxides. Thus, in one example, CMOS circuitry on one wafer includes one or more of a charge pump, string driver, and voltage regulator, and does not include circuitry that uses low voltage devices (e.g., logic circuitry, data path circuitry, and static page buffers). In this example, the CMOS circuitry on the other wafer would include circuitry that uses low voltage devices (e.g., one or more of logic circuitry, data path circuitry, and static page buffers) and would not include circuitry that uses high voltage devices (e.g., charge pumps, string drivers, and voltage regulators).

In another example (not shown), one die consists of an array plus CMOS, while the second die contains only an array. This reduces the processing cost of the second wafer and the total cost per Gigabyte (GB), although it is accompanied by a performance degradation.

Fig. 1B shows a cross section of another example of a 3D flash memory storage component with shared CMOS circuitry formed using wafer bonding. The 3D flash memory storage component in fig. 1B is similar to the component in fig. 1A, except that the dies in fig. 1B are stacked and bonded without flipping one of the dies. Thus, die 200C and 200D have the same orientation. Due to the orientation and bonding location of the die, the CMOS circuit 201C of the die 200C and the CMOS circuit 201D of the die 200D are not adjacent to each other. Thus, to share CMOS circuitry between two dies, vias are used to electrically couple the CMOS circuitry of the dies. In the example shown in FIG. 1B, there is no single via directly connecting the CMOS circuitry. The wafer is bonded to via 227D, but must pass through several metal and via layers (e.g., conductive interconnect 218C).

Also, in contrast to the example shown in fig. 1A, fig. 1B shows an example without a bond pad. Thus, die 200C and die 200D are bonded together at the exposed bottom surface of via 227D and the exposed upper surface of bitline 264C. The area between the joints may be air or may be filled with an insulating material. In the illustrated example, some of the metal layers and the passivation layer may be eliminated. For example, die 200C does not include additional metal layers and passivation layers (such as conductive interconnects 212B and passivation layer 210B of fig. 1A) over bit lines 264C. Unlike conventional 3D NAND devices, metal 212D on top of array 203D may also be used to access circuitry on die 200C (in addition to being used for die 200D), and thus may eliminate the additional metal layer for die 200C. Thus, although the illustrated example may reduce cost by eliminating one or more layers, the connection between the CMOS circuits of the two dies is longer than if one of the dies were flipped relative to the other die.

Similar to fig. 1A, the components in fig. 1B include shared CMOS circuitry. The CMOS circuits 201C, 201D, or both, may include shared circuitry for accessing the array 203C on the first die 200C and the array 203D on the die 200D. Thus, fig. 1A and 1B illustrate two different examples of using wafer bonding to share peripheral circuitry between two or more dies. As previously mentioned, the use of wafer-to-wafer bonding is not limited to two dies. By fabricating vias across the thinned die, connections can be made through a stack of multiple dies. This enables the periphery to be shared across multiple dies, which can be used to further reduce die area and power consumption. An additional benefit of this approach is that packaging costs can be reduced since connections between the dies are already present. Sharing peripheral circuitry between two or more independent dies may enable reducing die size and increasing (e.g., doubling) the number of planes in each die in CuA-constrained designs. The memory cells in a 3D NAND memory are grouped into planes (e.g., where a plane typically includes 16 kbytes, but may be smaller or larger in size). All bits in a plane are read or written in parallel. A user can read or write multiple planes in parallel, thus having more planes provides the user with better performance. The shared peripherals may also achieve power/performance improvements. For example, if the number of planes is increased, the throughput/power is higher because the peripheral power consumption is amortized over a larger number of planes. Even where the die is not necessarily limited by CuA, wafer-to-wafer bonding and sharing CMOS circuitry may enable other optimizations, such as reducing die footprint. For example, if the die is too large to fit into a package, the die may be divided into two dies and then the two dies bonded together (e.g., as discussed below with reference to fig. 4B).

Fig. 2A and 2B also show cross-sections of examples of 3D flash memory storage components. Fig. 2A shows a 3D flash memory component with two wafers with substrate-to-substrate bonding, and fig. 2B shows a 3D flash memory component with two wafers with top metal-to-top metal bonding. Thus, the components in FIG. 2A are similar to those shown in FIG. 1A in that one of the wafers is flipped so that the CMOS circuits of the wafers face each other.

Similar to fig. 1A and 1B, the 3D flash memory components in fig. 2A and 2B each include two dies, each including a memory array and CMOS circuitry, bonded together via wafer bonding. For example, fig. 1A shows dies 280A and 280B. Referring to die 280A, CMOS circuit 282A underlies array 281A and there are conductive interconnects 284A coupling array 281A with CMOS circuit 282A. The CMOS circuit 282A may be the same as or similar to the CMOS circuit described with respect to fig. 1A and 1B. Similarly, die 280B includes CMOS circuitry 282B "beneath" array 281B and coupled with conductive interconnects 284B.

In the example shown in fig. 2A, CMOS circuits 282A and 282B across die 280A and 280B include shared string drivers 288A and 288B. The string driver includes transistors for driving word lines of the arrays 281A and 281B. A conventional 3D flash memory storage unit will include a string driver circuit dedicated to driving only the array on the die. In contrast, in the example shown in fig. 2A, half of the string drivers are on one die and the other half of the string drivers are on the other die, with the string drivers on both dies driving the array on both dies. For example, a string driver for driving odd word lines may be on the top die 280A and a string driver for driving even word lines may be on the bottom die 280B (or vice versa). Thus, driving odd and even word lines in an array of one of the dies is accomplished using string drivers on both dies. Thus, the string drivers for driving the word lines on die 280A and the word lines on die 280B are located on both dies. In contrast, conventional 3D flash memory devices utilize string drivers to drive even and odd word lines on the same die as the array and word lines being driven. Thus, for both arrays, the conventional component would include twice as many string drivers as the example of fig. 2A.

In the example shown in fig. 2A, the components include vias 286A and 286B through the CMOS circuitry and the substrate to couple the CMOS circuitry 282A with the CMOS circuitry 282B. Typically, vias are not formed through the CMOS, but rather are formed over the CMOS to couple the CMOS to the array (for CuA). Forming vias through CMOS presents potential challenges. For example, different voltages between the substrate and the vias may result in parasitic current paths from the string driver to the substrate. To prevent potential leakage, insulating liners may be added to the vias in CMOS. In addition, because each string driver is driving a higher capacitance (e.g., doubling the capacitance as compared to a conventional string driver), the string driver of fig. 2A includes larger transistors as compared to a conventional string driver. Also, the example shown in fig. 2A enables improved routing and increased signal density relative to conventional 3D flash memory storage components. For example, routing in string drivers is improved because all metal lines in both dies can be combined for routing of word lines.

Fig. 2B also shows the two wafers bonded together, but the wafers are bonded with top metal layers 290C and 290D facing each other. Although metal layers 290C and 290D are shown in fig. 2B, one of metal layers 290C or 290D may be eliminated. Eliminating one of the metal layers may reduce cost (in terms of materials and processing). Because metal layers 290C and 290D are between arrays 281C and 281D and between CMOS circuits 282C and 282D, the example in fig. 2B does not include through-CMOS vias. Thus, the components shown in fig. 2B do not face the challenges mentioned above with respect to fig. 2A with respect to potential current leakage due to the through CMOS vias. However, the lack of through-component vias for coupling the CMOS circuitry of each die presents other potential challenges. Other interconnects, external to the array or through the array, couple CMOS circuits 282C and 282D. Thus, CMOS is not directly connected to the vias, but through many (up to all) of the metal/via stacks in both dies. In this example, wafer-to-wafer bonding only connects the top portions of the metal stacks together.

Similar to the components shown in fig. 2A, although fig. 2B does not show bond pads between conductive interconnects 290C and 290D, bond pads similar to or the same as bond pads 242 of fig. 1A may be included. The 3D flash memory storage component may also include bond pads at the top and/or bottom to couple the component with circuitry external to the component (e.g., at the package level). To couple the conductive interconnects 290C and 290D with bond pads at the top and/or bottom, there may be vias formed through the CMOS 282C and 282D. However, unlike via 286A of fig. 2A, a via coupling a conductive interconnect with an upper or lower bond pad will be located at (e.g., below or above) the bond pad.

Fig. 3A and 3B illustrate examples of different techniques for stacking and bonding 3D flash memory die in a package. Fig. 3A shows staggered dies, and fig. 3B shows an example of vertically stacked dies with analog vias for connecting the dies at the package level. Fig. 3A and 3B each show four 3D flash memory die (or two die pairs). For example, fig. 3A shows dies 301, 302, 303, and 304. The dies 301 and 302 are bonded together via the wafer bonding techniques described above. The dies 303 and 304 are also bonded together via wafer bonding. Similarly, dies 351 and 352 and dies 353 and 354 of fig. 3B are bonded together via wafer bonding techniques. In the example shown in fig. 3A and 3B, the dies are bonded together with their respective CMOS circuits facing each other, such as shown in fig. 1A and 2A. Thus, dies 301 and 302 include at least some shared CMOS circuitry on those bonded dies, and dies 303 and 304 include at least some shared CMOS circuitry. Similarly, dies 351 and 352 include at least some shared CMOS circuitry, and dies 353 and 354 include at least some shared CMOS circuitry. The die pairs are then stacked on top of each other in the package (but not bonded together like the dies in the die pairs). In the illustrated example, a die pair including dies 301 and 302 is stacked on top of a die pair including dies 303 and 304. Similarly, a die pair including dies 351 and 352 is stacked on top of a die pair including dies 353 and 354.

Fig. 3A shows an example where the bonded die are staggered like a roof deck. Thus, a portion of the surface of each of the bonded dies (e.g., a portion of the top surface of die 301 and the top surface of die 303) is exposed to enable connection of the pair to external circuitry or contacts at the package level. Bond pads (e.g., wire bond pads, such as pads 310A and 310B) can be placed on exposed portions of the surface for connection to external circuitry or contacts. Wires may then be bonded to bond pads 310A and 310B. Thus, in addition to the bond pads (if present) between dies 301 and 302 and between dies 303 and 304, the wire bond pads can also access each die pair at the package level.

Fig. 3B shows another example of bonding and connecting two die pairs. In contrast to the interleaving approach of fig. 3A, the dies in fig. 3B are stacked directly on top of each other. Each die pair includes bond pads at its top and bottom surfaces. For example, dies 351 and 353 include bond pads on their top surfaces (bond pads 310C and 310E, respectively), and dies 352 and 354 include bond pads on their bottom surfaces (bond pads 310D and 310F, respectively). The die pairs are then bonded together at wafer bond pads 310D and 310E to electrically couple the die to external circuitry or contacts. In the example shown in fig. 3B, the wires need not be bonded to each die or die pair, but may be bonded to only one bond pad (e.g., top bond pad 310C) to access each of the dies (e.g., each of dies 351, 352, 353, and 354). Thus, the through-CMOS vias, the conductive interconnects of each die, and the bond pads 310D and 310E between the die pairs simulate vias extending from the top die 351 to the bottom die 354. Thus, the effect of vias can be achieved without etching through the entire die stack to create a single via through the entire stack. Although only four dies (two die pairs) are shown in each stack, more dies (e.g., 8 or more) may be stacked using the described techniques.

Fig. 4A shows a top view of a chip plan showing CMOS circuitry for accessing a 3D flash memory array. The chip plan view shown in fig. 4A illustrates one possible layout of CMOS circuitry, including CMOS (coa)402A outside the array, CMOS (cua)404A below the array, Static Page Buffer (SPB)406A, and String Driver (SD) 408A. The COA402A is located outside of the array (i.e., not below or above the array) and the remaining CMOS circuitry is below (or above) the array. The CUA404A may include CMOS circuitry, such as control logic, charge pumps, and/or other CMOS circuitry. The numbers 0, 1, 2 and 3 are plane numbers representing different planes.

Fig. 4B shows a top view of a chip plan view showing shared CMOS circuitry for accessing a 3D flash memory array using wafer-to-wafer bonding. The chip plan view shown in fig. 4B shows a plan view of two dies 401 and 403 bonded together via wafer-to-wafer bonding. Like in fig. 4A, numerals 0, 1, 2, and 3 are plane numbers indicating different planes. In the example shown in fig. 4B, each die 401 and 403 includes cmos (coa) outside the array, cmos (cua) below the array, Static Page Buffer (SPB), and String Driver (SD). However, as described above, the dies may include different types of control circuitry (e.g., circuitry on one die that uses one type of transistor and circuitry on another die that uses another type of transistor). In this example, die 401 would be stacked on top of die 403 and bonded (at wafer level, prior to dicing). The length 410B of each die in the z-direction is half the length 410A of the die 400 of fig. 4A. Thus, the area available for CMOS circuitry in each die 401 and 403 is half of the area available in die 400. In the illustrated example, COA 402B is half as long as COA402A, and the area available for CUA, SD, and SPB in each die 401 and 403 is half the area available relative to die 400. However, the total available area for the CMOS circuitry in fig. 2B is the same, assuming that there are two stacked dies 401 and 403, such that the thickness of the stacked dies is twice (in the y-direction, it will come out of the page in fig. 4A and 4B).

Stacking and bonding the dies such that the CMOS circuits of each die are adjacent to each other may have several advantages. As described above, the dimensions of the stacked die in fig. 4B are: half the length of the die in fig. 4A, but twice the thickness of the die in fig. 4A. For some packages, it may be desirable to have a small footprint in the z-x plane. However, fewer die pairs in fig. 4B may be stacked in a given package than the die of fig. 4A. One benefit of the stack bonded die of fig. 4B is that the "islands" of CMOS circuitry on each of the dies can be placed adjacent to each other, enabling easier and better communication between the CMOS islands. For example, referring to FIG. 4A, CMOS circuitry is distributed in small areas or islands across the z-x plane. It may be difficult to route and connect all islands (e.g., all islands labeled CUA) to each other. For example, the routing of the CMOS in fig. 4A may include metal lines on the edge, above the array, below the array, and/or through the array. Not only are routing difficult, but the long signal lines slow the operation of the CMOS circuits.

In contrast, it is simpler to connect islands of CMOS circuitry stacked on top of each other and bonded via wafer-to-wafer bonding. For example, if die 401 is stacked on top of die 403, CUA 404C will be above CUA 404D, forming a CUA island having an area larger than the CUA island of fig. 4A. Thus, the CUA 404C can be electrically coupled with the CUA 404D without vias and without routing through or around other circuitry. By stacking and bonding dies 401 and 403, the size of the area available for a given island in fig. 4B is twice the area relative to fig. 4A.

Fig. 5 is a flow chart of an example of a method of forming a 3D flash memory device having shared CMOS circuitry and multiple dies bonded together via wafer-to-wafer bonding. The method 500 of fig. 5 may be used to form a 3D flash memory storage component, such as the component shown in fig. 1A, 1B, 2A, or 2B.

The method 500 begins by forming a 3D non-volatile memory array on two wafers at operations 502 and 504. Shared CMOS circuitry is also formed in or on at least one of the wafers. Forming the array and CMOS circuitry involves a number of processing steps including deposition, doping and etching of various materials to form the array and control circuitry. After the first and second memory arrays and the shared CMOS circuitry are formed, the wafers are bonded together at operation 506. Bonding the wafers together includes wafer-to-wafer bonding techniques to bond pads attached to the wafers together or to bond the wafers together at conductive contacts of the wafers. Wafer-to-wafer bonding with sub-micron alignment accuracy is possible and may involve the following process flows. The wafer is first cleaned and the surface activated (by surface treatment) to enhance bonding. The wafers are then aligned using face-to-face (F2F) precision optical alignment, which achieves sub- μm alignment accuracy. Once aligned, the wafers are bonded by thermal compression in a conventional clean room environment. Optimized tools and process sequences can ensure that sub- μm alignment accuracy is maintained across the entire wafer.

Fig. 6A-6D illustrate cross-sections of a 3D flash memory storage component at various stages of processing according to an exemplary method, such as method 500 of fig. 5. Fig. 6A shows a portion of a first wafer 601A and a portion of a second wafer 601B. Wafers 601A and 601B each include a substrate 602A and 602B, respectively. In the example shown in FIG. 6A, CMOS circuits 604A and 604B are formed in the substrate of both wafers 601A and 601B. However, in other examples, only one of the wafers includes CMOS circuitry. One or both of the CMOS circuits 604A and 604B may comprise shared CMOS circuits. Over the CMOS circuitry, memory arrays 606A and 606B are formed, and over the arrays, metal layers 608A and 608B are formed, which may couple the arrays with external contacts and/or circuitry.

Fig. 6B-6D show examples of using bond pads. Referring to fig. 6B, wafers 601A and 601B are first flipped so that the backside of the wafer (e.g., the side of the wafer having the CMOS circuitry) faces upward. The backside of the wafer is then thinned to expose the conductive contacts of CMOS circuits 604A and 604B. After thinning the back side of wafers 601A and 601B, wafer bond pads 610 are attached to the back side of the wafers as shown in fig. 6C. One of the wafers is then flipped again so that the wafer bond pads 610 attached to each wafer face each other and the wafers are bonded at the bond pads 610, as shown in fig. 6D.

After wafer bonding, the wafer may be cut into individual dies and packaged with other logic, such as a flash controller, to form a 3D flash memory device. By bonding the wafer at the CMOS circuits, CMOS circuits on one or both dies may be shared to access the arrays 606A and 606B on both dies.

Fig. 7 illustrates a block diagram of a flash memory device 702 in which die bonding and sharing CMOS circuitry may be implemented, according to an example. Although the term flash memory is used for device 702 and throughout this disclosure, a flash memory device may also be referred to as a flash memory device. In one example, the flash storage 702 is a Solid State Drive (SSD) that includes flash storage components 722. The flash memory storage unit 722 includes a non-volatile memory array 731 for storing data. The flash memory storage section 722 also includes CMOS circuitry 733 to access the storage array 731. As described above, the flash memory storage component 722 may include multiple dies bonded together. Each die may include a memory array, and shared CMOS circuitry on a given die enables access to the arrays on multiple dies. Although a single flash memory component is shown in fig. 7, flash memory device 702 may include more than one flash memory component.

In one example, flash storage device 702 may be a flash-based drive that connects to a processor using a PCI express (PCIe), serial Advanced Technology Attachment (ATA), parallel ATA, and/or Universal Serial Bus (USB) interface. The memory array 731 may include one or more of NAND flash, NOR flash, Phase Change Memory (PCM), phase change memory with Switch (PCMs), resistive memory, or other non-volatile storage media. The data may be stored in Single Level Cell (SLC), Three Level Cell (TLC), four level cell (QLC), and/or multi-level cell (MLC) formats.

The flash memory device 702 may include DRAM 708 (or other volatile memory) in addition to non-volatile storage 731. The DRAM 708 includes volatile memory that can store data when the flash memory device 702 is powered on (e.g., operated). The DRAM may conform to standards promulgated by the electronic device engineering association (JEDEC), such as JESD79F for DDR Double Data Rate (DDR) SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A, LPDDR3 for DDR4 SDRAM (low power double data rate version 3, original version JESD209-3B published by JEDEC (electronic device engineering association) (8 months 2013, JEDEC), LPDDR4 (low power double data rate (LPDDR) version 4, JESD209-4 originally published by JEDEC in 2014 8 months, or other JEDEC standards (which are available at www.jedec.org.) other volatile memories may be used. Such as logical to physical indirection tables or other such information.

The flash memory device 702 also includes a controller 730 to control access to the memory components 722. In one example, the controller 730 includes an input/output (I/O) interface to the storage 722 and includes an interface to a host (not shown in FIG. 7). The controller 730 includes hardware logic (e.g., command logic) for communication to control writing to and reading from the memory unit 722. The command logic includes circuitry to generate and issue commands to read the memory cells of storage 731. The CMOS circuitry applies voltage strobes to read and write memory cells of the memory array 731 in response to commands from the controller 730. Thus, the CMOS circuit 733 includes circuitry to decode commands from the controller 730 and apply a read or write strobe to the memory cells in accordance with the received commands. The controller may also include Error Code Correction (ECC) logic to detect and correct errors in the data read from storage 731. The controller 730 may be an application specific integrated circuit controller (ASIC) device connected to an interface such as serial ATA or an integrated drive electronics controller. In another example, the controller 730 includes a processor or other processing circuitry (not shown). In one example, controller 730 may be included in a system on a chip (SoC) on a single integrated circuit chip.

The flash memory storage 702 may also include firmware (not shown). The firmware may perform various functions such as translation, garbage collection, wear leveling, and other functions for operation and optimization of the flash memory device 702. In one example, the firmware may include a Flash Translation Layer (FTL) that includes logic to provide a physical address space that is indirect to identify a logical address (e.g., a Logical Block Address (LBA) of a request received from a file system).

The flash memory device 702 may be present within the range of a computer package (e.g., within a laptop/notebook or other computer), or the flash memory device 702 may also be accessible via a larger network, such as a local area network (e.g., ethernet), or even a wide area network (e.g., wireless cellular network, the internet, etc.).

Fig. 8 provides an exemplary depiction of a computing system 800 (e.g., a smartphone, tablet, laptop, desktop, server computer, etc.). As observed in fig. 8, system 800 may include one or more processors or processing units 801 (e.g., host processors). Processor 801 may include one or more Central Processing Units (CPUs), each of which may include, for example, a plurality of general purpose processing cores. The processor 801 may also or alternatively include one or more Graphics Processing Units (GPUs) or other processing units. Processor 801 may include memory management logic (e.g., a memory controller) and I/O control logic.

The system 800 also includes memory 802 (e.g., system memory), non-volatile storage 804, a communication interface 806, and other components 808. Other components may include, for example, a display (e.g., touchscreen, tablet), a power source (e.g., battery or other power source), a sensor, power management logic, or other components. The communication interface 806 may include logic and/or features to support a communication interface. For these examples, communication interface 806 may include one or more communication interfaces that operate in accordance with various communication protocols or standards to communicate over direct or network communication links or channels. Direct communication may occur via use of a communication protocol or standard described in one or more industry standards (including progeny and variants) such as those associated with the PCIe specification. Network communication may occur via use of a communication protocol or standard such as those described in one or more ethernet standards promulgated by IEEE. For example, one such ethernet standard may include IEEE 802.3. Network communication may also occur in accordance with one or more OpenFlow specifications, such as the OpenFlow switch specification. Other examples of communication interfaces include, for example, a local wired point-to-point link (e.g., USB) interface, a wireless local area network (e.g., WiFi) interface, a wireless point-to-point link (e.g., bluetooth) interface, a global positioning system interface, and/or other interfaces.

The computing system also includes non-volatile storage 804, which may be a mass storage component of the system. The non-volatile storage 804 may be similar to or the same as the flash memory device 702 of FIG. 7 described above. The non-volatile type of memory may include byte or block addressable non-volatile memory such as, but not limited to, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), Magnetoresistive Random Access Memory (MRAM) incorporating memristor technology, spin transfer torque MRAM (STT-MRAM), three dimensional (3D) cross point memory structures including chalcogenide phase change materials (e.g., chalcogenide glass) (hereinafter "3D cross point memory"), or a combination of any of the above. In one example, the non-volatile storage 804 may include a mass storage comprised of one or more SSDs. The SSD may be composed of flash memory chips that include shared CMOS circuitry and die bonded via wafer-to-wafer bonding techniques as described above.

The following are some examples. In one example, a non-volatile storage device includes: a first die comprising a first three-dimensional (3D) array of non-volatile memory cells and CMOS (complementary metal oxide semiconductor) circuitry; and a second die vertically stacked and bonded with the first die, the second die including a second 3D array of non-volatile memory cells, at least a portion of the CMOS circuitry of the first die being used to access both the first 3D array of non-volatile memory cells of the first die and the second 3D array of non-volatile memory cells of the second die. In one such example, the CMOS circuitry of the first die is disposed between the first 3D array of non-volatile memory cells and the second 3D array of non-volatile memory cells. In one example, the second die further includes a second CMOS circuit for accessing the first and second 3D arrays of non-volatile memory cells. In one such example, a portion of the shared CMOS circuitry is included in first CMOS circuitry of the first die and a remaining portion of the shared CMOS circuitry is included in second CMOS circuitry of the second die. The shared CMOS circuit includes one or more of a charge pump, static page buffers, IO, control logic, and string drivers. In one example, shared string driver circuitry is used to access the first and second 3D arrays of non-volatile memory cells, and a portion of the string driver circuitry for the first and second 3D arrays of non-volatile memory cells is included in the CMOS circuitry of the first die, and a remaining portion of the string driver circuitry is included in the second CMOS circuitry of the second die. In one example, the portion of the shared CMOS circuitry on the first die includes a first type of transistor and the remaining portion of the shared CMOS circuitry on the second die includes a second type of transistor. In one such example, the first class of transistors includes high voltage transistors and the second class of transistors includes low voltage transistors.

In one example, a third die is vertically stacked and bonded with the first or second die, the third die including a third 3D array of non-volatile memory cells, the CMOS circuitry of the first die for accessing the third 3D array of non-volatile memory cells. In one example, the layers of the first die are arranged in a reverse order relative to the second die, and the conductive contacts of the CMOS circuits of the first die are bonded with the conductive contacts of the second CMOS circuits of the second die. In one example, the component includes a bond pad between a conductive contact of the first CMOS circuit and a conductive contact of the second CMOS circuit.

In one example, a system includes a processor and a non-volatile storage coupled with the processor, the storage including: a first die comprising a first three-dimensional (3D) array of non-volatile memory cells and CMOS (complementary metal oxide semiconductor) circuitry for accessing the first 3D array of non-volatile memory cells; and a second die vertically stacked and bonded with the first die, the second die including a second 3D array of non-volatile memory cells, the CMOS circuitry of the first die for accessing the second 3D array of non-volatile memory cells of the second die.

In one example, a three-dimensional (3D) NAND memory device includes: a first die comprising a first three-dimensional (3D) array of non-volatile NAND memory cells and control circuitry; and a second die vertically stacked and bonded with the first die, the second die including a second 3D array of non-volatile NAND memory cells, at least a portion of the control circuitry of the first die being for accessing the first 3D array of non-volatile NAND memory cells of the first die and the second 3D array of non-volatile NAND memory cells of the second die.

In one example, a method of manufacturing a non-volatile memory device includes: the method includes forming a first 3D non-volatile memory array and first CMOS circuitry on a first wafer, forming a second 3D non-volatile memory array on a second wafer, the first CMOS circuitry for accessing the first and second 3D non-volatile memory arrays, bonding the first wafer to the second wafer, dicing the bonded first and second wafers, and forming a non-volatile memory device using the diced bonded wafers. In one example, bonding the first wafer to the second wafer includes bonding conductive contacts of the first CMOS circuitry with second conductive contacts of second CMOS circuitry of the second wafer. In one example, the method further comprises: turning over the first wafer; thinning the back side of the first wafer, wherein the first CMOS circuit is arranged close to the back side of the first wafer; and attaching a wafer bond pad to the back side of the first wafer over the conductive contact of the first CMOS circuit, wherein bonding the first wafer to the second wafer comprises bonding the second conductive contact of the second CMOS circuit with the bond pad attached to the first wafer.

Embodiments of the invention may include various processes as described above. The processes may be embodied in machine-executable instructions. The instructions may be used to cause a general-purpose or special-purpose processor to perform certain processes. Alternatively, the processes may be performed by specific/custom hardware components that contain hardwired or programmable logic for performing the processes (e.g., FPGAs, PLDs), or by any combination of programmed computer components and custom hardware components.

Elements of the present invention may also be provided as a machine-readable medium for storing the machine-executable instructions. The machine-readable medium may include, but is not limited to: floppy disks, optical disks, CD-ROMs, and magneto-optical disks, flash memory, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, propagation media, or other type of media/machine-readable medium suitable for storing electronic instructions. For example, the present invention may be downloaded as a computer program which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network connection).

The flow diagrams illustrated herein provide examples of sequences of various process actions. The flow diagrams may indicate operations performed by software or firmware routines and physical operations. In one example, the flow diagram may show the state of a Finite State Machine (FSM), which may be implemented in hardware, software, or a combination. Although shown in a particular order or sequence, the order of the acts may be modified unless otherwise indicated. Thus, the illustrated embodiments should be understood only as examples, and the processes may be performed in a different order, and some actions may be performed in parallel. Moreover, one or more acts may be omitted in various examples; thus, not all acts may be required of each embodiment. Other process flows are also possible.

To the extent various operations or functions are described herein, the operations or functions may be described or defined as software code, instructions, configurations, data, or combinations. The content may be directly executable ("object" or "executable" form), source code, or difference code ("delta" or "patch" code). The software content of the embodiments described herein may be provided via an article of manufacture having the content stored thereon, or via a method of operating a communication interface to transmit data via the communication interface. A machine-readable storage medium may cause a machine to perform the functions or operations described, and includes any mechanism for storing information in a form accessible by a machine (e.g., a computing device, an electronic system, etc.), such as recordable/non-recordable media (e.g., Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism that interfaces to any of a hardwired, wireless, optical, etc. medium to communicate with another device, such as a memory bus interface, a processor bus interface, an internet connection, a disk controller, etc. The communication interface may be configured by providing configuration parameters or sending signals or both to prepare the communication interface to provide data signals describing the software content. The communication interface may be accessed via one or more commands or signals sent to the communication interface.

The various components described herein may be devices for performing the operations or functions described. Each component described herein includes software, hardware, or a combination of these. The components may be implemented as software modules, hardware modules, special purpose hardware (e.g., application specific hardware, Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), etc.), embedded controllers, hardwired circuitry, etc.

Various modifications may be made to the disclosed embodiments and implementations of the invention, in addition to those described herein, without departing from the scope thereof. Terms used above to describe the orientation and positioning of features, such as "top," "bottom," "over," "under," and other such terms describing positioning, are intended to clarify the relative position of features with respect to other features and do not describe a fixed or absolute positioning. For example, a wafer described as a top wafer above or over a bottom wafer may be described as a bottom wafer below or under the top wafer. Accordingly, the illustrations and examples herein should be construed in an illustrative, and not a restrictive, sense. The scope of the invention should be measured solely by reference to the claims that follow.