阅读说明：本技术 用于对经由ddr接口参数的特定于设备的自定义来减少存储器功耗的系统和方法 (System and method for reducing memory power consumption via device-specific customization of DDR interface parameters ) 是由 D·全 R·斯图尔特 于 2018-03-26 设计创作，主要内容包括：公开了用于对经由DDR接口参数的特定于设备的自定义来减少双倍数据速率(DDR)存储器功耗的系统和方法。一个实施例包括用于使双倍数据速率(DDR)功耗最小化的方法。该方法选择多个操作点中的一个操作点以用于DDR接口将DDR存储器电力地耦合到存在于片上系统(SoC)的存储器控制器。存储器控制器在所选择的操作点处经由DDR接口来执行存储器测试。在所选择的操作点处执行存储器测试期间,该方法确定用于与DDR接口相关联的一个或多个DDR接口参数的设置的最佳值,所述最佳值使存储器功耗最小化并维持预先确定的DDR眼图容限。(Systems and methods for reducing Double Data Rate (DDR) memory power consumption via device-specific customization of DDR interface parameters are disclosed. One embodiment includes a method for minimizing Double Data Rate (DDR) power consumption. The method selects one of a plurality of operating points for a DDR interface to electrically couple a DDR memory to a memory controller residing in a system on a chip (SoC). The memory controller performs memory testing via the DDR interface at the selected operating point. During performance of memory testing at the selected operating point, the method determines an optimal value for settings of one or more DDR interface parameters associated with the DDR interface that minimizes memory power consumption and maintains a predetermined DDR eye margin.)

1. A method for minimizing Double Data Rate (DDR) power consumption, the method comprising:

selecting one of a plurality of operating points for a DDR interface to electrically couple a DDR memory to a memory controller residing in a system on a chip (SoC);

the memory controller performing a memory test via the DDR interface at the selected operating point; and

determining values for settings of one or more DDR interface parameters associated with the DDR interface that minimize memory power consumption and maintain a predetermined DDR eye margin during performance of the memory test at the selected operating point.

2. The method of claim 1, wherein the plurality of operating points comprise a plurality of voltage/frequency levels for the DDR interface.

3. The method of claim 1, wherein determining the value for the setting of the one or more DDR interface parameters during execution of the test mode at the selected operating point comprises:

adjusting the settings for the one or more DDR interface parameters;

measuring memory power consumption at the adjusted setting; and

measuring the DDR eye margin.

4. The method of claim 1, wherein the one or more DDR interface parameters comprise one or more of: transmitter drive strength, receiver termination value, duty cycle correction on/off value, equalization on/off value, data bus inversion on/off value, and link Error Correction Code (ECC) on/off value.

5. The method of claim 1, further comprising:

storing the set values for one or more DDR interface parameters in a non-volatile memory.

6. The method of claim 1, wherein the memory test is performed during factory installation of a computing device that includes the SoC and the DDR memory.

7. The method of claim 1, wherein the computing device comprises one of a smartphone, a desktop computer, and a wearable computing device.

8. The method of claim 1, wherein the memory test is performed during boot-up of the SoC.

9. A system for minimizing Double Data Rate (DDR) power consumption, the system comprising:

means for selecting one of a plurality of operating points for a DDR interface to electrically couple a DDR memory to a memory controller residing in a system on a chip (SoC);

means for performing a memory test via the DDR interface at the selected operating point; and

means for determining values for settings of one or more DDR interface parameters associated with the DDR interface during performance of the memory test at the selected operating point, the values to minimize memory power consumption and maintain a predetermined DDR eye margin.

10. The system of claim 9, wherein the plurality of operating points comprise a plurality of voltage/frequency levels for the DDR interface.

11. The system of claim 9, wherein means for determining the set of values for the one or more DDR interface parameters during execution of the test mode at the selected operating point comprises:

means for adjusting the settings for the one or more DDR interface parameters;

means for measuring memory power consumption at the adjusted setting; and

means for measuring the DDR eye margin.

12. The system of claim 9, wherein the one or more DDR interface parameters include one or more of: transmitter drive strength, receiver termination value, duty cycle correction on/off value, equalization on/off value, data bus inversion on/off value, and link Error Correction Code (ECC) on/off value.

13. The system of claim 9, wherein the memory test is performed during factory installation of a computing device that includes the SoC and the DDR memory.

14. The system of claim 9, wherein the computing device comprises one of a smartphone, a desktop computer, and a wearable computing device.

15. The system of claim 9, wherein the memory test is performed in response to a boot of the SoC.

16. A computer program embodied in a non-transitory computer readable medium and executed by a processor for minimizing Double Data Rate (DDR) power consumption, the computer program comprising logic configured to:

selecting one of a plurality of operating points for a DDR interface to electrically couple a DDR memory to a memory controller residing in a system on a chip (SoC);

performing a memory test via the DDR interface at the selected operating point; and

determining values for settings of one or more DDR interface parameters associated with the DDR interface that minimize memory power consumption and maintain a predetermined DDR eye margin during performance of the memory test at the selected operating point.

17. The computer program of claim 16, wherein the plurality of operating points comprise a plurality of voltage/frequency levels for the DDR interface.

18. The computer program of claim 16, wherein the logic configured to determine the set of values for the one or more DDR interface parameters during execution of the test mode at the selected operating point comprises logic configured to:

adjusting the settings for the one or more DDR interface parameters;

measuring memory power consumption at the adjusted setting; and

measuring the DDR eye margin.

19. The computer program of claim 16, wherein the one or more DDR interface parameters include one or more of: transmitter drive strength, receiver termination value, duty cycle correction on/off value, equalization on/off value, data bus inversion on/off value, and link Error Correction Code (ECC) on/off value.

20. The computer program of claim 16, wherein the memory test is performed during factory installation of a computing device comprising the SoC and the DDR memory, and the computer program further comprises logic configured to:

storing the values for the settings of the one or more DDR interface parameters in a non-volatile memory; and

retrieving the values for the settings of the one or more DDR interface parameters from the non-volatile memory in response to a subsequent boot-up of the computing device.

21. The computer program of claim 16, wherein the computing device comprises one of a smartphone, a desktop computer, and a wearable computing device.

22. The computer program of claim 16, wherein the memory test is performed during a boot-up of the SoC.

23. A system for minimizing Double Data Rate (DDR) power consumption, the system comprising:

a Double Data Rate (DDR) memory; and

a system on a chip (SoC) including a memory controller electrically coupled to the DDR memory via a DDR interface, the memory controller configured to: performing a memory test via the DDR interface at one or more of a plurality of operating points, and determining values for settings of one or more DDR interface parameters associated with the DDR interface during performance of the memory test, the values minimizing memory power consumption and maintaining a predetermined DDR eye tolerance.

24. The system of claim 23, further comprising:

a power supply electrically coupled to the SoC and the DDR memory, the power supply including a power monitoring component for measuring the memory power consumption during the memory test.

25. The system of claim 23, wherein the plurality of operating points comprise a plurality of voltage/frequency levels for the DDR interface.

26. The system of claim 23, wherein the memory controller is to determine the value for the setting of the one or more DDR interface parameters during execution of the test mode at the selected operating point by:

adjusting the settings for the one or more DDR interface parameters;

measuring memory power consumption at the adjusted setting; and

measuring the DDR eye margin.

27. The system of claim 23, wherein the one or more DDR interface parameters include one or more of: transmitter drive strength, receiver termination value, duty cycle correction on/off value, equalization on/off value, data bus inversion on/off value, and link Error Correction Code (ECC) on/off value.

28. The system of claim 23, wherein the memory test is performed during factory installation of a computing device that includes the SoC and the DDR memory.

29. The system of claim 23, wherein the computing device comprises one of a smartphone, a desktop computer, and a wearable computing device.

30. The system of claim 23, wherein the memory test is performed during boot-up of the SoC.

Background

Portable computing devices (e.g., cellular phones, smart phones, tablets, Portable Digital Assistants (PDAs), portable gaming consoles, wearable devices, and other battery-powered devices) and other computing devices continue to provide an ever-expanding array of functions and services, as well as providing users with an unprecedented level of access to information, resources, and communications. To keep pace with these service enhancements, such devices have become increasingly powerful and complex. Portable computing devices now typically include a system on a chip (SoC) that includes multiple memory clients (e.g., one or more Central Processing Units (CPUs), Graphics Processing Units (GPUs), Digital Signal Processors (DSPs), etc.) embedded on a single substrate. The memory clients may read and store data in an external Dynamic Random Access Memory (DRAM) electrically coupled to the SoC via a high speed bus, such as a Double Data Rate (DDR) bus.

While various memory standards define the protocols and timing with which a SoC may interface with DRAM, existing systems have several drawbacks for selecting an optimal bandwidth/frequency operating point. In existing systems, there are typically three degrees of freedom from which the SoC can select the optimal operating point. First, there is a wide variety of silicon between DRAM suppliers, between different process nodes, and to a large extent between different wafers from the same supplier and process node. Second, there are channel variations between platform industry designs, SoC and DRAM package designs, and radio frequency compatibility. Third, various DRAM interface parameter settings (e.g., clock frequency, delay, on-die termination resistance, etc.) may be adjusted.

Existing systems employ best effort lumped parameters for these variables that are designed to provide reliable error-free operation. Such a "one size fits all" parameter setting may be wasteful of energy, as there may be device samples that are out of reference and may benefit from an optimized setting.

Accordingly, there is a need for an improved system and method for customizing DRAM interface parameter settings to enable individual units to consume minimal power and allow finer granularity of bandwidth/frequency operating points.

Disclosure of Invention

Systems and methods for reducing Double Data Rate (DDR) memory power consumption via device-specific customization of DDR interface parameters are disclosed. One embodiment includes a method for minimizing Double Data Rate (DDR) power consumption. The method selects one of a plurality of operating points for a DDR interface to electrically couple a DDR memory to a memory controller residing in a system on a chip (SoC). The memory controller performs memory testing via the DDR interface at the selected operating point. During performance of memory testing at the selected operating point, the method determines an optimal value for settings of one or more DDR interface parameters associated with the DDR interface that minimizes memory power consumption and maintains a predetermined DDR eye margin (eye margin).

Another embodiment of a system includes a Double Data Rate (DDR) memory and a system on a chip (SoC). The SoC includes a memory controller electrically coupled to a DDR memory via a DDR interface. The memory controller is configured to perform memory testing via the DDR interface at one or more of the plurality of operating points. During performance of memory testing, the memory controller determines optimal values for settings of one or more DDR interface parameters associated with the DDR interface that minimize memory power consumption and maintain a predetermined DDR eye margin.

Drawings

In the drawings, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals utilizing an alphabetical character name such as "102A" or "102B," the alphabetical character name can distinguish two similar parts or elements given in the same figure. When a reference numeral is intended to cover a whole part having the same reference numeral in all drawings, an alphabetic character name for the reference numeral may be omitted.

FIG. 1 is a block diagram of an embodiment of a system for reducing Double Data Rate (DDR) memory power consumption by customizing device-specific DDR interface parameters.

FIG. 2 is a flow diagram illustrating an embodiment of a method for reducing DDR memory power consumption by customizing device-specific DDR interface parameters.

FIG. 3 is an exemplary diagram illustrating memory power consumption at various voltage frequency bins for two different example devices incorporated into the system of FIG. 1.

FIG. 4 is a flow diagram illustrating another embodiment for reducing DDR memory power consumption during OEM testing by customizing device-specific DDR interface parameters.

FIG. 5 is a table illustrating various exemplary common DDR interface parameters that may be customized to minimize memory power consumption while maintaining predetermined DDR eye tolerances.

Fig. 6 illustrates an embodiment of a physical layer lane coupling a SoC memory controller PHY to a DRAM PHY.

FIG. 7 illustrates an exemplary DDR data eye with a corresponding predetermined DDR eye margin.

FIG. 8 is a block diagram of an exemplary embodiment of a portable computing device for incorporation into the system of FIG. 1.

Detailed Description

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

In this description, the term "application" may also include files with executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, an "application" as referred to herein may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.

Furthermore, the term "content" may also include files with executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, "content" as referred to herein may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.

As used in this description, the terms "component," "database," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in operation. For example, a component may be, but is not limited to being: a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).

In this description, the terms "communication device," "wireless telephone," "wireless communication device," and "wireless handheld device" are used interchangeably. With the advent of third generation ("3G"), fourth generation ("4G"), fifth generation ("5G"), and other wireless technologies, greater bandwidth availability has enabled more portable computing devices with more diverse wireless capabilities.

FIG. 1 illustrates an embodiment of a system 100 for reducing memory power consumption by customizing device-specific Double Data Rate (DDR) interface parameters. The system 100 includes a system on a chip (SoC)102 electrically coupled to a memory via a DDR interface. As is known in the art, a DDR interface includes a physical layer channel or bus that transfers data on both the rising and falling edges of a clock signal. In the embodiment of FIG. 1, the memory includes Dynamic Random Access Memory (DRAM)104, and the DDR interface includes DRAM clock 136 and DRAM control and data bus 134. It should be appreciated that system 100 may be implemented in any computing device including: personal computers, workstations, servers, laptops, game consoles, and Portable Computing Devices (PCDs) such as cellular phones, smart phones, Portable Digital Assistants (PDAs), portable game consoles, navigation devices, tablets, fitness computers, and wearable devices (e.g., sports watches, fitness tracking devices, etc.) or other battery-powered devices with wireless connections or links.

The SoC 102 includes various on-chip components that are electrically coupled via a SoC bus 115. In the embodiment of fig. 1, SoC 102 includes one or more memory clients (e.g., Central Processing Unit (CPU)112, Graphics Processing Unit (GPU), Digital Signal Processor (DSP)), Static Random Access Memory (SRAM)116, Read Only Memory (ROM)118, DRAM controller 114, memory controller 122, power controller 124, and Dynamic Clock and Voltage Scaling (DCVS) controller 120 interconnected via SoC bus 115.

The CPU 112 may support a high-level operating system (O/S) 126. As described in more detail below, the CPU 112 may execute various modules (e.g., DDR data eye training module 128, DDR interface parameter customization module 130) for performing customization of device-specific DDR interface parameters.

The power controller 124 is electrically coupled to the power 138 via a power control bus 142, the power control bus 142 including a power monitor 140, the power monitor 140 configured to measure energy usage associated with the SoC 102 and DRAM104, and thereby monitor memory power consumption.

As further shown in fig. 1, the memory controller 122 may be electrically coupled to external memory (such as, for example, flash memory 144 or other non-volatile memory device) via a memory bus 146. The memory controller 122 controls communication with the external memory.

DCVS controller 120 is configured to implement various DCVS techniques. As known in the art, the DCVS technique refers to: the frequency and/or voltage applied to SoC components (e.g., CPU 112, power controller 124, and other hardware devices) are selectively adjusted to produce desired performance and/or power efficiency characteristics.

DRAM controller 114 includes a physical layer 132 that is electrically coupled to physical layer 106 present on DRAM 104. The physical layer 106 is coupled to DRAM peripheral logic 108, and the DRAM peripheral logic 108 is coupled to a cell array 110.

As further shown in fig. 1, system 100 includes a specially configured module for implementing device-specific customization of DDR interface parameters (i.e., DDR interface parameter customization module 130). It should be appreciated that finer granularity control of bandwidth/frequency operating points via device-specific customized DDR interface parameters may enable individual units of the same system design to consume less power at any given bandwidth/frequency operating point.

As is known in the art, the memory interface frequency may be determined by the required traffic bandwidth requested from all memory clients. The frequency may rise or fall as traffic bandwidth requirements change. Typically, several voltage/frequency bands may be used. For each frequency operating point, the system, including the SoC, physical channel, and DRAM, is tuned during factory initialization (factory initialization) to establish "common parameter settings" that will provide reliable operation. FIG. 5 illustrates an exemplary embodiment of common parameter settings that may be used to improve the electrical signal quality of DRAM control and data bus 134. The common parameter settings resulting from tuning are tested across identical system design units of large sample size (the units are differentiated only by independent SoC and DRAM component serial numbers), and then the common parameter settings are deployed, which represent a yield to the least common denominator that supports changes across sections to sections. Common parameter settings are reliable and easy to deploy, but may be conservative for most systems due to chip-to-chip and system variability, and result in unnecessary power consumption and/or performance degradation.

Fig. 2 is an embodiment illustrating a method 200 implemented in system 100 for reducing DDR memory power consumption by customizing device-specific DDR interface parameters. The method 200 may begin at block 202 as part of a factory initialization/configuration process or upon device startup. It should be appreciated that the method 200 may be performed continuously at device startup to compensate for aging throughout the life of the device. The method 200 may be initiated and controlled by the DDR interface parameter customization module 130. As illustrated by decision block 204, method 200 may be repeated for each of a plurality of bandwidth/frequency operating points. At block 206, one of the bandwidth/frequency operating points is selected. At block 208, the memory test mode 151 is initiated at the selected operating point. At block 210, during execution of memory test 151 at the selected operating point, method 200 determines an optimal value for the setting of one or more DDR interface parameters associated with the DDR interface (i.e., buses 134 and 136), which is: (1) minimize memory power consumption, and (2) maintain a predetermined DDR data eye margin. The features that minimize memory power consumption are described below with reference to fig. 3. The feature of maintaining a predetermined DDR data eye tolerance may be facilitated by communication with DDR data eye training module 120, DDR data eye training module 120 being described below with reference to fig. 6 and 7. At block 212, the optimal values for the DDR interface parameter settings are stored in memory for use in operating at the selected operating point. For example, in one embodiment, the optimal value for the DDR interface parameter setting may be stored in non-volatile memory, and in response to a subsequent boot-up of the computing device, the optimal value for the setting may be retrieved from non-volatile memory.

In this manner, DDR interface parameter settings at each frequency operating point may be optimized for individual devices or units to account for potential chip-to-chip changes. During execution of memory test mode 151 at various frequency operating points, power monitor 140 may measure the power consumption of SoC 102 and DRAM104 while adjusting DDR interface parameter settings. It should be appreciated that the memory test mode 151 employs the DRAM104 to characterize the magnitude of power consumption for each frequency band. There may be multiple reliable or successful parameter settings for each frequency band. In one embodiment, the optimal setting is determined to be the setting that results in the lowest power consumption while maintaining the DDR data eye margin within the predetermined margin.

Fig. 3 shows an exemplary power bandwidth comparison graph 300 for two different samples (i.e., sample a and sample B) having identical system designs 100. For example, sample a may include a first portable computing device having a system design 100, and sample B may include a second portable computing device having the same system design 100. In this example, the system 100 provides six voltage frequency bands. First voltage frequency bin₀Including the frequency range of 0-400 MHz. Second voltage frequency bin₄₀₀Including the frequency range of 400-800 MHz. Third voltage frequency bin₈₀₀Including the frequency range of 800-1200 MHz. Fourth voltage frequency bin₁₂₀₀Including the frequency range of 1200-1600 MHz. Fifth voltage frequency bin₁₆₀₀Including the frequency range 1600-2000 MHz. Sixth voltage frequency bin₂₀₀₀Including the frequency range of 2000-2400 MHz. The solid line plots the memory power consumption measured by power monitor 140 for the first device (sample a). The dashed line plots the memory power consumption measured by power monitor 140 for the second device (sample B).

One of ordinary skill in the art will recognize that variations in memory power consumption between exemplar A and exemplar B may be caused by chip-to-chip variations associated with the SoC 102 chip, the DRAM104 chip, and/or variations in the physical channels comprising the DRAM control and data bus 134 and the DRAM clock bus 136. These and other variations between different devices with identical system designs may be caused by silicon process variations between chips that affect DDR interface parameter settings that determine operating characteristics such as interface power, frequency of operation, and bit error rate. For example, if the SoC 102 or any DRAM104 die is "slow," it may need to be configured with parameters such as drive strength or termination strength to compensate for a given target frequency of operation, resulting in higher power consumption than a "fast" die. "fast" or "slow" refers to circuit signal propagation delay, rise/fall time, and skew characteristics.

Exemplary diagram 300 shows that power monitor 140 may determine different power consumption levels for sample a and sample B in the same frequency band. For example, sample A is at low frequencies (i.e., in bin)₀P in (1)_A0) Has the lowest energy. Sample B is at the peak frequency (i.e., in bin)₂₀₀₀P in (1)_B2000) Has the lowest energy. The slope of sample A is typically steeper than sample B (i.e., [ P ]_A800-P_A0]>[P_B800-P_B0]). Sample a requires an earlier power boost at 1100MHz compared to sample B at 1500 MHz. To minimize memory power consumption, power monitors 140 present in samples a and B may measure the corresponding illustrated memory power consumption and determine DDR interface parameter settings for each frequency band that result in the lowest memory power consumption for each sample.

FIG. 4 is a flow diagram illustrating another embodiment for reducing DDR memory power consumption by customizing device-specific DDR interface parameters. Factory initialization may begin at block 402. At block 404, a controlled laboratory test (captive lab testing) is performed for a plurality of units or devices comprising the system 100. Controllable laboratory testing involves determining common voltage and timing parameters. In an embodiment, the multi-unit controllable laboratory test may involve the determination of common parameter settings or values in a conventional manner as described hereinabove. For example, the common parameter setting or value may relate to any of the parameters shown in column 502 of data table 500 of fig. 5: SoC TX drive strength, DRAM TX drive strength, SoC RX termination, DRAM RX termination, write duty cycle correction, read duty cycle correction, write equalization, read equalization, write data bus inversion, read data bus inversion, write link ECC/EDC, read link ECC/EDC, and control bus link ECC/EDC. Column 504 describes how adjustments in corresponding values or settings affect memory power consumption. It should be appreciated that multi-unit controllable laboratory testing may determine so-called common parameter settings or values that result in reliable, error-free operation of the system 100.

At block 406, the common parameter settings or values may be delivered to a software build of a device incorporated into the system 100. At block 408, during OEM factory installation, devices incorporated into the system 100 may first boot up. At block 410, common parameter settings or values may be applied to the device, and the system 100 may begin executing the memory test mode 151. At block 412, the DDR data eye training module 128 may begin training DDR data eye parameters (e.g., horizontal eye sampling points, vertical eye sampling points) to maximize DDR data eye margin for each frequency operating point. It should be appreciated that these DDR data eye parameters may not affect the shape, size, and/or quality of the data eye. For example, DDR data eye training may determine the optimal sampling decision point within the eye. In contrast, common parameter settings can change the shape, size, and/or quality of the data eye (e.g., make the eye relatively clean from noise, relatively large from occlusion, etc.).

Referring to fig. 6, the SoC 102 and the DRAM104 transmit and receive data using a data strobe signal (DQS)604 and a data signal (DQ) 602. The DQS signal 604 includes a reference signal that transitions between logic 0 and 1. DQ data 602 is captured on the transition edges (both rising and falling) of the DQs signal 604. As is known in the art, the DDR data eye 700 (fig. 7) is generated when a plurality of captured data signals are superimposed on one another. The rise time refers to the time to transition from logic 0 to 1, and the fall time refers to the time to transition from logic 1 to 0. The reference voltage refers to a threshold voltage for distinguishing between logic 1 and 0.

Fig. 7 illustrates an exemplary DDR data eye 700. Time is represented on the x-axis and reference voltage is represented on the y-axis. DDR data eye 700 includes a plurality of captured DQ signals superimposed on one another. The DDR data eye training module 128 may be configured to determine the center of the DDR data eye 700, which corresponds to the optimal data strobe arrangement 702 and the optimal reference voltage 704. The DDR data eye training module 128 may implement various algorithms for efficiently determining the optimal data strobe arrangement and reference voltage value pairs for each of the frequency operating points.

Referring again to fig. 4, the method 400 may begin the process of determining custom, device-specific common parameters when the "eye" parameter has been determined to maximize DDR data eye tolerance for various frequency operating points. At block 414, settings or values for the common parameters may be adjusted while power monitor 140 measures power consumption (FIG. 5). In one embodiment, DDR interface parameter customization module 130 (FIG. 1) scans through values for one or more parameters identified in the table of FIG. 5 to determine the setting that yields the lowest power consumption for each frequency. At decision block 416, if the lowest power setting does not maintain the DDR data eye 700 within the predetermined eye tolerance, the process may return to block 412. For example, referring to fig. 7, the predetermined eye margin may include a minimum value in the time domain (e.g., 176 picoseconds) and/or minimum upper and lower voltage margins (e.g., 38 millivolts for the upper margin and 78 millivolts for the lower margin). However, if the lowest power setting maintains the DDR data eye 700 within the predetermined eye tolerance, the table 500 may be updated with the optimal setting or value (block 418). After determining the adjusted settings or values for the common interface parameters for each frequency, factory initialization may terminate at block 420. In this manner, the end result is reliable bus operation that meets the predetermined eye margin with the common parameter settings using the least amount of energy.

As mentioned above, the system 100 may be incorporated into any desired computing system. FIG. 8 shows the system 100 incorporated into an exemplary Portable Computing Device (PCD) 800. It will be readily appreciated that certain components of system 100 may be included on SoC 822 (e.g., DRAM controller 114, DRAM PHY 132, test mode 151, DDR data eye training module 128, DDR interface parameter customization module 130, etc.), while other components (e.g., DRAM 104) may be external components coupled to SoC 822. SoC 822 may include a multi-core CPU 802. The multi-core CPU802 may include a zeroth core 810, a first core 812, and an Nth core 814. For example, one of the cores may include a Graphics Processing Unit (GPU), with the other core or cores including the CPU 802.

Display controller 828 and touchscreen controller 830 may be coupled to CPU 802. In turn, a touchscreen display 806 external to the on-chip system 822 can be coupled to the display controller 828 and the touchscreen controller 830.

FIG. 8 further illustrates that a video encoder 834, such as a Phase Alternating Line (PAL) encoder, a sequential couleur a memoire (SECAM) encoder, or a National Television Standards Committee (NTSC) encoder, is coupled to the multi-core CPU 802. Further, a video amplifier 836 is coupled to the video encoder 834 and the touchscreen display 806. Additionally, a video port 838 is coupled to the video amplifier 836. As shown in fig. 8, a Universal Serial Bus (USB) controller 840 is coupled to the multicore CPU 802. Additionally, a USB port 842 is coupled to USB controller 840.

Further, as shown in fig. 8, a digital camera 848 may be coupled to the multicore CPU 802. In an exemplary aspect, the digital camera 848 is a Charge Coupled Device (CCD) camera or a Complementary Metal Oxide Semiconductor (CMOS) camera.

As further shown in fig. 8, a stereo audio coder decoder (CODEC)850 can be coupled to the multi-core CPU 802. Further, an audio amplifier 852 can be coupled to the stereo audio CODEC 850. In an exemplary aspect, a first stereo speaker 854 and a second stereo speaker 856 are coupled to the audio amplifier 852. Fig. 8 shows that a microphone amplifier 858 may also be coupled to the stereo audio CODEC 850. Additionally, a microphone 860 may be coupled to the microphone amplifier 858. In a particular aspect, a Frequency Modulation (FM) radio tuner 862 may be coupled to the stereo audio CODEC 850. In addition, an FM antenna 864 is coupled to the FM radio tuner 862. Further, stereo headphones 866 can be coupled to the stereo audio CODEC 850.

FIG. 8 further illustrates that a Radio Frequency (RF) transceiver 868 may be coupled to the multi-core CPU 802. The RF switch 870 may be coupled to an RF transceiver 868 and an RF antenna 872. The keyboard 804 may be coupled to the multicore CPU 802. Additionally, a mono headset with a microphone 876 may be coupled to the multicore CPU 802. Further, a vibrator device 878 may be coupled to the multicore CPU 802.

FIG. 8 also illustrates that a power supply 880 may be coupled to the system-on-chip 822. In a particular aspect, the power supply 880 is a Direct Current (DC) power supply that provides power to the various components of the PCD 800 that require power. Further, in certain aspects, the power source is a rechargeable DC battery or a DC power source derived from an Alternating Current (AC) to DC converter connected to an AC power source.

Fig. 8 further indicates that the PCD 800 may also include a network card 888, which the network card 888 may use to access a data network (e.g., a local area network, a personal area network, or any other network). Network card 888 may be a bluetooth network card, a WiFi network card, a Personal Area Network (PAN) card, a personal area network ultra low power technology (peanout) network card, a television/cable/satellite tuner unit, or any other network card known in the art. Further, the network card 888 may be incorporated into a chip, i.e., the network card 888 may be a complete solution in a chip and may not be a separate network card 888.

As depicted in fig. 8, the touchscreen display 806, the video port 838, the USB port 842, the camera 848, the first stereo speaker 854, the second stereo speaker 856, the microphone 860, the FM antenna 864, the stereo headphones 866, the RF switch 870, the RF antenna 872, the keypad 874, the mono headset 876, the vibrator 878, and the power supply 880 may be external to the system-on-chip 822.

It should be recognized that one or more of the method steps described herein may be stored in memory as computer program instructions (such as the modules described above). These instructions may be executed by any suitable processor in conjunction with or in conjunction with corresponding modules to perform the methods described herein.

Certain steps in a process or process flow described in this specification naturally precede other steps in the invention to achieve the functionality as described. However, the invention is not limited to the order or sequence of steps described if such order or sequence does not alter the functionality of the invention. That is, it is to be appreciated that some steps may be performed before, after, or in parallel with (substantially simultaneously with) other steps without departing from the scope or spirit of the present invention. In some instances, certain steps may be omitted or not performed without departing from the invention. Further, words such as "thereafter," "then," "next," etc. are not intended to limit the order of the steps. These words are merely used to guide the reader through the description of the exemplary methods.

In addition, one of ordinary skill in the programming arts can write computer code or identify appropriate hardware and/or circuitry to implement the disclosed invention without difficulty, e.g., based on the flowcharts and associated descriptions in this specification.

Therefore, a specific set of program code instructions or detailed hardware device disclosure is not considered necessary for a thorough understanding of how the present invention may be utilized and used. The innovative functions of the claimed computer-implemented process are explained in greater detail in the description above and in conjunction with the drawings that can illustrate various process flows.

In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code in a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, NAND flash, NOR flash, M-RAM, P-RAM, R-RAM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line ("DSL"), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.

Disk and disc, as used herein, includes compact disc ("CD"), laser disc, optical disc, digital versatile disc ("DVD"), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

Alternative embodiments will become apparent to those of ordinary skill in the art to which the present invention pertains without departing from its spirit and scope. Thus, while selected aspects have been illustrated and described in detail, it will be understood that various substitutions and alterations may be made therein without departing from the spirit and scope of the invention, as defined by the following claims.