阅读说明：本技术 一种集成碳化硅晶体管及其制造方法 (Integrated silicon carbide transistor and manufacturing method thereof ) 是由 温正欣 张新河 陈施施 叶怀宇 张国旗 于 2019-10-11 设计创作，主要内容包括：本发明涉及功率半导体技术领域,公开了基于同一外延结构的碳化硅集成管,包括NPN型晶体管和PNP型晶体管。其中NPN型晶体管主要结构包括一N+衬底,其上方依次为一P+隔离层,一N+集电区,一N型漂移区,一P型基区和一N+发射区。P型基区上有一P+型基区接触区。在N+发射区上方有发射级,P+接触区上方有基极,N+集电区上方有集电极。PNP型晶体管主要结构包括一N+衬底,其上方依次为一P+隔离层,一N+基区,一N型漂移区,一P型集电区和一P型发射区排布在N型漂移区上方两侧,P型集电区和P型发射区不接触,其上方分别为P+集电极接触区和P+型发射极接触区。本发明还提供了该碳化硅NPN型晶体管和PNP型晶体管器件制备的工艺方法。(The invention relates to the technical field of power semiconductors, and discloses a silicon carbide integrated tube based on the same epitaxial structure, which comprises an NPN transistor and a PNP transistor. The NPN type transistor mainly comprises an N + substrate, and a P + isolation layer, an N + collector region, an N type drift region, a P type base region and an N + emitter region are sequentially arranged above the N + substrate. The P-type base region is provided with a P + type base region contact area. An emitter is arranged above the N + emitter region, a base is arranged above the P + contact region, and a collector is arranged above the N + collector region. The PNP type transistor mainly comprises an N + substrate, wherein a P + isolation layer, an N + base region, an N type drift region, a P type collector region and a P type emitter region are sequentially arranged above the N + substrate on two sides above the N type drift region, the P type collector region is not contacted with the P type emitter region, and a P + collector contact region and a P + emitter contact region are respectively arranged above the P type collector region and the P type emitter region. The invention also provides a preparation method of the silicon carbide NPN type transistor and the PNP type transistor.)

1. An integrated silicon carbide transistor, comprising: the PNP type epitaxial light source comprises an NPN type transistor and a PNP type transistor which use the same epitaxial structure, wherein an N type drift region (5) of the NPN type transistor and an N type drift region (6) of the PNP type transistor are the same epitaxial layer, a P type base region (7) of the NPN type transistor, a P type collector region (13) and a P type emitter region (15) of the PNP type transistor are the same epitaxial layer, and an N + collector region (3) of the NPN type transistor and an N + base region (4) of the PNP type transistor are the same epitaxial layer.

2. The integrated silicon carbide transistor of claim 1, wherein: the same epitaxial structure comprises an N + substrate (1) and a P + isolation layer (2).

3. The integrated silicon carbide transistor of claim 1, wherein: the NPN transistor comprises an N + substrate (1), and a P + isolation layer (2), an N + collector region (3), a first N type drift region (5), a P type base region (7) and an N + emitter region (9) are sequentially arranged above the N + substrate; a P + type base region contact region (8) on the P type base region (7); a first emitter (10) above the N + emitter region (9), a first base (11) above the P + contact region (8), and a first collector (12) above the N + collector region (3).

4. The integrated silicon carbide transistor of claim 1, wherein: the PNP transistor comprises an N + substrate (1), a P + isolation layer (2), an N + base region (4), a second N type drift region (6), a P type collector region (13) and a P type emitter region (15) which are arranged on two sides above the N type drift region (2) (6), wherein the P type collector region (13) is not in contact with the P type emitter region (15), and a P + collector contact region (14) and a P + emitter contact region (16) are respectively arranged above the P type collector region and the P type emitter region; above the P + collector contact region (14) is a second collector (18) and above the P + emitter contact region is a second emitter (19).

5. The integrated silicon carbide transistor of claim 1, wherein: the N + substrate (1) is a silicon carbide N-type highly doped substrate with the doping concentration of 1 multiplied by 10¹⁸cm^-3-1×10²¹cm^-3(ii) a The doping concentration of the P + type isolation layer (2) is more than 1 multiplied by 10¹⁸cm^-3A thickness of 1 μm to 5 μm; the doping concentration of the N + collector region (3) of the NPN type transistor and the N + base region (4) of the PNP type transistor is 5 multiplied by 10¹⁸cm^-3-5×10¹⁸cm^-9The thickness is 0.2-2 μm; a first N-type drift region (5) of the NPN-type transistor and a second N-type drift region of the PNP-type transistor(6) The doping concentration is 2 x 10¹⁴cm^-3-1×10¹⁶cm^-3The thickness is 1-100 μm; the doping concentration of the P-type base region (7) of the NPN-type transistor, the P-type emitter region (15) of the PNP-type transistor and the P-type collector region (13) of the PNP-type transistor is 1 multiplied by 10¹⁷cm^-3-1×10¹⁸cm^-30.2-1 μm thick; the doping concentration of the emitter (10) of the NPN transistor is 1 multiplied by 10¹⁹cm^-3The thickness is 0.1-0.5 μm.

6. The integrated silicon carbide transistor of claim 1, wherein: the P + type base region contact region (8) of the NPN type transistor, the P + collector contact region (14) of the PNP type transistor and the P + emitter contact region (16) are formed by one-time ion implantation, the implanted ions are metal Al, and the doping concentration is 5 multiplied by 10¹⁸cm^-3To 5X 10¹⁹cm^-3And a depth of 0.1 μm to 0.3. mu.m.

7. A method of fabricating an integrated silicon carbide transistor includes

S1: epitaxially growing a P + \ N + \ N \ P \ N + structure on an N + substrate;

s2: etching the silicon carbide to form an emitting region of the NPN transistor;

s3: performing P-type ion implantation on the surface layer of the silicon carbide;

s4: etching the silicon carbide to separate an emitter region and a collector region of the PNP transistor;

s5: etching the silicon carbide to expose the N + layer;

s6: etching the silicon carbide to isolate the NPN transistor and the PNP transistor;

s7: and preparing electrodes of the NPN type transistor and the PNP type transistor.

8. The integrated silicon carbide transistor fabrication method of claim 7, wherein: said S3 includes

S3.1, after cleaning, depositing silicon dioxide, and etching the silicon dioxide to form an injection mask;

s3.2, the ion implantation temperature is 550 ℃, RCA is cleaned after the ion implantation is finished, a carbon film is deposited, annealing and activation are carried out for 30 minutes at the temperature of more than 1800 ℃, and finally a P + type implantation area and a P + type implantation area are formed.

9. The integrated silicon carbide transistor fabrication method of claim 7, wherein: said S4 includes

S4.1, after cleaning, depositing silicon dioxide on the surface of the silicon carbide, and etching the silicon dioxide after coating, photoetching, developing and hardening;

and S4.2, etching the silicon carbide material to the surface of the N-type region by taking the etched silicon dioxide as a mask, dividing the P + type injection region into two parts, and dividing the P-type region into two parts.

10. The integrated silicon carbide transistor fabrication method of claim 6, wherein: said S5 includes

S5.1, after the surface of the epitaxial wafer is cleaned for the first time, thick silicon dioxide is deposited on the surface of the silicon carbide;

s5.2, after coating glue, photoetching, developing and hardening, etching silicon dioxide;

and S5.3, etching the silicon carbide material to the surface of the N + type region by taking the etched silicon dioxide as a mask, dividing the P type region into two parts, and dividing the N type region into two parts.

11. The integrated silicon carbide transistor fabrication method of claim 7, wherein: said S6 includes

S6.1, cleaning the surface of the epitaxial wafer again, and depositing thick silicon dioxide on the surface of the silicon carbide;

s6.2, after photoresist coating, photoetching, developing and hardening, etching silicon dioxide. And etching the silicon carbide material to the surface of the N + type region by taking the etched silicon dioxide as a mask, and dividing the N + type region into two parts.

12. The integrated silicon carbide transistor fabrication method of claim 7, wherein: said S7 includes

S7.1, cleaning the surface of the wafer, coating glue, photoetching and developing, sputtering metal Ni/Ti/Al alloy to be used as an ohmic contact material, and stripping to form contact metal;

s7.2, carrying out rapid thermal annealing at 950 ℃ for 1 minute and 30 seconds to form an emitter, a base and a collector of the NPN type transistor and a base, a collector and an emitter of the PNP type transistor.

Technical Field

The invention belongs to the technical field of semiconductor power devices, and particularly relates to an integrated silicon carbide transistor and a manufacturing method thereof.

Background

Compared with the traditional Si material, the SiC wide bandgap semiconductor material has excellent physical and chemical properties, so that the SiC material has great application potential in the field of power semiconductors. SiC discrete power devices have been developed for over thirty years and many common devices have been commercialized. It is well known that the development of discrete devices often results in the accumulation of many process and reliability achievements and experiences, which in turn can be used in the development of integrated circuits. The popularization of silicon carbide integrated circuits is the most obstructive in material aspect, because the integrated circuits comprise a plurality of components which are transversely integrated on a plane, each component needs to normally work to ensure the normal operation of the integrated circuits. Thus, silicon carbide integrated circuits have high requirements for epitaxial wafer quality, but this problem is gradually being solved as substrate and epitaxial technologies improve.

Currently, the most common device in silicon power integrated circuits is the LDMOS, which requires the gate oxide capacitance to be charged to control the channel turn-on. Since the silicon carbide-silicon dioxide interface still has more problems, which are more serious in high temperature operation, the basic components of early silicon carbide power integrated circuits are more likely to be BJT or JFET based lateral devices that do not include a gate oxide.

Disclosure of Invention

Technical problem to be solved

The invention aims to provide a silicon carbide NPN type transistor and a silicon carbide PNP type transistor aiming at the characteristics of a silicon carbide material and an integrated circuit, which can be prepared on the same epitaxial wafer, are convenient to simultaneously apply the NPN type transistor and the PNP type transistor in the integrated circuit, have simple preparation process and are compatible with the conventional vertical device process.

(II) technical scheme

The technical scheme provided by the invention comprehensively considers the aspects of material characteristics, process difficulty, device performance, cost and the like, and provides an integrated silicon carbide transistor which comprises an NPN type transistor and a PNP type transistor with the same epitaxial structure, wherein an N type drift region (5) of the NPN type transistor and an N type drift region (6) of the PNP type transistor are the same epitaxial layer, a P type base region (7) of the NPN type transistor and a P type collector region (13) and a P type emitter region (15) of the PNP type transistor are the same epitaxial layer, and an N + collector region (3) of the NPN type transistor and an N + base region (4) of the PNP type transistor are the same epitaxial layer.

Preferably, the same epitaxial structure is an N + substrate (1) and a P + isolation layer (2).

Preferably, the NPN transistor comprises an N + substrate (1), and a P + isolation layer (2), an N + collector region (3), a first N type drift region (5), a P type base region (7) and an N + emitter region (9) are sequentially arranged above the N + substrate; a P + type base region contact region (8) on the P type base region (7); a first emitter (10) above the N + emitter region (9), a first base (11) above the P + contact region (8), and a first collector (12) above the N + collector region (3).

Preferably, the PNP type transistor includes an N + substrate (1), on which a P + isolation layer (2), an N + base region (4), a second N type drift region (6), a P type collector region (13) and a P type emitter region (15) are sequentially disposed on two sides above the N type drift region 2(6), the P type collector region (13) and the P type emitter region (15) are not in contact, and on which a P + collector contact region (14) and a P + emitter contact region (16) are respectively disposed; above the P + collector contact region (14) is a second collector (18) and above the P + emitter contact region is a second emitter (19).

Preferably, the N + substrate (1) is a silicon carbide N-type highly doped substrate with the doping concentration of 1 x 10¹⁸cm^-3-1×10²¹cm^-3(ii) a The doping concentration of the P + type isolation layer (2) is more than 1 multiplied by 10¹⁸cm^-3A thickness of 1 μm to 5 μm; the doping concentration of the N + collector region (3) of the NPN type transistor and the N + base region (4) of the PNP type transistor is 5 multiplied by 10¹⁸cm^-3-5×10¹⁸cm^-9The thickness is 0.2-2 μm; the doping concentration of the first N-type drift region (5) of the NPN-type transistor and the second N-type drift region (6) of the PNP-type transistor is 2 multiplied by 10¹⁴cm^-3-1×10¹⁶cm^-3The thickness is 1-100 μm; p-type base of NPN transistorThe doping concentration of the region (7), the P-type emitter region (15) of the PNP transistor and the P-type collector region (13) is 1 multiplied by 10¹⁷cm^-3-1×10¹⁸cm^-30.2-1 μm thick; the doping concentration of the emitter (10) of the NPN transistor is 1 multiplied by 10¹⁹cm^-3The thickness is 0.1-0.5 μm.

Preferably, the P + base region contact region (8) of the NPN type transistor, the P + collector contact region (14) of the PNP type transistor and the P + emitter contact region (16) of the PNP type transistor are formed by one-time ion implantation, the implanted ions are metal Al, and the doping concentration is 5 multiplied by 10¹⁸cm^-3To 5X 10¹⁹cm^-3And a depth of 0.1 μm to 0.3. mu.m.

In another aspect of the present invention, it is proposed that the simultaneous preparation of the integrated silicon carbide transistors comprises the steps of:

s1: epitaxially growing a P + \ N + \ N \ P \ N + structure on an N + substrate;

s2: etching the silicon carbide to form an emitting region of the NPN transistor;

s3: performing P-type ion implantation on the surface layer of the silicon carbide;

s4: etching the silicon carbide to separate an emitter region and a collector region of the PNP transistor;

s5: etching the silicon carbide to expose the N + layer;

s6: etching the silicon carbide to isolate the NPN transistor and the PNP transistor;

s7: and preparing electrodes of the NPN type transistor and the PNP type transistor.

Preferably, said S3 includes

S3.1, after cleaning, depositing silicon dioxide, and etching the silicon dioxide to form an injection mask;

s3.2, the ion implantation temperature is 550 ℃, RCA is cleaned after the ion implantation is finished, a carbon film is deposited, annealing and activation are carried out for 30 minutes at the temperature of more than 1800 ℃, and finally a P + type implantation area and a P + type implantation area are formed.

Preferably, said S4 includes

S4.1, after cleaning, depositing silicon dioxide on the surface of the silicon carbide, and etching the silicon dioxide after coating, photoetching, developing and hardening;

and S4.2, etching the silicon carbide material to the surface of the N-type region by taking the etched silicon dioxide as a mask, dividing the P + type injection region into two parts, and dividing the P-type region into two parts.

Preferably, said S5 includes

S5.1, after the surface of the epitaxial wafer is cleaned for the first time, thick silicon dioxide is deposited on the surface of the silicon carbide;

s5.2, after coating glue, photoetching, developing and hardening, etching silicon dioxide;

and S5.3, etching the silicon carbide material to the surface of the N + type region by taking the etched silicon dioxide as a mask, dividing the P type region into two parts, and dividing the N type region into two parts.

Preferably, said S6 includes

S6.1, cleaning the surface of the epitaxial wafer again, and depositing thick silicon dioxide on the surface of the silicon carbide;

s6.2, after photoresist coating, photoetching, developing and hardening, etching silicon dioxide. And etching the silicon carbide material to the surface of the N + type region by taking the etched silicon dioxide as a mask, and dividing the N + type region into two parts.

Preferably, said S7 includes

S7.1, cleaning the surface of the wafer, coating glue, photoetching and developing, sputtering metal Ni/Ti/Al alloy to be used as an ohmic contact material, and stripping to form contact metal;

s7.2, carrying out rapid thermal annealing at 950 ℃ for 1 minute and 30 seconds to form an emitter, a base and a collector of the NPN type transistor and a base, a collector and an emitter of the PNP type transistor.

(III) beneficial results

According to the invention, through unique epitaxial structure and device structure design, a transverse integrated tube containing a silicon carbide NPN type transistor and a silicon carbide PNP type transistor is designed, and the device selection range of silicon carbide-based integrated circuit design is greatly expanded.

Epitaxial structures of silicon carbide NPN transistors and PNP transistors are grown on commercial N + type substrates at low cost. The introduction of the epitaxial P + isolation layer avoids the interference between adjacent devices and improves the reliability of the system.

The NPN type transistor and the PNP type transistor use the same epitaxial structure, wherein the drift region of the NPN type transistor and the drift region of the PNP type transistor are the same epitaxial layer, the base region of the NPN type transistor and the collector region and the emitter region of the PNP type transistor are the same epitaxial layer, and the collector region of the NPN type transistor and the base region of the PNP type transistor are the same epitaxial layer. The silicon carbide NPN type transistor and the silicon carbide PNP type transistor can be simultaneously prepared and formed through a device process, the integration level is improved through the multiplexing of the epitaxial region, and the preparation cost is reduced.

Drawings

FIG. 1 is a schematic diagram of the structure of a silicon carbide NPN transistor and a PNP transistor according to the present invention;

FIG. 2 is a process flow diagram of an embodiment of the invention;

FIG. 3 is a schematic view of process step S1 according to an embodiment of the present invention;

FIG. 4 is a schematic view of process step S2 according to an embodiment of the present invention;

FIG. 5 is a schematic view of process step S3 according to an embodiment of the present invention;

FIG. 6 is a schematic view of process step S4 according to an embodiment of the present invention;

FIG. 7 is a schematic view of process step S5 according to an embodiment of the present invention;

FIG. 8 is a schematic view of process step S6 according to an embodiment of the present invention.

The emitter comprises an N + substrate 1, a P + isolation layer 2, an N + collector region 3, a first N-type drift region 5, a P-type base region 7, a P + base region contact region 8, an N + emitter region 9, a first emitter stage 10, a base 11, a first collector 12, an N + base region 4, a second N-type drift region 6, a P-type collector region 13, a P-type emitter region 15, a P + collector contact region 14, a P + emitter contact region 16, a second base 17, a second collector 18 and a second emitter 19.

Detailed Description

In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.