阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 曾思惟 蔡国强 于 2019-06-26 设计创作，主要内容包括：本发明实施例提供一种半导体装置,包含：第一栅极结构和第二栅极结构,各自设置于基板之上；第一导电接触件和第二导电接触件,各自设置于基板之上；第一导孔,设置于所述第一导电接触件之上；第二导孔,设置于所述第二导电接触件之上；第一栅极接触件,设置于所述第一栅极结构之上；以及介电结构,设置于所述第一栅极结构之上和第二栅极结构之上。其中,介电结构的第一部分设置于第一导孔和第二导孔之间且电性隔离第一导孔和第二导孔；介电结构的第二部分设置于第一导孔和第一栅极接触件之间且电性隔离第一导孔和第一栅极接触件；介电结构的第一部分和第二部分各自包含单一类型的介电材料；第一导电接触件和第一导孔之间的第一界面在剖面图中构成所述第一导电接触件的上表面区域的第一百分比；第一栅极结构和第一栅极接触件之间的第二界面在剖面图中构成所述第一栅极结构的上表面区域的第二百分比。所述第一百分比大于所述第二百分比。(An embodiment of the present invention provides a semiconductor device, including: the first grid structure and the second grid structure are respectively arranged on the substrate; a first conductive contact and a second conductive contact each disposed on the substrate; a first via disposed over the first conductive contact; a second via disposed over the second conductive contact; a first gate contact disposed over the first gate structure; and a dielectric structure disposed over the first gate structure and over the second gate structure. Wherein the first portion of the dielectric structure is disposed between and electrically isolates the first via and the second via; a second portion of the dielectric structure disposed between and electrically isolating the first via and the first gate contact; the first and second portions of the dielectric structure each comprise a single type of dielectric material; a first interface between a first conductive contact and a first via constitutes a first percentage of an upper surface area of the first conductive contact in a cross-sectional view; a second interface between the first gate structure and the first gate contact constitutes a second percentage of an upper surface area of the first gate structure in the cross-sectional view. The first percentage is greater than the second percentage.)

1. A semiconductor device, comprising:

a first gate structure and a second gate structure, each disposed on a substrate;

a first conductive contact and a second conductive contact, each disposed on the substrate;

a first via disposed above the first conductive contact;

a second via hole disposed above the second conductive contact;

a first gate contact disposed on the first gate structure; and

a dielectric structure disposed over the first gate structure and over the second gate structure;

wherein:

a first portion of the dielectric structure disposed between and electrically isolating the first via and the second via;

a second portion of the dielectric structure disposed between and electrically isolating the first via and the first gate contact;

the first portion and the second portion of the dielectric structure each comprise a single type of dielectric material;

a first interface between the first conductive contact and the first via constitutes a first percentage of an upper surface area of the first conductive contact in cross-section;

a second interface between the first gate structure and the first gate contact constitutes a second percentage of an upper surface area of the first gate structure in the cross-sectional view; and

the first percentage is greater than the second percentage.

Technical Field

Embodiments of the present invention relate to semiconductor devices and methods of fabricating the same, and more particularly, to vias and gate contacts in semiconductor devices and methods of fabricating the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. Technological advances in the materials and design of integrated circuits have resulted in generations of integrated circuits, each with smaller and more complex circuits than the previous generation. As integrated circuit (ic) devices have evolved, as geometries (i.e., the smallest devices or lines that can be created during fabrication) have decreased, so has the functional density (i.e., the number of interconnected devices per chip area).

As semiconductor devices continue to shrink, manufacturing challenges also increase. For example, the shrinking distances between various semiconductor elements may cause bridging or electrical shorting problems, which may reduce the performance of the semiconductor device or even cause device failure.

Thus, while existing semiconductor fabrication methods generally meet their intended purpose, these methods are not entirely satisfactory in every aspect.

Disclosure of Invention

According to an embodiment of the present invention, there is provided a semiconductor device including: the first grid structure and the second grid structure are respectively arranged on the substrate; a first conductive contact and a second conductive contact each disposed on the substrate; a first via disposed over the first conductive contact; a second via disposed over the second conductive contact; a first gate contact disposed over the first gate structure; and a dielectric structure disposed over the first gate structure and over the second gate structure. Wherein the first portion of the dielectric structure is disposed between and electrically isolates the first via and the second via; a second portion of the dielectric structure disposed between and electrically isolating the first via and the first gate contact; the first and second portions of the dielectric structure each comprise a single type of dielectric material; a first interface between a first conductive contact and a first via constitutes a first percentage of an upper surface area of the first conductive contact in a cross-sectional view; a second interface between the first gate structure and the first gate contact constitutes a second percentage of an upper surface area of the first gate structure in the cross-sectional view. The first percentage is greater than the second percentage.

According to another embodiment of the present invention, there is provided a semiconductor device including: a plurality of gate structures disposed on the substrate; a plurality of conductive contacts disposed on the substrate; a plurality of gate contacts disposed over a first subset of the gate structures; a first dielectric material disposed over a second subset of the gate structures; a plurality of vias disposed over a first subset of the conductive contacts; a second dielectric material disposed over a second subset of the conductive contacts; and a third dielectric material disposed over the second dielectric material, wherein the first, second, and third dielectric materials have different material compositions than one another. Wherein, in a cross-sectional view: each via occupies a first percentage of an upper surface area of a conductive contact disposed therebelow; each gate contact occupies a second percentage of an upper surface area of the gate structure disposed therebelow. The first percentage is greater than the second percentage.

According to still another embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, including: providing a plurality of gate structures and a plurality of conductive contacts, each formed on a substrate, wherein a plurality of gate caps are formed on the gate structures, respectively; etching back the conductive contacts, thereby forming a plurality of openings; forming a first dielectric layer over the gate cap and over the conductive contact, wherein the first dielectric layer fills the opening; etching back the first dielectric layer into a plurality of first dielectric segments, wherein each first dielectric segment is disposed on a respective one of the conductive contacts and partially fills a respective one of the openings; forming a second dielectric layer over the gate cap and over the first dielectric segment, wherein the second dielectric layer fills the opening; etching the second dielectric layer to form a plurality of first vias over at least a subset of the conductive contacts; forming a conductive material to fill the first via; and performing a planarization process to remove a portion of the conductive material and a portion of the second dielectric layer, thereby forming a plurality of first vias in the first vias.

Drawings

The embodiments of the present invention will be understood more fully from the detailed description given below and from the accompanying drawings. It is emphasized that, in accordance with industry standard practice, many of the features (features) are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion. It is also emphasized that the drawings illustrate only typical embodiments of the invention and are therefore not to be considered limiting of its scope, for the embodiments of the invention may be applied to other embodiments as well.

Fig. 1-14 illustrate cross-sectional side views of a semiconductor device at various stages of fabrication, in accordance with an embodiment of the present invention.

Fig. 15 shows a flowchart of a method of manufacturing a semiconductor device, according to an embodiment of the invention.

Wherein the reference numerals are as follows:

200-semiconductor device

210-substrate

220. 221, 222, 223, 224, 225-source/drain regions

230. 231, 232, 233, 234, 235, 236-gate structure

240-Gate spacer

245 interlayer dielectric

260. 261, 262, 263, 264, 265-conductive contact

280. 281, 282, 283, 284, 285, 286 to gate cap

300. 370-etching back process

310. 311, 312, 313, 430, 520, 521, 530 to opening

330. 400, 620-deposition process

350. 410 dielectric layer

380. 381, 382, 383, 384, 385 to section

390. 440, 540 to thickness

420. 500, 600-etching process

430A, 430B, 430C, 530A, 530B, 530C

450. 550-distance

640-conductive material

680 to planarization process

700. 701, 702, 703-guide holes/contacts

704. 705-Gate contact

720. 740 upper surface area

730. 750 to interface

780-height

900 to method

910. 920, 930, 940, 950, 960, 970, 980

Detailed Description

The following provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present embodiments. These are, of course, merely examples and are not intended to limit the embodiments of the invention. For example, references in the description to a first feature being formed on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. Moreover, embodiments of the present invention may repeat reference numerals and/or letters in the various examples, for purposes of simplicity and clarity, and do not represent a particular relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below … …," "below … …," "below," "above … …," "above," and the like, may be used herein to facilitate describing the relationship of one element(s) or component(s) to another element(s) or component(s) as shown. These spatially relative terms encompass different orientations of the device in use or during a procedure, and the orientation depicted in the figures. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.

Further, when a number or range of numbers is described in terms of "about", "about" and the like, the term is intended to include numbers within a reasonable range, including numbers such as within +/-10% of the number or other value as would be understood by one of skill in the art. For example, the term "about 5 nm" includes a size range from 4.5nm to 5.5 nm.

As semiconductor technology nodes continue to shrink, manufacturing challenges arise. For example, as device dimensions become smaller, bridging problems may occur in which elements that should remain electrically isolated from each other are undesirably shorted together. Techniques to prevent bridging, such as overlay control, may place stringent requirements on lithography, but they do not adequately prevent bridging problems. In contrast, as discussed in more detail below, embodiments of the present invention utilize a novel manufacturing process to "self-align" the devices and automatically prevent bridging problems.

Fig. 1-14 illustrate schematic partial cross-sectional side views of a semiconductor device 200 at various stages of fabrication, according to some embodiments. Referring now to fig. 1, a semiconductor device 200 includes a substrate 210. In some embodiments, the substrate 210 comprises silicon. Alternatively or additionally, the substrate 210 may comprise other elemental semiconductors, such as germanium. The substrate 210 may also contain a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate 210 may also include an alloy semiconductor such as silicon germanium (sige), silicon germanium carbide (sige), gallium arsenic phosphide (galllium arsenic phosphide), and gallium indium phosphide (galllium indium phosphide). In one embodiment, the substrate 210 comprises an epitaxial layer. For example, the substrate 210 may have an epitaxial layer overlying a bulk semiconductor. In addition, the substrate 210 may include a semiconductor-on-insulator (SOI) structure. For example, the substrate 210 may include a Buried Oxide (BOX) layer formed by a process such as SIMOX (separation by implantation of oxygen) or other suitable techniques such as wafer bonding and polishing.

The substrate 210 may also include various p-type doped regions and/or n-type doped regions implemented by processes such as ion implantation and/or diffusion. These doped regions include n-wells, p-wells, lightly doped regions (LDDs) and various channel doping profiles (channel profiles) configured to form various integrated circuit devices, such as complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs), imaging sensors and/or Light Emitting Diodes (LEDs). By way of example, FIG. 1 illustrates a plurality of source/drain regions 220-223 formed in a substrate 210.

The substrate 210 may also include various electrically isolated regions. The electrically isolated regions provide electrical isolation between various device regions (e.g., doped regions) in the substrate 210. The electrically isolated regions may comprise different structures formed by using different process techniques. For example, the electrically isolated regions may comprise Shallow Trench Isolation (STI) structures. The formation of the shallow trench isolation structure may include etching a trench into the substrate 210 and filling the trench with one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or combinations of the foregoing. The filled trench may have a multi-layer structure, such as a thermal oxide liner (liner layer), in which silicon nitride fills the trench. A polishing or planarization process, such as Chemical Mechanical Polishing (CMP), may be performed to polish away (polish back) excess insulating material and planarize the top surface of the isolation features.

The semiconductor device 200 includes a plurality of gate structures, such as the gate structures 230-233 shown in FIG. 1. In some embodiments, the gate structures 230-233 are high-k metal gate structures, i.e., each gate structure 230-233 includes a high-k gate dielectric and a metal gate electrode. The high-dielectric-constant dielectric material has a dielectric constant greater than that of SiO₂A dielectric constant of (about 4). In one embodiment, the high-k gate dielectric comprises hafnium oxide (HfO) having a dielectric constant in the range of about 18 to about 40₂). In an alternative embodiment, the high-k gate dielectric may comprise ZrO₂、Y₂O₃、La₂O₅、Gd₂O₅、TiO₂、Ta₂O₅HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO or SrTiO. A metal gate electrode is formed over the high-k gate dielectric. In some embodiments, the metal gate electrode may include a work function metal element and a fill metal element. The work function metal elements are configured to adjust the work function of their respective transistors to achieve a desired threshold voltage Vt. In various embodiments, the work function metal element may comprise TiAl, TiAlN, TaCN, TiN, WN, W, or a combination of the foregoing. The filler metal element is configured to serve as a primary conductive portion of the gate electrode. In various embodiments, the filler metal elements may comprise aluminum, tungsten, copper, or combinations of the foregoing.

Gate replacement processes may be used to form gate structures 230-233. In this regard, a dummy gate electrode (e.g., a polysilicon gate electrode) is first formed over the high-k gate dielectric. Source/drain regions (e.g., source/drain regions 220-223) of the transistors are formed in the substrate and on opposite sides of the dummy gate electrode. Thereafter, an interlayer dielectric (ILD) 245 is formed over the substrate and around the dummy gate electrode therein. A polishing process, such as chemical mechanical polishing, may be performed to planarize the upper surface of the inter-layer dielectric 245. The dummy gate electrode is then removed, leaving an opening in the interlayer dielectric in place of the removed dummy gate electrode. Then, a metal gate electrode is formed in the opening. The above process may also be referred to as gate last process. In some other embodiments, the formation of the high-k metal gate structure may also involve a high-k last (high-k last) process that first forms a dummy gate dielectric (e.g., silicon oxide) and forms a dummy gate electrode over the dummy gate dielectric. After the source/drain regions and interlayer dielectric are formed, both the dummy gate dielectric and dummy gate electrode may be removed to form an opening in interlayer dielectric 245. Then, a high-k gate dielectric and a metal gate electrode are formed in the opening.

With continued reference to FIG. 1, gate spacers 240 are formed on sidewalls of the gate structures 230-233. In some embodiments, each gate spacer 240 may comprise multiple layers, such as one layer comprising silicon oxide and another layer comprising silicon nitride. For the sake of simplicity, the detailed structure or shape of the gate spacers is not specifically shown here.

A plurality of conductive contacts 260-263 (also referred to as "MD" contacts) are formed on the source/drain regions 220-223, respectively, to provide electrical connections to the source/drain regions 220-223. The surface of the conductive contacts 260-263 may be planarized by etching a trench in the interlayer dielectric 245, followed by one or more suitable deposition processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or combinations thereof to fill the trench, and then a polishing process to planarize the surface of the conductive contacts 260-263. In some embodiments, the conductive contacts 260-263 comprise a metallic material, such as a metallic material comprising tungsten, aluminum, copper, or the like.

A plurality of gate masks 280-283 are respectively located on the gate structures 230-233. The gate caps 280-283 include a dielectric material. In some embodiments, the dielectric material is silicon nitride (SiN). The use of silicon nitride as the gate cap material is different from conventional processes in thatOther types of dielectric materials are often selected for the gate cap (if formed). In other embodiments, the gate caps 280-283 may comprise dielectric materials, such as YSiO_x、SiOC、Al₂O₃、HfO₂、TiO₂、ZrSiO₄、HfSiO₄、Si₃N₄、Ta₂O₅、SrO、Y₂O₃、La₂O₃、LaLuO₂、CaO、MgO、Gd₂O₃、PrO₂、CeO₂、ZrHfO₂AlON or a combination of the foregoing. Gate caps 280-283 are also located over the gate spacers 240. For example, the top surface of the gate spacer 240 is in direct physical contact with a portion of the gate caps 280-283. Each of the gate caps 280-283 has a T-shaped cross-sectional profile due to the presence of the gate spacers.

Referring now to FIG. 2, an etch-back process 300 is performed to remove a portion of each of the conductive contacts 260-263, thereby forming openings 310-313 (also referred to as "slots") respectively, in place of the partially removed conductive contacts. As discussed in more detail below, these openings 310-313 are reserved for forming conductive holes (also referred to as "VD" vias) above the conductive contacts 260-263.

Referring now to fig. 3, a deposition process 330 is performed to form a layer (also referred to as a dielectric layer) 350. A layer 350 is formed over the gate caps 280-283 and the conductive contacts 260-263. A portion of the layer 350 also fills the openings 310-313. The layer 350 may comprise a dielectric material different from that of the gate caps 280-283. In some embodiments, layer 350 comprises zirconium oxide (ZrO)₂). In other embodiments, layer 350 may comprise a dielectric material, such as YSiO_x、SiOC、Al₂O₃、HfO₂、TiO₂、ZrSiO₄、HfSiO₄、Si₃N₄、Ta₂O₅、SrO、Y₂O₃、La₂O₃、LaLuO₂、CaO、MgO、Gd₂O₃、PrO₂、CeO₂、ZrHfO₂AlON or combinations thereof, as long as layer 350 and gate cap 280 to 283 has an etching selectivity. As discussed in more detail below, a portion of layer 350 will act as an etch stop layer in a subsequent etch process, such as for via etching.

Referring now to fig. 4, an etch back process 370 may be performed to partially remove layer 350. For example, portions of the layer 350 over the gate caps 280-283 are removed and the layer 350 fills a portion of each of the openings 310-313. As a result, segments (segments) 380-383 of the layer 350 remain in the openings 310-313. It is noted that the etch-back process 370 is performed such that the top surfaces of the segments 380-383 are now below the top surfaces of the gate caps 280-283. As shown in FIG. 4, each section 380-383 has a thickness 390. In some embodiments, thickness 390 is in a range of about 8 angstroms to about 12 angstroms. At least some of the segments 380-383 can serve as etch stops for etching vias (e.g., VD vias over conductive contacts 260-261) in subsequent processing. The range of thickness 390 is configured such that the segments 380-383 can sufficiently perform their function as etch stop layers, e.g., thick enough to withstand etching, but not so thick that they become difficult to remove later.

Referring now to fig. 5, a deposition process 400 is performed to form a dielectric layer 410. A dielectric layer 410 is formed over the gate caps 280-283 and the segments 380-383. A portion of the dielectric layer 410 is also filled in the openings 310-313. The dielectric layer 410 may comprise a dielectric material that is different from the dielectric material of the gate caps 280-283 and different from the material of the segments 380-383, such that there is an etch selectivity between these materials in one or more subsequent etches. In some embodiments, dielectric layer 410 comprises silicon oxide (SiO)₂). The dielectric layer 410 is used as an etch layer (e.g., a layer that etches a via opening) to be formed.

Referring now to fig. 6, an etching process 420 is performed to etch an opening 430 in the semiconductor device 200. It is understood that the etch process 420 may involve forming a patterned photoresist layer over the layer (also referred to as a dielectric layer) 410. Using the patterned photoresist layer as an etching mask, the portion of the semiconductor device 200 exposed by the photoresist layer is etched through an etching process 420. Opening 430 extends vertically through a portion of dielectric layer 410 and exposes gate cap 281 and a portion of gate caps 280 and 282 and segments 380 and 381. The openings 430 are subsequently filled with a conductive material to form VD vias over the conductive contacts 260-261.

As will be more apparent from the discussion that follows, the formation of the openings 430 allows for the formation of self-aligned vias (self-aligned vias) over the conductive contacts 260-261. This is because the formation of the openings 430 is wide enough to laterally cover the conductive contacts 260-261, and thus any vias formed within the openings 430 will automatically self-align with their respective conductive contacts. This is advantageous over conventional via definition methods, where individual (individual) vias are defined to be separated from each other to align with corresponding conductive contacts therebelow (undercut). To do so, conventional methods require strict overlay control (to ensure that the vias and conductive contacts are vertically aligned) and lithography capability (to ensure that the vias do not bridge each other).

Referring still to FIG. 6, because the material of segments 380-381 is tuned to have an etch selectivity (e.g., greater than 10: 1) with respect to dielectric layer 410, segments 380-381 herein act as an etch stop layer during etch process 420. In other words, dielectric layer 410 has a significantly (substitially) higher etch rate during etch process 420, while segments 380-381 have a significantly lower etch rate during etch process 420. For example, in some embodiments, the difference in etch rate may be greater than or equal to 10: 1. thus, the etching process 420 can etch the exposed portion of the dielectric layer 410, but can be "stopped" by the segments 380-381.

However, since the etch selectivity cannot be infinitely high, the thickness of segments 380 and 381 may also be slightly reduced by etch process 420. For example, after the etching process 420 is performed, each of the segments 380-381 has a thickness 440 that is less than a thickness 390 (see FIG. 4) before the etching process 420 is performed. In some embodiments, thickness 440 is in a range from about 3nm to about 7 nm. As can be seen in FIG. 6, after the etch process 420, the sections 380-381 are substantially thinner than the sections 382-383 (which have not been etched). It should be appreciated that the segments 380-381 protect the underlying conductive contacts 260-261 from damage by the etch process 420.

As shown in fig. 6, opening 430 includes portions 430A and 430B that are directly over conductive contacts 260 and 261, respectively. VD vias for providing electrical connection to the conductive contacts 260-261 will be formed in these portions 430A and 430B. Portions 430A and 430B are separated by a distance 450, distance 450 being the distance between adjacent conductive contacts. The distance 450 may be very small (e.g., less than about 33nm in some embodiments). Since photolithography is limited by the distance 450 becoming smaller, it may be difficult to define portions 430A and 430B separately, so portions 430A-430B are also connected together by portion 430C of opening 430 located above portions 430A-430B. In other words, if distance 450 is large enough, portions 430A and 430B may be defined as separate via openings and a portion of layer 410 may remain between portions 430A and 430B of opening 430, which would provide electrical isolation between VD vias. However, as distance 450 shrinks, the two portions 430A and 430B of opening 430 may merge together, even though they are designed to define separate via openings. It should be understood that embodiments of the present invention may define large openings 430 to purposefully merge portions 430A-430B in some embodiments, or the merging of portions 430A-430B may not necessarily be by design, but rather may be due to lithographic limitations (lithographics).

In any event, the merging of portions 430A-430B may additionally create bridging problems between the VD vias, as the conductive material filling portion 430C may bridge the VD vias together. Similar bridging problems may be problematic for conventional fabrication processes that do not use the fabrication flow discussed above with reference to fig. 1-6, and therefore will have structures that appear different. In other words, adjacent VD vias manufactured according to conventional process flows may have a significant risk of bridging when they become too small apart, it being understood that their structure differs from that shown in fig. 6. For example, conventional processes may not intentionally attempt to form an opening similar to opening 430, which may result in bridging between the two portions 430A-430B. In contrast, conventional processes may attempt to define via openings as separate from one another, but due to lithographic limitations, the two via openings may eventually merge together, similar to the case of opening 430.

In contrast, even though the distance 450 separating the portions 430A and 430B may be small, bridging of adjacent VD vias is not a problem in embodiments of the present invention. For example, a subsequent polishing process will polish away the conductive material filling portion 430C, which will effectively "sever" the connection between the VD vias formed in portions 430A and 430B. It should also be understood that embodiments of the present invention define the opening 430 as a "large" opening that in some embodiments laterally spans the conductive contacts 260-261, but also define two via openings individually (e.g., similar to portions 430A-430B), if the two via openings merge, the result remains similar to the previously defined "large" opening 430, and the end result should be the same, i.e., no bridging between adjacent vias.

As discussed above, another benefit of the process flow of the present embodiment is that the VD vias formed are "self-aligned" with the conductive contacts 260-261. For example, in some embodiments, an opening (e.g., opening 430) wide enough to laterally cover both of the conductive contacts 260-261 can be defined. Thus, once the segments 380-381 are removed in subsequent processes, VD vias can be formed over the entire top surface of the conductive contacts 260-261. The interface between the conductive contacts 260-261 and the VD vias is much larger than the interface between the conductive contacts and the VD vias in conventional processes. For example, conventional processes require complex overlay control to individually define VD via openings to align with the underlying conductive contacts, and thus only a portion of the upper surface of the conductive contacts may be in direct contact with the VD vias formed thereon. The larger via-to-contact (via-to-contact) interface provided by embodiments of the present invention improves device performance, such as lower resistivity.

Referring now to fig. 7, an etch process 500 is performed on the semiconductor device 200. The etching process 500 is configured to etch openings 520-521, each opening 520-521 extending vertically through the layer 410 and the gate caps 280 and 282. For example, a patterned photoresist layer may be formed over the semiconductor device 200, wherein the patterned photoresist layer defines the openings 520-521. When the etching process 500 is performed, the patterned photoresist layer is used as an etching mask, thereby etching the exposed material of the opening.

As described above, due to the different material compositions between the segments 380-383, the layer 410, and the gate caps 280-283, the etch process 500 can etch through the layer 410 and the gate caps 280 and 282 (when the gate cap 281 is protected by the patterned photoresist layer) without completely etching through the segment 382. However, after the etch process 500 is performed, the segment 382 has a reduced thickness 540. In some embodiments, thickness 540 is similar in value to thickness 440, such as in a range of about 3nm to about 7 nm. It should be appreciated that the segment 382 protects the underlying conductive contact 262 from damage by the etching process 500.

The openings 520-521 are reserved for gate contacts (or vias) to be formed over the gate structures 230 and 232, and thus the openings 520-521 may also be referred to as gate contact openings. The opening 520 is aligned with a portion of the gate structure 230 and exposes a portion of the gate structure 230, and the opening 520 is reserved for the formation of a "regular" gate contact (or via) VG, and may be referred to as a VG opening. In contrast, the opening 521 is aligned with the gate structure 232 and the conductive contact 262, and the opening 521 is reserved for the formation of a "slot" contact, also referred to as a body contact or a connection contact. Slotted contacts may be implemented in certain integrated circuit applications, such as Static Random Access Memory (SRAM) devices. In other words, the slotted contact to be formed in the opening 521 means that the gate structure 232 and the conductive contact 262 are electrically connected together, and thus the "bridging" between the gate structure 232 and the conductive contact 262 is by design rather than a defect.

It should be appreciated that although only one VG opening 520 is shown in fig. 7 for simplicity, the etch process 500 may actually form a plurality of other VG openings, some of which may be adjacent to each other. Similar to the VD via openings discussed above, when the distance between these VG openings is too small, a risk of bridging (e.g., bridging between adjacent VG contacts) may occur in conventional devices. For example, referring to fig. 8, a cross-sectional view of various portions of a semiconductor device 200 is shown. Source/drain regions 224-225, similar to the source/drain regions 220-223, are formed in the substrate 210. Gate structures 234-236 (with gate spacers 240 formed on sidewalls) similar to gate structures 230-233 are formed over substrate 210. Conductive contacts 264-265 similar to the conductive contacts 260-263 are formed on the source/drain regions 224-225, respectively. Gate caps 284-286 (or residues thereof) similar to gate caps 280-283 are formed over gate structures 234-236. Segments 384-385 (of the dielectric layer 350) similar to segments 380-383 are formed over the conductive contacts 264-265, respectively. Layer 410 is formed over gate caps 284-286 and over segments 384-385.

It should be appreciated that the portion of the semiconductor device 200 shown in fig. 8 has undergone the same manufacturing processes as discussed above, such as the etch-back process 300 of fig. 2, the deposition process 330 of fig. 3, the etch-back process 370 of fig. 4, the deposition process 400 of fig. 5, the etch process 420 of fig. 6 (although VD openings are not actually formed because the portion of the semiconductor device 200 in fig. 8 may be protected by a patterned photoresist layer), and the etch process 500 of fig. 7. In addition to etching the openings 520-521 as shown in FIG. 7, the etching process 500 etches an opening 530 as shown in FIG. 8. Opening 530 includes a portion 530A, a portion 530B, and a portion 530C. Portions 530A and 530B expose a portion of gate structure 235 and a portion of gate structure 236, respectively. Portions 530A and 530B define openings for gate contacts of gate structures 235-236. Portion 530C connects portions 530A-530B together. Similar to the case of the VD openings 430A-430B discussed above, when the distance 550 between adjacent gate structures 235-236 becomes too small, a bridging risk between adjacent gate contacts will occur in conventional processes. Here, the risk of gate contact bridging is substantially eliminated by the unique manufacturing flow for reasons similar to those discussed above with respect to the via openings.

Referring now to fig. 9-10, an etching process 600 is performed on the semiconductor device 200. The etching process 600 etches the exposed sections 380-382 and 385, thereby "breaking through" the openings 430 and 521. Due to the etch selectivity between the segments 380-385 and the gate caps 280-286 and the layer 410, the gate caps 280-286 and the layer 410 are substantially unaffected by the etch process 600. After the etching process 600 is performed, the conductive contacts 260-262 and a portion of the gate structures 230, 232, 235, and 236 are exposed.

Referring now to fig. 11-12, a deposition process 620 is performed on the semiconductor device 200 to form a conductive material 640 thereon. The conductive material is filled in the openings 520-521, 430 and 530. The conductive material 640 may include a metal material having good conductivity and good gap (gap) filling characteristics. In some embodiments, the conductive material 640 comprises tungsten.

Referring now to fig. 13-14, a planarization process 680 is performed on the semiconductor device 200. In some embodiments, the planarization process 680 includes a polishing (polishing) process, such as a Chemical Mechanical Polishing (CMP) process. The planarization process 680 polishes and/or etches away a portion of the conductive material 640 and a portion of the layer 410 until the gate caps 280-286 are reached. In other words, the gate caps 280-286 are configured to act as polish stops during the planarization process 680.

As a result of the planarization process 680, the remaining portions of the conductive material 640 form vias or contacts 700-705. For example, as shown in fig. 13, a gate contact 702 (also referred to as a VG contact) is formed over the gate structure 230. A via 701 (also referred to as a VD via) and a via 702 are formed over the conductive contacts 260 and 261, respectively. A via 703 (also referred to as a slotted contact) is formed over the gate structure 232 and the conductive contact 262, thereby electrically interconnecting the gate structure 232 and the conductive contact 262. As discussed above, the "bridging" of the gate structure 232 and the conductive contact 262 provided by the via or slotted contact 703 is by design. The portion of the slotted contact 703 that overlies the conductive contact 262 can be used as a VD rail (VD rail) in certain integrated circuit applications, such as in an sram device. Also shown in fig. 14, gate contact 704 and gate contact 705 are formed over gate structures 235 and 236, respectively.

The planarization process 680 eliminates the risk of bridging due to the unique manufacturing flow discussed above. For example, in FIG. 13, the portion of conductive material 640 disposed over vias 701-702 is removed by a planarization process 680, which eliminates the risk of vias 701-702 bridging together. Therefore, it can be said that the embodiment of the present invention prevents bridging of VD via holes. At the same time, the trenched contact 703 should be electrically connected to both the gate structure 232 and the conductive contact 262, and the planarization process 680 should not cut off but rather preserve the desired (interrupted) interconnection. As shown in FIG. 14, the portion of the conductive material 640 disposed over the gate contacts 704-705 is also removed by the planarization process 680, which eliminates the risk of bridging the gate contacts 704-705 together. Thus, in addition to preventing bridging of VD vias, embodiments of the present invention also prevent bridging of VG contacts.

Due to the unique manufacturing flow, the semiconductor device 200 may have many different physical characteristics compared to conventional devices. One of the different physical characteristics of the semiconductor device 200 herein is that, in addition to the gate spacers 240, the electrical isolation between the gate contact and the via is provided by a dielectric structure comprising a single type of dielectric material. For example, the gate caps 280-286 can be considered dielectric structures that include silicon nitride. In contrast, semiconductor devices formed by conventional fabrication processes may require many different dielectric layers formed on top of each other (each dielectric layer having a different dielectric material composition than the other dielectric materials) to provide electrical isolation between the gate contact and the via. This simplifies the device structure of the semiconductor device 200 compared to conventional devices.

Another of these physical characteristics is the difference in interface area between the gate structure and the VG contacts formed above it, and between the conductive contacts and the VD vias formed above it. For example, referring to fig. 13, the conductive contact 260 (as one example of a conductive contact) has a top surface area 720 in a cross-sectional view therein, and the conductive contact 260 and the via 701 have an interface 730. The interface 730 occupies or constitutes M percent of the upper surface area 720 in the cross-sectional view. In some embodiments, M is close to or substantially equal to 100%. This high percentage overlap between the interface 730 and the upper surface region 720 is due, at least in part, to the unique manufacturing flow, as discussed above, the VD vias (e.g., vias 701) are "self-aligned" to their corresponding contacts (e.g., conductive contacts 260).

Meanwhile, the gate structure 230 (as one example of a gate structure) has a top surface area 740 in the cross-sectional view of fig. 13, and the gate contact 700 and the gate structure 230 form an interface 750. The interface 750 occupies or constitutes a percentage N of the upper surface area 740 in the cross-sectional view. N is substantially less than 100% because the bottom surface of the gate cap 280 also occupies a portion of the upper surface area 740 of the gate structure 230. Thus, M is substantially greater than N. In some embodiments, M: the ratio of N is between about 1.8: 1 to about 1.4: 1, in the above range.

Another unique physical characteristic of the semiconductor device 200 is that different types of dielectric materials are formed over the gate structure and over the conductive contacts over which the vias are not formed. For example, the gate caps 280-286 formed over the gate structures 230-236 may be silicon nitride. However, the dielectric section 383 and the layer 410 formed over the conductive contact 263 comprise zirconium oxide and silicon oxide, respectively. The same is true for the conductive contacts 264-265 and the dielectric material formed thereon. In contrast, conventional semiconductor devices are typically formed with the same dielectric material (or at least some of the same material) over the gate structure and over the conductive contact.

Another unique physical characteristic of the semiconductor device 200 is the reduced height of the vias. For example, as shown in fig. 13, via 702 has a via height 780 measured from an upper surface of via 702 to a bottom surface of via 702. Due to the unique manufacturing flow discussed above, less dielectric layer remains in the final structure compared to conventional processes. As a result, after performing the planarization process 680, the height 780 is typically significantly less than the height of a via fabricated under conventional processes. In some embodiments, height 780 is in the range of about 15nm to about 23nm, whereas similar vias of conventional semiconductor devices may typically exceed 30nm in height. It is to be appreciated that for similar reasons, embodiments of the present invention also reduce the height of the slotted contact 703 and the gate contact (e.g., gate contact 700). Shorter via heights (and wider via widths) correspond to better gap fill performance (and less chance of bubbles or voids being trapped within the via) and reduced resistivity.

Various aspects of embodiments of the present invention may be applied to a wide variety of semiconductor integrated circuit applications, including but not limited to sram cells and/or standard logic cells. For example, the slotted contact 703 may be implemented in an SRAM cell as a Body Contact (BCT) or a connection contact. Vias (e.g., vias 701-702) may also be used in standard logic cell arrays to implement VD rails. Additional details regarding static random access memory cells or standard logic cells may be found in U.S. patent application No. 15/492,777 entitled FinFET static random access memory (PMOS Fin Lines) with Discontinuous P-type metal oxide semiconductor fins, the disclosure of which is incorporated herein by reference in its entirety. It should also be understood that various aspects of embodiments of the present invention may be applied to conventional planar transistors as well as recently developed three-dimensional fin field effect transistors (finfets). Exemplary finfet devices and their FABRICATION are described in more detail in U.S. patent No. 9,711,533, entitled "finfet device having different SOURCE/drains adjacent to i/o devices and NON-i/o devices and method OF fabricating the same" (FINFET DEVICES HAVING DIFFERENT SOURCE/drain FOR INPUT/OUTPUT DEVICES AND NON-INPUT/OUTPUT DEVICES AND method OF failure thermal) filed on 16/10/2015 and approved on 18/7/2017, the entire disclosure OF which is incorporated herein by reference. For the sake of brevity, details of the sram cell, standard logic cell, or finfet are not specifically discussed herein.

Fig. 15 shows a flow diagram of a method 900 according to an embodiment of the invention. The method 900 includes a step 910 of providing a plurality of gate structures and a plurality of conductive contacts, each formed on a substrate. A plurality of gate caps are respectively formed over the gate structures.

The method 900 includes a step 920 of etching back the conductive contacts, thereby forming a plurality of openings.

The method 900 includes a step 930 of forming a first dielectric layer over the gate cap and over the conductive contact. A first dielectric layer fills the opening.

The method 900 includes a step 940 of etching back the first dielectric layer into a plurality of first dielectric segments. Each dielectric segment is disposed on a respective one of the conductive contacts and partially fills a respective one of the openings.

The method 900 includes a step 950 of forming a second dielectric layer over the gate cap and over the first dielectric segment. A second dielectric layer fills the opening.

The method 900 includes a step 960 of etching the second dielectric layer to form a plurality of first vias over at least a subset of the conductive contacts.

The method 900 includes a step 970 of forming a conductive material to fill the first via.

The method 900 includes a step 980 of performing a planarization process to remove a portion of the conductive material and a portion of the second dielectric layer, thereby forming a plurality of first vias in the first vias.

In some embodiments, at least some of the first vias bridge with each other after etching the second dielectric layer (fig. 6, portion 430C).

In some embodiments, the first dielectric segment and the second dielectric layer have an etch selectivity and prevent the conductive contact located thereunder from being etched during the etching back of the first dielectric layer or during the etching of the second dielectric layer.

In some embodiments, a planarization process is performed until the gate cap is reached.

In some embodiments, the gate cap comprises silicon nitride, the first dielectric layer comprises zirconium oxide, and the second dielectric layer comprises silicon oxide.

It should be understood that additional processes may be performed before, during, or after steps 910-980 of method 900. For example, after etching the second dielectric layer but before forming the conductive material, the method 900 further comprises the step of etching the second dielectric layer and the gate cap with a plurality of second vias over at least a subset of the gate structures. The formation of the conductive material fills the second via and the planarization process forms a plurality of second vias in the second via. In some embodiments, the gate structure comprises a first gate structure, the conductive contact comprises a first conductive contact, at least one of the second vias is etched to laterally span the first gate structure and the first conductive contact, and a slotted contact is formed in the at least one second via, the slotted contact electrically connecting the first gate structure with the first conductive contact. The method 900 may further include steps such as forming additional metal layers, testing, packaging, etc. For the sake of brevity, other additional steps are not discussed in detail herein.

In summary, embodiments of the present invention relate to a unique manufacturing process for forming vias for conductive contacts and gate contacts for gate structures in semiconductor devices. The unique manufacturing flow cuts off a portion of the conductive material that may cause an electrical bridge between two adjacent vias or gate contacts. Accordingly, embodiments of the present invention provide advantageous advantages over conventional devices. However, it is to be understood that other embodiments may provide additional advantages, that not all advantages need be disclosed herein, and that not all embodiments need have a particular advantage. An advantage of an embodiment of the present invention is that the risk of bridging is prevented or reduced. As feature sizes of semiconductor devices continue to shrink, it may be difficult for photolithography to accurately resolve via openings (or gate contact openings) that are too close to each other. In conventional manufacturing methods, the via openings bridge with each other, which results in the final device having electrical short defects. The unique manufacturing flow of embodiments of the present invention prevents this bridging problem by self-aligning the vias and the source/drain contacts and using a grinding process to cut off the portion of conductive material that will bridge two adjacent vias (or gate contacts). Another benefit is that embodiments of the present invention can still maintain the formation of slotted contacts designed to "bridge" the gate structure and the source/drain contacts together while preventing inadvertent bridging between vias or gate contacts. Slotted contacts may be used in certain integrated circuit applications, such as sram cells. Another advantage is that the self-aligned vias formed in accordance with embodiments of the present invention have better electrical properties, such as resistivity, than conventional devices. Other advantages include compatibility with existing semiconductor device designs and fabrication, so embodiments of the present invention do not require additional processing and are therefore easy and inexpensive to implement.

One aspect of embodiments of the present invention relates to a semiconductor device. The first gate structure and the second gate structure are respectively disposed on the substrate. First and second conductive contacts are each disposed over the substrate. The first via is disposed above the first conductive contact. The second via is disposed over the second conductive contact. A first gate contact is disposed over the first gate structure. A dielectric structure is disposed over the first gate structure and over the second gate structure. The first portion of the dielectric structure is disposed between and electrically isolates the first via and the second via. The second portion of the dielectric structure is disposed between and electrically isolates the first via and the first gate contact. The first and second portions of the dielectric structure each comprise a single type of dielectric material. A first interface between the first conductive contact and the first via constitutes a first percentage of an upper surface area of the first conductive contact in cross-section. A second interface between the first gate structure and the first gate contact constitutes a second percentage of an upper surface area of the first gate structure in the cross-sectional view. The first percentage is greater than the second percentage.

In some embodiments, the ratio of the first percentage to the second percentage ranges between about 1.8: 1 to about 1.4: 1. in some embodiments, the first percentage is substantially equal to 100% in cross-sectional view. In some embodiments, the semiconductor device further comprises a plurality of gate spacers disposed on sidewalls of the first and second gate structures, wherein an upper surface of the gate spacers is disposed below and in direct contact with a portion of the dielectric structure. In some embodiments, the substrate comprises a first source/drain region and a second source/drain region, the first conductive contact disposed over the first source/drain region; and the second conductive contact is disposed over the second source/drain region. In some embodiments, the substrate further comprises a third source/drain region, and wherein the semiconductor device further comprises: a third gate structure disposed over the substrate; a third conductive contact disposed over the third source/drain region; and the slotted contact piece is arranged on the third grid structure and the third conductive contact piece and is electrically connected with the third grid structure and the third conductive contact piece. In some embodiments, the semiconductor device further comprises: a fourth conductive contact disposed over the substrate; a first dielectric layer disposed over the fourth conductive contact; and a second dielectric layer disposed over the first dielectric layer. In some embodiments, the semiconductor device further comprises: a fourth gate structure and a fifth gate structure disposed over the substrate, respectively, wherein a fourth conductive contact is disposed between the fourth gate structure and the fifth gate structure; a second gate contact disposed over the fourth gate structure; and a third gate contact disposed over the fifth gate structure, wherein the first and second dielectric layers are disposed between the second and third gate contacts. In some embodiments, the first dielectric layer has a first material composition; the second dielectric layer has a second material composition different from the first material composition; and the dielectric structure has a third material composition that is different from the first material composition and the second material composition. In some embodiments, the first material composition comprises zirconia; the second material composition comprises silicon oxide; and the third material composition comprises silicon nitride.

Another aspect of embodiments of the present invention relates to a semiconductor device. The gate structures are disposed on a substrate. A plurality of conductive contacts are disposed on the substrate. A plurality of gate contacts is disposed over the first subset of gate structures. A first dielectric material is disposed over the second subset of gate structures. A plurality of vias is disposed over the first subset of conductive contacts. A second dielectric material is disposed over a second subset of the conductive contacts. A third dielectric material is disposed over the second dielectric material. The first, second and third dielectric materials have different material compositions from one another. In the sectional view: each via occupies a first percentage of an upper surface area of a conductive contact disposed therebelow; each gate contact occupies a second percentage of an upper surface area of the gate structure disposed thereunder; and the first percentage is greater than the second percentage.

In some embodiments, the ratio of the first percentage to the second percentage ranges between about 1.8: 1 to about 1.4: 1. in some embodiments, the first dielectric material comprises silicon nitride; the second dielectric material comprises zirconium oxide; and the third dielectric material comprises silicon oxide.

Another aspect of embodiments of the present invention relates to a method for manufacturing a semiconductor device. A plurality of gate structures and a plurality of conductive contacts are each formed on a substrate, wherein a plurality of gate caps are each formed on the gate structures. The conductive contacts are etched back, thereby forming a plurality of openings. A first dielectric layer is formed over the gate cap and over the conductive contact, wherein the first dielectric layer fills the opening. The first dielectric layer is etched back into a plurality of first dielectric segments, wherein each first dielectric segment is disposed on a respective one of the conductive contacts and partially fills a respective one of the openings. A second dielectric layer is formed over the gate cap and over the first dielectric segment, wherein the second dielectric layer fills the opening. Etching the second dielectric layer to form a plurality of first vias over at least a subset of the conductive contacts. Forming a conductive material to fill the first via. A planarization process is performed to remove a portion of the conductive material and a portion of the second dielectric layer, thereby forming a plurality of first vias in the first vias.

In some embodiments, at least some of the first vias bridge with each other after etching the second dielectric layer. In some embodiments, the first dielectric segment has an etch selectivity with the second dielectric layer and prevents the conductive contact located thereunder from being etched during etching back the first dielectric layer or during etching the second dielectric layer. In some embodiments, the planarization process is performed until the gate cap is reached. In some embodiments, after etching the second dielectric layer but before forming the conductive material, further comprising: the second dielectric layer and gate cap are etched to form a plurality of second vias over at least a subset of the gate structures. In some embodiments, the forming of the conductive material fills the second via and the performing of the planarization process forms a plurality of second vias in the second via. In some embodiments, the gate structure comprises a first gate structure; the conductive contact comprises a first conductive contact; etching at least one second via to laterally cross the first gate structure and first conductive contact; and forming a slotted contact in the at least one second via, the slotted contact electrically connecting the first gate structure with the first conductive contact. In some embodiments, the providing includes forming a plurality of gate caps, the gate caps including silicon nitride; forming the first dielectric layer comprises forming zirconium oxide; and forming the second dielectric layer comprises forming silicon oxide.

The components of several embodiments are summarized above so that those skilled in the art to which the present invention pertains can more clearly understand the orientation of the embodiments of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure. For example, by making the bit line (bit line) conductor and word line (word line) conductor have different thicknesses, these conductors can be made to have different resistances. However, other techniques for changing the resistance of the metal conductor may also be used.