阅读说明：本技术 稳压器、动态随机存取存储器、及位元线电压的稳定方法 (Voltage stabilizer, dynamic random access memory and method for stabilizing bit line voltage ) 是由 陈至仁 许庭硕 于 2018-10-26 设计创作，主要内容包括：本公开提供一种稳压电路、动态随机存取存储器、以及位元线电压的稳定方法。该稳压电路包括一分压模块、一第一稳压模块和一第二稳压模块。该分压模块经配置以产生复数个参考电压。该分压模块包括复数个电阻器和一晶体管单元。该晶体管单元耦合至复数个电阻器且经配置以互补式调整该复数个电阻器的电阻。该第一稳压模块耦合至该分压模块且经配置以产生一第一稳压。该第一稳压相同于该复数个参考电压的一中间参考电压。该第二稳压模块耦合至该分压模块且经配置以产生一第二稳压。该第二稳压相同于该复数个参考电压中的一参考电压,但不同于该中间参考电压。(The present disclosure provides a voltage stabilizing circuit, a dynamic random access memory, and a method for stabilizing a bit line voltage. The voltage stabilizing circuit comprises a voltage dividing module, a first voltage stabilizing module and a second voltage stabilizing module. The voltage divider module is configured to generate a plurality of reference voltages. The voltage division module comprises a plurality of resistors and a transistor unit. The transistor unit is coupled to a plurality of resistors and configured to complementarily adjust resistances of the plurality of resistors. The first voltage stabilization module is coupled to the voltage division module and configured to generate a first stabilized voltage. The first stable voltage is the same as an intermediate reference voltage of the plurality of reference voltages. The second voltage stabilization module is coupled to the voltage division module and configured to generate a second stabilized voltage. The second stable voltage is the same as one of the plurality of reference voltages, but different from the intermediate reference voltage.)

1. A voltage regulator circuit, comprising:

A voltage division module configured to generate a plurality of reference voltages;

A first voltage stabilization module coupled to the voltage division module and configured to generate a first voltage stabilization, wherein the first voltage stabilization is the same as an intermediate reference voltage of the plurality of reference voltages; and

A second voltage stabilization module coupled to the voltage division module and configured to generate a second voltage stabilization, wherein the second voltage stabilization is the same as one of the plurality of reference voltages but different from the intermediate reference voltage.

2. The voltage regulator circuit of claim 1, further comprising:

A first enable module coupled to the first voltage regulator module and configured to generate a first enable signal; and

A second enable module coupled to the second voltage regulator module and configured to generate a second enable signal.

3. The voltage regulator circuit of claim 2, further comprising a control module coupled to the first enable module and the second enable module, wherein the control module is configured to send a control signal to the first enable module and the second enable module.

4. The voltage regulator circuit of claim 3, wherein the control module sends the control signal to the first enable module and the second enable module under different conditions.

5. The voltage regulator circuit of claim 1, wherein:

The voltage divider module is further configured to convert a memory array voltage into the plurality of reference voltages; and

The voltage division module includes a plurality of resistors and a transistor unit coupled to the plurality of resistors and configured to complementarily adjust resistances of the plurality of resistors.

6. The voltage regulator circuit of claim 1, wherein:

The first voltage stabilizing module comprises an operational amplifier coupled to the voltage dividing module; and

The operational amplifier is configured to generate the first regulated voltage.

7. the voltage regulator circuit of claim 1, wherein:

The second voltage stabilizing module comprises two operational amplifiers coupled to the voltage dividing module; and

One of the two operational amplifiers is configured to generate the second regulated voltage.

8. a dynamic random access memory comprising:

A memory array;

a plurality of bit lines in the memory array; and

a voltage stabilizing module coupled to the plurality of bit lines;

Wherein this steady voltage module includes:

A voltage divider module configured to generate a plurality of reference voltages;

A first voltage stabilization module coupled to the voltage division module and configured to generate a first voltage stabilization, wherein the first voltage stabilization is the same as an intermediate reference voltage of the plurality of reference voltages; and

A second voltage stabilization module coupled to the voltage division module and configured to generate a second voltage stabilization, wherein the second voltage stabilization module is the same as a reference voltage of the plurality of reference voltages but different from the intermediate reference voltage.

9. The dynamic random access memory of claim 8, further comprising:

A first enable module coupled to the first voltage regulator module and configured to generate a first enable signal; and

A second enable module coupled to the second voltage regulator module and configured to generate a second enable signal.

10. the dynamic random access memory of claim 9, further comprising a control module coupled to the first enable module and the second enable module, wherein the control module is configured to send a control signal to the first enable module and the second enable module.

11. The dynamic random access memory according to claim 10, wherein the control module sends the control signal to the first enabling module and the second enabling module under different conditions.

12. The dynamic random access memory of claim 8, wherein:

The voltage divider module is further configured to convert a memory array voltage into the plurality of reference voltages; and

The voltage division module includes a plurality of resistors and a transistor unit coupled to the plurality of resistors and configured to complementarily adjust resistances of the plurality of resistors.

13. The dynamic random access memory of claim 8, wherein the first voltage regulation module comprises an operational amplifier coupled to the voltage division module and configured to generate the first voltage regulation.

14. The dynamic random access memory of claim 8, wherein:

the second voltage stabilizing module comprises two operational amplifiers coupled to the voltage dividing module; and

One of the two operational amplifiers is configured to generate the second regulated voltage.

15. A method for stabilizing a bit line voltage, comprising:

Generating a plurality of reference voltages;

generating a first stable voltage which is a middle reference voltage identical to the plurality of reference voltages; and

The first voltage regulator is coupled to a bit line voltage in a first operating state or a second operating state.

16. The method of claim 15, wherein the plurality of reference voltages are generated by distributing a memory array voltage.

17. The method of claim 15, further comprising enabling a first regulation module configured to generate the first regulation voltage.

18. The method of claim 17, further comprising:

Generating a second regulated voltage that is the same as one of the plurality of reference voltages but different from the intermediate reference voltage; and

In the second operating state, the second regulator is coupled to the bit line voltage.

19. the method of claim 18, further comprising enabling a second regulation module configured to generate the second regulation voltage.

20. the method of claim 19, further comprising: a control signal is generated under different conditions and configured to control a first enabling module and a second enabling module.

Technical Field

The present disclosure relates to a circuit, a Dynamic Random Access Memory (DRAM), and a method. More particularly, to a regulator circuit, a dynamic random access memory, and a method for stabilizing a bit line voltage.

background

The dynamic random access memory comprises a memory array, wherein the memory array comprises a plurality of bit lines. When the memory array reads or writes data, the memory array current is consumed, thereby reducing the voltage of the plurality of bit lines.

The above description of "prior art" is merely provided as background, and it is not an admission that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute prior art to the present disclosure, and that any description of "prior art" above should not be taken as an admission that it is any part of the present disclosure.

Disclosure of Invention

an embodiment of the present disclosure provides a voltage regulator circuit. The voltage stabilizing circuit comprises a voltage dividing module, a first voltage stabilizing module and a second voltage stabilizing module. The voltage divider module is configured to generate a plurality of reference voltages. The first voltage stabilization module is coupled to the voltage division module and configured to generate a first voltage stabilization, wherein the first voltage stabilization is the same as an intermediate reference voltage of the plurality of reference voltages. The second voltage stabilization module is coupled to the voltage division module and configured to generate a second voltage stabilization, wherein the second voltage stabilization is the same as one of the plurality of reference voltages but different from the intermediate reference voltage.

In some embodiments of the present disclosure, the voltage regulator circuit further includes a first enable module and a second enable module. The first enable module is coupled to the first voltage regulation module and configured to generate a first enable signal. The second enabling module is coupled to the second voltage stabilizing module and configured to generate a second enabling signal.

In some embodiments of the present disclosure, the voltage regulator circuit further includes a control module coupled to the first enable module and the second enable module, wherein the control module is configured to send a control signal to the first enable module and the second enable module.

In some embodiments of the present disclosure, the control module sends the control signal to the first enabling module and the second enabling module under different conditions.

In some embodiments of the present disclosure, the voltage divider module is further configured to convert a memory array voltage into the plurality of reference voltages. In some embodiments of the present disclosure, the voltage divider module includes a plurality of resistors and a transistor unit. The transistor unit is coupled to the plurality of resistors and configured to complementarily adjust the resistances of the plurality of resistors.

In some embodiments of the present disclosure, the first voltage stabilization module includes an operational amplifier coupled to the voltage division module, wherein the operational amplifier is configured to generate the first stabilization voltage.

in some embodiments of the present disclosure, the second voltage stabilization module includes two operational amplifiers coupled to the voltage divider module. In some embodiments of the present disclosure, one of the two operational amplifiers is configured to generate the second regulated voltage.

Another embodiment of the present disclosure provides a Dynamic Random Access Memory (DRAM). The DRAM includes a memory array, a plurality of bit lines and a voltage stabilizing module. The plurality of bit lines are located in the memory array. The voltage stabilizing module is coupled to the plurality of bit lines. In some embodiments of the present disclosure, the voltage stabilization module includes a voltage division module, a first voltage stabilization module, and a second voltage stabilization module. The voltage divider module is configured to generate a plurality of reference voltages. The first voltage stabilization module is coupled to the voltage division module and configured to generate a first stabilized voltage, wherein the first stabilized voltage is identical to an intermediate reference voltage of the plurality of reference voltages. The second voltage stabilization module is coupled to the voltage division module and configured to generate a second voltage stabilization, wherein the second voltage stabilization is the same as one of the plurality of reference voltages but different from the intermediate reference voltage.

In some embodiments of the present disclosure, the DRAM further includes a first enabling module and a second enabling module. The first enable module is coupled to the first voltage regulation module and configured to generate a first enable signal. The second enabling module is coupled to the second voltage stabilizing module and configured to generate a second enabling signal.

In some embodiments of the present disclosure, the DRAM further comprises a control module coupled to the first enable module and the second enable module, wherein the control module is configured to send a control signal to the first enable module and the second enable module.

In some embodiments of the present disclosure, the control module sends the control signal to the first enabling module and the second enabling module under different conditions.

In some embodiments of the present disclosure, the voltage divider module is further configured to convert a memory array voltage into the plurality of reference voltages. In some embodiments of the present disclosure, the voltage divider module includes a plurality of resistors and a transistor unit. The transistor unit is coupled to the plurality of resistors and configured to complementarily adjust the resistances of the plurality of resistors.

In some embodiments of the present disclosure, the first voltage stabilization module includes an operational amplifier coupled to the voltage division module, wherein the operational amplifier is configured to generate the first stabilization voltage.

In some embodiments of the present disclosure, the second voltage stabilization module includes two operational amplifiers coupled to the voltage divider module. In some embodiments of the present disclosure, one of the two operational amplifiers is configured to generate the second regulated voltage.

another embodiment of the present disclosure provides a method for stabilizing a bit line voltage. The method comprises the following steps. A plurality of reference voltages are generated. A first regulated voltage is generated that is the same as an intermediate reference voltage of the plurality of reference voltages. The first voltage regulator is coupled to a bit line voltage in a first operating state and a second operating state.

In some embodiments of the present disclosure, the plurality of reference voltages are generated by distributing a memory array voltage.

In some embodiments of the present disclosure, the method further comprises a step of: a first voltage stabilization module is enabled and configured to generate the first voltage stabilization.

In some embodiments of the present disclosure, the method further comprises the following steps. A second regulated voltage is generated that is the same as one of the plurality of reference voltages but different from the intermediate reference voltage. In the second operating state, the second regulator is coupled to the bit line voltage.

In some embodiments of the present disclosure, the method further comprises a step of: enabling a second voltage stabilization module configured to generate the second stabilization voltage.

In some embodiments of the present disclosure, the method further comprises a step of: a control signal is generated under different conditions and configured to control a first enabling module and a second enabling module.

The working current required for stabilizing the bit line voltage is reduced by using the configured voltage stabilizing circuit. In addition, the efficiency and the precision of the voltage stabilizing procedure are improved.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

The disclosure will become more fully understood from the consideration of the following description and the appended claims, taken in conjunction with the accompanying drawings, wherein like reference numerals refer to like elements.

Fig. 1 is a block diagram illustrating a DRAM according to an embodiment of the present disclosure.

FIG. 2 is a block diagram illustrating a voltage stabilizing circuit of a DRAM according to an embodiment of the present disclosure.

FIG. 3 is a block diagram illustrating a voltage divider module of a voltage regulator circuit according to an embodiment of the present disclosure.

FIG. 4 is a block diagram illustrating a first voltage regulation module of the voltage regulation circuit of the present disclosure.

FIG. 5 is a block diagram illustrating a second voltage regulation module of the voltage regulation circuit of the present disclosure.

FIG. 6 is a block diagram illustrating another voltage stabilizing circuit of the DRAM according to the disclosed embodiment.

FIG. 7 is a flow chart illustrating a method for stabilizing bit line voltage according to an embodiment of the present disclosure.

Fig. 8 is a schematic diagram illustrating an enabled state of the first voltage regulation module and the second voltage regulation module according to the embodiment of the disclosure.

FIG. 9 is a diagram illustrating voltage swing of bit lines according to an embodiment of the disclosure.

FIG. 10 is a block diagram of a comparative voltage regulator circuit.

FIG. 11 is a block diagram illustrating a voltage divider module of a comparison voltage regulator circuit.

FIG. 12 is a block diagram illustrating a first voltage regulation module of the comparison voltage regulation circuit.

FIG. 13 is a block diagram illustrating a second voltage regulation module of the comparison voltage regulation circuit.

FIG. 14 is a diagram illustrating the voltage swing of the bit line when the DRAM includes the comparison voltage regulator circuit.

Description of reference numerals:

1 Voltage regulator circuit

1' voltage stabilizing circuit

2 method

9 Dynamic Random Access Memory (DRAM)

10 output voltage

11 voltage division module

11' voltage division module

12 first voltage stabilization module

12' first voltage stabilization module

13 first enabling module

14 second voltage stabilization module

14' second voltage stabilization module

15 second enabling module

16 control module

17 bit line precharge Voltage (VBLP) output

Step 21

22 step

23 step (ii)

91 memory array

92 column decoder

93 address buffer

94 sense amplifier

95 input/output (I/O) buffer

96-line decoder

97 instruction decoder

98 word line

99 bit line

111 Voltage measuring Unit

112 transistor cell

111' Voltage measurement Unit

112' transistor cell

121 first operational amplifier

121' first operational amplifier

122' second operational amplifier

141 first operational amplifier

142 second operational amplifier

141' third operational amplifier

142' fourth operational amplifier

Sc control signal

Se1 first enable signal

Se2 second enable signal

VBL bit line voltage

Vma memory array voltage

VR1 reference voltage

VR1' reference voltage

VR2 reference voltage

VR2' reference voltage

VR3 reference voltage

Vs1 first stabilization

Vs2 second stabilization

Vs1' first stabilization

Vs2' second stabilization

R1 transistor

R1' resistor

R2 transistor

R2' resistor

R3 transistor

R3' resistor

R4 transistor

Detailed Description

The following description of the present disclosure, which is accompanied by the accompanying drawings incorporated in and forming a part of the specification, illustrates embodiments of the present disclosure, however, the present disclosure is not limited to the embodiments. In addition, the following embodiments may be appropriately integrated to complete another embodiment.

References to "one embodiment," "an example embodiment," "other embodiments," "another embodiment," etc., indicate that the embodiment described in this disclosure may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, repeated usage of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may.

The following description provides detailed steps and structures in order to provide a thorough understanding of the present disclosure. It will be apparent that the implementation of the disclosure does not limit the specific details known to those skilled in the art. In addition, well-known structures and steps are not shown in detail to avoid unnecessarily limiting the disclosure. Preferred embodiments of the present disclosure are described in detail below. However, the present disclosure may be practiced in other embodiments, which depart from the specific details. The scope of the present disclosure is not limited by the detailed description but is defined by the claims.

fig. 1 is a block diagram illustrating a DRAM9 of the disclosed embodiment. Referring to FIG. 1, in some embodiments, DRAM9 includes a memory array 91, a plurality of row decoders 92, an address buffer 93, a plurality of sense amplifiers 94, an input/output (I/O) buffer 95, a plurality of column decoders 96, a command decoder 97, a plurality of word lines 98, and a plurality of bit lines 99. In some embodiments, an address buffer 93 is coupled to the plurality of row decoders 92. In some embodiments, a plurality of sense amplifiers 94 are coupled to the memory array 91. In some embodiments, an input-output (I/O) buffer 95 is coupled to the plurality of sense amplifiers 94. In some embodiments, a plurality of column decoders 96 are coupled to a plurality of sense amplifiers 94. In some embodiments, the command decoder 97 is coupled to an address buffer 93, a plurality of column decoders 96, a plurality of sense amplifiers 94, and an input/output (I/O) buffer 95. In some embodiments, a plurality of word lines 98 are located in the memory array 91. In some embodiments, a plurality of bit lines 99 are located in the memory array 91 and intersect the plurality of word lines 98. In some embodiments, the DRAM9 includes a voltage regulator 1 coupled to a plurality of bit lines 99.

Fig. 2 is a block diagram illustrating a voltage stabilizing circuit 1 of the DRAM9 according to the embodiment of the present disclosure. Referring to fig. 2, in some embodiments, the voltage regulator circuit 1 includes an output voltage 10, a voltage divider module 11, a first voltage regulator module 12, a first enable module 13, a second voltage regulator module 14, a second enable module 15, a control module 16, and a bit line precharge Voltage (VBLP) output 17.

referring to FIG. 2, in some embodiments, the first regulation module 12 is coupled to the VBLP output 17 and is configured to generate a first regulation voltage (Vs 1). In some embodiments, the second regulation module 14 is coupled to the VBLP output 17 and is configured to generate a second regulation voltage (Vs 2). In some embodiments, the first enable module 13 is coupled to the first regulator module 12 and configured to generate a first enable signal (Se 1). In some embodiments, the second enabling module 15 is coupled to the second voltage stabilizing module 14 and configured to generate a second enabling signal (Se 2). In some embodiments, voltage divider module 11 is coupled between voltage input 10 and first voltage regulation module 12, and is coupled between voltage input 10 and second voltage regulation module 14. In some embodiments, the voltage divider module 11 is configured to divide the memory array voltage (Vma) into a plurality of reference voltages. In some embodiments, control module 16 is coupled to first enabling module 13 and second enabling module 15. In some embodiments, control module 16 is configured to generate a control signal (Sc).

Referring to fig. 2, in some embodiments, when the DRAM9 is in a first operation state (e.g., a standby state), the control module 16 sends a control signal (Sc) to the first enabling module 13 to control the first enabling module 13 to send a first enabling signal (Se1) to start the first voltage stabilizing module 12, and when the DRAM9 is in a second operation state (e.g., a read/write state), the control module 16 sends a control signal (Sc) to the first enabling module 13 to control the first enabling module 13 to send a first enabling signal (Se1) to start the first voltage stabilizing module 12, and sends another control signal (Sc) to the second enabling module 15 to control the second enabling module 15 to send a second enabling signal (Se2) to start the second voltage stabilizing module 14.

Fig. 3 is a block diagram illustrating the voltage dividing module 11 of the voltage stabilizing circuit 1 according to the embodiment of the present disclosure. Referring to fig. 3, in some embodiments, the voltage dividing module 11 includes a voltage measuring unit 111, a transistor unit 112, and a plurality of resistors. In some embodiments, the voltage measurement unit 111 is coupled to the voltage input 10 and is configured to measure the memory array voltage (Vma) with the voltage input 10. In some embodiments, the transistor unit 112 is coupled between the voltage measurement unit 111 and a plurality of resistors. The transistor unit 112 is configured to complementarily adjust the resistances of the plurality of resistors. In some embodiments, the voltage divider module 11 is configured to generate a plurality of reference voltages. In some embodiments, the memory array voltage (Vma) is converted to the plurality of reference voltages by the plurality of resistors. In some embodiments, the resistances of the plurality of resistors are all the same, while in other embodiments, the resistances of the plurality of resistors may be different from one another.

Referring to fig. 3, in some embodiments, the transistor unit 112 includes a plurality of transistors. In some embodiments, the plurality of transistors may be Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). In some embodiments, the plurality of transistors each include a gate, a drain, and a source, and each of the plurality of transistors has a linear resistance when the plurality of transistors are driven, thereby defining a drain-source on-resistance. In some embodiments, the complementary resistances of the plurality of transistors may be implemented by respective drain-source on-resistances of the plurality of transistors.

Referring to fig. 3, in some embodiments, since RDS is controlled by the gate-to-source voltage, RDS may be varied by adjusting the gate-to-source voltage. Thus, complementary resistance can be achieved by a plurality of transistors at different gate-to-source voltages.

Referring to fig. 3, in some embodiments, the voltage dividing module 11 includes 4 transistors (R1, R2, R3, and R4), however, in other embodiments, the number of transistors in the voltage dividing module 11 may vary. In some embodiments, 4 transistors (R1, R2, R3, and R4) split the memory array voltage (Vma) into three reference voltages (VR1, VR2, and VR3), although in other embodiments such a configuration may vary.

FIG. 4 is a block diagram illustrating the first regulator module 12 of the voltage regulator circuit 1 according to an embodiment of the present disclosure. Referring to fig. 4, in some embodiments, the first regulation module 12 includes a first operational amplifier 121 coupled between the voltage divider module 11 (see fig. 3) and the VBLP output 17, and the first operational amplifier 121 is configured to generate a first regulated voltage (Vs 1). In some embodiments, the first regulated voltage (Vs1) is the same as an intermediate reference voltage of the plurality of reference voltages. In some embodiments, the first regulated voltage (Vs1) is the same as the second reference voltage (VR 2). In some embodiments, the first regulated voltage (Vs1) is coupled to a plurality of bit lines 99 (see FIG. 1) via the VBLP output 17. In some embodiments, the first voltage regulator module 12 may be a voltage follower circuit (voltage follower circuit), but in other embodiments, may vary with configuration.

Referring to fig. 4, in some embodiments, generating the first enable signal is configured to initiate operation of the first operational amplifier 121 in the first voltage stabilization module 12 when the DRAM9 is in a standby state or a read/write state.

FIG. 5 is a block diagram illustrating the second voltage regulation module 14 of the voltage regulation circuit 1 of the present disclosure. Referring to fig. 5, in some embodiments, the second voltage stabilization module 14 includes a second operational amplifier 141 and a third operational amplifier 142. In some embodiments, the second operational amplifier 141 and the third operational amplifier 142 are coupled between the voltage divider module 11 (see fig. 3) and the VBLP output 17. In some embodiments, a first reference voltage (VR1) is sent to the second operational amplifier 141 and a third reference voltage (VR3) is sent to the third operational amplifier 142, although in other embodiments such a configuration may vary. In some embodiments, the second voltage stabilization module 141 may be implemented by two voltage follower circuits, the second voltage stabilization module 141 is coupled to one of the two voltage follower circuits, and the third operational amplifier 142 is coupled to the other of the two voltage follower circuits. In other embodiments, the combination of the two voltage follower circuits may vary. In some embodiments, the second regulated voltage (Vs2) is the same as the highest or lowest voltage of the plurality of reference voltages. In some embodiments, the second regulated voltage (Vs2) is the same as the first reference voltage (VR1) or the third reference voltage (VR 3). In some embodiments, the second regulated voltage (Vs2) is coupled to a plurality of bit lines 99 (see FIG. 1) via the VBLP output 17.

referring to fig. 5, in some embodiments, when the DRAM9 is in the read/write state, the second enable signal (Se2) is generated to start the operation of the second operational amplifier 141 or the third operational amplifier 142 in the second voltage stabilizing module 14. In some embodiments, based on the second enable signal (Se2), the second operational amplifier 141 or the third operational amplifier 142 is configured to generate a second regulated voltage (Vs 2).

FIG. 6 is a block diagram illustrating another voltage stabilizing circuit 100 for the DRAM9 of the disclosed embodiment. Referring to FIG. 6, in some embodiments, the regulator circuit 100 is substantially similar to the regulator circuit 1 except for the number of the second regulator modules 14 and the second enable modules 15. In some embodiments, the voltage regulator circuit 1 of fig. 2 includes a second voltage regulator module 14 and a second enable module 15, and the second enable module 15 is coupled to the second voltage regulator module 14; in contrast, the voltage regulator circuit 100 includes a plurality of second voltage regulator modules 14 and a plurality of second enable modules 15, and the second enable modules 15 are respectively coupled to the second voltage regulator modules 14.

FIG. 7 is a flowchart illustrating a bit line Voltage (VBL) stabilization method 2 according to an embodiment of the present disclosure. Referring to fig. 7, in some embodiments, method 2 includes step 21: generating a plurality of reference voltages; step 22: generating a first regulated voltage (Vs1) that is the same as an intermediate reference voltage of the plurality of reference voltages; step 23: coupling the first regulated voltage (Vs1) and the bit line Voltage (VBL).

Fig. 8 is a schematic diagram illustrating an enabled state of the first voltage regulation module 12 and the second voltage regulation module 14 according to the embodiment of the disclosure. Referring to fig. 8, in some embodiments, the operation of the DRAM9 may be divided into 3 states: a dormant state: DRAM9 is not activated; standby state: the elements of the DRAM9 are precharged to a preset value; and read/write state: the memory array 91 (see fig. 1) of the DRAM9 performs a data read program or a data write program.

Referring to fig. 8, in some embodiments, when the DRAM9 is in a sleep state, the first and second voltage stabilization modules 12 and 14 are not activated; when the DRAM9 is in the standby state, the first voltage stabilization module 12 is activated and configured to generate a first voltage stabilization (Vs1) (see FIG. 1) on the plurality of bit lines 99, so that the bit line voltage of the plurality of bit lines 99 is stabilized at a second reference voltage, and the second voltage stabilization module 14 is not activated as well; and when the DRAM9 is in the read/write state, the first voltage stabilizing module 12 is activated to continuously generate the first voltage (Vs1), and the second voltage stabilizing module 14 is activated to generate the second voltage (Vs2), such that the second voltage (Vs2) stabilizes the bit line Voltage (VBL) of the plurality of bit lines 99 for the second time.

Referring to FIG. 8, in some embodiments, when the DRAM9 is in a standby state, the bit line voltage of each of the plurality of bit lines 99 is not lowered; and the bit line Voltage (VBL) of the plurality of bit lines 99 is stabilized at the second reference voltage (VR2) by the first stabilizing voltage (Vs 1). In some embodiments, when the DRAM9 is in the read/write state, since the current flowing in the plurality of bit lines 99 is consumed by operating the memory array 91, the voltage of each bit line of the plurality of bit lines 99 is lowered, thereby causing a voltage drop of the plurality of bit lines 99; in some embodiments, when the bit line Voltage (VBL) of each bit line 99 drops below the minimum reference voltage, the second voltage stabilization (Vs2) stabilizes the bit line Voltage (VBL) for a second time.

FIG. 9 is a diagram illustrating voltage swing of the bit line 99 according to the embodiment of the disclosure. Referring to fig. 9, in some embodiments, before the first time point (t1), the DRAM9 is in a standby state, and between the first time point (t1) and the second time point (t2), the DRAM9 is in a read/write state. In some embodiments, when the DRAM9 is in the standby state, the bit line Voltage (VBL) of each bit line 99 oscillates around the second reference voltage (VR2) under the influence of the first voltage (Vs 1). In some embodiments, when the DRAM9 is in the read/write state, the bit line Voltage (VBL) of each bit line 99 first drops to less than the third reference voltage (VR3) due to the voltage drop of each bit line 99, and then the second regulated voltage (Vs2) pulls the bit line Voltage (VBL) of each bit line 99 to the first regulated voltage (VR 1). In some embodiments, when the voltage drop occurs on each bit line 99, the bit line Voltage (VBL) of each bit line 99 is reduced to be less than the third reference voltage (VR3), and the second voltage stabilization (Vs2) pulls the bit line Voltage (VBL) of each bit line 99 to the first voltage stabilization (VR 1). In some embodiments, the amplitude of the oscillation of the bit line Voltage (VBL) of each bit line 99 when the DRAM9 is in the read/write state is greater than the amplitude of the oscillation of the bit line Voltage (VBL) of each bit line 99 when the DRAM9 is in the standby state.

Fig. 10 is a block diagram of a comparative voltage stabilizing circuit 1'. Referring to fig. 10, the comparison voltage stabilizing circuit 1 'is substantially similar to the voltage stabilizing circuit 1 of the present disclosure, except that the voltage dividing module 11', the first voltage stabilizing module 12 'and the second voltage stabilizing module 14' are different. The first and second voltage regulation modules 12', 14' are coupled to the VBLP output 17. The first enabling module 13 is coupled to the first regulator module 12'. The second enabling module 15 is coupled to the second voltage stabilizing module 14'. The voltage divider module 11' is coupled between the voltage input 10 and the first voltage regulation module 12' and between the voltage input 10 and the second voltage regulation module 14 '.

Fig. 11 is a block diagram illustrating a voltage dividing module 11 'of the comparison voltage stabilizing circuit 1'. Referring to fig. 11, the voltage division module 11' is configured to generate two reference voltages (VR1' and VR2') and includes a voltage measurement unit 111', a transistor unit 112', and a plurality of resistors. The configuration of the voltage measuring unit 111 'and the transistor unit 112' is similar to the configuration of the voltage measuring unit 111 and the transistor unit 112 in the voltage stabilizing circuit 1 of the present disclosure (see fig. 3). The voltage divider module 11' includes three resistors (R1', R2', and R3') for converting the memory array voltage (Vma) into two reference voltages (VR1' and VR2') by means of the three resistors (R1', R2', and R3 ').

FIG. 12 is a block diagram illustrating a first voltage regulation module 12 'of the comparative voltage regulation circuit 1'. Referring to fig. 12, the voltage divider module 12 includes a first operational amplifier 121' and a second operational amplifier 122', both coupled between the voltage divider module 11' (see fig. 11) and the VBLP output 17. The first reference voltage (VR1') is sent to the first operational amplifier 121' and the second reference voltage (VR2') is sent to the second operational amplifier 122'. The first voltage stabilization module 12' may be two voltage follower circuits, with a first operational amplifier 121' coupled to one of the two voltage follower circuits and a second operational amplifier 122' coupled to the other of the two voltage follower circuits. The first trim module 12 'is configured to generate a first trim voltage (Vs 1'). The first regulated voltage (Vs1') is the same as the first reference voltage (VR1') or the second reference voltage (VR2 '). One of the first operational amplifier 121' or the second operational amplifier 122' will be configured to generate a first regulated voltage (Vs1') based on the first enable signal (Se1) in the first enable module 13. The first regulated voltage (Vs1') is coupled to a plurality of bit lines 99 (see FIG. 1) via VBLP output 17.

FIG. 13 is a block diagram illustrating the second voltage regulation module 14 'of the comparison voltage regulation circuit 1'. Referring to fig. 13, the second voltage stabilization module 14 'includes a third operational amplifier 141' and a fourth operational amplifier 142 'both coupled between the voltage divider module 11' (see fig. 11) and the VBLP output 17. The first reference voltage (VR1') is sent to the third operational amplifier 141' and the second reference voltage (VR2') is sent to the fourth operational amplifier 142'. The second voltage stabilization module 14' may be implemented by two voltage follower circuits, a third operational amplifier 141' coupled to one of the two voltage follower circuits, and a fourth operational amplifier 142' coupled to the other of the two voltage follower circuits. The second trim module 14 'is configured to generate a second trim (Vs 2'). The second regulated voltage (Vs2') is the same as the first reference voltage (VR1') or the second reference voltage (VR2 '). One of the third operational amplifier 141' or the fourth operational amplifier 142' is configured to generate a second regulated voltage (Vs2') based on a second enable signal (Se2) in the second enabling module 15. The second regulated voltage (Vs2') is coupled to a plurality of bit lines 99 (see FIG. 1) via VBLP output 17.

The first and second voltage regulation modules 12', 14' are substantially similar to each other, with the primary difference being that the first and second voltage regulation modules 12', 14' include the basic parameters of a plurality of transistors. For example, the gate length, gate width, and resistance of each transistor included in the first voltage regulation block 12 'are different from the gate length, gate width, and resistance of each transistor included in the second voltage regulation block 14'.

During the voltage stabilization of the comparison voltage stabilizing circuit 1', when the DRAM9 is in a standby state, the bit line Voltage (VBL) of the bit line 99 may be greater than the first reference voltage (VR1') or less than the second reference voltage (VR2'), and the first voltage stabilizer (Vs1') pulls up or down the bit line Voltage (VBL) of the bit line 99 to stabilize the bit line Voltage (VBL) of the bit line 99 between the first reference voltage (VR1') and the second reference voltage (VR 2'). When the DRAM9 is in the read/write state, and when the voltage drop occurs on the bit line 99, the bit line Voltage (VBL) of the bit line 99 is lowered to a voltage less than the second reference voltage (VR2'), and the second reference voltage (VR2') will again stabilize the bit line Voltage (VBL) of the bit line 99 between the first reference voltage (VR1') and the second reference voltage (VR 2').

FIG. 14 is a schematic diagram illustrating the voltage swing of the bit line 99 when the DRAM9 includes the comparison regulator 1'. Referring to fig. 14, when the DRAM9 is in a standby state, the bit line Voltage (VBL) of each bit line 99 oscillates between a first reference voltage (VR1') and a second reference voltage (VR2') under the influence of a first regulated voltage (Vs1 '). When the DRAM9 is in the read/write state, the bit line Voltage (VBL) is first decreased to be less than the second reference voltage (VR2') due to the voltage drop of the bit line Voltage (VBL) of each bit line 99, and then the second regulated voltage (Vs2') pulls up the bit line Voltage (VBL) of each bit line 99 to the first regulated voltage (Vs1 '). When another voltage drop occurs to the bit line Voltage (VBL) of each bit line 99, the bit line Voltage (VBL) of each bit line 99 is again decreased to a voltage less than the third reference voltage (VR3'), and the second regulated voltage (Vs2') again pulls up the bit line Voltage (VBL) of each bit line 99 to the first reference voltage (VR1 ').

during the voltage stabilization of the comparison voltage stabilizing circuit 1', when the DRAM9 is in a standby state, the bit line Voltage (VBL) of the bit line 99 oscillates between the first reference voltage (VR1') or the second reference voltage (VR2 '). In such a configuration, when the DRAM9 is changed from the standby state to the read/write state and a voltage drop occurs in the bit line Voltage (VBL) of the bit line 99, a large amount of time and an operating current are required to stabilize the bit line Voltage (VBL) of the bit line 99. In contrast, the voltage stabilizing circuit 1 of the present disclosure has a small amplitude of oscillation of the bit line Voltage (VBL) of the bit line 99 because the bit line Voltage (VBL) of the bit line 99 oscillates around the second reference voltage (VR2) when the DRAM9 is in the standby state during the voltage stabilization. In addition, when the DRAM9 is changed from the standby state to the read/write state and the bit line Voltage (VBL) of the bit line 99 drops, less time and a small amount of operating current are required to stabilize the bit line Voltage (VBL) of the bit line 99. Therefore, the voltage stabilizing process of the voltage stabilizing circuit 1 in the present disclosure has higher stabilizing accuracy and better efficiency than the comparative structure.

An embodiment of the present disclosure provides a voltage regulator circuit. The voltage stabilizing circuit comprises a voltage dividing module, a first voltage stabilizing module and a second voltage stabilizing module. The voltage divider module is configured to generate a plurality of reference voltages. The first voltage stabilization module is coupled to the voltage division module and configured to generate a first voltage stabilization, wherein the first voltage stabilization is the same as an intermediate reference voltage of the plurality of reference voltages. The second voltage stabilization module is coupled to the voltage division module and configured to generate a second voltage stabilization, wherein the second voltage stabilization is the same as one of the plurality of reference voltages but different from the intermediate reference voltage.

An embodiment of the present disclosure provides a Dynamic Random Access Memory (DRAM). The DRAM includes a memory array, a plurality of bit lines and a voltage stabilizing module. The plurality of bit lines are located in the memory array. The voltage stabilizing module is coupled to the plurality of bit lines. In some embodiments, the voltage stabilization module includes a voltage divider module, a first voltage stabilization module, and a second voltage stabilization module. The voltage divider module is configured to generate a plurality of reference voltages. The first voltage stabilization module is coupled to the voltage division module and configured to generate a first stabilized voltage, wherein the first stabilized voltage is identical to an intermediate reference voltage of the plurality of reference voltages. The second voltage stabilization module is coupled to the voltage division module and configured to generate a second voltage stabilization, wherein the second voltage stabilization is the same as one of the plurality of reference voltages but different from the intermediate reference voltage.

An embodiment of the present disclosure provides a method for stabilizing a bit line voltage. The method comprises the following steps. A plurality of reference voltages are generated. A first regulated voltage is generated that is the same as an intermediate reference voltage of the plurality of reference voltages. The first voltage regulator is coupled to a bit line voltage in a first operating state and a second operating state.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of this disclosure.