阅读说明：本技术 电路边界阵列架构中的动态资源管理 (Dynamic resource management in circuit boundary array architecture ) 是由 T.T.霍昂 M.利克-博登 A.库卡尼 于 2021-04-06 设计创作，主要内容包括：本发明题为“电路边界阵列架构中的动态资源管理”。本发明描述了用于在存储器操作期间将存储器阵列管芯动态地分配到多个堆叠管芯中的CMOS管芯的系统和方法。多个堆叠管芯可竖直堆叠并经由一个或多个竖直硅通孔(TSV)连接而连接在一起。存储器阵列管芯可仅包括存储器单元结构(例如,竖直NAND串),而没有列解码器、行解码器、电荷泵、感测放大器、控制电路、页面寄存器或状态机。CMOS管芯可包含执行存储器操作诸如读取和写入存储器操作所必需的支持电路。一个或多个竖直TSV连接可允许多个堆叠管芯中的每个存储器阵列管芯与多个堆叠管芯中的一个或多个CMOS管芯通信或电连接。(The invention provides dynamic resource management in a circuit boundary array architecture. Systems and methods are described for dynamically allocating memory array dies to CMOS dies in a plurality of stacked dies during memory operations. Multiple stacked dies may be vertically stacked and connected together via one or more vertical through-silicon-via (TSV) connections. The memory array die may include only memory cell structures (e.g., vertical NAND strings) without column decoders, row decoders, charge pumps, sense amplifiers, control circuits, page registers, or state machines. The CMOS die may contain the support circuitry necessary to perform memory operations such as read and write memory operations. The one or more vertical TSV connections may allow each memory array die of the plurality of stacked dies to communicate with or electrically connect to one or more CMOS dies of the plurality of stacked dies.)

1. An apparatus, comprising:

a plurality of stacked dies including a first memory array die; and

a die map control circuit configured to identify a first memory operation of the first memory array die and determine a first set of support circuit dies of the plurality of stacked dies for the first memory operation, the die map control circuit configured to set configurable electrical connections within the plurality of stacked dies such that the first memory array die is electrically connected to memory array support circuits within the first set of support circuit dies and cause the first memory operation of the first memory array die to be performed using the memory array support circuits within the first set of support circuit dies.

2. The apparatus of claim 1, wherein:

the memory array support circuitry within the first set of support circuit dies includes sensing circuitry for sensing memory cell currents associated with memory cells within the first memory array die.

3. The apparatus of claim 1, wherein:

the die mapping control circuit is configured to detect that more than one support circuit die of the plurality of stacked die should be used during the first memory operation to satisfy a performance metric of the first memory operation, and determine the first set of support circuit dies in response to detecting that more than one support circuit die should be used during the first memory operation.

4. The apparatus of claim 3, wherein:

the first set of support circuit dies includes two support circuit dies.

5. The apparatus of claim 3, wherein:

the performance metric of the first memory operation includes satisfying at least a particular read bandwidth.

6. The apparatus of claim 1, wherein:

the first memory operation comprises a read operation.

7. The apparatus of claim 1, wherein:

the die map control circuit is disposed on one of the first set of support circuit dies.

8. The apparatus of claim 1, wherein:

the die mapping control circuit is configured to identify a second memory operation of a second memory array die of the plurality of stacked dies, and determine a second set of support circuit dies of the plurality of stacked dies for the second memory operation.

9. The apparatus of claim 7, wherein:

the die mapping control circuitry is configured to cause the second memory operation of the second memory array die to be performed using memory array support circuitry within the second set of support circuitry dies, the second memory operation of the second memory array die being performed concurrently with the first memory operation of the first memory array die.

10. The apparatus of claim 1, wherein:

the first memory array die includes vertical NAND strings.

11. A method, comprising:

identifying a first memory operation of a first memory array die of a plurality of stacked dies;

identifying a second memory operation of a second memory array die of the plurality of stacked dies;

detecting that a first support circuit die of the plurality of stacked dies should be time-shared by the first memory array die and the second memory array die;

providing configurable electrical connections such that memory cells within the first memory array die are electrically connected to memory array support circuitry within the first support circuit die;

performing the first memory operation of the first memory array die while the memory cells within the first memory array die are electrically connected to the memory array support circuitry within the first support circuit die;

adjusting the configurable electrical connections so that memory cells within the second memory array die are electrically connected to the memory array support circuitry within the first support circuitry die; and

performing the second memory operation of the second memory array die while the memory cells within the second memory array die are electrically connected to the memory array support circuitry within the first support circuit die.

12. The method of claim 11, wherein:

the setting of the configurable electrical connections results in a sensing circuit within the first support circuit die being electrically connected to the memory cells within the first memory array die.

13. The method of claim 11, wherein:

the disposing of the configurable electrical connections includes disposing crossbar switches located within one or more of the plurality of stacked dies.

14. The method of claim 11, wherein:

the first memory operation comprises a read operation.

15. The method of claim 14, wherein:

the second memory operation comprises a program operation.

16. The method of claim 11, wherein:

the first memory array die includes vertical NAND strings.

17. An apparatus, comprising:

a plurality of vertically stacked dies including a first memory array die and a first CMOS die; and

control circuitry configured to detect that a first memory operation is to be performed using the first memory array die and to identify the first CMOS die in response to detecting that the first memory operation is to be performed using the first memory array die, the control circuitry configured to cause memory cell sensing circuitry disposed on the first CMOS die to be electrically connected to one or more memory cells disposed on the first memory array die, the control circuitry configured to cause memory cell currents associated with the one or more memory cells disposed on the first memory array die to be sensed during the first memory operation using the memory cell sensing circuitry disposed on the first CMOS die.

18. The apparatus of claim 17, wherein:

the memory cell sensing circuit includes a sense amplifier.

19. The apparatus of claim 17, wherein:

the first memory operation comprises a read operation.

20. The apparatus of claim 17, wherein:

the control circuit is disposed on the first CMOS die.

Background

The growth in demand for portable consumer electronics has driven the need for high capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory cards, have been widely used to meet the increasing demand for digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, make such memory devices ideal for use in a variety of electronic devices, including, for example, digital cameras, digital music players, video game controllers, PDAs, cellular telephones, and Solid State Drives (SSDs). The semiconductor memory device may include a nonvolatile memory or a volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery). Examples of the nonvolatile memory include flash memories (e.g., NAND-type flash memories and NOR-type flash memories) and electrically erasable programmable read-only memories (EEPROMs).

Semiconductor memory dies are typically placed in packages to allow for easier handling and assembly, and to protect the die from damage. Although the plural form of "die" is "dice," it is common industry practice to use "die" as the plural form as well as the singular form. In one example, one or more semiconductor memory dies and other integrated circuits (such as processors) may be packaged within a package, where the dies may be stacked on top of each other within the package. The package may comprise a surface mount package, such as a BGA package or a TSOP package. One benefit of stacking multiple dies vertically within a package (e.g., eight dies stacked within a single package) is that the overall form factor and package size can be reduced. In some cases, the package may include a stacked multi-chip package, a System In Package (SiP), or a chip stacked multi-chip module (MCM). Vertical connections between stacked dies, including direct vertical connections through the die substrate (e.g., through a silicon substrate), may be formed within each die before or after die-to-die bonding. The vertical connections may include through-silicon vias (TSVs).

Drawings

Like numbered elements refer to common features in different figures.

FIG. 1 is a block diagram depicting one implementation of a memory system.

Fig. 2A depicts one embodiment of two separate dies.

Fig. 2B depicts one embodiment of a plurality of stacked dies including a memory array die and a CMOS die.

Fig. 3A-3B depict various embodiments of integrated memory components.

Figure 4 is a perspective view of a portion of one embodiment of a monolithic three-dimensional memory structure.

FIG. 5 depicts threshold voltage distributions.

FIG. 6A is a table depicting one example of assigning data values to data states.

FIG. 6B depicts one implementation of a series of program and verify pulses applied to a selected word line during a program operation.

Fig. 7A depicts one embodiment of a plurality of stacked dies.

Fig. 7B depicts one embodiment of the plurality of stacked dies depicted in fig. 7A, in which a memory operation is being performed.

Fig. 7C depicts one embodiment of the plurality of stacked dies depicted in fig. 7A, wherein a second vertical TSV bus is utilized during memory operations of the memory array die.

Fig. 7D depicts one embodiment of the plurality of stacked dies depicted in fig. 7A, where a memory operation is being performed using the memory array die.

Figure 7E depicts one embodiment of multiple stacked die layers during memory operations.

Figure 7F depicts one embodiment of the plurality of stacked die layers depicted in figure 7E during a second memory operation.

Figure 7G depicts one implementation of the multiple stacked die layers depicted in figure 7E during two memory operations.

Fig. 7H depicts one embodiment of a plurality of stacked dies communicating with each other via vertical TSV buses.

Fig. 7I depicts one embodiment of a set of four memory array dies disposed below a CMOS die.

Fig. 8A is a flow chart describing one embodiment of a process for dynamically allocating one or more memory array dies having one or more CMOS dies during memory operations.

Fig. 8B is a flow chart describing another embodiment of a process for dynamically allocating one or more memory array dies having one or more CMOS dies during memory operations.

Fig. 8C is a flow chart describing an alternative embodiment of a process for dynamically allocating one or more memory array dies having one or more CMOS dies during memory operations.

Detailed Description

Techniques are described for dynamically pairing or allocating one or more memory array dies (e.g., NAND memory dies) containing memory cells with one or more CMOS dies containing support circuits (e.g., charge pumps, sense amplifiers, decoders, and state machines) for performing memory operations using the one or more memory array dies. To reduce memory system cost and energy consumption, multiple stacked dies including one or more memory array dies and one or more support circuit dies may be vertically stacked and connected together via one or more vertical through-silicon-via (TSV) connections. The one or more memory array dies may include one or more memory arrays. In some cases, one or more memory array dies can include a column decoder and/or a row decoder and a memory cell structure. In other cases, one or more memory array dies may include only memory cell structures (e.g., vertical NAND strings) without column decoders, row decoders, charge pumps, sense amplifiers, control circuits, page registers, and/or state machines. The memory cell structure may include a planar NAND structure, a vertical NAND structure, a bit-cost scalable (BiCS) NAND structure, a 3D NAND structure, or a 3D ReRAM structure. One or more CMOS dies may contain support circuitry for performing various memory operations such as read, erase, and write memory operations. The support circuits may include voltage regulators, charge pumps, sense amplifiers, page registers, and state machines. One or more CMOS dies may also include computational cores and/or control circuitry that may be used to perform various computational tasks, such as performing data error detection and correction. The vertical TSV connections may allow reconfigurable electrical connections to span two or more adjacent dies within the plurality of stacked dies. In one example, the plurality of stacked dies may include eight dies, and the vertical TSV connections may include a vertical TSV bus that spans all eight dies and allows each of the eight dies to be electrically connected to one or more of the other seven dies. The vertical TSV bus may allow each memory array die of the plurality of stacked dies to communicate or electrically connect with each CMOS die of the plurality of stacked dies.

In some embodiments, a die mapping control circuit or state machine disposed on one of the one or more support circuit dies may determine a mapping between the first memory array die and a first support circuit die for supporting memory operations of the first memory array die based on availability of the first support circuit die and/or performance metrics for the memory operations. The die map control circuitry may include one or more control circuits including state machines and/or combinational logic circuits. The memory operations may include a read operation for reading data from the first memory array die or a program operation for writing data to memory cells disposed on the first memory array die. The performance metrics may include read bandwidth or program bandwidth for memory operations. In one example, to meet a particular read bandwidth, two or more support circuit dies within the plurality of stacked dies may be electrically connected to the first memory array die in order to increase read throughput. In the case where two support circuit dies are assigned to the first memory array die, the number of memory cells sensed during a read operation may increase by a factor of two. In another example, to meet a particular programming bandwidth, two or more support circuit dies within the plurality of stacked dies may be electrically connected to the first memory array die in order to increase programming throughput. In the case where three support circuit dies are allocated to the first memory array die during a programming operation, the number of memory cells that are concurrently programmed during the programming operation can be increased by a factor of three, since a factor of three write drivers can be utilized. Since the first memory array die may require more read and/or write circuitry in order to meet the read or write performance metric, the die mapping control circuitry disposed on one of the plurality of stacked dies may increase the number of support circuit dies allocated to the first memory array die. The die mapping control circuit may reallocate the number of support circuit dies allocated to the first memory array die over time based on real-time availability of the support circuit dies and real-time performance requirements for memory operations. In one embodiment, the allocation of support circuit resources may be performed dynamically in real time. In another embodiment, the non-uniform distribution of support circuit resources may be made in the manufacturing facility prior to shipment of the product based on the intended use.

In some cases, die mapping circuitry disposed on a first CMOS die of the plurality of stacked dies may assign the first CMOS die to the first memory array die at a first point in time and then assign both the first CMOS die and the second CMOS die to the first memory array die at a second point in time after the first point in time. The die mapping circuitry may include one or more control circuits. In this case, at a second point in time, two CMOS dies may be needed to double the number of sense amplifiers or write circuits used by the first memory array die in order to meet or comply with the read or write performance metrics. In another embodiment, die mapping circuitry disposed on a first CMOS die of the plurality of stacked dies may assign the first memory array die to two support circuit dies during a first memory operation of the first memory array die and assign the second memory array die to three support circuit dies during a second memory operation of the second memory array die. The first memory operation of the first memory die and the second memory operation of the second memory array die may be performed concurrently.

Each CMOS die may include a memory array support circuit die having a voltage regulator, a charge pump, a sense amplifier, a page register, and/or a state machine. Each CMOS die may include peripheral I/O circuitry to support one or more memory dies, a dedicated core to accelerate a particular application domain (e.g., ECC, compression, filtering, reconfigurable logic, etc.), and a lightweight CPU to support a general-purpose application domain. The peripheral I/O circuitry may include sense amplifiers, decoders, charge pumps, and the like. The number of CMOS dies allocated to a memory array die may depend on the type of memory operation to be performed using the memory array die. For example, if a read operation is to be performed using a memory array die, four CMOS dies may be electrically connected to the memory array die; however, if the memory array die is to be used to perform a programming operation, then two CMOS dies may be electrically connected to the memory array die.

The number of CMOS dies allocated to a memory array die may also depend on the read bandwidth or write bandwidth required for memory operations. For example, if a read operation is to be performed using the memory array die and the read bandwidth for the read operation is greater than a threshold bandwidth, then two CMOS dies may be electrically connected to the memory array die; however, if the read bandwidth for the read operation is not greater than the threshold bandwidth, only one CMOS die may be electrically connected to the memory array die.

In some cases, the plurality of stacked dies may include a first set of CMOS dies and a second set of memory array dies. The CMOS die may be physically smaller or have a smaller die area than the memory array die and utilize a cheaper fabrication process than the memory array die. The plurality of stacked dies may include a first memory array die disposed on a first layer and two or more different CMOS dies disposed on a second layer positioned above the first layer. A second memory array die may then be disposed on a third layer above the second layer. In this case, the combination of the horizontal and vertical buses along with the crossbar switching transistors may allow each of the CMOS dies within the plurality of stacked dies to be electrically connected to either the first memory array die or the second memory array die. Vertical and horizontal crossbar structures may be used to allow each of the CMOS dies to be connected to any of the memory array dies within the plurality of stacked dies. Vertical connections may be made through the substrate of the die using TSVs. In one example, an internal node (e.g., a bit line node) within a first memory array die of the plurality of stacked dies may be connected with an internal node (e.g., a sense amplifier node) of a second die of the plurality of stacked dies using a crossbar structure of one or more TSVs.

In one embodiment, a non-volatile storage system may include one or more two-dimensional arrays of non-volatile memory cells. The memory cells within a two-dimensional memory array may form a single layer of memory cells and may be selected in the X and Y directions by control lines (e.g., word lines and bit lines). In another embodiment, a non-volatile memory system may include one or more monolithic three dimensional memory arrays in which two or more layers of memory cells may be formed over a single substrate without any intervening substrates. In some cases, a three-dimensional memory array may include one or more vertical columns of memory cells located above and orthogonal to the substrate, or substantially orthogonal to the substrate (e.g., within 1 to 2 degrees of a normal vector orthogonal to the substrate). In one example, a non-volatile storage system may include a memory array having vertical bit lines or bit lines arranged orthogonal to a semiconductor substrate. The substrate may comprise a silicon substrate.

FIG. 1 is a block diagram of one embodiment of a memory system 100 implementing the techniques of the present invention including countermeasures to avoid unrecoverable errors due to over-programming. In one implementation, the memory system 100 is a solid state drive ("SSD"). The memory system 100 may also be a memory card, a USB drive, or other type of storage system. The techniques of this disclosure are not limited to any one type of memory system. The memory system 100 is connected to a host 102, which may be a computer, a server, an electronic device (e.g., a smartphone, tablet, or other mobile device), an appliance, or another apparatus that uses memory and has data processing capabilities. In some implementations, the host 102 is separate from but connected to the memory system 100. In other embodiments, the memory system 100 is embedded within the host 102.

The components of the memory system 100 depicted in fig. 1 are electronic circuits. The memory system 100 includes a controller 120 connected to one or more memory dies 130 and local high speed volatile memory 140 (e.g., DRAM). The one or more memory dies 130 each include a plurality of non-volatile memory cells. More information about the structure of each memory die 130 is provided below. The controller 120 uses the local high speed volatile memory 140 to perform certain functions. For example, the local high speed volatile memory 140 stores the logic in a physical address translation table ("L2P table").

The controller 120 includes a host interface 152 that is connected to and communicates with the host 102. In one embodiment, the host interface 152 provides a PCIe interface. Other interfaces, such as SCSI, SATA, etc., may also be used. The host interface 152 is also connected to a Network On Chip (NOC) 154. NOCs are communication subsystems on integrated circuits. NOCs may span both synchronous and asynchronous clock domains, or use asynchronous logic that is not clocked. NOC technology applies network theory and methodology to on-chip communications and represents a significant improvement over conventional bus and crossbar interconnects. NOCs improve the scalability of systems on chip (SoC) and the power efficiency of complex socs compared to other designs. The wires and links of the NOC are shared by many signals. Since all links in the NOC can run simultaneously on different data packets, a high degree of parallelism is achieved. Thus, as the complexity of integrated subsystems continues to increase, NOCs provide enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 may be replaced by a bus. Processor 156, ECC engine 158, memory interface 160, and DRAM controller 164 are connected to and communicate with NOC 154. The DRAM controller 164 is used to operate and communicate with local high speed volatile memory 140 (e.g., DRAM). In other embodiments, the local high speed volatile memory 140 may be SRAM or another type of volatile memory.

The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding according to the implemented ECC techniques. In one embodiment, the ECC engine 158 is an electronic circuit programmed by software. For example, the ECC engine 158 may be a programmable processor. In other embodiments, the ECC engine 158 is a custom, dedicated hardware circuit without any software. In another embodiment, the functionality of the ECC engine 158 is implemented by the processor 156.

The processor 156 performs various controller memory operations such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, the processor 156 is a custom dedicated hardware circuit without any software. The processor 156 also implements the conversion module as a software/firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is addressed internally to the memory system using physical addresses associated with one or more memory dies. However, the host system may use logical addresses to address various memory locations. This enables the host to assign data to consecutive logical addresses while the memory system is idle to store data as desired among locations of one or more memory die. To implement such a system, a controller (e.g., a translation module) performs address translation between logical addresses used by the host and physical addresses used by the memory die. One exemplary implementation is to maintain a table (i.e., the L2P table described above) that identifies the current translation between logical and physical addresses. An entry in the L2P table may include an identification of a logical address and a corresponding physical address. Although the logical to physical address tables (or L2P tables) include the word "table," they need not be literally tables. Rather, the logical to physical address table (or L2P table) may be any type of data structure. In some examples, the memory space of the storage system is so large that local memory 140 cannot hold all L2P tables. In this case, the entire set of L2P tables is stored in memory die 130, and a subset of the L2P tables is cached (L2P cache) in local cache volatile memory 140.

Memory interface 160 communicates with one or more memory dies 130. In one embodiment, the memory interface provides a switched mode interface. Other interfaces may also be used. In some example implementations, the memory interface 160 (or another portion of the controller 120) implements a scheduler and buffers for transmitting data to and receiving data from one or more memory dies.

Fig. 2A depicts an embodiment in which elements of a memory system are grouped into two separate dies including a memory fabric die 303 (e.g., a die having only a memory array fabric) and a memory array support circuit die 301 (e.g., a die including control circuitry to facilitate memory operations of memory fabric 326). In some cases, the memory structure die 303 and the memory array support circuit die 301 may be bonded together or arranged as a vertical stack of dies within an integrated memory assembly. Memory fabric die 303 may include non-volatile memory cells and word lines and bit lines for accessing the non-volatile memory cells. The arrangement of control circuitry for performing memory operations (e.g., read operations and write operations) using the memory structures 326 on the memory array support circuit die 301 allows the control circuitry (e.g., row decoders, column decoders, and read/write circuits) to be fabricated using a different process technology than the process technology used to fabricate the memory structure die 303. Thus, the memory structure die 303 may be optimized for a memory array structure without concern for CMOS elements or control circuitry.

In some cases, memory structure 326 may be formed on one die (such as memory structure die 303), and some or all of the peripheral circuit elements (including one or more control circuits) may be formed on a separate die (such as memory array support circuit die 301). In one example, the memory fabric die 303 may be formed of only a memory array of memory elements, such as an array of memory cells of a flash NAND memory, a PCM memory, or a ReRAM memory. In some cases, each of the one or more memory dies 130 of fig. 1 may correspond to the memory fabric die 303 of fig. 2A.

Referring to fig. 2A, word lines within the memory structure 326 may be biased by a row decoder 324 within the memory array support circuit die 301 and bit lines within the memory structure 326 may be biased by a column decoder 332 within the memory array support circuit die 301. The read/write circuits 328 include multiple sense blocks 350 that include SB1, SB2, …, SBp (sense circuits) and allow one (or more) pages of data in multiple memory cells to be read or programmed (written) in parallel. In one embodiment, each sense block includes a sense amplifier and a set of latches. The latches store data to be written and/or data that has been read. Commands and data may be transferred between a controller, such as controller 120 in fig. 1, and memory array support circuit die 301 via lines 319.

Control circuitry 310 cooperates with the read/write circuits 328 to perform memory operations (e.g., writing, reading, erasing, etc.) on the memory structures 326. In one embodiment, control circuit 310 includes a state machine 312, an on-chip address decoder 314, a power control circuit 316, a temperature sensor circuit 318, and an ECC engine 330. ECC engine 330 may generate ECC codes for protecting data to be stored within memory structure 326. The state machine 312 provides die-level control of memory operations. In one embodiment, the state machine 312 may be programmed by software. In other embodiments, the state machine 312 is implemented without software and entirely in hardware (e.g., electronic circuitry). In some embodiments, the state machine 312 may be replaced by a programmable microcontroller or microprocessor. In one embodiment, the control circuit 310 includes buffers such as registers, ROM fuses, and other storage devices for storing default values such as base voltage and other parameters. The temperature sensor circuit 318 detects the die temperature of the memory array support circuit die 301.

In some embodiments, one or more components within memory array support circuit die 301 (alone or in combination) may be referred to as a management or control circuit. For example, the one or more managing or control circuits may include any one or combination of control circuit 310, state machine 312, decoder 314, power control 316, sense block 350, or read/write circuit 328. The one or more managing circuits or the one or more control circuits may perform or facilitate one or more memory array operations, including erase, program, or read operations.

The on-chip address decoder 314 provides an address interface between the addresses used by the controller 120 to the hardware addresses used by the decoder 324 and the decoder 332. The power control module 316 controls the power and voltages supplied to the word lines and bit lines during memory operations. The power control module 316 may include a charge pump for generating the voltage.

In one implementation, memory structure 326 comprises a monolithic three dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may include any type of non-volatile memory that is monolithically formed in one or more physical layers of a memory cell array, having an active region disposed above a silicon (or other type) substrate. In one example, the non-volatile memory cells of memory structure 326 may be arranged in vertical NAND strings. In another implementation, memory structure 326 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates.

The exact type of memory array architecture or memory cells included in memory structure 326 is not limited to the examples described above. Many different types of memory array architectures or memory cell technologies may be used to form memory structure 326. Other examples of suitable technologies for the memory cells of memory structure 326 include ferroelectric memory (FeRAM or FeFET), ReRAM memory, magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), phase change memory (e.g., PCM), and the like. Examples of suitable techniques for the architecture of memory structure 326 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like.

One example of a ReRAM, or PCMRAM, cross-point memory includes reversible resistance-switching elements arranged in a cross-point array accessed by X-lines and Y-lines (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory elements may also be referred to as programmable metallization cells. The conductive bridge memory element may function as a state-change element based on physical repositioning of ions within the solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one being relatively inert (e.g., tungsten) and the other being electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases, which results in a lower programming threshold for the conductive bridge memory cell. Thus, the conductive bridge memory element can have a wide range of programming thresholds over the entire temperature range.

Magnetoresistive memories (MRAMs) store data through magnetic storage elements. The element is formed from two ferromagnetic plates, each of which can be kept magnetized, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the magnetization of the other plate can be changed to match the magnetization of the external magnetic field to store the memory. The memory device is constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines arranged at right angles to each other, parallel to the cell, one above the cell and one below the cell. When a current is passed through them, an induced magnetic field is generated.

Phase Change Memories (PCMs) take advantage of the unique properties of chalcogenide glasses. One embodiment uses a Ge2Sb2Te5 alloy to achieve the phase change by electrically heating the phase change material. The programmed dose is an electrical pulse of different amplitude and/or length resulting in different resistance values of the phase change material.

Those of ordinary skill in the art will recognize that the techniques described herein are not limited to a single particular memory structure, but encompass many related memory structures within the spirit and scope of the techniques described herein and as understood by those of ordinary skill in the art.

Fig. 2B depicts one embodiment of a plurality of stacked dies including a memory array die 331 and a CMOS die 335. Memory array die 331 may correspond to memory fabric die 303 in fig. 2A. The CMOS die 335 may correspond to the memory array support circuit die 301 in fig. 2A. As shown in fig. 2B, memory array die 331 has been positioned over and bonded to CMOS die 335. Memory array die 331 includes a memory array 329 having a plurality of memory cells. In one example, memory array 329 can include multiple vertical NAND strings. The CMOS die 335 also includes die mapping circuitry 317 for mapping or electrically connecting one or more CMOS dies within the plurality of stacked dies with one or more memory array dies within the plurality of stacked dies. The die mapping circuitry 317 may cause the gated sensing circuitry 313 to be electrically connected to the bitline connections 325 or to be electrically disconnected from the bitline connections 325. The die mapping circuit 317 may electrically connect the gated wordline WL driver 315 to the wordline connection 323 or electrically disconnect or disconnect from the wordline connection 323.

CMOS die 335 also includes gated sensing circuit 313 and gated wordline WL driver 315. The gated sensing circuitry 313 can include a bank of sense amplifiers (or a bank of read/write circuitry, such as read/write circuitry 328 in fig. 2A) in series with analog multiplexers or other gating transistors that can disconnect the gated sensing circuitry 313 from the bitline connections 325. Since bit line connection 325 is already connected to bit line BL 309 of memory array die 301 by bond pad 331, the set of sense amplifiers within gated sense circuit 313 can bias bit line BL 309 connected to memory array 329 and sense current from a memory cell within memory array 329 if the set of sense amplifiers are electrically connected to bit line connection 325. However, if the sense amplifiers from another CMOS die, not shown, are instead electrically connected to the bitline connections 325, the gated sense circuitry 313 will prevent the set of sense amplifiers from being electrically connected to the bitline connections 325.

The gated wordline WL driver 315 may include a set of wordline drivers (or last stage row decoders) in series with an analog multiplexer or other gating transistor that may disconnect or electrically disconnect the gated wordline WL driver 315 from the wordline connection 323. Since the wordline connection 323 is already connected to the wordline WL311 of the memory array 329, the set of wordline drivers within the gated wordline WL driver 315 may drive or bias the wordline WL311 connected to the memory array 329 if the set of wordline drivers is electrically connected to the wordline connection 323. However, if a wordline driver from another CMOS die, not shown, is instead electrically connected to wordline WL311 connected to memory array 329, gated wordline WL driver 315 will prevent the set of wordline drivers within gated wordline WL driver 315 from being electrically connected to wordline connection 323. The word line connection 323 and the word line WL311 connected to the memory array 329 are both electrically connected to a portion of the vertical TSV bus that includes a first TSV 325 that extends through the substrate 305 of the memory array die 331 and a second TSV 327 that extends through the substrate 307 of the CMOS die 335. This portion of the vertical TSV bus may allow other dies, not shown, disposed above or below the memory array die 331 to be electrically connected to the word line WL 311.

FIG. 3A depicts one embodiment of the integrated memory component 104. As shown, the memory die 302 is bonded to the control die 304. Note that although gaps are depicted between adjacent die pairs, such gaps may be filled with epoxy or other resins or polymers. Memory die 302 includes memory structure 326. Memory structure 326 may be fabricated on a substrate 1072 of memory die 302. In some implementations, the substrate 1072 can be formed from a portion of a silicon wafer. Memory structure 326 may comprise a three-dimensional memory array or an array of vertical NAND strings. As shown, memory structure 326 may include multiple Word Line (WL) layers and Bit Line (BL) layers. The word line layers may be separated by dielectric layers. The dielectric layer is represented by the gaps between the word line layers. There are a plurality of columns of stacks extending through the word line layer. One column 1002 is referred to by reference numeral 1002 in each stack. The columns contain memory cells. For example, each column may contain one NAND string. There are many Bit Lines (BL) stacked adjacent to each other.

The word line drivers 560 concurrently provide voltages to the word lines 1042 in the memory die 302. The conductive paths from the word line driver 560 to the word line 1042 include a conductive path 1032, a bond pad 574a1, a bond pad 570a1, and a conductive path 1034. In some embodiments, the conductive vias 1032, 1034 are referred to as via pairs. The conductive vias 1032, 1034 may each include one or more through-holes (which may extend vertically relative to a major surface of the die) and one or more metal interconnects (which may extend horizontally relative to a major surface of the die). The conductive paths 1032, 1034 may include transistors or other circuit elements. In one embodiment, the transistor may actually be used to open or close a path. Other word line drivers (not shown in FIG. 3A) provide voltages to other word lines. Thus, in addition to the bond pads 574a1, 570a1, there are additional bond pads 574a, 570 a. The bond pads may be formed of, for example, copper, aluminum, and alloys thereof.

The sense amplifiers 350 communicate with bit lines in the memory die 302. The path from sense amplifier 350 to the bit line includes conductive path 1052, bond pad 574b, bond pad 570b, and conductive path 1054. In some embodiments, conductive paths 1052, 1054 are referred to as a pair of paths. Conductive vias 1052, 1054 can include one or more through-holes (which can extend vertically relative to a major surface of the die) and one or more metal interconnects (which can extend horizontally relative to a major surface of the die). The metal interconnects can be formed from various conductive metals, including aluminum, tungsten, and copper, and the vias can be lined and/or filled with various conductive metals, including tungsten, copper, and copper alloys. Conductive paths 1052, 1054 may include transistors or other circuit elements. In one embodiment, the transistor may actually be used to open or close a path.

The control die 304 has a substrate 1076, which may be formed from a silicon wafer. The sense amplifiers 350, word line drivers 560, and other circuitry 1020 can be formed on and/or in a substrate 1076. The circuit 1020 may include some or all of the control circuit 310 shown in fig. 2A. In some implementations, the sense amplifiers 350, word line drivers 560, and/or other circuitry 1020 include CMOS circuitry.

There may be external signal paths that allow the circuitry on the control die 304 to communicate with entities external to the integrated memory component 104 (e.g., the memory controller 102 in fig. 1). Thus, the circuitry 1020 on the control die 304 may communicate with the controller 102. The external vias include vias 1058, bond pads 574c, bond pads 570c, Through Silicon Vias (TSVs) 1060 and external pads 1078 in the control die 304. The TSV 1060 extends through the substrate 1072. The TSVs 1060 may be formed before, during, or after the formation of the integrated circuits in the semiconductor dies 302, 304. TSVs may be formed by etching holes through the wafer. For example, holes may be etched through the substrate 1072.

Fig. 3B depicts another embodiment of the integrated memory component 104. The configuration in fig. 3B adds an additional memory die relative to the configuration depicted in fig. 3A. Accordingly, similar reference numerals are used for memory die 302a in fig. 3B, as are used for memory die 302 in fig. 3A. In one embodiment, the first memory die 302a is bonded to the control die 304, and the control die 304 is bonded to the second memory die 302 b. Note that although gaps are depicted between adjacent die pairs, such gaps may be filled with epoxy or other resins or polymers.

Each memory die 302a, 302b includes a memory structure 326. Memory structure 326a is adjacent to substrate 1072 of memory die 302 a. Memory structure 326b is adjacent to substrate 1074 of memory die 302 b. In some implementations, the substrates 1072, 1074 are formed from a portion of a silicon wafer. In this example, memory structures 326 each comprise a three-dimensional memory array.

The word line driver 560 concurrently provides a voltage to a first word line 1042 in the memory die 302a and a second word line 1044 in the memory die 302 b. The path from the word line driver 560 to the second word line 1044 includes a conductive path 1032, a Through Silicon Via (TSV)1068, a bond pad 576a1, a bond pad 572a1, and a conductive path 1036. Other word line drivers (not shown in fig. 3B) provide voltages to other word lines.

The sense amplifier 350a communicates with bit lines in the memory die 302 a. The path from sense amplifier 350a to the bit line includes conductive path 1052, bond pad 574b, bond pad 570b, and conductive path 1054. The sense amplifier 350b communicates with bit lines in the memory die 302 b. The path from sense amplifier 350b to the bit lines includes conductive path 1054, TSV 1056, bond pad 576b, bond pad 572b, and conductive path 1048. Many modifications to the embodiment depicted in fig. 3B are possible. One modification is to have the sense amplifier 350a on the first memory die 302a and the sense amplifier 350b on the second memory die 302 b.

FIG. 4 is a perspective view of a portion of one exemplary embodiment of a monolithic three dimensional memory array that can include a memory structure 326 that includes a plurality of non-volatile memory cells arranged as vertical NAND strings. For example, FIG. 4 shows a portion of one memory block. The depicted structure includes a set of bit lines BL located over a stack of alternating dielectric and conductive layers. For purposes of illustration, one of the dielectric layers is labeled D and one of the conductive layers (also referred to as a word line layer) is labeled W. The number of alternating dielectric and conductive layers may vary based on the particular implementation requirements. One set of embodiments includes 108 to 300 alternating dielectric and conductive layers. One example embodiment includes 96 data word line layers, 8 select layers, 6 dummy word line layers, and 110 dielectric layers. More or less than 108 to 300 layers may also be used. As will be explained below, the alternating dielectric and conductive layers are divided into four "fingers" by local interconnects LI. Fig. 4 shows two fingers and two local interconnects LI. The source line layer SL is located below the alternating dielectric and word line layers. A memory hole is formed in the stack of alternating dielectric and conductive layers. For example, the memory hole is labeled MH. Note that in fig. 4, the dielectric layers are depicted as a perspective view so that the reader can see the memory holes in the stack of alternating dielectric and conductive layers. In one implementation, a NAND string is formed by filling a memory hole with a material including a charge trapping material to form a vertical column of memory cells. Each memory cell may store one or more bits of data.

The memory systems discussed herein can be erased, programmed, and read. At the end of a successful programming process (with verification), the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. FIG. 5 is a graph of threshold voltage versus number of memory cells and illustrates exemplary threshold voltage distributions for the memory array when each memory cell stores three bits of data. However, other embodiments may use other data capacities per memory cell (e.g., such as one bit of data, two bits of data, four bits of data, or five bits of data per memory cell). FIG. 5 shows eight threshold voltage distributions, which correspond to eight data states. For data state N, the data state N has a higher threshold voltage than data state N1 and a lower threshold voltage than data state N + 1. The first threshold voltage distribution (data state) S0 represents an erased memory cell. The other seven threshold voltage distributions (data states) S1-S7 represent programmed memory cells, and are therefore also referred to as a programmed state or a programmed data state. In some implementations, the data states S1-S7 may overlap, with the controller 122 relying on error correction to identify the correct data being stored.

FIG. 5 shows seven read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 for reading data from memory cells. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine the data state (i.e., S0, S1, S2, S3, …) in which the memory cell is located.

FIG. 5 also shows seven verify reference voltages, Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 (also referred to as verify target voltages). When programming memory cells to data state S1, the system will test whether those memory cells have threshold voltages greater than or equal to Vv 1. When programming memory cells to data state S2, the system will test whether the memory cells have threshold voltages greater than or equal to Vv 2. When programming memory cells to data state S3, the system will determine whether memory cells have their threshold voltage greater than or equal to Vv 3. When programming memory cells to data state S4, the system will test whether those memory cells have threshold voltages greater than or equal to Vv 4. When programming memory cells to data state S5, the system will test whether those memory cells have threshold voltages greater than or equal to Vv 5. When programming memory cells to data state S6, the system will test whether those memory cells have threshold voltages greater than or equal to Vv 6. When programming memory cells to data state S7, the system will test whether those memory cells have threshold voltages greater than or equal to Vv 7.

In one implementation, referred to as full sequence programming, memory cells can be programmed from the erased data state S0 directly to any of the programmed data states S1 through S7. For example, a population of memory cells to be programmed may first be erased such that all memory cells in the population are in erased data state S0. Then, a programming process is used to program the memory cells directly into data states S1, S2, S3, S4, S5, S6, and/or S7. For example, while some memory cells are being programmed from data state S0 to data state S1, other memory cells are being programmed from data state S0 to data state S2 and/or from data state S0 to data state S3, and so on. The arrows in fig. 5 indicate full sequence programming. In addition to full sequence programming, the techniques described herein may also be used with other types of programming (including but not limited to multi-level/multi-phase programming).

Each threshold voltage distribution (data state) of FIG. 5 corresponds to a predetermined value of a set of data bits stored in a memory cell. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the memory cell depends upon the data encoding scheme adopted for the memory cells. In one implementation, data values are allocated to threshold voltage ranges using a Gray code allocation such that if the threshold voltage of a memory erroneously shifts to its neighboring physical state, only one bit will be affected.

FIG. 6A is a table depicting one example of assigning data values to data states. In the table of fig. 6A, S0 ═ 111 (erased state), S1 ═ 110, S2 ═ 100, S3 ═ 000, S4 ═ 010, S5 ═ 011, S6 ═ 001, and S7 ═ 101. Other encodings of data may also be used. The techniques disclosed herein do not require specific data encoding. In one implementation, when the block is subjected to an erase operation, all memory cells are moved to data state S0, the erased state.

Generally, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal) whose level is specified for each read operation (e.g., see read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 of FIG. 5) or verify operation (e.g., see verify reference voltages Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 of FIG. 5) in order to determine whether the threshold voltage of the relevant memory cell has reached this level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a particular value, then it is assumed that the memory cell did not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, the unselected memory cells are provided with one or more read pass voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conduct current regardless of whether they are programmed or erased).

There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured at the rate that the memory cell discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or does not allow) the NAND string that includes the memory cell to discharge the corresponding bit line. The voltage on the bit line is measured after a certain period of time to see if it has discharged. It is noted that the techniques described herein may be used with different methods for verification/reading known in the art. Other reading and verification techniques known in the art may also be used.

As described above, the memory cell may become over programmed. For example, consider an example of a memory cell intended to be programmed to data state S4. The programming process is designed to increase the threshold voltage of the memory cells from the threshold voltage distribution of data state S0 to the threshold voltage distribution of data S4 by: the program signal is applied as a set of program pulses that increase in amplitude by a step size, and it is tested between program pulses whether the threshold voltage for the memory cell reaches Vv 4. However, due to structural variations or increased programming speed caused by program/erase cycling, when the threshold voltage of the memory cell reaches Vv4, it also exceeds Vr5, which may cause errors in later reading of the memory cell. This is an example of over-programming. If a small number of memory cells become over programmed, the ECC process during reading may be able to correct the errors. However, if too many memory cells are over programmed or in error, the ECC may not be able to correct all errors and the read process may fail, resulting in data loss.

To prevent data loss, it has been proposed that non-volatile storage systems include mechanisms to compensate for over-programming during the programming process. That is, after the programming process is started for a set of data and target memory cells and before the programming process is completed for the set of data and target memory cells, the system determines whether there are more than a threshold number of over-programmed memory cells, and if so, the system adjusts the programming process partway (e.g., in progress) through the programming process to compensate for over-programming that occurred so far in the programming process that is currently being performed.

FIG. 6B depicts one implementation of a series of program and verify pulses applied to a selected word line during a program operation. The program operation may include multiple program-verify iterations, where each iteration applies one or more program pulses to a selected word line, followed by one or more verify pulses (e.g., to verify or determine a program state or program level of the memory cell). In one implementation, the programming pulses are increased in successive iterative steps. Further, each program pulse may include a first portion having a pass voltage (Vpass) level (e.g., 6V to 8V) followed by a second highest magnitude portion at a program voltage (Vpgm) level (e.g., 12V to 25V). For example, as shown in fig. 6B, the first, second, third, and fourth program pulses 800, 802, 804, and 806 have program voltage levels of Vpgm1, Vpgm2, Vpgm3, and Vpgm4, respectively. One or more verify voltages 808, such as verify voltages Vva, Vvb and Vvc, can be provided after each program pulse. In some cases, one or more initial programming pulses are not followed by verify pulses because it is not expected that any storage elements may have reached the lowest programmed state (e.g., the A-state). Subsequently, in some cases, a program iteration may verify pulses for the A-state, then a program iteration using verify pulses for the A-state and B-state, then a program iteration using verify pulses for the B-state and C-state.

Fig. 7A depicts one embodiment of a plurality of stacked dies. As shown, the plurality of stacked dies includes memory array dies 701-703 and CMOS dies 706-708 that are staggered in a vertical stack. CMOS dies 706-708 may include CMOS circuitry for controlling various memory operations performed using memory array dies 701-703. The CMOS die 706 includes a controller 713 that may include a die mapping controller for assigning one or more CMOS dies within the plurality of stacked dies to one or more memory array dies within the plurality of stacked dies. In one example, controller 713 may correspond to die mapping circuitry 317 in fig. 2B. Each die of the plurality of stacked dies may communicate with another die of the plurality of stacked dies via a vertical TSV bus 712. The vertical TSV bus 712 may include configurable electrical connections that span the length of the stacked die and may include through-silicon vias that pass through each of the memory array dies 701-703. The configurable electrical connections may utilize crossbar structures or transistor-based multiplexers.

CMOS die 706 may be flipped such that its substrate is positioned over the interconnect layers of CMOS die 706 and then positioned over and connected to memory array die 702. Some of the memory array die and CMOS die may utilize flip chips that mate with active elements of support circuitry 711 positioned over interconnects of CMOS die 706 and memory array 710 (e.g., comprising vertical NAND strings) positioned over substrate 709 of memory array die 702. Electrical connections including a portion of the vertical TSV bus 712 may extend from the CMOS die 706 through the substrate 709 of the memory array die 702 using TSVs. The portion of the vertical TSV bus 712 may be connected to support circuitry of the CMOS die 707, which may then extend from the CMOS die 707 through the substrate of the memory array die 703 using another TSV. Although the vertical TSV buses 712 are depicted as extending along one side of the multiple stacked dies, other vertical TSV buses or electrical connections may extend through a middle portion of the stacked dies.

Fig. 7B depicts one embodiment of the plurality of stacked dies depicted in fig. 7A, in which a memory operation is being performed. The memory operation may include a read operation, a program verify operation, or a program operation. In this case, a one-to-one pairing has been made between memory array die 702 and CMOS die 706. In one example, the CMOS die 706 may include 1024 sense amplifiers electrically connected to a column decoder disposed on the memory array die 702; in this case, the memory array die 702 may include a memory array (e.g., including a 3D BiCS structure) and a row decoder for selecting word lines and a column decoder for selecting bit lines of the memory array. In some cases, the memory array die 702 may not include any support circuitry other than the last level row decoder and the last level column. In another example, CMOS die 706 may include memory array support circuitry that is directly connected to bit lines within memory array die 702. Electrical connections from the CMOS die 706 to the memory array die 702 may be configured or formed using the vertical TSV buses 712. In some embodiments, additional circuitry disposed on each of the plurality of stacked dies may provide a crossbar or selector network in which sense amplifier nodes of CMOS die 706 may be electrically connected to column decoder nodes of one of memory array dies 701-703.

In some embodiments, the memory array die 702 may provide an "in-memory computation" system that performs logical operations (e.g., AND, XOR, etc.) via modification of the word line driver circuitry AND/or the sense amplifier circuitry. In this case, instead of storing user data within memory cells of the memory array die 702, the memory cell transistors within the memory array die 702 may be configured with word line driver circuitry and/or sense amplifier circuitry to perform logical operations.

Fig. 7C depicts one embodiment of the plurality of stacked dies depicted in fig. 7A, wherein a second vertical TSV bus 713 is utilized during memory operations of the memory array dies 702-703. In one example, the CMOS die 706 may be paired with the memory array die 702 during a read operation using the vertical TSV bus 712, and then the CMOS die 706 may be paired with the memory array die 703 during a write operation using the vertical TSV bus 713. In this case, the vertical TSV bus 713 may connect write drivers or programming circuitry to control lines within the memory array die 703, and the vertical TSV bus 712 may connect sense amplifiers or read circuitry to control lines within the memory array die 702. Thus, memory array support circuitry located on CMOS die 706 may be time-shared by memory array dies 702-703. The CMOS die 706 may be time-shared by two or more of the memory array dies within the plurality of stacked dies, in the event that read or write performance may be relaxed or other CMOS dies within the plurality of stacked dies are unavailable.

Fig. 7D depicts one embodiment of the multiple stacked dies depicted in fig. 7A, where a memory operation is being performed using the memory array die 702. As shown, both CMOS die 706 and CMOS die 707 have been electrically connected to memory array die 702 during memory operations. The memory operation may include a read operation, a program verify operation, an erase operation, or a program operation. The CMOS die 706 may be electrically connected to the memory array die 702 via vertical TSV buses 712, and the CMOS die 707 may be electrically connected to the memory array die 702 via vertical TSV buses 713. In this case, the read or write performance of the memory operation may be improved by utilizing two different CMOS dies during the memory operation. To improve read performance, the number of CMOS dies electrically connected to the memory array die 702 may be increased, and thus the number of sense amplifiers used to determine the data state of memory cells within the memory array die 702 may be increased. The determination of the number of CMOS dies allocated to the memory array die 702 during a memory operation may be made by a mapping circuit or controller disposed on one of the CMOS dies 706-708.

Figure 7E depicts one embodiment of multiple stacked die layers during memory operations. As shown, each of the CMOS die layers includes two different CMOS dies. Memory array die 703 is disposed over CMOS die 708 and 728. A CMOS die 707 and a CMOS die 727 are disposed over the memory array die 703. The memory array die 702 is disposed over the CMOS die 707 and the CMOS die 727. CMOS die 706 and CMOS die 726 are disposed above memory array die 702. Memory array die 701 is disposed over CMOS die 706 and CMOS die 726. During memory operations, the CMOS dies 706-707 may be electrically connected to the memory array die 702 via vertical TSV bus 723, and the CMOS dies 726-727 may be electrically connected to the memory array die 702 via vertical TSV bus 722. Thus, memory array support circuitry from four CMOS dies may be electrically connected to the memory array die 702 during memory operations. In some implementations, the memory operation can include a program operation. During a programming operation, CMOS dies 726-727 may generate programming voltages via voltage regulators and charge pumps located on CMOS dies 726-727, and CMOS dies 706-707 may provide write circuitry and data buffering for memory array die 702.

Figure 7F depicts one embodiment of the plurality of stacked die layers depicted in figure 7E during a second memory operation. The second memory operation may be performed after the memory operation depicted in FIG. 7E. As shown in fig. 7F, during the second memory operation, CMOS dies 706-708 and 726 have been electrically connected to memory array die 702. The CMOS dies 706-708 may be electrically connected to the memory array die 702 via vertical TSV buses 723 and the CMOS die 726 may be electrically connected to the memory array die 702 via vertical TSV buses 722. In this case, two CMOS dies for the layers with CMOS dies 706 and 726 have been electrically connected to memory array die 702, while only one CMOS die from the layers with CMOS dies 707 and 708 has been electrically connected to memory array die 702. Unequal die distribution per layer may be via vertical TSV buses 722-723 and corresponding crossbar switches within each of the plurality of stacked dies.

Figure 7G depicts one implementation of the multiple stacked die layers depicted in figure 7E during two memory operations. As shown, CMOS die 706 may be paired with memory array die 702 during a first memory operation of memory array die 702 (e.g., during a read operation of memory array die 702), and CMOS die 726 may be paired with memory array die 701 during a second memory operation of memory array die 701 (e.g., during a write operation of memory array die 701). A mapping circuit or controller disposed on a CMOS die, such as CMOS die 728, may determine that a first memory operation of memory array die 702 and a second memory operation of memory array die 701 should be performed concurrently, and thus assign one CMOS die to memory array die 702 and another CMOS die to memory array die 701.

In another embodiment, a mapping circuit or controller disposed on a CMOS die in the plurality of stacked dies may determine that CMOS die 706 and CMOS die 726 should be time-shared between memory array die 701 and memory array die 702. In this case, a first memory operation of memory array die 702 may be performed while both CMOS die 706 and CMOS die 726 are electrically connected to memory array die 702; subsequently, a second memory operation of memory array die 701 may be performed while both CMOS die 706 and CMOS726 are electrically connected to memory array die 701.

Fig. 7H depicts one embodiment of a plurality of stacked dies communicating with each other via vertical TSV buses 762. The vertical TSV bus 762 may include a plurality of vertical TSV connections and switching transistors for selecting which of the plurality of stacked dies is electrically connected to the plurality of vertical TSV connections. As shown, the plurality of stacked dies includes memory array dies 751 and 754 (e.g., including a 3D BiCS memory array), memory buffer 756 (e.g., including DRAM), dedicated hardware and CPU757, decoders and sense amplifiers 752 and 755, and charge pump and voltage regulator 753. The mapping circuit or controller may determine that memory buffer 756 and charge pump and voltage regulator 753 are to be electrically connected to memory array die 751 during a first memory operation of memory array die 751 (e.g., during a programming operation), while decoder and sense amplifiers 755 are electrically connected to memory array die 754 during a second memory operation of memory array die 754 (e.g., during a read operation). In this case, different CMOS dies within the multiple stacked dies may include specific support circuitry, such as charge pumps and sense amplifiers. One technical reason to separate the charge pump from the sense amplifiers is that the layout area of the charge pump can be much larger than the layout area of the sense amplifiers, so a greater number of sense amplifiers can be placed on a dedicated die for the decoder and sense amplifiers 755 if the die also does not need to use the charge pump to provide voltage multiplication.

In some embodiments, electronic components from one or more of the plurality of stacked dies depicted in fig. 7H may be combined into a single die. For example, the memory buffer 756 and the charge pump and voltage regulator 753 can be disposed on or provided by a single die. The dedicated hardware and CPU757 may include one or more dedicated cores and/or one or more lightweight CPUs for accelerating a particular application domain (e.g., ECC, compressor, etc.).

Fig. 7I depicts one embodiment of four memory array dies 772-775 arranged below a CMOS die 778. CMOS die 778 may include four TSV bus regions, including vertical TSV bus 782 and vertical TSV bus 783. The crossbar switches (e.g., transistors) of the vertical TSV buses may be disposed on the CMOS die 778. The vertical TSV busses 782 may allow memory array support circuits disposed on the CMOS die 778 to be electrically connected to either the memory array die 772 or the memory array die 773. The vertical TSV buses 783 may allow memory array support circuitry disposed on the CMOS die 778 to be electrically connected to either the memory array die 772 or the memory array die 774. The vertical TSV buses 784 may allow memory array support circuits disposed on the CMOS die 778 to be electrically connected to the memory array die 773 or the memory array die 775. In some cases not shown, the vertical TSV bus 782 may extend below the layer with the memory array dies 772 to 775 to connect to another CMOS die disposed below the memory array dies 772 to 775.

Fig. 8A is a flow chart describing one embodiment of a process for dynamically allocating one or more memory array dies having one or more CMOS dies during memory operations. In one embodiment, the process of fig. 8A may be performed by control circuitry, such as control circuitry 310 depicted in fig. 2A. In another embodiment, the process of fig. 8A may be performed by one or more control circuits (such as controller 120 in fig. 1). The process of fig. 8A may also be performed using a controller or state machine disposed on a CMOS die, such as CMOS die 706 in fig. 7B.

In step 802, a memory operation of a memory array die of a plurality of stacked dies is identified. The plurality of stacked dies may correspond to the plurality of stacked dies depicted in fig. 7B-7I. The plurality of stacked dies may include one or more support circuit dies and one or more memory array dies. The one or more support circuit dies may correspond to CMOS dies 706-708 in fig. 7B. The memory operation may include a read operation, a program verify operation, an erase operation, or a program operation. In one example, a memory operation may be identified using a controller disposed on one of a plurality of stacked dies. In step 804, it is detected that more than one support circuit die of the plurality of stacked dies should be used during a memory operation to meet a performance metric for the memory operation. In one example, the memory operations may include read operations, and the performance metrics may include a particular read throughput or read bandwidth. In another example, the memory operations may include programming operations and the performance metrics may include a particular write throughput or write bandwidth.

In step 806, a first support circuit die of the plurality of stacked dies and a second support circuit die of the plurality of stacked dies are identified. In this case, the mapping circuit or controller may determine that at least two supporting circuit dies are needed to perform the memory operation such that the performance metric is satisfied. In one example, the first support circuit die and the second support circuit die may be disposed above the memory array die. In another example, the first support circuit die may be disposed above the memory array die and the second support circuit die may be disposed below the memory array die. In step 808, the vertical TSV bus is configured to electrically connect the memory array die to the first support circuit die and the second support circuit die. In one example, the memory array die may correspond to the memory array die 702 in fig. 7D, the first support circuit die may correspond to the CMOS die 706 in fig. 7D, and the second support circuit die may correspond to the CMOS die 707 in fig. 7D. In step 810, a memory operation of the memory array die is performed using the memory array support circuitry from the first support circuit die and the second support circuit die. The memory array support circuitry may include control logic, a page register, a sense amplifier, a charge pump, a voltage regulator, a decoder, and a bandgap voltage reference. The memory operations of the memory array die may include read operations in which sense amplifiers from both the first support circuit die and the second support circuit die are electrically connected to bit lines of a memory array located on the memory array die.

In step 812, a third support circuit die of the plurality of stacked dies is identified. In step 814, the vertical TSV bus is configured to electrically connect the memory array die to the first, second, and third support circuit dies. In one example, the memory die may correspond to memory array die 702 in fig. 7F, the first support circuit die may correspond to CMOS die 706 in fig. 7F, the second support circuit die may correspond to CMOS die 707 in fig. 7F, and the third support circuit die may correspond to CMOS die 708 in fig. 7F. In step 816, a second memory operation of the memory array die may be performed using the first support circuit die, the second support circuit die, and the third support circuit die. In one embodiment, the memory operation may comprise a read operation and the second memory operation may comprise a write operation. In another embodiment, the memory operation may include a read operation having a first read bandwidth and the second memory operation may include a read operation having a second read bandwidth greater than the first read bandwidth. In another embodiment, the memory operation may include a program operation having a first programming bandwidth, and the second memory operation may include a program operation having a second programming bandwidth greater than the first programming bandwidth.

Fig. 8B is a flow chart describing another embodiment of a process for dynamically allocating one or more memory array dies having one or more CMOS dies during memory operations. In one embodiment, the process of fig. 8B may be performed by control circuitry (such as control circuitry 310 depicted in fig. 2A). In another embodiment, the process of fig. 8B may be performed by one or more control circuits (such as controller 120 in fig. 1). In another embodiment, the process of fig. 8B may be performed using a controller or state machine disposed on a CMOS die (such as CMOS die 706 in fig. 7B).

In step 822, a first memory operation of a first memory array die of the plurality of stacked dies is identified. In step 824, a second memory operation of a second memory array die of the plurality of stacked dies is identified. The first memory operation may include a read operation and the second memory operation may include a program operation. In step 826, it is detected that a first support circuit die of the plurality of stacked dies should be shared by the first memory array die and the second memory array die. In step 828, the vertical TSV bus is configured to electrically connect the first memory array die to the first support circuit die. In step 830, a first memory operation of the first memory array die is performed using memory array support circuitry (e.g., sense amplifiers) from the first support circuitry die. In step 832, the vertical TSV bus is configured to electrically connect the second memory array die to the first support circuit die. In step 834, a second memory operation of a second memory array die is performed using memory array support circuitry (e.g., a charge pump) from the first support circuitry die. In step 836, the vertical TSV bus is configured to electrically connect the first memory array die to the first support circuit die. In step 838, a third memory operation of the first memory array die is performed using circuitry located on the first support circuit die. Thus, support circuitry disposed on one or more CMOS die may be time-shared between different memory array dies within multiple stacked dies.

Fig. 8C is a flow chart describing an alternative embodiment of a process for dynamically allocating one or more memory array dies having one or more CMOS dies during memory operations. In one embodiment, the process of fig. 8C may be performed by control circuitry (such as control circuitry 310 depicted in fig. 2A). In another embodiment, the process of fig. 8C may be performed by one or more control circuits (such as controller 120 in fig. 1). In another embodiment, the process of fig. 8C may be performed using a controller or state machine disposed on a CMOS die (such as CMOS die 706 in fig. 7B).

In step 852, a first memory operation of a first memory array die of the plurality of stacked dies is identified. In step 854, a second memory operation of a second memory array die of the plurality of stacked dies is identified. The plurality of stacked dies may correspond to the plurality of stacked dies depicted in fig. 7B. In step 856, a first set of supporting circuit dies of the plurality of stacked dies is determined for the first memory operation. The first set of support circuit dies may include one or more CMOS dies. In step 858, a second set of supporting circuit dies of the plurality of stacked dies is determined for the second memory operation. The second set of support circuit dies may include one or more other CMOS dies. The number of CMOS die within the first set of support circuit dies may be greater than, equal to, or less than the number of CMOS die within the second set of support circuit dies. In step 860, the first set of vertical TSVs are configured to electrically connect the first memory array die to the first set of support circuit dies. The first set of vertical TSVs may be in communication with a set of crossbar switches or transistors that may be arranged to configure the reconfigurable electrical connections to the first memory array die. In step 862, a second set of vertical TSVs are configured to electrically connect the second memory array die to a second set of support circuit dies. In step 864, a first memory operation of the first memory array die is performed using the first set of supporting circuit dies while a second memory operation of the second memory array die is performed using the second set of supporting circuit dies. In this case, the first memory operation and the second memory operation may be performed concurrently or may overlap each other in time.

One embodiment of the disclosed technology includes a plurality of stacked dies having a first memory array die and a die mapping control circuit. The die mapping control circuit is configured to identify a first memory operation of a first memory array die and determine a first set of support circuit dies of the plurality of stacked dies for the first memory operation. The die mapping control circuit is configured to configure the configurable electrical connections within the plurality of stacked dies such that the first memory array die is electrically connected to the memory array support circuits within the first set of support circuit dies and causes a first memory operation of the first memory array die to be performed using the memory array support circuits within the first set of support circuit dies.

One embodiment of the disclosed technology includes: identifying a first memory operation of a first memory array die of a plurality of stacked dies; identifying a second memory operation of a second memory array die of the plurality of stacked dies; detecting that a first support circuit die of the plurality of stacked dies should be time-shared by a first memory array die and a second memory array die; providing configurable electrical connections such that memory cells within the first memory array die are electrically connected to memory array support circuitry within the first support circuit die; performing a first memory operation of the first memory array die while the memory cells within the first memory array die are electrically connected to the memory array support circuitry within the first support circuitry die; adjusting the configurable electrical connections such that the memory cells within the second memory array die are electrically connected to the memory array support circuits within the first support circuit die; and performing a second memory operation of the second memory array die while the memory cells within the second memory array die are electrically connected to the memory array support circuitry within the first support circuit die.

One embodiment of the disclosed technology includes a controller and a plurality of vertically stacked dies including a first memory array die and a first CMOS die. The controller may include one or more control circuits. The controller is configured to detect that a first memory operation is to be performed using the first memory array die, and identify the first CMOS die in response to detecting that the first memory operation is to be performed using the first memory array die. The controller is configured to cause the memory cell sensing circuitry disposed on the first CMOS die to be electrically connected to the one or more memory cells disposed on the first memory array die. The controller is configured to cause, during a first memory operation, sensing a memory cell current associated with one or more memory cells disposed on the first memory array die using memory cell sensing circuitry disposed on the first CMOS die.

For purposes herein, a first layer may be on or above a second layer if zero, one, or more intervening layers are between the first layer and the second layer.

For the purposes of this document, it is noted that the dimensions of the various features depicted in the drawings are not necessarily drawn to scale.

For purposes herein, references in the specification to "an embodiment", "one embodiment", "some embodiments", or "another embodiment" may be used to describe different embodiments, and do not necessarily refer to the same embodiment.

For purposes herein, a connection may be a direct connection or an indirect connection (e.g., through another moiety). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element.

Two devices may be "in communication" if they are directly or indirectly connected, such that they can communicate electronic signals therebetween.

For the purposes of this document, the term "based on" may be understood as "based at least in part on".

For purposes of this document, the use of digital terms such as "first" object, "second" object, and "third" object, without additional context, may not imply a ranking of the objects, but may be used for identification purposes to identify different objects.

For purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.