阅读说明：本技术 改善第零层内介电层的填充能力的栅极及工艺方法 (Improve the grid and process of the filling capacity of level 0 inner-dielectric-ayer ) 是由 刘雪娇 刘哲宏 许佑铨 于 2019-08-29 设计创作，主要内容包括：本发明公开了一种改善第零层内介电层的填充能力的栅极,在半导体基板上具有多个栅极,所述多个栅极之间具有一定间距；所述栅极的剖面呈梯形,即栅极剖面的顶部宽度小于底部的宽度。本发明通过形成一种剖面呈梯形结构的栅极以取代传统的垂直型栅极设计,从而增加栅极之间沟槽顶部的开口距离,降低其深宽比,以此有效改善第零层内介电层制备过程中填充能力有限的问题,从而减少空洞的形成,提高器件的性能进而提高产品良率。本发明所述的工艺方法简单易于实施。(The invention discloses a kind of grids of filling capacity for improving level 0 inner-dielectric-ayer, have multiple grids on a semiconductor substrate, have between the multiple grid at regular intervals；The section of the grid is trapezoidal, i.e. width of the top width of grid section less than bottom.The present invention is by forming a kind of grid of trapezoidal structure of section to replace traditional vertical-type gate design, to increase the extended distance of the top of the groove between grid, reduce its depth-to-width ratio, the problem that filling capacity is limited in level 0 inner-dielectric-ayer preparation process is effectively improved with this, to reduce the formation in cavity, improves the performance of device and then improve product yield.Process of the present invention is simply easy to implement.)

1. a kind of grid for the filling capacity for improving level 0 inner-dielectric-ayer, it is characterised in that: semiconductor substrate is provided, in institute Stating has multiple grids on semiconductor substrate, have between the multiple grid at regular intervals；

The section of the grid is trapezoidal, i.e. width of the top width of grid section less than bottom.

2. improving the grid of the filling capacity of level 0 inner-dielectric-ayer as described in claim 1, it is characterised in that: described is more Between a grid, it is also filled with level 0 inner-dielectric-ayer.

3. improving the grid of the filling capacity of level 0 inner-dielectric-ayer as claimed in claim 2, it is characterised in that: described the Zero layer inner-dielectric-ayer is insulating medium layer, it is therefore preferable to silica.

4. improving the grid of the filling capacity of level 0 inner-dielectric-ayer as described in claim 1, it is characterised in that: described half Conductor substrate is bulk silicon substrate GaAs, germanium silicon substrate or extension.

5. improving the grid of the filling capacity of level 0 inner-dielectric-ayer as described in claim 1, it is characterised in that: the ladder The grid of shape structure can increase the opening width between grid, have higher filling capacity.

6. improving the grid of the filling capacity of level 0 inner-dielectric-ayer as described in claim 1, it is characterised in that: the grid Between pole and semiconductor substrate, also there is gate dielectric layer.

7. a kind of process for the filling capacity for improving level 0 inner-dielectric-ayer, it is characterised in that: include:

Step 1 provides semiconductor substrate, successively deposited on the semiconductor substrate gate dielectric layer, the first polysilicon layer, Silicon nitride hardmask layer, silicon oxide hard mask layer and amorphous carbon layer；

Step 2 by controlling etch mode, forms multiple parallel, sections by the height and width of lithographic definition grid Shape is up-small and down-big trapezoidal grid；The amorphous carbon layer at top is removed again；

Step 3 forms first layer side wall in the grid two sides；

Step 4 carries out LDD injection；

Step 5 re-forms second layer side wall in the grid two sides；

Step 6, then ion implanting is carried out, form source region, the drain region of device；

Step 7 removes photoresist, removes the hard mask layer at top, including silicon oxide hard mask layer, silicon nitride hardmask layer；It goes Except second layer side wall；

Step 8 deposits one layer of tungsten contact hole etching stop-layer in entire semiconductor substrate surface；

Step 9 deposits one layer of level 0 dielectric layer again on entire semiconductor substrate, fills the gap between grid.

8. improving the process of the filling capacity of level 0 inner-dielectric-ayer as claimed in claim 7, it is characterised in that: described In step 3, the technique for forming first layer side wall includes depositional coating, etching and wet clean process.

9. improving the process of the filling capacity of level 0 inner-dielectric-ayer as claimed in claim 7, it is characterised in that: described In step 4, the technique for forming LDD includes photoetching, ion implanting, dry ashing and wet clean process；According to different devices The LDD of part demand formation different components.

10. improving the process of the filling capacity of level 0 inner-dielectric-ayer as claimed in claim 7, it is characterised in that: institute It states in step 5, the technique for forming first layer side wall includes depositional coating, etching and wet clean process.

11. improving the process of the filling capacity of level 0 inner-dielectric-ayer as claimed in claim 7, it is characterised in that: institute It states in step 6, forms the source region of device, the technique in drain region includes photoetching, ion implanting, dry ashing and wet-cleaning work Skill；The LDD of different components is formed according to different device requirements.

12. improving the process of the filling capacity of level 0 inner-dielectric-ayer as claimed in claim 7, it is characterised in that: institute It states in step 7, photoresist is carried out by photoetching, etching and wet-cleaning standard technology and returns quarter process, it will be hard above grid Mask layer removal, eliminates the height fall between width grid.

13. improving the process of the filling capacity of level 0 inner-dielectric-ayer as claimed in claim 7, it is characterised in that: institute It states in step 8, one layer of tungsten contact hole etching stop-layer with tensile stress is grown using chemical vapor deposition process.

14. improving the process of the filling capacity of level 0 inner-dielectric-ayer as claimed in claim 7, it is characterised in that: institute It states in step 9, insulating medium layer is filled in the gap between grid using high-aspect-ratio technique.

Technical field

The present invention relates to process for fabrication of semiconductor device fields, particularly relate to a kind of post tensioned unbonded prestressed concrete technique in semiconductors manufacture The grid of the middle filling capacity for improving level 0 inner-dielectric-ayer.

The present invention also provides the processes of the grid.

Background technique

CMOS complementary metal-oxide-semiconductor device (CMOS: Complementary Metal-Oxide- Semiconductor) manufacturing technology is continued to develop along Moore's Law, the continuous diminution of adjoint device size, gate dielectric Thickness constantly be thinned, the leakage current of grid also increases with it, in 5nm hereinafter, due to electronics tunneling effect, SiO₂As grid Leakage current caused by medium can not receive.SiO is replaced using high dielectric constant (high-k) medium₂Seeing effectively to drop Low effect silicon dioxide insulator thickness, while the physical thickness of biggish gate dielectric can be obtained, to block grid in source Electric leakage.It at present can be using first grid (gate-first) technique and post tensioned unbonded prestressed concrete (gate-last) technique two in 32nm node Processing procedure is planted to obtain high-dielectric constant metal grid pole (HKMG:High-K Metal Gate) structure.In 28nm HK post tensioned unbonded prestressed concrete work In skill, i.e. replacement gate (RMG:Replacement Metal Gate) technique, High-K material does not have to experience pyroprocess, The drift of threshold voltage vt can be effectively reduced, so that the reliability of device is improved, but RMG technique need to be walked comprising more Alternative Suddenly, more challenges are brought to manufacture.

In RMG technique, need to fill a kind of insulating materials between different grids to separate, i.e. level 0 inner-dielectric-ayer (ILD0)).It however as the miniature of device size, is limited by Design Rule, the gap between grid is smaller and smaller, ditch The depth-to-width ratio of slot becomes larger, and empty (Void) is inevitably generated during filling inner-dielectric-ayer, in follow-up process In, since ILD0 is easily consumed in process of lapping by acid attack or again, between two grids than relatively thin at the top of cavity An open hole slot is formed, to lose isolation features.

For the filling capacity for improving ILD0 layers, the better ILD0 preparation process means of filling capacity are generally selected now, such as High-aspect-ratio technique (HARP:High Aspect Ratio Process), however since the technique directlys adopt O₂And TEOS Thermal chemical reaction occurs for (ethyl orthosilicate), without plasmaassisted, so still having empty formation.

Summary of the invention

Technical problem to be solved by the present invention lies in provide a kind of grid of filling capacity for improving level 0 inner-dielectric-ayer Pole structure.

The grid of the filling capacity of the present invention for improving level 0 inner-dielectric-ayer, comprising: semiconductor substrate is provided, There are multiple grids on the semiconductor substrate, have between the multiple grid at regular intervals.

The section of the grid is trapezoidal, i.e. width of the top width of grid section less than bottom.

A further improvement is that being also filled with level 0 inner-dielectric-ayer between multiple grids.

A further improvement is that the level 0 inner-dielectric-ayer is insulating medium layer, it is therefore preferable to silica.

It is bulk silicon substrate or GaAs, germanium silicon substrate a further improvement is that the semiconductor substrate, Either extension.

A further improvement is that the grid of the trapezium structure, can increase the opening width between grid, have higher Filling capacity.

A further improvement is that also there is gate dielectric layer between the grid and semiconductor substrate.

To solve the above problems, the present invention provides a kind of process of filling capacity for improving level 0 inner-dielectric-ayer, To form above-mentioned gate structure, technique includes:

Step 1 provides semiconductor substrate, successively deposited on the semiconductor substrate gate dielectric layer, the first polysilicon layer, Silicon nitride hardmask layer, silicon oxide hard mask layer and amorphous carbon layer.

Step 2, by the height and width of lithographic definition grid, by controlling etch mode, formed it is multiple it is parallel, Section shape is up-small and down-big trapezoidal grid；The amorphous carbon layer at top is removed again.

Step 3 forms first layer side wall in the grid two sides.

Step 4 carries out LDD injection.

Step 5 re-forms second layer side wall in the grid two sides.

Step 6, then ion implanting is carried out, form source region, the drain region of device.

Step 7 removes photoresist, removes the hard mask layer at top, including silicon oxide hard mask layer, silicon nitride hard mask Layer；Remove second layer side wall.

Step 8 deposits one layer of tungsten contact hole etching stop-layer in entire semiconductor substrate surface.

Step 9 deposits one layer of level 0 dielectric layer again on entire semiconductor substrate, fills the gap between grid.

A further improvement is that in the step 3, formed first layer side wall technique include depositional coating, etching and Wet clean process.

A further improvement is that in the step 4, formed LDD technique include photoetching, ion implanting, dry ashing with And wet clean process；The LDD of different components is formed according to different device requirements.

A further improvement is that in the step 5, formed first layer side wall technique include depositional coating, etching and Wet clean process.

A further improvement is that forming the source region of device in the step 6, the technique in drain region includes photoetching, ion note Enter, dry ashing and wet clean process；The LDD of different components is formed according to different device requirements.

A further improvement is that carrying out photoetching by photoetching, etching and wet-cleaning standard technology in the step 7 Glue returns quarter process, and the hard mask layer above grid is removed, and eliminates the height fall between width grid.

A further improvement is that growing one layer using chemical vapor deposition process has tensile stress in the step 8 Tungsten contact hole etching stop-layer.

A further improvement is that being filled absolutely in the gap between grid in the step 9 using high-aspect-ratio technique Edge dielectric layer.

The gate structure of the filling capacity of the present invention for improving level 0 inner-dielectric-ayer is in by forming a kind of section The grid of trapezium structure is to replace traditional vertical-type gate design, thus increase the extended distance of the top of the groove between grid, Its depth-to-width ratio is reduced, the problem that filling capacity is limited in level 0 inner-dielectric-ayer preparation process is effectively improved with this, to reduce The formation in cavity improves the performance of device and then improves product yield.Process of the present invention is simply easy to implement.

Detailed description of the invention

Fig. 1 is the schematic diagram that existing fill process has gap between the post tensioned unbonded prestressed concrete for completing filling.

Fig. 2 is the structure of grid provided by the invention, and up-small and down-big trapezium structure is presented in section, can increase grid Between groove openings of sizes, be conducive to fill.

Fig. 3~11 are process block diagrams provided by the invention.

Description of symbols

1 is substrate, and 2 be polysilicon (grid), and 3 be cavity or gap, and 4 be level 0 inner-dielectric-ayer ILD0, and 5 be gate dielectric layer, 6 It is silicon nitride hardmask layer, 7 be silicon oxide hard mask layer, and 8 be amorphous carbon layer, and 9 be first layer side wall, and 10 be LDD, and 11 be Two layers of side wall, 12 be source/drain region, and 13 be tungsten contact hole etching stop-layer.

Specific embodiment

In order to keep the contents of the present invention more clear and easy to understand, combined with specific embodiments below with attached drawing to the contents of the present invention It is described in detail, but technology contents according to the present invention are not limited only to given specific embodiment.

The present invention is described in further detail below in conjunction with the drawings and specific embodiments.It is wanted according to following explanation and right Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non- Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.

As shown in Figure 1, being limited in 32nm process node below by design rule, the gap between grid is more next Smaller, the depth-to-width ratio of the groove formed between grid becomes larger, when filling inner-dielectric-ayer in the gap between grid, due to deep width Than becoming larger, the filling capacity of making technology is limited, can inevitably generate cavity.This makes in follow-up process, due to The ILD0 layer at empty top is easily consumed by acid attack or during the grinding process, the shape between two grids than relatively thin At the hole slot of an aperture, to lose isolation features.For the filling capacity for improving ILD0 layers, the present invention provides a kind of cross-section structure The grid of trapezoidal structure is to replace traditional vertical-type gate design, to increase the extended distance at the top of gate trench, drops Its low depth-to-width ratio improves the problem that filling capacity is limited in level 0 inner-dielectric-ayer preparation process to be effectively improved, to subtract The formation in few cavity improves the performance of device and then improves product yield.As shown in Fig. 2, having on semiconductor substrate more A parallel grid has between the multiple grid at regular intervals.Level 0 inner-dielectric-ayer is filled between grid, the present invention increases The opening of groove can improve the filling capacity of groove between big grid, and the cavity of filling or gap are reduced or eliminated.

To realize above-mentioned gate structure, the present invention provides a kind of grid knot of filling capacity for improving level 0 inner-dielectric-ayer The process of structure, one embodiment combination attached drawing 3~11 are described as follows:

Step 1, as shown in figure 3, being sequentially depositing gate dielectric layer, more than first on the device wafers substrate based on manufacture of semiconductor Crystal silicon layer and silicon nitride hard mask layer and silicon oxide hardmask layer, top layer cover one layer of amorphous carbon layer.

Step 2 by control etch mode, for example passes through control dry method by the width and height of lithographic definition grid The angle etc. of etching, acquisition cross-section structure are up-narrow and down-wide trapezoidal gate structure.

Step 3 deposits one layer of nitride film in substrate surface, using etching and wet-cleaning standard technology preparation first Layer side wall.

Step 4 carries out shallow source, the leakage ion implanting of photoetching, injection, dry ashing and wet-cleaning standard technology, shape At the LDD of device.For different devices, need to define the LDD of different components according to device requirement.

Step 5, circulation technology, in the redeposited one layer of nitride film of substrate surface, etching and wet-cleaning standard technology system Standby second side wall.

Step 6 carries out ion implanting, dry ashing and wet-cleaning standard technology, shaper by lithographic definition The source region of part, drain region；The source-drain electrode of different components is defined according to device requirement.

Step 7 carries out photoresist by photoetching, etching and wet-cleaning standard technology and returns quarter process (PR Etch Back, PREB), the silicon oxide hardmask layer of grid is removed, the height fall between width grid is eliminated, makes at top portions of gates In on same plane.The second side wall is removed again.

Step 8 grows one layer of tungsten contact hole etching stop-layer with tensile stress using chemical vapour deposition technique.

Step 9 fills the silica of insulation using high-aspect-ratio technique between grid gap, to obtain without cavity ILD0 layers of level 0 inner-dielectric-ayer.

Subsequent technique further includes to ILD0 layers of progress CMP process so that surface planarisation, CPM, which is ground to, grinds off top portions of gates Tungsten contact hole etching stop-layer so that original shape at grid polysilicon expose.Based on post tensioned unbonded prestressed concrete technique, which is moved It removes, then deposited metal fills up the space formed after the removal of former polysilicon, forms metal gates.

The above is only a preferred embodiment of the present invention, is not intended to limit the present invention.Come for those skilled in the art It says, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any modification, equivalent Replacement, improvement etc., should all be included in the protection scope of the present invention.