阅读说明：本技术 一种高速状态分析方法及系统 (High-speed state analysis method and system ) 是由 戴志坚 杨万渝 武建 于 2021-07-30 设计创作，主要内容包括：本发明公开了一种高速状态分析方法及系统,系统包括采集单元、调节单元、时钟沿识别单元、压缩单元和存储单元；所述调节单元连接采集单元和时钟沿识别单元,压缩单元连接时钟沿识别单元和存储单元；时钟通道和数据通道进入采集单元实现50GSPS采样率的采样,再调节单元调节保持时间和建立时间,之后对时钟上升沿位置识别,将其作为数据有效的标志位,并将其适当压缩后存入存储单元。本发明通过对数据通道/时钟通道交替采样,利用25GSPS的高速收发口实现了50GSPS的采样率,在分析速率变快的同时,还能准确获取时钟沿位置的数据；即便在高频率的时钟频率下,也能够正常工作；同时,还能实现建立时间和保持时间的微小调节。(The invention discloses a high-speed state analysis method and a system, wherein the system comprises an acquisition unit, an adjusting unit, a clock edge identifying unit, a compression unit and a storage unit; the adjusting unit is connected with the acquisition unit and the clock edge identification unit, and the compression unit is connected with the clock edge identification unit and the storage unit; the clock channel and the data channel enter the acquisition unit to realize sampling of 50GSPS sampling rate, the regulation unit regulates the holding time and the establishing time, the rising edge position of the clock is identified and used as a mark bit of effective data, and the mark bit is properly compressed and stored in the storage unit. According to the invention, the data channel/clock channel are alternatively sampled, the sampling rate of 50GSPS is realized by using the high-speed receiving and transmitting port of 25GSPS, and the data of the clock edge position can be accurately obtained while the analysis rate is increased; even under the clock frequency of high frequency, can also work normally; at the same time, a small adjustment of the setup time and the hold time can be achieved.)

1. A high-speed state analysis method, comprising the steps of:

step 1: sampling a data channel and a clock channel by using two GTY high-speed transceiving ports respectively, and performing serial-parallel conversion on the sampled data to obtain 128-bit sampled data; splicing the acquired data and the clock to obtain a new sampling rate;

step 2: continuously sampling to obtain 256-bit wide clock channel data at the previous moment, the current moment and the next moment, splicing the clock channel data acquired at the current moment with the clock channel data acquired at the previous moment and the next moment respectively, and intercepting the 256-bit wide clock channel data after left shift or right shift so as to realize the adjustment of 20ps stepping of both the establishment time and the retention time;

and step 3: identifying the clock edge to obtain a data effective zone bit;

and 4, step 4: performing 8-time compression on the data of the data channel according to the effective zone bit of the data to obtain 32-bit wide data;

and 5: according to the effective zone bit of the data, advancing the effective data to enable the first n bits and the nth bit of the 32-bit wide data to be effective data, and enabling the data after the n bits to be invalid data; meanwhile, a data buffer area is established, and valid data are stored by taking the number of the bit data as an address increment each time; when valid data is stored for a certain number of bits, it is stored in the FIFO at the next time.

2. The method according to claim 1, wherein the phases of the two GTY high-speed transceivers in step 1 are different by 180 °.

3. The method according to claim 1, wherein the sampling rates of the two GTY high-speed transceiving ports in step 1 are both 25 GSPS.

4. A high-speed status analysis method according to claim 1, wherein said step 2 adjusting is performed by collecting data on a rising edge of a clock.

5. The high-speed state analysis method according to claim 1, wherein the step 3 specifically comprises: and performing exclusive-or operation on adjacent bits of the acquired 256-bit clock signal, and performing exclusive-or operation on the adjacent bits and the current bit to realize that the rising edge position is set to be 1 and the non-rising edge position is set to be 0, and obtaining 255-bit clock rising edge detection data as a valid data flag bit.

6. A high-speed state analysis system is characterized by comprising a collecting unit, an adjusting unit, a clock edge identifying unit, a compressing unit and a storing unit; the adjusting unit is connected with the acquisition unit and the clock edge identification unit, and the compression unit is connected with the clock edge identification unit and the storage unit;

the acquisition unit samples a data channel and a clock channel through two GTY high-speed transceiving ports;

the adjusting unit splices the data of the clock channel acquired at the moment with the data of the clock channel acquired at the previous moment and the data of the clock channel acquired at the next moment respectively, and intercepts the data of the clock channel with 256 bit width after left shift or right shift so as to realize the adjustment of 20ps stepping of the setup time and the hold time;

the clock edge identification unit carries out exclusive-or operation on adjacent bits of the acquired 256-bit clock signal, and the exclusive-or operation is carried out on the adjacent bits of the 256-bit clock signal and the current bit, so that the rising edge position can be set to be 1, and the non-rising edge position can be set to be 0, and 255-bit clock rising edge detection data is obtained and serves as a data effective marker bit;

the compression unit compresses the data of the data channel by 8 times according to the effective zone bit of the data to obtain 32-bit wide data;

the storage unit is used for storing valid data.

Technical Field

The invention relates to the field of data field testing, in particular to a high-speed state analysis method and system.

Background

With the high-speed development of digital systems, the composition of modern digital systems is more and more complex, the requirement for data transmission is increased rapidly, and the working frequency of the systems is higher and higher, which puts new and higher requirements on the field of data testing.

In order to better perform test analysis on a digital circuit, as a data field test instrument, the state analysis rate of a logic analyzer is urgently required to be greatly improved. In the state analysis mode, the logic analyzer captures a state signal of the system under test, and the sampling of the signal is completed according to the clock of the system under test. The data channel samples on the clock signal edge to represent the system under test condition when the logic signal is stable. At a high clock frequency, the analysis rate becomes faster, and it is more important how to accurately acquire data of the clock edge position, wherein the accurate acquisition of the clock edge position directly affects the test and analysis results.

The design principle of state analysis in the current logic analyzer is generally as follows: and inputting the state clock to the clock end of the trigger, and collecting data of the data channel by the rising edge or the falling edge of the state clock. And, in order to realize the regulation of the setup time and the hold time, the state clock or the data channel is delayed. If data behind the edge of the state clock needs to be acquired, delaying the state clock; and if the data in front of the state clock edge needs to be acquired, delaying the data channel.

But at clock frequencies up to 2GHz, ordinary flip-flops cannot work properly. Moreover, the number of data channels of the logic analyzer is generally hundreds, and if data in front of the edge of the state clock is to be acquired, all the data channels need to be delayed, so that the problem of asynchronization of different data channels is caused. Therefore, it is desirable to provide a new scheme for accurately extracting data of the state clock edge, and at the same time, to realize a small adjustment of the setup time and the hold time.

The setup time (setup time) is the time when data is stable and unchangeable before the rising edge of the clock signal of the trigger arrives, and if the setup time is not enough, the data cannot be driven into the trigger at the rising edge of the clock; hold time (hold time) refers to the time after the rising edge of the clock signal of a flip-flop the data is stable and does not change, if the hold time is not sufficient, the data can not be driven into the flip-flop as well.

The patent with the application number of CN201310142187.4 discloses a USB interface high-speed real-time sampling logic analyzer, which comprises a single chip microcomputer system and an FPGA system, wherein the single chip microcomputer system comprises a USB interface module, a GPIF module, an SPI bus module, an FPGA guide configuration module and an RAM program execution module; the FPGA system comprises an FPGA program execution module, an FIFO controller module, an indicator light module and a channel sampling rate selection/sampling module. The invention adopts a single chip system and an FPGA system architecture, thereby realizing high-speed sampling; then the invention can not realize normal work under the clock frequency as high as 2GHz, and the analysis rate is still too low.

An adaptive delay-compensated serial ADC sampling system sampling calibration method is disclosed in patent application No. CN 202011044795.8. The invention is realized by the following technical scheme: the ADC chip is connected with the FPGA through an analog-digital (AD) multichannel serial interface and is connected with the clock subcircuit group in parallel to form a sampling rate system; a signal source transmits multi-channel serial data configured by an ADC (analog-to-digital converter) chip to an FPGA (field programmable gate array) operation delay parameter compensation algorithm, high-speed serialized data are converted into parallel data, a clock distribution circuit changes sampling frequency as required through a clock source CLK (clock), and the delay of a differential clock IDELAY is adjusted by using a serialization factor; the time delay parameters are arranged in the FPGA, and data and a clock in the channel are aligned; and the AD chip configures a relevant register to exit the test sequence, and outputs real sampling data and an analog-to-digital AD test sequence, thereby completing the calibration process and realizing the calibration of the input delay of the serial ADC sampling system. However, the scheme is based on that the time delay parameter is put into the FPGA to align the data and the clock in the channel, so that the problem that a common trigger cannot work normally under the clock frequency of 2GHz can not be solved; moreover, the number of data channels of the logic analyzer is generally hundreds, and if data in front of the edge of the state clock is to be acquired, all the data channels need to be delayed, so that the problem of asynchronization of different data channels is caused.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provide a high-speed state analysis method and a high-speed state analysis system, which can realize the adjustment of 20ps stepping of set-up time and hold time while realizing accurate continuous high-speed state analysis.

The purpose of the invention is realized by the following technical scheme:

a high speed state analysis method, comprising the steps of:

step 1: sampling a data channel and a clock channel by using two GTY high-speed transceiving ports respectively, and performing serial-parallel conversion on the sampled data to obtain 128-bit sampled data; splicing the acquired data and a clock to obtain a new sampling rate, wherein the data bit width is 256 bits;

step 2: continuously sampling to obtain 256-bit wide clock channel data at the previous moment, the current moment and the next moment, splicing the clock channel data acquired at the current moment with the clock channel data acquired at the previous moment and the next moment respectively, and intercepting the 256-bit wide clock channel data after left shift or right shift so as to realize the adjustment of 20ps stepping of both the establishment time and the retention time; then, collecting data on the rising edge of the clock;

and step 3: setting a flag bit and identifying a clock edge;

and 4, step 4: because the sampling rate reaches 50GSPS, and the maximum state clock is only 2GHz, the data of the data channel can be compressed 8 times according to the effective zone bit of the data to obtain 32-bit wide data, and the data processing amount is reduced;

and 5: for the convenience of storage, according to the flag bit of the data valid, the valid data is moved forward, so that the first n bits and the nth bit of the 32-bit data are valid data, and the data after the n bits are invalid data. Meanwhile, a data buffer is established, and valid data is stored by taking the number of the bit data as an address increment each time. When valid data is stored for a certain number of bits, it is stored in the FIFO at the next time.

Further, the phase difference between the two GTY high-speed transceiving ports in step 1 is 180 °.

Further, the sampling rates of the two GTY high-speed transceiving ports in step 1 are both 25 GSPS.

Further, the step 3 specifically includes: and performing exclusive-or operation on adjacent bits of the acquired 256-bit clock signal, and performing exclusive-or operation on the adjacent bits and the current bit to realize that the rising edge position is set to be 1 and the non-rising edge position is set to be 0, so as to obtain 255-bit clock rising edge detection data which is used as a valid data flag bit.

A high-speed state analysis system comprises a collecting unit, an adjusting unit, a clock edge identifying unit, a compressing unit and a storing unit; the adjusting unit is connected with the acquisition unit and the clock edge identification unit, and the compression unit is connected with the clock edge identification unit and the storage unit;

the acquisition unit samples a data channel and a clock channel through two GTY high-speed transceiving ports;

the adjusting unit splices the data of the clock channel acquired at the moment with the data of the clock channel acquired at the previous moment and the data of the clock channel acquired at the next moment respectively, and intercepts the data of the clock channel with 256 bit width after left shift or right shift so as to realize the adjustment of 20ps stepping of the setup time and the hold time;

the clock edge identification unit carries out exclusive-or operation on adjacent bits of the acquired 256-bit clock signal, and the exclusive-or operation is carried out on the adjacent bits of the 256-bit clock signal and the current bit, so that the rising edge position can be set to be 1, and the non-rising edge position can be set to be 0, and 255-bit clock rising edge detection data is obtained and serves as a data effective marker bit;

the compression unit compresses the data of the data channel by 8 times according to the effective zone bit of the data to obtain 32-bit wide data;

the storage unit is used for storing valid data.

The invention has the beneficial effects that: by alternately sampling the time of a data channel/a clock channel, the sampling rate of 50GSPS is realized by using a high-speed transceiving port of 25GSPS, and the data of the position of the clock edge can be accurately acquired while the analysis rate is faster; even under the clock frequency of 2GHz, can also work normally; at the same time, a small adjustment of the setup time and the hold time can be achieved.

Drawings

FIG. 1 is a block diagram of a high speed state analysis implementation;

FIG. 2 is a block diagram of an acquisition unit;

FIG. 3 is a block diagram of a conditioning unit;

FIG. 4 is a shift implementation block diagram;

FIG. 5 is a memory implementation block diagram.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to more clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will now be described with reference to the accompanying drawings.

In this embodiment, the number of lanes of the high-speed status logic analysis system is 136, wherein there are 128 data lanes and 8 clock lanes, the maximum timing analysis rate is 50GSPS, and the maximum status clock frequency is 2 GHz.

The hardware design block diagram of the high-speed state analysis system is shown in fig. 1 and comprises a collecting unit, an adjusting unit, a clock edge identifying unit, a compressing unit and a storing unit; the adjusting unit is connected with the acquisition unit and the clock edge identification unit, and the compression unit is connected with the clock edge identification unit and the storage unit.

The clock channel and the data channel enter the acquisition unit to realize sampling of 50GSPS sampling rate, and the adjustment unit adjusts the holding time and the establishing time.

And then, recognizing the rising edge position of the clock, using the rising edge position as a valid flag bit of the data, and storing the valid flag bit into a storage unit after the valid flag bit is properly compressed.

In this embodiment:

(1) acquisition unit

And sampling the data channel/clock channel by using two GTY high-speed transceiving ports with the phase difference of 180 degrees, wherein the rate of each high-speed transceiving port is 25GSPS, and respectively obtaining 128-bit sampling data through serial-parallel conversion. The collected data/clocks are spliced to obtain a sampling rate of 50GSPS, and at the moment, the data is 256 bits wide.

(2) Adjusting unit

And splicing the data of the 256-bit wide clock channel acquired at the moment with the data of the 256-bit wide clock channel acquired at the previous moment and the next moment, and intercepting the data of the 256-bit wide clock channel after left shift or right shift so as to realize the step adjustment of the setup time and the hold time of both 20 ps. At this point, data is collected on the rising edge of the clock.

(3) Clock edge identification unit

The collected adjacent bits of the 256-bit clock signal are subjected to exclusive-or operation, and the sum of the collected adjacent bits and the current bit can be used for setting the rising edge position to be 1 and setting the non-rising edge position to be 0, so that 255-bit clock rising edge detection data is obtained and is used as an effective data flag bit.

(4) Compression unit

Because the sampling rate reaches 50GSPS, and the maximum state clock is only 2GHz, the data of the data channel can be compressed 8 times according to the effective zone bit of the data to obtain 32-bit wide data, and the data processing amount is reduced.

(5) Memory cell

For the convenience of storage, according to the flag bit of the data valid, the valid data is shifted forward, so that the first n bits (including the nth bit) of the 32-bit data are valid data, and the data after the n bits are invalid data. Meanwhile, a data buffer is established, and valid data is stored by taking the number of the bit data as an address increment each time. When valid data is stored for a certain number of bits, it is stored in the FIFO at the next time.

The invention adopts a high-speed transceiver inside the FPGA as an acquisition unit. The GTY transceiver is a Virtex UltraScale + series FPGA, and can realize a sampling rate of 25 Gbps. By giving reference clocks with different QUAD phases with 180 degrees to the high-speed receiving and transmitting port, the 25GSPS sampling rate with 180-degree phase difference of two paths can be realized. And performing data splicing on the two paths to realize the sampling rate of 50 GSPS. The 25GSPS sampling rate of each path is converted into low-speed 128-bit wide data after serial conversion and speed reduction processing through a high-speed receiving and transmitting port. Therefore, the 50GSPS sampling rate is spliced and converted into 256-bit wide data.

The present invention acquires one clock channel and a plurality of data channels at a high speed with a sampling rate of 50 GSPS.

To achieve the adjustment of the hold time and the setup time, the state clock may be delayed or advanced first, and then data corresponding to the rising edge position of the clock may be collected.

The data of the clock channels at three moments are spliced, 256-bit data at the time of n-1 is used as the lowest bit, 256-bit data at the time of n +1 is used as the highest bit, and the 256-bit data at the time of n is placed between the time of n-1 and the time of n +1 (the default lowest bit is the data collected firstly), so that the data of the clock channels with 768 bit width can be obtained. Shifting it left or right according to the set value (neither left nor right can exceed 256 bits) can achieve 20ps adjustment per shift. The shifted 257 th to 512 th bit data are taken as data of a 256-bit clock channel at time n. As shown in fig. 3, the diagram is a schematic diagram of clock edge advancing by 20 ps.

In this embodiment, the concatenation is performed by directly concatenating the beginning of the previous data with the end of the previous data.

In the clock edge identification unit, 256-bit wide data is xored two by two and summed with the current bit at each sampling clock as shown in the following equation:

edge_clk[i] = (clk[i-1]^clk[i])&&clk[i]

in the formula, edge _ clk [ i ] represents flag bit data with valid data, clk [ i-1] represents adjacent bit data at the last time of the collected 256-bit clock signal, and clk [ i ] represents data of the currently collected 256-bit clock signal.

This may be accomplished by taking the data at position 1 and the other position 0 as the valid flag bit of the data channel data at the position of the rising edge of the clock.

Because the sampling rate is 50Gbps and is far higher than the 2GHz state clock, the collected clock channel data and data channel data can be compressed. According to the scheme, the data is compressed 8 times according to the valid flag bit of the data, the data processing amount is reduced, the data with the bit width of 32 bits (including invalid data and valid data) is obtained, and meanwhile, the valid bit of the data is compressed.

The data valid flag bit width is 256 bits, and consecutive 8 bits are 1 group, and can be divided into 32 groups. Because the sampling rate is much higher than the state analysis clock rate, only one data valid flag bit exists in the continuous 8 bits, and the continuous 8 bits can be bitwise or the value is taken as the data valid flag bit of the group. And recombining the 32 groups of data effective zone bits to obtain the compressed 32-bit wide data effective zone bits.

The data channel data bit width is 256 bits, and the consecutive 8 bits are 1 group, which can be divided into 32 groups. Similarly, the data bit width can be compressed along with the data valid flag bit, the data valid flag bit and the data in the same group are bitwise and, at this time, the invalid data bit is cleared, and then the 8-bit data is bitwise OR to obtain the data in the group. And recombining the 32 groups of data to obtain the compressed 32-bit wide data.

Since it is not possible to determine whether 32 bits of data are valid at the same time as being completed in one clock cycle. Therefore, the 32-bit data and the data valid flag are shifted first, so that the first n-bit data (including the nth bit) are all valid data, and the last n-bit data are all invalid data.

If the current bit and the data valid flag bit before the current bit have 0, the data valid flag and the data are shifted from the highest bit to the lowest bit by one bit, and if the highest bit is also shifted, the highest bit is shifted by 0, and the shift diagram is shown in fig. 4.

At most one time, in order to realize that the first n bits (including the nth bit) are all valid bits, the shift is fixed 32 times, and at this time, the first n bits are all valid bits. Meanwhile, the number of effective data can be obtained according to the falling edge position of the data effective zone bit.

As shown in fig. 5, a data buffer is defined, and since the FPGA cannot store data with unknown bit width, data with a certain bit width is stored each time, and when the data with 128 bit width is full, the data is stored in the FIFO. Each time the data bit width is compressed to 32 bits, the data buffer bit width is at least 160 bits. Meanwhile, the first address of each time of storing data takes the number of the effective digits in the last time of storing data as increment until the effective digits are 128 bits, and then the effective digits are stored into the FIFO. If the nth data address exceeds 128, the data is stored in the data buffer area from address zero after truncation.

The invention discloses a method for realizing high-speed state analysis in a logic analyzer, which realizes a sampling rate of 50GSPS by alternately sampling data channel/clock channel time and utilizing a high-speed receiving and transmitting port of 25 GSPS. The high-speed receiving and transmitting port converts high-speed serial data into low-speed parallel data, signals collected by the clock channel are spliced and then shifted left and right, so that the adjustment of the setup time and the hold time can be realized, and the adjustment step is 20 ps.

The rising edge data of the clock can be obtained by utilizing the combinational logic to carry out XOR processing on the adjacent data bits of the clock channel, and the rising edge data of the clock can be used as the effective zone bit of the data channel data. Because the sampling rate of 50GSPS is much higher than the 2GHz state clock frequency, the data of the data channel can be compressed according to the data valid flag bit. For convenient storage, the compressed data is shifted to make the first n bits all effective data. And establishing a data buffer area, and storing by taking the number of the effective data as an address increment each time. The data is stored in the FIFO at the next moment after a certain number of bits are stored.

It should be noted that, for simplicity of description, the above-mentioned embodiments of the method are described as a series of acts or combinations, but those skilled in the art should understand that the present application is not limited by the order of acts described, as some steps may be performed in other orders or simultaneously according to the present application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and elements referred to are not necessarily required in this application.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a ROM, a RAM, etc.

The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it is therefore to be understood that the invention is not limited by the scope of the appended claims.