阅读说明：本技术 半导体结构及其制备方法 (Semiconductor structure and preparation method thereof ) 是由 张坤 吴林春 周文犀 夏志良 于 2020-06-02 设计创作，主要内容包括：本发明提供一种半导体结构及其制备方法,制备方法包括：提供第一半导体衬底,形成接触牺牲层及栅极底层,形成沟道结构,形成栅极隔槽及具有底部开口的隔槽间隔层,去除接触牺牲层及功能结构层显露沟道层,形成掺杂半导体层。本发明的半导体结构及其制备方法,基于栅极隔槽去除接触牺牲层形成层间间隙,并基于层间间隙去除功能结构层以显露底部外延层,再沉积形成掺杂半导体层,同时实现了底部外延层的电性引出,降低了核心区的面积,从而可以在栅极隔槽中填充绝缘材料形成绝缘填充层,解决了在栅极隔槽中填充金属导电材料所导致的栅极字线与共源线之间的漏电问题,并解决二者之间形成寄生电容的问题。本发明还在器件结构制备中实现了焊盘的加倍。(The invention provides a semiconductor structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a first semiconductor substrate, forming a contact sacrificial layer and a grid bottom layer, forming a channel structure, forming grid isolation grooves and isolation groove spacing layers with bottom openings, removing the contact sacrificial layer and the functional structure layer to expose the channel layer, and forming a doped semiconductor layer. According to the semiconductor structure and the preparation method thereof, the interlayer gap is formed by removing the contact sacrificial layer based on the grid separation groove, the functional structure layer is removed based on the interlayer gap to expose the bottom epitaxial layer, then the doped semiconductor layer is deposited, meanwhile, the electrical leading-out of the bottom epitaxial layer is realized, and the area of the core region is reduced, so that the insulating material can be filled in the grid separation groove to form an insulating filling layer, the problem of electric leakage between a grid word line and a common source line caused by filling the metal conductive material in the grid separation groove is solved, and the problem of parasitic capacitance formed between the grid word line and the common source line is solved. The invention also realizes the doubling of the bonding pad in the preparation of the device structure.)

1. A method for fabricating a semiconductor structure, the method comprising:

providing a first semiconductor substrate;

forming a laminated structure on the first semiconductor substrate, wherein the laminated structure comprises a contact sacrificial layer and a grid laminated layer positioned on the contact sacrificial layer, and the grid laminated layer comprises a plurality of sacrificial layers and dielectric layers which are alternately stacked;

forming a channel structure in the laminated structure, wherein the channel structure comprises a channel layer and a functional structure layer positioned outside the channel layer, and the channel structure penetrates through the laminated structure and extends into the first semiconductor substrate;

forming a grid electrode separation groove in the grid electrode lamination layer, wherein the grid electrode separation groove exposes the contact sacrificial layer;

forming a separation groove spacing layer on the side wall and the bottom of the grid separation groove, and forming a bottom opening exposing the contact sacrificial layer at the bottom of the separation groove spacing layer;

removing the contact sacrificial layer based on the bottom opening to form an interlayer gap between the first semiconductor substrate and the gate stack;

removing the separation groove spacing layer and the functional structure layer exposed from the interlayer gap to expose the channel layer corresponding to the interlayer gap; and

filling a semiconductor material in the interlayer gap to form a doped semiconductor layer covering the exposed channel layer;

forming an insulating layer on the first semiconductor substrate and the laminated structure;

and forming a second conductive contact structure penetrating through the insulating layer until the second conductive contact structure is contacted with the doped semiconductor layer, wherein the doped semiconductor layer is electrically connected with the part of the channel layer exposed in the interlayer gap, so that the doped semiconductor layer is electrically connected with the channel layer, and the second conductive contact structure is used for carrying out electrical leading-out.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein a plurality of steps are formed at the end of the stacked structure, and each step is further covered with a barrier layer.

3. The method of claim 1, wherein a surface of the channel layer is filled with a hole-filling insulating layer having interstitial cavities formed therein.

4. The method of claim 1, wherein forming the doped semiconductor layer comprises:

removing the sacrificial layer based on the grid isolation groove, and forming a grid structure layer at a position corresponding to the sacrificial layer;

and filling an insulating material in the grid isolation groove to form an isolation structure.

5. The method as claimed in claim 4, wherein the isolation structure comprises a protrusion at the gate structure layer.

6. The method of claim 1, wherein the channel layer comprises a bottom portion and a side portion above the bottom portion, and wherein an upper surface of the bottom portion protrudes above an upper surface of the contact sacrificial layer.

7. The method of claim 1, wherein the functional structure layer is made of the same material as the trench isolation layer, and the trench isolation layer is removed by wet etching while the functional structure layer exposed by the inter-layer gap is removed.

8. The method of claim 1, further comprising, prior to forming the stacked structure: performing ion implantation on the first semiconductor substrate to form a first well region; and/or, the preparation method further comprises the following steps: and performing ion implantation on one side of the first semiconductor substrate far away from the doped semiconductor layer to form a second well region.

9. The method of claim 4, further comprising: forming a first conductive contact structure electrically connected with each gate structure layer in the gate stack through the insulating layer; and forming a third conductive contact structure electrically connected with the channel layer on the channel structure.

10. The method of claim 9, wherein the first semiconductor substrate comprises adjacent core and peripheral regions, the method further comprising: and forming a fourth conductive contact structure which passes through the insulating layer and is in contact with the first semiconductor substrate on the peripheral area, wherein the laminated structure is formed on the core area and has a distance with the fourth conductive contact structure, and the fourth conductive contact structure, the first conductive contact structure, the second conductive contact structure and the third conductive contact structure are prepared on the basis of the same process step.

11. The method of claim 10, further comprising:

forming an insulating layer on one side of the first semiconductor substrate, which is far away from the laminated structure;

and forming a first lead-out pad structure in the insulating layer, wherein the first lead-out pad structure penetrates through the insulating layer and the first semiconductor substrate and is electrically connected with the fourth conductive contact structure.

12. The method of fabricating a semiconductor structure according to any one of claims 1 to 11, further comprising:

providing a second base, wherein the second base comprises a second semiconductor substrate, an insulating medium layer formed on the second semiconductor substrate, a functional device formed in the insulating medium layer and a metal contact end formed on the insulating medium layer; the second base is electrically connected with the functional structure on the first semiconductor substrate through the metal contact end, and the back surfaces of the first semiconductor substrate and the second semiconductor substrate are exposed.

13. The method of claim 12, wherein the second base further comprises a conductive contact post that contacts the second semiconductor substrate through the insulating dielectric layer, the method further comprising:

an isolation layer is formed on one side, away from the functional device, of the second semiconductor substrate;

and preparing a second lead-out bonding pad structure in the isolation layer, wherein the second lead-out bonding pad structure penetrates through the isolation layer and the second semiconductor substrate and is electrically connected with the conductive contact column.

14. A semiconductor structure, comprising:

the stacked structure comprises a doped semiconductor layer and a grid stacked layer, wherein the grid stacked layer comprises a plurality of grid structure layers and dielectric layers which are stacked alternately;

a channel structure passing through the stacked structure, the channel structure including a channel layer and a functional structure layer located outside the channel layer, the doped semiconductor layer passing through the functional structure layer in a direction parallel to the gate stack and contacting the channel layer, the doped semiconductor layer serving as a source;

an insulating layer on the stacked structure; and the doped semiconductor layer is electrically connected with the channel layer and is electrically led out based on the second conductive contact structure.

15. The semiconductor structure of claim 14, wherein the end of the stacked structure is formed with a plurality of steps, each of the steps further covered with a barrier layer.

16. The semiconductor structure of claim 14, wherein a surface of the channel layer is filled with a hole-filling insulating layer having interstitial cavities formed therein.

17. The semiconductor structure of claim 14, further comprising: an isolation structure passing through the gate stack, the isolation structure extending in a set direction to separate the gate stack into portions, the isolation structure comprising a material comprising an insulating material.

18. The semiconductor structure of claim 17, wherein the isolation structure comprises a protrusion at the gate structure layer.

19. The semiconductor structure of claim 14, wherein the channel layer comprises a bottom portion and a side portion above the bottom portion, wherein an upper surface of the bottom portion protrudes above an upper surface of the doped semiconductor layer.

20. The semiconductor structure of claim 14, wherein the gate structure layer comprises a gate dielectric structure formed on a surface of the dielectric layer and a gate electrode layer formed on a surface of the gate dielectric structure.

21. The semiconductor structure of claim 14, further comprising a first semiconductor substrate, the doped semiconductor layer being located between the first semiconductor substrate and the gate stack.

22. The semiconductor structure of claim 21, wherein the first semiconductor substrate has a first well region formed based on ion implantation from a side of the semiconductor substrate proximate to the doped semiconductor layer; and/or a second well region is further formed in the first semiconductor substrate, and the second well region is formed from one side, away from the doped semiconductor layer, of the first semiconductor substrate on the basis of ion implantation.

23. The semiconductor structure of claim 14, further comprising: a first conductive contact structure electrically connected to each of the gate structure layers in the gate stack through the insulating layer; a third conductive contact structure electrically connected to the channel layer is formed on the channel structure.

24. The semiconductor structure of claim 21, wherein the first semiconductor substrate comprises adjacent core and peripheral regions, the peripheral region having a fourth conductive contact structure formed thereon through the insulating layer to contact the first semiconductor substrate, the stacked structure being formed on the core region with a spacing from the fourth conductive contact structure.

25. The semiconductor structure of claim 24, wherein a first landing pad structure is formed on the first semiconductor substrate, an insulating layer is formed on a side of the first semiconductor substrate remote from the stack structure, and the first landing pad structure is electrically connected to the fourth conductive contact structure through the insulating layer and the first semiconductor substrate.

26. The semiconductor structure of any one of claims 14-25, further comprising a second base comprising a second semiconductor substrate, an insulating dielectric layer formed on the second semiconductor substrate, a functional device formed in the insulating dielectric layer, and a metal contact formed on the insulating dielectric layer; the second base is electrically connected with the functional structure on the first semiconductor substrate through the metal contact end, and the back surfaces of the first semiconductor substrate and the second semiconductor substrate are exposed.

27. The semiconductor structure of claim 26, wherein a second pad structure and a conductive contact pillar are further formed in the second base, the conductive contact pillar contacts the second semiconductor substrate through the insulating dielectric layer, an isolation layer is formed on a side of the second semiconductor substrate away from the functional device, and the second pad structure is electrically connected to the conductive contact pillar through the isolation layer and the second semiconductor substrate.

Technical Field

The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor structure and a preparation method thereof.

Background

With the development of the planar flash memory, the manufacturing process of the semiconductor has been greatly improved. In recent years, however, the development of planar flash memories has met with various challenges: physical limits, existing development technology limits, and storage electron density limits, among others. In this context, to solve the difficulties encountered by flat flash memories and to maximize the lower production cost of a unit cell, various three-dimensional (3D) flash memory structures have come into play, such as 3D NOR (3D NOR) flash memory and 3D NAND (3D NAND) flash memory. However, in the conventional three-dimensional memory structure, the problem that the occupied area of the core region of the device is large often exists, and the problems of electric Leakage, parasitic capacitance (WL-ACS Leakage and capacitor) and the like between the gate word line and the common source line in the preparation of the device are difficult to effectively solve, so that the performance and the preparation of the device are influenced.

Therefore, how to provide a semiconductor structure and a method for fabricating the same to solve the above-mentioned problems in the prior art is necessary.

Disclosure of Invention

In view of the above drawbacks of the prior art, an object of the present invention is to provide a semiconductor structure and a method for fabricating the same, which are used to solve the problems of the prior art, such as a large occupied area of a core region for device structure fabrication, leakage and parasitic capacitance between a gate word line and a common source line.

To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor structure, the method comprising the steps of:

providing a first semiconductor substrate;

forming a laminated structure on the first semiconductor substrate, wherein the laminated structure comprises a contact sacrificial layer and a grid laminated layer positioned on the contact sacrificial layer, and the grid laminated layer comprises a plurality of sacrificial layers and dielectric layers which are alternately stacked;

forming a channel structure in the laminated structure, wherein the channel structure comprises a channel layer and a functional structure layer positioned outside the channel layer, and the channel structure penetrates through the laminated structure and extends into the first semiconductor substrate;

forming a grid electrode separation groove in the grid electrode lamination layer, wherein the grid electrode separation groove exposes the contact sacrificial layer;

forming a separation groove spacing layer on the side wall and the bottom of the grid separation groove, and forming a bottom opening exposing the contact sacrificial layer at the bottom of the separation groove spacing layer;

removing the contact sacrificial layer based on the bottom opening to form an interlayer gap between the first semiconductor substrate and the gate stack;

removing the separation groove spacing layer and the functional structure layer exposed from the interlayer gap to expose the channel layer corresponding to the interlayer gap; and

filling a semiconductor material in the interlayer gap to form a doped semiconductor layer covering the exposed channel layer;

forming an insulating layer on the first semiconductor substrate and the laminated structure;

and forming a second conductive contact structure penetrating through the insulating layer until the second conductive contact structure is contacted with the doped semiconductor layer, wherein the doped semiconductor layer is electrically connected with the part of the channel layer exposed in the interlayer gap, so that the doped semiconductor layer is electrically connected with the channel layer, and the second conductive contact structure is used for carrying out electrical leading-out.

Optionally, the end of the stacked structure is formed with a plurality of steps, and each step is further covered with a barrier layer.

Optionally, a surface of the channel layer is filled with a hole-filling insulating layer, and a clearance cavity is formed in the hole-filling insulating layer.

Optionally, the forming the doped semiconductor layer includes:

removing the sacrificial layer based on the grid isolation groove, and forming a grid structure layer at a position corresponding to the sacrificial layer;

and filling an insulating material in the grid isolation groove to form an isolation structure.

Optionally, the isolation structure includes a protrusion at the gate structure layer.

Optionally, the channel layer includes a bottom portion and a side portion located above the bottom portion, and an upper surface of the bottom portion protrudes above an upper surface of the contact sacrificial layer.

Optionally, the material of the functional structure layer is the same as that of the separation groove spacing layer, and the separation groove spacing layer is removed by a wet etching process and the functional structure layer exposed from the interlayer gap is removed at the same time.

Optionally, before forming the stacked structure, the method further includes: performing ion implantation on the first semiconductor substrate to form a first well region; and/or, the preparation method further comprises the following steps: and performing ion implantation on one side of the first semiconductor substrate far away from the doped semiconductor layer to form a second well region.

Optionally, the preparation method further comprises: forming a first conductive contact structure electrically connected with each gate structure layer in the gate stack through the insulating layer; and forming a third conductive contact structure electrically connected with the channel layer on the channel structure.

Optionally, the first semiconductor substrate includes a core region and a peripheral region adjacent to each other, and the preparation method further includes: and forming a fourth conductive contact structure which passes through the insulating layer and is in contact with the first semiconductor substrate on the peripheral area, wherein the laminated structure is formed on the core area and has a distance with the fourth conductive contact structure, and the fourth conductive contact structure, the first conductive contact structure, the second conductive contact structure and the third conductive contact structure are prepared on the basis of the same process step.

Optionally, the preparation method further comprises:

forming an insulating layer on one side of the first semiconductor substrate, which is far away from the laminated structure;

and forming a first lead-out pad structure in the insulating layer, wherein the first lead-out pad structure penetrates through the insulating layer and the first semiconductor substrate and is electrically connected with the fourth conductive contact structure.

Optionally, the method for manufacturing a semiconductor structure further includes:

providing a second base, wherein the second base comprises a second semiconductor substrate, an insulating medium layer formed on the second semiconductor substrate, a functional device formed in the insulating medium layer and a metal contact end formed on the insulating medium layer; the second base is electrically connected with the functional structure on the first semiconductor substrate through the metal contact end, and the back surfaces of the first semiconductor substrate and the second semiconductor substrate are exposed.

Optionally, the second base further includes a conductive contact pillar contacting the second semiconductor substrate through the insulating dielectric layer, and the preparation method further includes:

an isolation layer is formed on one side, away from the functional device, of the second semiconductor substrate;

and preparing a second lead-out bonding pad structure in the isolation layer, wherein the second lead-out bonding pad structure penetrates through the isolation layer and the second semiconductor substrate and is electrically connected with the conductive contact column.

The present invention also provides a semiconductor structure comprising:

the stacked structure comprises a doped semiconductor layer and a grid stacked layer, wherein the grid stacked layer comprises a plurality of grid structure layers and dielectric layers which are stacked alternately;

a channel structure passing through the stacked structure, the channel structure including a channel layer and a functional structure layer located outside the channel layer, the doped semiconductor layer passing through the functional structure layer in a direction parallel to the gate stack and contacting the channel layer, the doped semiconductor layer serving as a source;

an insulating layer on the stacked structure; and the doped semiconductor layer is electrically connected with the channel layer and is electrically led out based on the second conductive contact structure.

Optionally, the end of the stacked structure is formed with a plurality of steps, and each step is further covered with a barrier layer.

Optionally, a surface of the channel layer is filled with a hole-filling insulating layer, and a clearance cavity is formed in the hole-filling insulating layer.

Optionally, an isolation structure passing through the gate stack, the isolation structure extending in a set direction to separate the gate stack into portions, the isolation structure comprising a material comprising an insulating material.

Optionally, the isolation structure includes a protrusion at the gate structure layer.

Optionally, the channel layer includes a bottom portion and a side portion located above the bottom portion, and an upper surface of the bottom portion protrudes above an upper surface of the doped semiconductor layer.

Optionally, the gate structure layer includes a gate dielectric structure formed on the surface of the dielectric layer and a gate electrode layer formed on the surface of the gate dielectric structure.

Optionally, the semiconductor structure further comprises a first semiconductor substrate, and the doped semiconductor layer is located between the first semiconductor substrate and the gate stack.

Optionally, the first semiconductor substrate has a first well region formed based on ion implantation from a side of the semiconductor substrate near the doped semiconductor layer; and/or a second well region is further formed in the first semiconductor substrate, and the second well region is formed from one side, away from the doped semiconductor layer, of the first semiconductor substrate on the basis of ion implantation.

Optionally, the semiconductor structure further comprises: a first conductive contact structure electrically connected to each of the gate structure layers in the gate stack through the insulating layer; a third conductive contact structure electrically connected to the channel layer is formed on the channel structure.

Optionally, the first semiconductor substrate includes a core region and a peripheral region adjacent to each other, a fourth conductive contact structure is formed on the peripheral region and contacts the first semiconductor substrate through the insulating layer, and the stacked structure is formed on the core region and has a gap with the fourth conductive contact structure.

Optionally, a first lead-out pad structure is formed on the first semiconductor substrate, an insulating layer is formed on one side of the first semiconductor substrate, which is far away from the stacked structure, and the first lead-out pad structure penetrates through the insulating layer and the first semiconductor substrate and is electrically connected to the fourth conductive contact structure.

Optionally, the semiconductor structure further includes a second base, where the second base includes a second semiconductor substrate, an insulating dielectric layer formed on the second semiconductor substrate, a functional device formed in the insulating dielectric layer, and a metal contact formed on the insulating dielectric layer; the second base is electrically connected with the functional structure on the first semiconductor substrate through the metal contact end, and the back surfaces of the first semiconductor substrate and the second semiconductor substrate are exposed.

Optionally, a second lead-out pad structure and a conductive contact pillar are further formed in the second base, the conductive contact pillar penetrates through the insulating medium layer to be in contact with the second semiconductor substrate, an isolation layer is formed on one side, far away from the functional device, of the second semiconductor substrate, and the second lead-out pad structure penetrates through the isolation layer and the second semiconductor substrate to be electrically connected with the conductive contact pillar.

As described above, according to the semiconductor structure and the method for manufacturing the same of the present invention, the contact sacrificial layer is removed based on the gate spacer to form the interlayer gap, the functional structure layer is removed based on the interlayer gap to expose the bottom epitaxial layer, the doped semiconductor layer is deposited to form the doped semiconductor layer, and the second conductive contact structure in contact with the doped semiconductor layer is formed, and at the same time, the electrical leading-out of the bottom epitaxial layer is achieved, and the area of the core region is reduced, so that the gate spacer can be filled with the insulating material to form the insulating filling layer, thereby solving the problem of the leakage between the gate word line and the common source line caused by filling the metal conductive material in the gate spacer, and solving the problem of the parasitic capacitance formed between the gate word line and the common source line. The invention also realizes the doubling of the bonding pad in the preparation of the device structure.

Drawings

FIG. 1 is a process flow diagram illustrating the fabrication of a semiconductor structure according to the present invention.

Fig. 2-27 show schematic views of structures resulting from various steps in the fabrication of a semiconductor structure according to an example of the present invention.

Fig. 28 shows a schematic structural view of a semiconductor structure obtained as another example of the present invention.

Description of the element reference numerals

101 first semiconductor substrate

1011 first well region

102 insulating layer

103 contact sacrificial layer

104 insulating dielectric layer

105. 107, 109, 111, 113 sacrificial layer

106. 108, 110, 112, 114 dielectric layers

115 laminated structure

116 barrier layer

117 barrier layer

118 first insulating dielectric layer

119 second insulating dielectric layer

120 channel structure

121 functional structural layer

122 barrier layer

123 charge trapping layer

124 tunneling layer

125 side part

126 bottom

127 pore-filling insulating layer

128 conductive contact post

129 gate spacer

130 separating groove spacing layer

131 first spacer layer

132 second spacer layer

133 third spacer layer

134 bottom opening

135 interlayer gap

136 doped semiconductor layer

137. 138, 139, 140, 141 gate structure layer

142 step laminated structure

143 first gate dielectric layer

144 second gate dielectric layer

145 gate electrode layer

146 isolation structure

147 second conductive contact structure

148 first conductive contact structure

149 third conductive contact Structure

150 fourth conductive contact structure

151 second contact point

152 first contact point

153 third contact point

154 fourth contact point

155 insulating layer

156 array wafer substrate

157 insulating layer

158 etch openings

159 first extraction layer

160 second lead-out layer

161 third extraction layer

162 conductive cap layer

163 first lead out pad structure

164 isolation layer

200 second substrate

201 second semiconductor substrate

202 functional device

203 metal contact terminal

204 dielectric layer

205 isolation layer

206 second lead out pad structure

S1-S8

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.

As shown in fig. 1, the present invention provides a method for fabricating a semiconductor structure, the method comprising the steps of:

s1: providing a first semiconductor substrate;

s2: forming a laminated structure on the first semiconductor substrate, wherein the laminated structure comprises a contact sacrificial layer and a grid laminated layer positioned on the contact sacrificial layer, and the grid laminated layer comprises a plurality of sacrificial layers and dielectric layers which are alternately stacked;

s3: forming a channel structure in the laminated structure, wherein the channel structure comprises a channel layer and a functional structure layer positioned outside the channel layer, and the channel structure penetrates through the laminated structure and extends into the first semiconductor substrate;

s4: forming a grid electrode separation groove in the grid electrode lamination layer, wherein the grid electrode separation groove exposes the contact sacrificial layer;

s5: forming a separation groove spacing layer on the side wall and the bottom of the grid separation groove, and forming a bottom opening exposing the contact sacrificial layer at the bottom of the separation groove spacing layer;

s6: removing the contact sacrificial layer based on the bottom opening to form an interlayer gap between the first semiconductor substrate and the gate stack;

s7: removing the separation groove spacing layer and the functional structure layer exposed from the interlayer gap to expose the channel layer corresponding to the interlayer gap; and

s8: and filling a semiconductor material in the interlayer gap to form a doped semiconductor layer covering the exposed channel layer.

The method for fabricating the semiconductor structure of the present invention will be described in detail with reference to the accompanying drawings. The method for manufacturing a semiconductor structure provided by the present invention is not limited to the above-mentioned sequence of steps, and can be adjusted according to common knowledge in the art, and this embodiment provides only one example of the method for manufacturing a semiconductor structure of the present invention.

First, as shown in S1 in fig. 1 and fig. 2-3, step S1 is performed to provide the first semiconductor substrate 101. The first semiconductor substrate 101 may include a silicon substrate, a Germanium (Ge) substrate, a silicon Germanium (SiGe) substrate, an SOI substrate, a GOI (Germanium-on-Insulator) substrate, and the like, in other embodiments, the first semiconductor substrate 101 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, silicon carbide, and the like, the first semiconductor substrate 101 may also be a stacked structure, such as a silicon/Germanium-silicon stacked structure, and the like, and in this embodiment, the first semiconductor substrate 101 includes a single crystal silicon substrate. In addition, the first semiconductor substrate 101 may be a substrate after ion doping, P-type doping may be performed, or N-type doping may be performed, and a plurality of peripheral devices, such as a field effect transistor, a capacitor, an inductor, and/or a pn junction diode, may be formed in the first semiconductor substrate 101.

As shown in fig. 3, the first semiconductor substrate 101 includes a core region a and a peripheral region B adjacent to each other as an example to facilitate the preparation of different devices, and of course, the first semiconductor substrate 101 may also have one or more other functional regions, which is not limited thereto.

In another example, a first well region 1011 formed by ion implantation is also formed in the first semiconductor substrate 101. In an example, a method for forming the first well 1011 is provided, as shown in fig. 2, the first semiconductor substrate 101 is provided first, and then the first well 1011 is formed by ion Implantation (IMP) as shown in fig. 3, the doping type of the first well 1011 can be selected according to actual requirements, in this embodiment, the first well 1011 is N-doped. In one example, the first well region 1011 is formed on the entire upper portion of the first semiconductor substrate 100, as shown in fig. 3, that is, ion implantation is performed from the upper surface of the first semiconductor substrate 101 to form the first well region 1011 with a thickness, which is set according to actual requirements and subsequent processes. In addition, in an example, after the first well region 1011 is formed, an insulating layer 102 is further formed on the upper surface of the first semiconductor substrate 101, and the material thereof includes, but is not limited to, silicon oxide. In an example, the insulating layer 102 covers the surface of the first well region 1011.

Next, as shown in S2 of fig. 1 and fig. 4, step S2 is performed to form a stacked structure on the first semiconductor substrate 101, where the stacked structure includes a contact sacrificial layer 103 and a gate stack 115 on the contact sacrificial layer 103, and the gate stack 115 includes a plurality of sacrificial layers 105, 107, 109, 111, 113 and dielectric layers 106, 108, 110, 112, 114 that are stacked alternately. In one example, the stacked structure is formed over a core region a of the semiconductor substrate.

In one example, as shown in fig. 4, a step of forming an insulating dielectric layer 104 on the contact sacrificial layer 103 may be further included, the contact sacrificial layer 103 may be protected during etching away the sacrificial layer in the stacked structure 115, and the material of the insulating dielectric layer 104 includes, but is not limited to, silicon oxide. In addition, after the stacked structure 115 is formed, a step of forming a barrier layer 116 and an isolation layer 117 is further included, the barrier layer 116 is formed on a sidewall surface of the stacked structure 115, and the isolation layer 117 is formed on a surface of the barrier layer 116, in an example, the stacked structure 115 is a step stacked structure, as shown in the structure of fig. 4, where the barrier layer 116 covers each step surface of the stacked structure 115. The isolation layer 117 comprises silicon oxide, silicon nitride, etc., the material of the barrier layer 116 comprises but is not limited to silicon nitride, and the barrier layer 116 may be prepared by an ALD (atomic layer deposition) process, so that the step coverage rate for forming a step structure may be improved.

Specifically, the dielectric layer in the gate stack includes, but is not limited to, a silicon dioxide layer, and the sacrificial layer in the gate stack includes, but is not limited to, a silicon nitride layer, and optionally, the dielectric layer and the sacrificial layer have a certain selection ratio in the same etching/etching process to ensure that the dielectric layer is hardly removed when the sacrificial layer is removed. The gate stack may be formed by a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, or the like. In addition, the gate stack may be formed by etching a stacked stack structure, and the stacked stack structure may include the dielectric layers and the sacrificial layers that are alternately stacked in sequence, in an example, both the bottom layer and the top layer of the stacked stack structure are the dielectric layers. In another example, the gate stack is a step structure, and the corresponding stack structure 115 is a step stack structure at this time, wherein the adjacent dielectric layers and the sacrificial layers in the gate stack form a stack unit, and one stack unit forms a step surface, so that the gate stack includes a plurality of stack units, and a plurality of step surfaces are correspondingly formed, optionally, each dielectric layer serves as a surface of each step surface. The number of layers of the dielectric layer and the sacrificial layer in the gate stack may include 32 layers, 64 layers, 96 layers, 128 layers, or the like, and specifically, the number of layers and the thickness of the dielectric layer and the sacrificial layer in the gate stack may be set according to actual needs, which is not limited herein.

Next, as shown in fig. 5, step S3 is performed to form a channel structure 120 in the stacked structure, where the channel structure 120 includes a channel layer and a functional structure layer 121 located outside the channel layer, and the channel structure 120 penetrates through the stacked structure and extends into the first semiconductor substrate 100. In an example, the channel layer includes a bottom portion 126 and a side portion 125 above the bottom portion 126, and an upper surface of the bottom portion 126 protrudes above an upper surface of the contact sacrificial layer 103, so that the upper surface of the bottom portion 126 is higher than a doped semiconductor layer subsequently formed at a position of the contact sacrificial layer 103. In an alternative example, when the first well region 1011 formed by ion implantation is further formed in the first semiconductor substrate 101, the channel structure 120 extends into the first well region 1011, and optionally, the lower surface of the channel structure 120 is higher than the lower surface of the first well region 1011 and lower than the upper surface of the first well region 1011.

In an example, the functional structure layer 121 includes a blocking layer 122, a charge trapping layer 123 and a tunneling layer 124, wherein the blocking layer 122 is located on a sidewall surface of a channel hole of the device channel structure, the charge trapping layer 123 is located on a surface of the blocking layer 122, the tunneling layer 124 is located on a surface of the charge trapping layer 123, and the channel layer is located on a surface of the tunneling layer 124. The material of the blocking layer 122 includes, but is not limited to, silicon dioxide, the material of the charge trapping layer 123 includes, but is not limited to, silicon nitride, the material of the tunneling layer 124 includes, but is not limited to, silicon dioxide, and the material of the channel layer 125 includes, but is not limited to, polysilicon, such as polysilicon that may be p-type doped.

In addition, the surface of the channel layer of the channel structure 120 may also be filled with a hole-filling insulating layer 127, and optionally, a clearance cavity is also formed in the hole-filling insulating layer 127, so that stress can be relieved. In other examples, the top of the channel structure 120 is also formed with a conductive contact pillar 128 to electrically lead it out. In other examples, a first insulating dielectric layer 118 and a second insulating dielectric layer 119 are further formed on the stacked structure 115 to facilitate protection and electrical connection of the device structure, in which in one example, the first insulating dielectric layer 118 is made of silicon nitride, and the second insulating dielectric layer 119 is made of silicon oxide, but not limited thereto.

Next, as shown in S4 of fig. 1 and fig. 6, step S4 is performed to form gate isolation trenches 129 in the gate stack, wherein the gate isolation trenches 129 expose the contact sacrificial layer 103. The gate spacer 129 may be used to etch a sacrificial layer in the stacked structure 115, and may also be used to divide a plurality of memory cells into memory blocks (blocks), and the gate spacer may be formed by a photolithography process. In one example, the gate spacers are formed in the core region a, and the number of the gate spacers 129 and the number and the position relationship between the gate spacers and the channel structures 120 are set according to practical requirements. In addition, the gate spacer of the present invention exposes the contact sacrificial layer 103, so as to etch the contact sacrificial layer 103 based on the gate spacer 129.

Next, as shown in S5 of fig. 1 and fig. 7-8, step S5 is performed to form a spacer 130 on the sidewalls and bottom of the gate spacer 129, and a bottom opening 134 exposing the contact sacrificial layer 103 is formed at the bottom of the spacer 130. The spacer 130 may be formed by a deposition process, and in an example, the spacer 130 includes a first spacer 131, a second spacer 132, and a third spacer 133 in sequence from the sidewall of the gate spacer 129 to the center, where the material of the first spacer 131 includes but is not limited to silicon nitride, the material of the second spacer 132 includes but is not limited to silicon oxide, and the material of the third spacer 133 includes but is not limited to silicon nitride.

In one example, the sidewalls of the gate spacers 129 and the surrounding material layer may be deposited sequentially, as shown in fig. 7, and then a portion of the spacer 130 on the material layer surrounding the gate spacers 129 is removed, and at the same time, the spacer 130 at the bottom of the gate spacers 129 is removed to form the bottom openings 134, as shown in fig. 8.

Next, as shown in S6 of fig. 1 and fig. 9-10, step S6 is performed to remove the contact sacrificial layer 103 based on the bottom opening 134 so as to form an interlayer gap 135 between the first semiconductor substrate 101 and the gate stack, in an example, the contact sacrificial layer 103 is made of polysilicon, but is not limited thereto, the contact sacrificial layer 103 may be removed by a wet etching process, and of course, the contact sacrificial layer 103 may be removed in other manners to form the interlayer gap 135. Wherein the formation of the interlayer gap 135 is not affected when there are other material layers between the first semiconductor substrate 101 and the gate stack. In an example, when another material layer is further formed on the upper surface of the first semiconductor substrate 101, the material layer is further removed in the process of removing the contact sacrificial layer 103, as shown in fig. 10, and when the insulating layer 102 is formed, the step of removing the insulating layer is further included, and the upper surface of the first semiconductor substrate 101 is exposed.

Next, as shown in S7 of fig. 1 and fig. 11, step S7 is performed to remove the groove-spacing layer 130 and simultaneously remove the functional structure layer 121 exposed by the interlayer gap 135 to expose a portion of the channel layer corresponding to the interlayer gap 135, in an example, when the portion of the functional structure layer 121 is removed, the bottom 126 of the channel layer is exposed. By this step, an outer surface portion of the bottom 126 of the channel layer is exposed, so that electrical connection thereof can be achieved based on this portion of the channel layer.

As an example, the material of the functional structure layer 121 is the same as the material of the trench isolation layer 130, where the same may be in one-to-one correspondence, that is, the number of layers of the material layers included is the same as the type and thickness of each material layer, and in addition, the type and thickness of the material layers included in the functional structure layer may also be the same as the type and thickness of the material layers included in the trench isolation layer, which may not be limited, and it is ensured that the bottom of the channel layer is removed from the functional structure layer exposed from the interlayer gap and exposed. In an example, the trench isolation layer 130 is removed by a wet etching process, and the functional structure layer 121 exposed by the interlayer gap 135 is removed at the same time, that is, the trench isolation layer 130 is removed in the process of exposing the bottom 126 of the channel layer, so that a step of removing the trench isolation layer 130 by using dry etching can be omitted, and defects existing in dry etching in a high aspect ratio are alleviated. In the above-mentioned removal of each material layer, a suitable wet etching solution may be selected according to the actual kind and thickness of the functional structure layer 121 and the spacer 130, and a suitable wet etching condition may be designed. In the present embodiment, as shown in fig. 12, the first spacer layer 131 is remained while the functional structure layer 121 is removed. Based on the forming mode of the invention, the bottom removing process of the side wall material layer of the grid spacer groove can be saved, and the removing process of the bottom material layer of the grid spacer groove can be saved.

Finally, as shown in S8 of fig. 1 and fig. 12, step S8 is performed to fill the interlayer gap 135 with a semiconductor material to form a doped semiconductor layer 136 covering the exposed channel layer. On one hand, the doped semiconductor layer 136 is electrically connected to the portion of the bottom 126 of the channel layer exposed in the interlayer gap 135, so as to electrically connect the doped semiconductor layer 136 and the channel layer, and an electrical lead-out is performed, and a separate lead-out structure is not required to be prepared, on the other hand, the doped semiconductor layer 136 may be doped to form a device well region, such as an N well, and a doped source region is not required to be formed in the substrate below the gate spacer 129, and in addition, in an example, the doped semiconductor layer 136 may be designed to cooperate with the first well region 1011, so as to achieve a desired function. The scheme of the invention can save the area of the core region, such as reducing by 1.5%, and reduce the size of the device. In one example, the material of the doped semiconductor layer 136 includes, but is not limited to, doped polysilicon. By adopting the scheme of the invention, the doped semiconductor layer 136 can be moved between the first semiconductor substrate 101 and the laminated structure 115, and meanwhile, the doped semiconductor layer 136 of the invention is electrically connected with the bottom 126 of the channel layer in a contact manner, so that the electrical leading-out can be carried out.

As an example, as shown in fig. 13 to 15, the method for manufacturing a semiconductor structure further includes the steps of:

first, as shown in fig. 13-14, the sacrificial layers 105, 107, 109, 111, and 113 are removed based on the gate isolation trench 129, and gate structure layers 137, 138, 139, 140, and 141 are formed at positions corresponding to the sacrificial layers 105, 107, 109, 111, and 113, so as to obtain a step stack structure 142. In an example, as shown in fig. 14, the gate structure layer includes a gate dielectric structure formed on a surface of the dielectric layer and a gate electrode layer 145 formed on a surface of the gate dielectric structure, optionally, the gate dielectric structure includes a first gate dielectric layer 143 and a second gate dielectric layer 144, where a material of the first gate dielectric layer 143 includes but is not limited to a high-K dielectric layer, a material of the second gate dielectric layer 144 includes but is not limited to TiN, and a material of the gate electrode layer 145 includes but is not limited to W. In addition, the formed gate structure layer is further filled in the gate separation groove 129, and after the gate structure layer is formed, the method further includes a step of removing the material of the gate structure layer in the gate separation groove, wherein an etching process may be adopted to remove this part of the material layer, so as to obtain the structure shown in fig. 14.

Next, as shown in fig. 15, the gate isolation trench 129 is filled with an insulating material to form an isolation structure 146. The material of the isolation structure 146 includes, but is not limited to, silicon oxide. By adopting the scheme of the invention, the bottom 126 of the channel layer can be electrically led out through the doped semiconductor layer 136, so that the gate isolation groove 129 can be filled with insulating materials to form the isolation structure 146. Additionally, device stress may also be relieved by the isolation structure 146.

In addition, the gate dielectric structure (e.g., the first gate dielectric layer 143) in the gate structure layer may also be formed on the material layer around the gate spacer 129, and in an example, the method further includes a step of removing the portion of the material layer to leave only the first gate dielectric layer 143 on the sidewall and the bottom of the gate spacer 129.

As an example, as shown in fig. 15, the isolation structure includes a protrusion at the gate structure layer, so as to form a recess structure, namely ACS (Array common source) in the gate structure layer.

As an example, as shown in fig. 16, the end of the stacked structure 115 is formed with several steps, that is, the stacked structure 115 is a step-stacked structure, and it can be understood by those skilled in the art that the sacrificial layer in the gate stack in the stacked structure 115 herein has been replaced by a gate structure layer, wherein the adjacent dielectric layer and the gate structure layer in the gate stack form a stacked unit, and one stacked unit forms one step surface, so that the gate stack includes several stacked units, and several steps are correspondingly formed, optionally, each dielectric layer serves as a surface of each step surface. The preparation method further comprises the following steps: an insulating layer, which may be the isolation layer 117 mentioned in the previous examples, is formed on the first semiconductor substrate 101 and the stack structure 115, forming a second conductive contact structure 147 through the insulating layer and the step up to contact the doped semiconductor layer 103.

As an example, the method for manufacturing a semiconductor structure further includes the steps of: a first conductive contact structure 148 electrically connected to a conductive layer (e.g., the gate structure layer) in each step is formed on each step of the stack structure 115, and a third conductive contact structure 149 electrically connected to the channel layer is formed on the channel structure 120.

As an example, the method for manufacturing a semiconductor structure further includes the steps of: a fourth conductive contact structure 150 is formed on the peripheral region B of the first semiconductor substrate 101 to contact the first semiconductor substrate 101 through the insulating layer, wherein the stacked structure is formed on the core region a and has a distance from the fourth conductive contact structure 150. In one example, the fourth conductive contact structure 150 is prepared based on the same process steps as the first conductive contact structure 148, the second conductive contact structure 147, and the third conductive contact structure 149.

In one example, as shown in fig. 17, the method further includes the steps of: forming an insulating layer 155 on top of each conductive contact structure, forming a first contact point 152 corresponding to the first conductive contact structure 148, forming a second contact point 151 corresponding to the second conductive contact structure 147, forming a third contact point 153 corresponding to the third conductive contact structure 149, and forming a fourth contact point 154 corresponding to the fourth conductive contact structure 150, preferably, each contact point is formed on the same process. In addition, in one example, each contact is formed through the insulating layer 155, as shown in fig. 17, wherein each contact is prepared in a post-process (BEOL), which may be prepared using techniques commonly used in the art. In one example, the upper surfaces of the conductive contact structures are flush, in another example, the conductive structures are columnar, can be circular columns or square columns, and optionally comprise a conductive layer in the center, such as a W layer, and a transition layer in the periphery, such as a TiN layer. Furthermore, the upper and lower surfaces of each contact point corresponding to each conductive contact structure are flush.

As an example, the method for manufacturing a semiconductor structure further includes the steps of: ion implantation is performed on a side of the first semiconductor substrate 101 away from the doped semiconductor layer 136 to form a second well region (not shown). In an optional example, a structure in which the second well region, the first well region 1011, and the doped semiconductor layer 136 are sequentially and adjacently disposed is formed to meet structural requirements of devices based on different manufacturing processes. In a preferred example, the second well region is implanted to coincide with the first well region 1011, so as to supplement the first well region formed for the first time, thereby meeting the device requirements.

As an example, as shown in fig. 18, the method for manufacturing a semiconductor structure further includes:

a second base 200 is provided, wherein the second base 200 includes a second semiconductor substrate 201, an insulating dielectric layer 204 formed on the second semiconductor substrate 201, a functional device 202 formed in the insulating dielectric layer 204, and a metal contact 203 formed on the insulating dielectric layer 204. The second substrate may be a CMOS wafer, on which a plurality of functional devices 202 may be fabricated, and the types and the number of the functional devices 202 may be designed according to actual requirements, and may be used as different functional devices of a memory, such as a buffer, an amplifier, a decoder, and the like. The second base 200 is electrically connected to the functional structure on the first semiconductor substrate 101 through the metal contact terminal 203, and specifically, the connection layout can be performed according to actual requirements, and the back surfaces of the first semiconductor substrate 101 and the second semiconductor substrate 201 are exposed, so as to form the bonding structure shown in fig. 18.

The first semiconductor substrate and the structures formed thereon by forming the devices are inverted, the second base 200 is bonded to the devices on the first semiconductor substrate, the back surfaces of the first semiconductor substrate 101 and the second semiconductor substrate 201 are exposed after bonding, and the metal contact 203 of the second base 200 is electrically connected to the electrical connection component on the first semiconductor, for example, to the contact points on the conductive contact structures. In this step, the second base is bonded to the first semiconductor substrate with the functional device layer formed thereon according to the present invention, in an example, a CMOS wafer (a peripheral circuit wafer, the second base) is bonded to an Array wafer (an Array wafer, the first semiconductor substrate and the functional device thereon), for example, direct contact bonding between a dielectric layer and the dielectric layer may be used, and of course, other bonding methods may also be used, and electrical connection between components on the second base and the first semiconductor substrate and the functional device thereon may be achieved through bonding according to actual requirements.

In addition, in an example, as shown in fig. 19, the first semiconductor substrate 101 may be actually thinned to form the array wafer substrate 156, and the thinned thickness may be designed according to practice, and in an example, may be thinned to the position of the first well region 1011.

In one example, as shown in fig. 20 to 27, a first lead-out pad structure may be prepared on the fourth conductive contact structure 150, and the method for preparing the semiconductor structure further includes the steps of:

first, as shown in fig. 20, an insulating layer 157 is formed on a side of the first semiconductor substrate 101 away from the stacked structure 115, wherein the insulating layer 157 is made of a material including, but not limited to, silicon oxide;

next, as shown in fig. 21, the insulating layer 157 and the first semiconductor substrate 101 are etched to form an etching opening 158 exposing the fourth conductive contact structure 150; in one example, the fourth conductive contact structure 150 extends into the first well region 1011, where it is etched into the first well region to expose the bottom of the fourth conductive contact structure;

finally, as shown in fig. 22 to 27, a first lead-out pad structure electrically connected to the fourth conductive contact structure 150 is formed in the etched opening 158, and in an example, a preparation process of the first lead-out pad structure is provided:

as shown in fig. 22, a first extraction layer 159 is formed on the bottom, the sidewall and the material layer around the etched opening 158, wherein the material of the first extraction layer 159 includes but is not limited to Ti, and then, as shown in fig. 23, a portion of the first extraction layer 159 on the material layer around the etched opening 158 is removed, and portions on the bottom and the sidewall are remained; then, as shown in fig. 24, a second extraction layer 160 is formed on the inner surface of the first extraction layer 159, a third extraction layer 161 is filled on the surface of the second extraction layer 160, and the third extraction layer 161 fills the etched opening, wherein the material of the second extraction layer 160 includes but is not limited to TiN, and the material of the third extraction layer 161 includes but is not limited to W; next, as shown in fig. 25, removing a portion of the first extraction layer 159 on the material layer around the etched opening 158, and leaving a portion of the second extraction layer 160 and the third extraction layer 161 located on the bottom and the side wall, thereby obtaining a filling portion including the first extraction layer 159, the second extraction layer 160, and the third extraction layer 161; next, as shown in fig. 26, a conductive cap layer 162 is formed on the structure with the filling portion, wherein the material of the conductive cap layer includes, but is not limited to, Al; finally, as shown in fig. 27, the conductive layer 162 is etched to cover each of the filling portions individually, which may be performed by a photolithography etching process, and the filling portions and the conductive layer thereon form each of the first pad structures 163, and optionally, an isolation layer 164 is further formed around the conductive cap layer 162, where the material of the isolation layer 164 includes, but is not limited to, silicon nitride.

As an example, as shown in fig. 28, the method for manufacturing a semiconductor structure further includes the steps of: a second pad structure 206 is formed in the second substrate 200, and the second pad structure 206 is located corresponding to the peripheral region B of the first semiconductor substrate 101, and may further include an isolation layer 205 located around the second pad structure. The preparation method of the second lead-out pad structure 206 and the obtained structure may refer to the preparation of the first lead-out pad structure 163, and of course, a metal conductive covering layer may also be directly prepared on the conductive contact pillar to form the structure shown in fig. 28, which is not limited to this and may effectively achieve electrical lead-out. Through the manner, the first lead-out pad structure 163 can be prepared on the first semiconductor substrate (such as an array wafer), the second lead-out pad structure 206 can be prepared on the second substrate 200 (such as a peripheral circuit wafer), and certainly, the lead-out pad structures can be prepared on two wafers simultaneously, so that double increase of lead-out pads can be realized, electric lead-out of a device can be realized, and space cost can be saved.

In addition, as shown in fig. 27 and fig. 28, referring to fig. 1 to fig. 26, the present invention further provides a semiconductor structure, wherein the semiconductor structure is preferably prepared by using the method for preparing a semiconductor structure of the present invention, and of course, the semiconductor structure can also be prepared by using other methods, wherein the features of each material layer of the semiconductor structure in this embodiment can refer to the description in the method for preparing a semiconductor structure in this embodiment, and are not described herein again. The semiconductor structure includes:

a first semiconductor substrate 101;

a stack structure 115 comprising a doped semiconductor layer 136 and a gate stack, wherein the doped semiconductor layer 136 is located between the first semiconductor substrate 101 and the gate stack, and the gate stack comprises several gate structure layers 137, 138, 139, 140, 141 and dielectric layers 106, 108, 110, 112, 114 which are alternately stacked;

a channel structure 120 passing through the stacked structure 115, the channel structure including a channel layer and a functional structure layer 121 located outside the channel layer, the doped semiconductor layer 136 passing through the functional structure layer 121 in a direction parallel to the first semiconductor substrate 101 and contacting the channel layer, the doped semiconductor layer serving as a source.

As an example, the semiconductor structure further includes: an isolation structure 146 through the gate stack, the isolation structure extending in a set direction to separate the gate stack into portions, the material of the isolation structure 146 comprising an insulating material.

As an example, the channel layer includes a bottom portion 126 and a side portion 125 above the bottom portion, and an upper surface of the bottom portion 126 protrudes above an upper surface of the doped semiconductor layer 136.

As an example, the gate structure layer 137, 138, 139, 140, 141 includes a gate dielectric structure formed on a surface of the dielectric layer and a gate electrode layer 145 formed on a surface of the gate dielectric structure.

As an example, the first semiconductor substrate 101 has a first well region 1011, and the first well region 1011 is formed from the semiconductor substrate 101 near the doped semiconductor layer 136 based on ion implantation.

As an example, a second well region (not shown in the figure) is further formed in the first semiconductor substrate, and the second well region is formed based on ion implantation from a side of the first semiconductor substrate 101 away from the doped semiconductor layer 136.

As an example, the end of the laminated structure 115 is formed with several steps; further comprising: an insulating layer on the first semiconductor substrate 101 and the stacked structure 115; through the insulating layer and the step to a second conductive contact structure 147 in contact with the doped semiconductor layer 136.

As an example, it further includes: a first conductive contact structure 148 electrically connected to each of the gate layers in the gate stack through the insulating layer; a third conductive contact structure 149 is formed on the channel structure in electrical connection with the channel layer.

As an example, the first semiconductor substrate includes a core region a and a peripheral region B adjacent to each other, the peripheral region B has a fourth conductive contact structure 150 formed thereon and contacting the first semiconductor substrate through the insulating layer, and the stacked structure 115 is formed on the core region a and spaced apart from the fourth conductive contact structure 150.

As an example, a first lead-out pad structure 163 is formed on the first semiconductor substrate 101, an insulating layer 157 is formed on a side of the first semiconductor substrate away from the stacked structure, and the first lead-out pad structure 163 is electrically connected to the fourth conductive contact structure 150 through the insulating layer 157 and the first semiconductor substrate 101.

As an example, the second base 200 is further included, and the second base 200 includes a second semiconductor substrate 201, an insulating medium layer 204 formed on the second semiconductor substrate, a functional device 202 formed in the insulating medium layer, and a metal contact 203 formed on the insulating medium layer; the second base 200 is electrically connected to the functional structure on the first semiconductor substrate through the metal contact, and exposes the back surfaces of the first semiconductor substrate and the second semiconductor substrate.

As an example, a second pad structure 206 and a conductive contact pillar are further formed in the second base, the conductive contact pillar contacts the second semiconductor substrate 201 through the insulating medium layer 204, an isolation layer 205 is formed on a side of the second semiconductor substrate 201 away from the functional device, and the second pad structure 206 is electrically connected to the conductive contact pillar through the isolation layer 205 and the second semiconductor substrate 201.

In summary, according to the semiconductor structure and the manufacturing method thereof of the present invention, the contact sacrificial layer is removed based on the gate spacer to form the interlayer gap, the functional structure layer is removed based on the interlayer gap to expose the bottom epitaxial layer, the doped semiconductor layer is deposited to form the doped semiconductor layer, and the second conductive contact structure in contact with the doped semiconductor layer is formed, so that the electrical leading-out of the bottom epitaxial layer is achieved, and the area of the core region is reduced, thereby the gate spacer can be filled with the insulating material to form the insulating filling layer, the problem of the leakage between the gate word line and the common source line caused by filling the metal conductive material in the gate spacer is solved, and the problem of the parasitic capacitance formed between the gate word line and the common source line is solved. The invention also realizes the doubling of the bonding pad in the preparation of the device structure. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.