阅读说明：本技术 一种半导体器件的形成方法 (Method for forming semiconductor device ) 是由 王楠 于 2020-05-12 设计创作，主要内容包括：本发明公开一种半导体器件的形成方法,包括：形成第一阻隔层；在第一组合区和第二组合区的交界处,形成第二阻隔层；以第二阻隔层为掩模,在第二阻隔层两侧的介质层中形成位于拉栅极结构上的第一栅接触开口；以第一阻隔层和第二阻隔层为掩模在介质层中形成位于第一延伸区上的第一插塞开口；去除第二阻隔层；在介质层中形成位于第二延伸区和第三延伸区上的第二插塞开口和位于传输栅极结构上的第二栅接触开口。本申请,避免了第一组合区上的第一插塞和第二组合区上的第一插塞短路,定义第二插塞开口位置的第一阻隔层、以及第二阻隔层在位置上相互不受到限制,有利于降低工艺难度。(The invention discloses a method for forming a semiconductor device, which comprises the following steps: forming a first barrier layer; forming a second barrier layer at the junction of the first combination area and the second combination area; forming a first gate contact opening on the pull gate structure in the dielectric layers on two sides of the second barrier layer by taking the second barrier layer as a mask; forming a first plug opening on the first extension area in the dielectric layer by using the first barrier layer and the second barrier layer as masks; removing the second barrier layer; and forming a second plug opening on the second extension region and the third extension region and a second gate contact opening on the transmission gate structure in the dielectric layer. This application has avoided the first bullet short circuit on first combination district and the second combination district on the first plug, and the first barrier layer of definition second plug open position and second barrier layer do not receive the restriction in position each other, are favorable to reducing the technology degree of difficulty.)

1. A method of forming a semiconductor device, comprising:

providing a substrate, wherein the substrate comprises a unit area, the unit area comprises a first combination area and a second combination area which is symmetrical to the center of the first combination area, the first combination area and the second combination area respectively comprise a first extension area, a second extension area and a third extension area which extend along a first direction, the second extension area and the third extension area are positioned on two sides of the first extension area in a second direction, and the second direction is perpendicular to the first direction;

forming a transfer gate structure between the first extension region and the second extension region and a pull gate structure between the first extension region and the third extension region on the first combination region and the second combination region; forming a dielectric layer covering the transmission gate structure and the pull gate structure on the substrate;

forming first barrier layers on parts of the dielectric layers of the first combination area and the second combination area, wherein each first barrier layer covers the first extension area at the edge of the unit area and extends to the second extension area;

forming a second barrier layer covering a part of the dielectric layer on the first extension region at the intersection of the first combination region and the second combination region;

forming a first gate contact opening on the pull gate structure in the dielectric layer on two sides of the second barrier layer by taking the second barrier layer as a mask;

forming a first plug opening located on the first extension region in the dielectric layer by using the first barrier layer and the second barrier layer as masks;

removing the second barrier layer after forming the first gate contact opening and the first plug opening;

and after removing the second barrier layer, forming a second plug opening on the second extension region and the third extension region in the dielectric layer, and forming a second gate contact opening on the transmission gate structure in the dielectric layer.

2. The method for forming a semiconductor device according to claim 1, further comprising:

after the second barrier layer is removed, forming a third barrier layer and a fourth barrier layer on the first combination area and the second combination area, wherein the third barrier layer is located on a part of the dielectric layer in the second extension area, and the fourth barrier layer is located on a part of the dielectric layer in the third extension area;

forming a second plug opening in the dielectric layer on the second extension region and the third extension region by using the first barrier layer, the third barrier layer and the fourth barrier layer as masks;

after the second plug opening is formed, removing the first barrier layer, the third barrier layer and the fourth barrier layer.

3. The method for forming a semiconductor device according to claim 2, further comprising: and after removing the first barrier layer, the third barrier layer and the fourth barrier layer, forming a second gate contact opening on the transmission gate structure in the dielectric layer.

4. The method of forming a semiconductor device according to claim 2, wherein after removing the third barrier layer and the fourth barrier layer, forming the second gate contact opening on the transfer gate structure in the dielectric layer using the first barrier layer as a mask; and removing the first barrier layer after the second gate contact opening is formed.

5. The method for forming a semiconductor device according to claim 2, further comprising: forming the second gate contact opening on the transmission gate structure in the dielectric layer by using the first barrier layer as a mask; after the second gate contact opening is formed, removing the first barrier layer, the third barrier layer and the fourth barrier layer.

6. The method of claim 2, wherein the third barrier layer further extends over a portion of the dielectric layer in the first extension region, and wherein the fourth barrier layer further extends over a portion of the dielectric layer in the first extension region.

7. The method for forming a semiconductor device according to claim 2, further comprising: after the second gate contact opening and the second plug opening are formed, and after the first barrier layer, the third barrier layer and the fourth barrier layer are removed, a first plug is formed in the first plug opening, a first gate plug is formed in the first gate contact opening, a second plug is formed in the second plug opening, and a second gate plug is formed in the second gate contact opening.

8. The method for forming a semiconductor device according to claim 7, further comprising: forming a first sacrificial layer in the first plug opening and a second sacrificial layer in the first gate contact opening before forming the third barrier layer and the fourth barrier layer; forming a third sacrificial layer in the second plug opening; after forming the second gate contact opening, removing the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer before forming the first plug, the first gate plug, the second plug, and the second gate plug.

9. The method of claim 1, wherein after the first plug opening on the first extension region is formed in the dielectric layer using the first barrier layer and the second barrier layer as masks, the first gate contact opening on the pull-gate structure is formed in the dielectric layer on both sides of the second barrier layer using the second barrier layer as a mask.

10. The method of claim 1, wherein after the first gate contact opening on the pull gate structure is formed in the dielectric layer on both sides of the second barrier layer using the second barrier layer as a mask, the first plug opening on the first extension region is formed in the dielectric layer using the first barrier layer and the second barrier layer as masks.

11. The method of forming a semiconductor device according to claim 1 or 2, wherein the second barrier layer further extends to a portion of the dielectric layer in the second extension region and to a portion of the dielectric layer in the third extension region.

12. A method of forming a semiconductor device, comprising:

providing a substrate, wherein the substrate comprises a unit area, the unit area comprises a first combination area and a second combination area which is symmetrical to the center of the first combination area, the first combination area and the second combination area each comprise a first extension area, a second extension area and a third extension area which extend along a first direction, the second extension area and the third extension area are positioned on two sides of the first extension area in the second direction, and the second direction is perpendicular to the first direction;

forming a transfer gate structure between the first extension region and the second extension region and a pull gate structure between the first extension region and the third extension region on the first combination region and the second combination region; forming a dielectric layer covering the transmission gate structure and the pull gate structure on the substrate;

forming first barrier layers on parts of the dielectric layers of the first combination area and the second combination area, wherein each first barrier layer covers the first extension area at the edge of the unit area and extends to the second extension area;

forming a third barrier layer and a fourth barrier layer on the first combination area and the second combination area, wherein the third barrier layer is located on a part of the dielectric layer in the second extension area, and the fourth barrier layer is located on a part of the dielectric layer in the third extension area;

forming a second gate contact opening on the transmission gate structure in the dielectric layer by using the first barrier layer as a mask;

forming a second plug opening located on the second extension region and the third extension region in the dielectric layer by using the first barrier layer, the third barrier layer and the fourth barrier layer as masks;

removing the third barrier layer and the fourth barrier layer after forming the second gate contact opening and the second plug opening;

after the third blocking layer and the fourth blocking layer are removed, a first gate contact opening located on the pull gate structure is formed in the dielectric layer on two sides of the junction of the first combination area and the second combination area, and a first plug opening located on the first extension area is formed in the dielectric layer.

13. The method for forming a semiconductor device according to claim 12, further comprising:

after removing the third barrier layer and the fourth barrier layer, forming a second barrier layer covering a part of the dielectric layer on the first extension region at the intersection of the first combination region and the second combination region;

forming a first gate contact opening on the pull gate structure in the dielectric layer on two sides of the second barrier layer by taking the second barrier layer as a mask;

forming a first plug opening located on the first extension region in the dielectric layer by using the first barrier layer and the second barrier layer as masks;

after the first gate contact opening and the first plug opening are formed, the first barrier layer and the second barrier layer are removed.

14. The method of claim 13, wherein after the first gate contact opening on the pull gate structure is formed in the dielectric layer on both sides of the second barrier layer using the second barrier layer as a mask, a first plug opening on the first extension region is formed in the dielectric layer using the first barrier layer and the second barrier layer as masks.

15. The method of claim 13, wherein after the first plug opening on the first extension region is formed in the dielectric layer using the first barrier layer and the second barrier layer as masks, the first gate contact opening on the pull-gate structure is formed in the dielectric layer on both sides of the second barrier layer using the second barrier layer as masks.

16. The method of forming a semiconductor device of claim 13, wherein the second barrier layer further extends over a portion of the dielectric layer of the second extension region and a portion of the dielectric layer of the third extension region.

17. The method of forming a semiconductor device according to claim 13, wherein a first plug is formed in the first plug opening after removing the first barrier layer and the second barrier layer; forming a first gate plug in the first gate contact opening; forming a second plug in the second plug opening; a second gate plug in the second gate contact opening.

18. The method for forming a semiconductor device according to claim 17, further comprising: forming a third sacrificial layer in the second plug opening and a fourth sacrificial layer in the second gate contact opening before forming the second barrier layer; forming a first sacrificial layer in the first plug opening before forming the first gate contact opening; after forming the first gate contact opening and the first plug opening, removing the third sacrificial layer, the fourth sacrificial layer, and the first sacrificial layer before forming the first plug, the first gate plug, the second plug, and the second gate plug;

or, before forming the second barrier layer, forming the third sacrificial layer in the second plug opening and forming the fourth sacrificial layer in the second gate contact opening; forming the second sacrificial layer in the first gate contact opening before forming the first plug opening; after the first gate contact opening and the first plug opening are formed, the third sacrificial layer, the fourth sacrificial layer and the second sacrificial layer are removed before the first plug, the first gate plug, the second plug and the second gate plug are formed.

19. The method of claim 12, wherein the third barrier layer further extends over a portion of the dielectric layer in the first extension region, and wherein the fourth barrier layer further extends over a portion of the dielectric layer in the first extension region.

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a method for forming a semiconductor device.

Background

In order to comply with the development of morgan's law and satisfy the requirements of people for smaller size, smaller occupied space, and more convenient carrying and operation of various electronic products, semiconductor manufacturing technologies are rapidly developing with the goal of high integration, low power consumption, and high performance. In the semiconductor industry, integrated circuit products can be classified into three major types: digital circuits, analog circuits, digital-to-analog hybrids, where memory is a very important type of digital circuit. In recent years, with the progress of semiconductor processes, memories having a strong data storage function, such as random access memories, have been developed as memories. Static Random-Access Memory (SRAM) is a representative example of Random Access Memory, and is widely used in various fields because it can constantly maintain data stored therein as long as it is powered on.

In addition, in order to continuously improve the driving capability of current to the semiconductor circuit and further suppress the short channel effect, the semiconductor device has been developed from a conventional single gate planar device to a multi-gate three-dimensional device, such as a fin field effect transistor (FinFET). In Middle-Of-Line (MEOL) Of FinFET process flow, device connections are made using plugs. However, as the size of the device decreases, the distance between the plugs decreases, and short circuits easily occur, which affects the performance of the device. And when the position of the plug opening is defined, the requirement on the position of the formed barrier layer is higher, and the process difficulty is higher.

Disclosure of Invention

The invention aims to solve the problems of poor performance and high process difficulty of a semiconductor device in the prior art. The invention provides a method for forming a semiconductor device, which can reduce the complexity of the process and improve the performance of the semiconductor device.

In order to solve the above technical problem, an embodiment of the present invention discloses a method for forming a semiconductor device, including: providing a substrate, wherein the substrate comprises a unit area, the unit area comprises a first combination area and a second combination area which is symmetrical to the center of the first combination area, the first combination area and the second combination area respectively comprise a first extension area, a second extension area and a third extension area which extend along a first direction, the second extension area and the third extension area are positioned on two sides of the first extension area in a second direction, and the second direction is perpendicular to the first direction; forming a transfer gate structure between the first extension region and the second extension region and a pull gate structure between the first extension region and the third extension region on the first combination region and the second combination region; forming a dielectric layer covering the transmission gate structure and the pull gate structure on the substrate; forming first barrier layers on parts of the dielectric layers of the first combination area and the second combination area, wherein each first barrier layer covers the first extension area at the edge of the unit area and extends to the second extension area; forming a second barrier layer covering a part of the dielectric layer on the first extension region at the intersection of the first combination region and the second combination region; forming a first gate contact opening on the pull gate structure in the dielectric layer on two sides of the second barrier layer by taking the second barrier layer as a mask; forming a first plug opening located on the first extension region in the dielectric layer by using the first barrier layer and the second barrier layer as masks; removing the second barrier layer after forming the first gate contact opening and the first plug opening; and after removing the second barrier layer, forming a second plug opening on the second extension region and the third extension region in the dielectric layer, and forming a second gate contact opening on the transmission gate structure in the dielectric layer.

Optionally, after removing the second barrier layer, a third barrier layer and a fourth barrier layer are formed on both the first combination region and the second combination region, where the third barrier layer is located on a portion of the dielectric layer in the second extension region, and the fourth barrier layer is located on a portion of the dielectric layer in the third extension region; forming a second plug opening in the dielectric layer on the second extension region and the third extension region by using the first barrier layer, the third barrier layer and the fourth barrier layer as masks; after the second plug opening is formed, removing the first barrier layer, the third barrier layer and the fourth barrier layer.

Optionally, the method further includes: and after removing the first barrier layer, the third barrier layer and the fourth barrier layer, forming a second gate contact opening on the transmission gate structure in the dielectric layer.

Optionally, after removing the third blocking layer and the fourth blocking layer, forming the second gate contact opening located on the transfer gate structure in the dielectric layer by using the first blocking layer as a mask; and removing the first barrier layer after the second gate contact opening is formed.

Optionally, the method further includes: forming the second gate contact opening on the transmission gate structure in the dielectric layer by using the first barrier layer as a mask; after the second gate contact opening is formed, removing the first barrier layer, the third barrier layer and the fourth barrier layer.

Optionally, the third barrier layer further extends to a portion of the dielectric layer in the first extension region, and the fourth barrier layer further extends to a portion of the dielectric layer in the first extension region.

Optionally, the method further includes: after the second gate contact opening and the second plug opening are formed, and after the first barrier layer, the third barrier layer and the fourth barrier layer are removed, a first plug is formed in the first plug opening, a first gate plug is formed in the first gate contact opening, a second plug is formed in the second plug opening, and a second gate plug is formed in the second gate contact opening.

Optionally, the method further includes: forming a first sacrificial layer in the first plug opening and a second sacrificial layer in the first gate contact opening before forming the third barrier layer and the fourth barrier layer; forming a third sacrificial layer in the second plug opening; after forming the second gate contact opening, removing the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer before forming the first plug, the first gate plug, the second plug, and the second gate plug.

Optionally, after the first plug opening located in the first extension region is formed in the dielectric layer by using the first blocking layer and the second blocking layer as masks, the first gate contact opening located on the pull gate structure is formed in the dielectric layer on both sides of the second blocking layer by using the second blocking layer as a mask.

Optionally, after the first gate contact opening located on the pull gate structure is formed in the dielectric layer on both sides of the second barrier layer by using the second barrier layer as a mask, the first plug opening located on the first extension region is formed in the dielectric layer by using the first barrier layer and the second barrier layer as masks.

Optionally, the second barrier layer further extends to a portion of the dielectric layer in the second extension region and a portion of the dielectric layer in the third extension region.

The embodiment of the invention also discloses another method for forming the semiconductor device, which comprises the following steps: providing a substrate, wherein the substrate comprises a unit area, the unit area comprises a first combination area and a second combination area which is symmetrical to the center of the first combination area, the first combination area and the second combination area each comprise a first extension area, a second extension area and a third extension area which extend along a first direction, the second extension area and the third extension area are positioned on two sides of the first extension area in the second direction, and the second direction is perpendicular to the first direction; forming a transfer gate structure between the first extension region and the second extension region and a pull gate structure between the first extension region and the third extension region on the first combination region and the second combination region; forming a dielectric layer covering the transmission gate structure and the pull gate structure on the substrate; forming first barrier layers on parts of the dielectric layers of the first combination area and the second combination area, wherein each first barrier layer covers the first extension area at the edge of the unit area and extends to the second extension area; forming a third barrier layer and a fourth barrier layer on the first combination area and the second combination area, wherein the third barrier layer is located on a part of the dielectric layer in the second extension area, and the fourth barrier layer is located on a part of the dielectric layer in the third extension area; forming a second gate contact opening on the transmission gate structure in the dielectric layer by using the first barrier layer as a mask; forming a second plug opening located on the second extension region and the third extension region in the dielectric layer by using the first barrier layer, the third barrier layer and the fourth barrier layer as masks; removing the third barrier layer and the fourth barrier layer after forming the second gate contact opening and the second plug opening; after the third blocking layer and the fourth blocking layer are removed, a first gate contact opening located on the pull gate structure is formed in the dielectric layer on two sides of the junction of the first combination area and the second combination area, and a first plug opening located on the first extension area is formed in the dielectric layer.

Optionally, the method further includes: after removing the third barrier layer and the fourth barrier layer, forming a second barrier layer covering a part of the dielectric layer on the first extension region at the intersection of the first combination region and the second combination region; forming a first gate contact opening on the pull gate structure in the dielectric layer on two sides of the second barrier layer by taking the second barrier layer as a mask; forming a first plug opening located on the first extension region in the dielectric layer by using the first barrier layer and the second barrier layer as masks; after the first gate contact opening and the first plug opening are formed, the first barrier layer and the second barrier layer are removed.

Optionally, after the first gate contact opening located on the pull gate structure is formed in the dielectric layer on both sides of the second barrier layer by using the second barrier layer as a mask, a first plug opening located on the first extension region is formed in the dielectric layer by using the first barrier layer and the second barrier layer as masks.

Optionally, after the first plug opening located in the first extension region is formed in the dielectric layer by using the first blocking layer and the second blocking layer as masks, the first gate contact opening located on the pull gate structure is formed in the dielectric layer on both sides of the second blocking layer by using the second blocking layer as a mask.

Optionally, the second barrier layer further extends to a portion of the dielectric layer in the second extension region and a portion of the dielectric layer in the third extension region.

Optionally, after removing the first barrier layer and the second barrier layer, forming a first plug in the first plug opening; forming a first gate plug in the first gate contact opening; forming a second plug in the second plug opening; a second gate plug in the second gate contact opening.

Optionally, the method further includes: forming a third sacrificial layer in the second plug opening and a fourth sacrificial layer in the second gate contact opening before forming the second barrier layer; forming a first sacrificial layer in the first plug opening before forming the first gate contact opening; after forming the first gate contact opening and the first plug opening, removing the third sacrificial layer, the fourth sacrificial layer, and the first sacrificial layer before forming the first plug, the first gate plug, the second plug, and the second gate plug; or, before forming the second barrier layer, forming the third sacrificial layer in the second plug opening and forming the fourth sacrificial layer in the second gate contact opening; forming the second sacrificial layer in the first gate contact opening before forming the first plug opening; after the first gate contact opening and the first plug opening are formed, the third sacrificial layer, the fourth sacrificial layer and the second sacrificial layer are removed before the first plug, the first gate plug, the second plug and the second gate plug are formed.

Optionally, the third barrier layer further extends to a portion of the dielectric layer in the first extension region, and the fourth barrier layer further extends to a portion of the dielectric layer in the first extension region.

The invention has the beneficial effects that:

in the method for forming the semiconductor device provided by the technical scheme of the invention, the first barrier layer is formed on part of the dielectric layers of the first combination area and the second combination area, and the second barrier layer covering part of the dielectric layers on the first extension area is formed at the junction of the first combination area and the second combination area. And forming a first plug opening on the first extension region in the dielectric layer by using the first barrier layer and the second barrier layer as masks. Because the second barrier layer is used as a mask, the first grid contact opening on the pull grid structure is formed in the dielectric layers on two sides of the second barrier layer, and the first grid contact opening is used for filling the first plug, the first grid contact opening on the first combination area and the first grid contact opening on the second combination area are disconnected by the second barrier layer, the first grid contact opening on the first combination area and the first grid contact opening on the second combination area are prevented from being mutually communicated due to position deviation, and therefore the first plug on the first combination area and the first plug on the second combination area are prevented from being short-circuited. And then removing the second barrier layer, forming a second plug opening on the second extension region and the third extension region in the dielectric layer, and forming a second gate contact opening on the transmission gate structure in the dielectric layer. Because the second barrier layer covering the first extension region is removed before the second plug opening and the second gate contact opening are formed, that is, the first barrier layer and the second barrier layer defining the second plug opening are not limited in position, which is beneficial to reducing the process difficulty. In conclusion, the performance of the semiconductor device is improved.

Furthermore, the third barrier layer also extends to a part of the dielectric layer of the first extension area, and the fourth barrier layer also extends to a part of the dielectric layer of the first extension area. Because before forming third barrier layer and fourth barrier layer, remove the second barrier layer, consequently, the formation of third barrier layer and fourth barrier layer can not receive the influence of second barrier layer, and third barrier layer and fourth barrier layer can extend to on the partial dielectric layer of first extension district, and third barrier layer and fourth barrier layer only need be restricted at the size of first direction like this, and size on the second direction can be great, consequently the technology degree of difficulty that forms third barrier layer and fourth barrier layer reduces.

Furthermore, the second barrier layer also extends to a part of the dielectric layer of the second extension region and a part of the dielectric layer of the third extension region, so that the size of the second barrier layer only needs to be limited in the first direction, and the size in the second direction can be larger, thereby reducing the difficulty of the process for forming the second barrier layer.

In another method for forming a semiconductor device provided in the technical solution of the present invention, a first blocking layer is formed on a portion of a dielectric layer in a first combination area and a second combination area, a third blocking layer and a fourth blocking layer are formed on the first combination area and the second combination area, and a second plug opening located on a second extension area and a third extension area is formed in the dielectric layer by using the first blocking layer, the third blocking layer and the fourth blocking layer as masks. And forming a second gate contact opening on the transmission gate structure in the dielectric layer by using the first barrier layer as a mask, wherein the second gate contact opening is used for filling a second gate plug. After the third blocking layer and the fourth blocking layer are removed, a first gate contact opening located on the pull gate structure is formed in the dielectric layers on two sides of the junction of the first combination area and the second combination area, a first plug opening located on the first extension area is formed in the dielectric layers, and the first plug opening is used for filling the first plug. The first plug opening and the second gate contact opening are separated by the first barrier layer, so that the first plug opening and the second gate contact opening cannot be communicated with each other, and short circuit between the first plug and the second gate plug is avoided. And secondly, before the first gate contact opening and the first plug opening are formed, the third barrier layer and the fourth barrier layer are removed, namely the barrier layer at the position of the first plug opening, the third barrier layer and the fourth barrier layer are defined not to be limited in position, and the process difficulty is favorably reduced. In conclusion, the performance of the semiconductor device is improved.

Drawings

Fig. 1 is a flow chart of a method of forming a semiconductor device provided by an embodiment of the invention;

fig. 2 to fig. 10 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor device according to an embodiment of the present invention;

fig. 11 is a flow chart of another method for forming a semiconductor device according to an embodiment of the present invention.

Detailed Description

As described in the background, in the prior art, as the size of the device is reduced, the distance between the plugs is also reduced, and short circuits are easily generated, which affects the performance of the device. And when the position of the plug opening is defined, the requirement on the position of the formed barrier layer is higher, and the process difficulty is higher.

In order to solve the above problem, the present embodiment proposes a method for forming a semiconductor device, which is provided by referring to a flowchart of a method for forming a semiconductor device shown in fig. 1, and includes the following steps:

step S11: providing a substrate, wherein the substrate comprises a unit area, the unit area comprises a first combination area and a second combination area which is symmetrical to the center of the first combination area, the first combination area and the second combination area respectively comprise a first extension area, a second extension area and a third extension area, the first extension area, the second extension area and the third extension area extend along a first direction, the second extension area and the third extension area are positioned on two sides of the first extension area in a second direction, and the second direction is vertical to the first direction;

step S12: forming a transfer gate structure between the first extension region and the second extension region and a pull gate structure between the first extension region and the third extension region on the first combination region and the second combination region; forming a dielectric layer covering the transmission gate structure and the pull gate structure on the substrate;

step S13: forming first barrier layers on partial dielectric layers of the first combination area and the second combination area, wherein each first barrier layer covers the first extension area at the edge of the unit area and extends to the second extension area;

step S14: forming a second barrier layer covering part of the dielectric layer on the first extension area at the junction of the first combination area and the second combination area;

step S15: forming a first gate contact opening on the pull gate structure in the dielectric layers on two sides of the second barrier layer by taking the second barrier layer as a mask;

step S16: forming a first plug opening on the first extension area in the dielectric layer by using the first barrier layer and the second barrier layer as masks;

step S17: removing the second barrier layer after forming the first gate contact opening and the first plug opening;

step S18: and after removing the second barrier layer, forming a second plug opening on the second extension region and the third extension region in the dielectric layer, and forming a second gate contact opening on the transmission gate structure in the dielectric layer.

By adopting the method, the first grid contact opening on the first combination area and the first grid contact opening on the second combination area are disconnected by the second barrier layer, so that the first grid contact opening on the first combination area and the first grid contact opening on the second combination area are prevented from being mutually communicated due to position deviation, and therefore, the first plug on the first combination area and the first plug on the second combination area are prevented from being short-circuited. In addition, the first barrier layer and the second barrier layer defining the opening of the second plug are not limited in position, which is beneficial to reducing the process difficulty. In conclusion, the performance of the semiconductor device is improved. Furthermore, the formation of the third barrier layer and the fourth barrier layer is not affected by the second barrier layer, and the difficulty of the process for forming the third barrier layer and the fourth barrier layer is reduced. Furthermore, the dimension of the second barrier layer only needs to be limited in the first direction, and the dimension in the second direction can be larger, so that the difficulty of the process for forming the second barrier layer is reduced.

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The following describes a method for forming a semiconductor device according to an embodiment of the present invention with reference to schematic structural diagrams corresponding to steps in a method for forming a semiconductor device according to an embodiment of the present invention shown in fig. 2 to 9.

Referring to fig. 2, a substrate is provided, the substrate includes a unit area 1, the unit area 1 includes a first combination area 11 and a second combination area 12 symmetrical to the center of the first combination area 11, each of the first combination area 11 and the second combination area 12 includes a first extension area 13, a second extension area 14 and a third extension area 15 extending along a first direction x, the second extension area 14 and the third extension area 15 are located on two sides of the first extension area 13 in a second direction y, and the second direction y is perpendicular to the first direction x.

In this embodiment, the material of the substrate includes, but is not limited to, silicon, germanium, silicon germanium, etc., which are not listed here. An isolation structure or other structures may also be formed on the substrate, which is not specifically limited in this embodiment.

It should be noted that in the present embodiment, mutually discrete fins 16 are further formed on the substrate, and the fins 16 may extend along the second direction y, but the present embodiment only schematically illustrates that the first combination region 11 and the second combination region 12 respectively have two fins 16, and a person skilled in the art may specifically determine the number of fins 16 according to actual situations.

Referring to fig. 2, on the first and second combined regions 11 and 12, a transfer gate structure 2 between the first and second extension regions 13 and 14 and a pull gate structure 3 between the first and third extension regions 13 and 15 are formed.

Further, the pull-gate structure 3 includes a pull-up gate structure (PU) and a pull-down gate structure (PD). For example, in fig. 2, the portion of the pull-gate structure 3 in the first combination region 11 around the left fin 16 in the first combination region 11 is a pull-down gate structure (PD), and the portion of the pull-gate structure 3 in the first combination region 11 around the right fin 16 in the first combination region 11 (including the portion extending into the second combination region 12) is a pull-up gate structure (PU). Of course, it may be specifically set as needed.

The structures of the pull-up gate structure (PU) and the pull-down gate structure (PD) included in the pull-gate structure 3 in the second combination region 12 and the structures of the pull-up gate structure (PU) and the pull-down gate structure (PD) included in the pull-gate structure 3 in the first combination region 11 are centrosymmetric, and are not described herein again.

Referring to fig. 3, a dielectric layer 17 covering the transfer gate structure 2 and the pull gate structure 3 is also formed on the substrate.

In this embodiment, referring to fig. 3, a dielectric layer 17 is formed on the substrate and covers the transfer gate structure 2, the pull gate structure 3 and the fin portion 16. The material of the dielectric layer 17 includes, but is not limited to, silicon carbide, silicon oxide, and other common dielectric layer materials, which is not specifically limited in this embodiment.

Referring to fig. 4, first barrier layers 6 are formed on portions of the dielectric layer 17 of the first combination region 11 and the second combination region 12, and each first barrier layer 6 covers the first extension region 13 at the edge of the cell region 1 and extends onto the second extension region 14.

It should be noted that, in this embodiment, the first barrier layer 6 is formed on the first extension region 13 and the second extension region 14, a portion of the dielectric layer 17 between the first extension region 13 and the second extension region 14, and a portion of the dielectric layer 17 between the first extension region 13 and the third extension region 15, and the first barrier layer 6 is not located on the third extension region 15.

With continued reference to fig. 4, at the intersection of the first combination area 11 and the second combination area 12, a second barrier layer 7 is formed covering a portion of the dielectric layer 17 on the first extension area 13.

It should be noted that, in this embodiment, the second barrier layer 7 spans part of the first combination region 11 and part of the second combination region 12 in the first direction x, and in the second direction y, the second barrier layer 7 is located on the first extension region 13 and part of the dielectric layer 17 on both sides of the first extension region 13.

In other embodiments, the second barrier layer 7 also extends to a portion of the dielectric layer in the second extension region and to a portion of the dielectric layer in the third extension region.

With continued reference to fig. 4, a first gate contact opening 31 on the pull gate structure 3 is formed in the dielectric layer 17 on both sides of the second barrier layer 7 using the second barrier layer 7 as a mask.

Further, in the present embodiment, the first gate contact opening 31 is formed on the pull-up gate structure (PU).

With continued reference to fig. 4, a first plug opening 4 is formed in the dielectric layer 17 over the first extension region 13 using the first barrier layer 6 and the second barrier layer 7 as masks.

In this embodiment, in other embodiments, the order of forming the first gate contact opening 31 and forming the first plug opening 4 may be: after forming the first gate contact opening 31 on the pull gate structure 3 in the dielectric layer on both sides of the second barrier layer 7 by using the second barrier layer 7 as a mask, the first plug opening 4 on the first extension region 13 is formed in the dielectric layer by using the first barrier layer 6 and the second barrier layer 7 as masks. In other embodiments, the order of forming the first gate contact opening 31 and forming the first plug opening 4 is: after forming the first plug opening 4 on the first extension region 13 in the dielectric layer by using the first barrier layer 6 and the second barrier layer 7 as masks, forming the first gate contact opening 31 on the pull gate structure 3 in the dielectric layer on both sides of the second barrier layer 7 by using the second barrier layer 7 as a mask. Referring to fig. 5, after the first gate contact opening 31 and the first plug opening 4 are formed, the second barrier layer 7 is removed.

Further, in this embodiment, after removing the second barrier layer 7, referring to fig. 6, a third barrier layer 8 and a fourth barrier layer 9 are formed on both the first combination area 11 and the second combination area 12, the third barrier layer 8 is located on a portion of the dielectric layer 17 of the second extension area 14, and the fourth barrier layer 9 is located on a portion of the dielectric layer 17 of the third extension area 15.

The third barrier layer 8 may also extend over a portion of the dielectric layer 17 of the first extension 13 and the fourth barrier layer 9 may also extend over a portion of the dielectric layer of the first extension 13.

Referring to fig. 7, a second plug opening 5 is formed in the dielectric layer 17 on the second extension region 14 and the third extension region 15 using the first barrier layer 6, the third barrier layer 8 and the fourth barrier layer 9 as masks.

Then, referring to fig. 8, after forming the second plug opening 5, the first barrier layer 6, the third barrier layer 8 and the fourth barrier layer 9 are removed.

Referring to fig. 9, after removing the first barrier layer 6, the third barrier layer 8, and the fourth barrier layer 9, a second gate contact opening 32 on the transfer gate structure 2 is formed in the dielectric layer.

It should be noted that the sequence of forming the second plug opening 5, removing the first barrier layer 6, the third barrier layer 8, and the fourth barrier layer 9, and forming the second gate contact opening 32 may not be limited to what is described in the above embodiment, and in this embodiment, the sequence of forming the second plug opening 5, removing the first barrier layer 6, the third barrier layer 8, and the fourth barrier layer 9, and forming the second gate contact opening 32 may also be:

after removing the third barrier layer 8 and the fourth barrier layer 9, forming a second gate contact opening 32 on the transfer gate structure 2 in the dielectric layer 17 by using the first barrier layer 6 as a mask; after forming the second gate contact opening 32, the first barrier layer 6 is removed.

Or, a second gate contact opening 32 located on the transfer gate structure 2 is formed in the dielectric layer by using the first blocking layer 6 as a mask; after forming the second gate contact opening 32, the first barrier layer 6, the third barrier layer 8, and the fourth barrier layer 9 are removed.

In this embodiment, after forming the second gate contact opening and the second plug opening, and after removing the first barrier layer 6, the third barrier layer 8, and the fourth barrier layer 9, the method further includes forming a first plug (not shown) in the first plug opening 4, forming a first gate plug (not shown) in the first gate contact opening 31, forming a second plug (not shown) in the second plug opening 5, and forming a second gate plug (not shown) in the second gate contact opening 32.

Further, before forming the third barrier layer 8 and the fourth barrier layer 9, a first sacrificial layer is formed in the first plug opening 4, and a second sacrificial layer is formed in the first gate contact opening 31; a third sacrificial layer is formed in the second plug opening 5.

After the second gate contact opening 32 is formed, the first, second, and third sacrificial layers are removed before the first, second, and second plugs are formed.

In this embodiment, the third barrier layer 8 further extends to a portion of the dielectric layer 17 of the first extension region 13, and the fourth barrier layer 9 further extends to a portion of the dielectric layer of the first extension region 13.

Referring to fig. 10, the second barrier layer 7 also extends onto a portion of the dielectric layer 17 of the second extension region 14 and onto a portion of the dielectric layer 17 of the third extension region 15.

By adopting the scheme, the first barrier layer is formed on part of the dielectric layers of the first combination area and the second combination area, and the second barrier layer covering part of the dielectric layers on the first extension area is formed at the junction of the first combination area and the second combination area. And forming a first plug opening on the first extension region in the dielectric layer by using the first barrier layer and the second barrier layer as masks. Because the second barrier layer is used as a mask, the first grid contact opening on the pull grid structure is formed in the dielectric layers on two sides of the second barrier layer, and the first grid contact opening is used for filling the first plug, the first grid contact opening on the first combination area and the first grid contact opening on the second combination area are disconnected by the second barrier layer, the first grid contact opening on the first combination area and the first grid contact opening on the second combination area are prevented from being mutually communicated due to position deviation, and therefore the first plug on the first combination area and the first plug on the second combination area are prevented from being short-circuited. And then removing the second barrier layer, forming a second plug opening on the second extension region and the third extension region in the dielectric layer, and forming a second gate contact opening on the transmission gate structure in the dielectric layer. Because the second barrier layer covering the first extension region is removed before the second plug opening and the second gate contact opening are formed, that is, the first barrier layer and the second barrier layer defining the second plug opening are not limited in position, which is beneficial to reducing the process difficulty. In conclusion, the performance of the semiconductor device is improved.

Furthermore, the third barrier layer also extends to a part of the dielectric layer of the first extension area, and the fourth barrier layer also extends to a part of the dielectric layer of the first extension area. Because before forming third barrier layer and fourth barrier layer, remove the second barrier layer, consequently, the formation of third barrier layer and fourth barrier layer can not receive the influence of second barrier layer, and third barrier layer and fourth barrier layer can extend to on the partial dielectric layer of first extension district, and third barrier layer and fourth barrier layer only need be restricted at the size of first direction like this, and size on the second direction can be great, consequently the technology degree of difficulty that forms third barrier layer and fourth barrier layer reduces.

Furthermore, the second barrier layer also extends to a part of the dielectric layer of the second extension region and a part of the dielectric layer of the third extension region, so that the size of the second barrier layer only needs to be limited in the first direction, and the size in the second direction can be larger, thereby reducing the difficulty of the process for forming the second barrier layer.

The present embodiment also provides another method for forming a semiconductor device, and further, refer to a flowchart of the method for forming another semiconductor device provided in the embodiment of the present invention shown in fig. 11. Another method for forming a semiconductor device provided by the embodiment of the invention includes:

step S21: providing a substrate, wherein the substrate comprises a unit area, the unit area comprises a first combination area and a second combination area which is symmetrical to the center of the first combination area, the first combination area and the second combination area respectively comprise a first extension area, a second extension area and a third extension area, the first extension area, the second extension area and the third extension area extend along a first direction, the second extension area and the third extension area are positioned at two sides of the first extension area in a second direction, and the second direction is vertical to the first direction;

step S22: forming a transfer gate structure between the first extension region and the second extension region and a pull gate structure between the first extension region and the third extension region on the first combination region and the second combination region; forming a dielectric layer covering the transmission gate structure and the pull gate structure on the substrate;

step S23: forming first barrier layers on partial dielectric layers of the first combination area and the second combination area, wherein each first barrier layer covers the first extension area at the edge of the unit area and extends to the second extension area;

step S24: forming a third barrier layer and a fourth barrier layer on the first combination area and the second combination area, wherein the third barrier layer is positioned on a part of the dielectric layer of the second extension area, and the fourth barrier layer is positioned on a part of the dielectric layer of the third extension area;

step S25: forming a second gate contact opening on the transmission gate structure in the dielectric layer by using the first barrier layer as a mask;

step S26: forming a second plug opening on a third extension area of the second extension area in the dielectric layer by taking the first barrier layer, the third barrier layer and the fourth barrier layer as masks;

step S27: removing the third barrier layer and the fourth barrier layer after forming the second gate contact opening and the second plug opening;

step S28: after the third blocking layer and the fourth blocking layer are removed, a first gate contact opening located on the pull gate structure is formed in the dielectric layers on two sides of the junction of the first combination area and the second combination area, and a first plug opening located on the first extension area is formed in the dielectric layers.

A method of forming the above semiconductor device is described below.

Firstly, a substrate is provided, the substrate comprises a unit area, the unit area comprises a first combination area and a second combination area which is symmetrical to the center of the first combination area, the first combination area and the second combination area respectively comprise a first extension area, a second extension area and a third extension area which extend along a first direction, the second extension area and the third extension area are arranged on two sides of the first extension area in a second direction, and the second direction is perpendicular to the first direction.

In this embodiment, the material of the substrate includes, but is not limited to, silicon, germanium, silicon germanium, etc., which are not listed here. An isolation structure or other structures may also be formed on the substrate, which is not specifically limited in this embodiment.

It should be noted that, in this embodiment, mutually discrete fin portions are further formed on the substrate, and a person skilled in the art may specifically determine the number of the fin portions according to an actual situation, which is not specifically limited in this embodiment.

Further, the structures of the substrate, the cell region, and the like are not substantially different from those in the prior art, and reference may also be made to fig. 2, which is not described herein again in this embodiment.

Next, forming a transfer gate structure between the first extension region and the second extension region and a pull gate structure between the first extension region and the third extension region on the first combination region and the second combination region; and forming a dielectric layer covering the transmission gate structure and the pull gate structure on the substrate.

Further, the pull-gate structure includes a pull-up gate structure (PU) and a pull-down gate structure (PD). The specific structure is not substantially different from the pull-up gate structure (PU) and the pull-down gate structure (PD) in the prior art, and reference may also be made to fig. 2. The part on the left side of the central axis of the first direction of the first combination area is a pull-down grid structure, the part on the right side of the central axis of the first direction of the first combination area is a pull-up grid structure, and the part on the right side of the central axis of the second combination area is a pull-up grid structure.

It should be noted that, in this embodiment, the dielectric layer is formed on the substrate and covers the transfer gate structure, the pull gate structure and the fin portion, and specifically, refer to fig. 3. The material of the dielectric layer includes, but is not limited to, silicon carbide, silicon oxide, and other common dielectric layer materials, which is not limited in this embodiment.

And then, forming first barrier layers on the first combination area and part of the dielectric layer of the first combination area, wherein each first barrier layer covers the first extension area at the edge of the unit area and extends to the second extension area.

Then, a third barrier layer and a fourth barrier layer are formed on both the first combined region and the second combined region. The third barrier layer is located on a part of the dielectric layer of the second extension area, and the fourth barrier layer is located on a part of the dielectric layer of the third extension area.

And then, forming a second gate contact opening on the transmission gate structure in the dielectric layer by taking the first barrier layer as a mask.

And then, forming a second plug opening on the second extension area and the third extension area in the dielectric layer by taking the first barrier layer, the third barrier layer and the fourth barrier layer as masks.

Then, the third barrier layer and the fourth barrier layer are removed.

In this embodiment, after removing the third blocking layer and the fourth blocking layer, a second blocking layer covering a portion of the dielectric layer in the first extension region is formed at a boundary between the first combination region and the second combination region.

And then, forming a first gate contact opening on the pull gate structure in the dielectric layers on two sides of the second barrier layer by taking the second barrier layer as a mask.

Then, a first plug opening located on the first extension region is formed in the dielectric layer by taking the first barrier layer and the second barrier layer as masks. After the first gate contact opening and the first plug opening are formed, the first barrier layer and the second barrier layer are removed.

It should be noted that the sequence of forming the first gate contact opening and forming the first plug opening may not be limited to the sequence described in the above embodiment, and in this embodiment, the sequence of forming the first gate contact opening and forming the first plug opening may also be: after a first plug opening located on the first extension area is formed in the dielectric layer by taking the first blocking layer and the second blocking layer as masks, a first gate contact opening located on the pull gate structure is formed in the dielectric layer on two sides of the second blocking layer by taking the second blocking layer as a mask.

Further, in this embodiment, after removing the first barrier layer and the second barrier layer, the method further includes: forming a first plug in the first plug opening; forming a first gate plug in the first gate contact opening; forming a second plug in the second plug opening; a second gate plug in the second gate contact opening.

Further, before forming the second barrier layer, forming a third sacrificial layer in the second plug opening and a fourth sacrificial layer in the second gate contact opening; forming a first sacrificial layer in the first plug opening before forming the first gate contact opening; after the first gate contact opening and the first plug opening are formed, the third sacrificial layer, the fourth sacrificial layer and the first sacrificial layer are removed before the first plug, the first gate plug, the second plug and the second gate plug are formed.

Or, before forming the second barrier layer, forming a third sacrificial layer in the second plug opening and forming a fourth sacrificial layer in the second gate contact opening; forming a second sacrificial layer in the first gate contact opening before forming the first plug opening; after the first gate contact opening and the first plug opening are formed, the third sacrificial layer, the fourth sacrificial layer and the second sacrificial layer are removed before the first plug, the first gate plug, the second plug and the second gate plug are formed.

In this embodiment, the second barrier layer may further extend to a portion of the dielectric layer in the second extension region and a portion of the dielectric layer in the third extension region.

It should be further noted that, in this embodiment, the third barrier layer may also extend to a portion of the dielectric layer in the first extension region, and the fourth barrier layer also extends to a portion of the dielectric layer in the first extension region.

It should be noted that, in the present embodiment, the structures of the barrier layer, the plug opening, and the gate contact opening are not substantially different from those in the prior art, and reference may also be made to the schematic structural diagrams shown in fig. 2 to fig. 10, which are not described again in this embodiment.

The method forms a first barrier layer on part of the dielectric layer of the first combination area and the second combination area, forms a third barrier layer and a fourth barrier layer on the first combination area and the second combination area, and forms a second plug opening on the second extension area and the third extension area in the dielectric layer by taking the first barrier layer, the third barrier layer and the fourth barrier layer as masks. And forming a second gate contact opening on the transmission gate structure in the dielectric layer by using the first barrier layer as a mask, wherein the second gate contact opening is used for filling a second gate plug. After the third blocking layer and the fourth blocking layer are removed, a first gate contact opening located on the pull gate structure is formed in the dielectric layers on two sides of the junction of the first combination area and the second combination area, a first plug opening located on the first extension area is formed in the dielectric layers, and the first plug opening is used for filling the first plug. The first plug opening and the second gate contact opening are separated by the first barrier layer, so that the first plug opening and the second gate contact opening cannot be communicated with each other, and short circuit between the first plug and the second gate plug is avoided. And secondly, before the first gate contact opening and the first plug opening are formed, the third barrier layer and the fourth barrier layer are removed, namely the barrier layer at the position of the first plug opening, the third barrier layer and the fourth barrier layer are defined not to be limited in position, and the process difficulty is favorably reduced. In conclusion, the performance of the semiconductor device is improved.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing is a more detailed description of the invention, taken in conjunction with the specific embodiments thereof, and that no limitation of the invention is intended thereby. Various changes in form and detail, including simple deductions or substitutions, may be made by those skilled in the art without departing from the spirit and scope of the invention.