阅读说明：本技术 解耦电容系统及方法 (Decoupling capacitance system and method ) 是由 刘思麟 王奕翔 洪照俊 于 2021-07-26 设计创作，主要内容包括：本发明的实施例公开了一种解耦电容系统及方法。一种解耦电容系统,包括：解耦电容电耦接在第一或第二参考电压轨与第一节点之间；偏压电路耦接于第一节点与对应的第二参考电压轨或第一参考电压轨之间。由于解耦电容电路和偏置电路之间的串联连接,偏置电路两端的电压降有效地降低了解耦电容电路两端的电压降,从而使解耦电容电路两端的电压降小于解耦电容系统两端的电压降。(The embodiment of the invention discloses a decoupling capacitor system and a decoupling capacitor method. A decoupling capacitance system comprising: the decoupling capacitor is electrically coupled between the first or second reference voltage rail and the first node; the bias circuit is coupled between the first node and the corresponding second reference voltage rail or the first reference voltage rail. Due to the series connection between the decoupling capacitor circuit and the bias circuit, the voltage drop at the two ends of the bias circuit effectively reduces the voltage drop at the two ends of the decoupling capacitor circuit, so that the voltage drop at the two ends of the decoupling capacitor circuit is smaller than the voltage drop at the two ends of the decoupling capacitor system.)

1. A decoupling capacitance system, comprising:

a decoupling capacitance circuit electrically coupled between the first or second reference voltage rail and a first node; and

a biasing circuit electrically coupled between the first node and the respective second or first reference voltage rails.

2. The decoupling capacitance system of claim 1, wherein:

the decoupling capacitor circuit includes a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) of a capacitor configuration electrically coupled between the first node and the first or second reference voltage rails.

3. The decoupling capacitance system of claim 2, wherein:

the gate oxide thickness of the thick oxide MOSFET is greater than about 0.2 nm;

a gate oxide thickness of the thin oxide MOSFET is equal to or less than about 0.2 nm; and is

The capacitor configured MOSFET is a thin oxide MOSFET.

4. The decoupling capacitance system of claim 2, wherein:

the capacitor configured MOSFET has a first configuration or a second configuration;

the first configuration has:

a gate terminal of a MOSFET of the capacitor configuration is electrically coupled to the first node; and

each of the source and drain terminals of the capacitor configured MOSFET is electrically coupled to:

(A) the first reference voltage rail; or

(B) The second reference voltage rail; and

the second configuration has:

each of the source terminal and the drain terminal of the capacitor configured MOSFET is electrically coupled to the first node; and

the gate terminal of the capacitor configured MOSFET is electrically coupled to:

the first reference voltage rail; or

The second reference voltage rail.

5. The decoupling capacitance system of claim 1, wherein:

the bias circuit is a self-bias circuit.

6. The decoupling capacitance system of claim 5, wherein:

the self-biasing circuit is a diode configured Metal Oxide Semiconductor Field Effect Transistor (MOSFET).

7. The decoupling capacitance system of claim 6, wherein:

the diode configured MOSFET has a first configuration or a second configuration;

the first configuration has:

each of a gate terminal and a drain terminal of the diode configured MOSFET is electrically coupled to the first node; and

a source terminal of the diode-configured MOSFET is correspondingly electrically coupled to the second reference voltage rail; and

the second configuration has:

the source terminal of the diode configured MOSFET is electrically coupled to the first node; and

each of the gate terminal and the drain terminal of the diode configured MOSFET is electrically coupled to the second reference voltage rail.

8. The decoupling capacitance system of claim 1, further comprising:

a bias current generator configured to provide a bias current to the first node, thereby boosting a voltage drop across the bias circuit.

9. A decoupling capacitance system, comprising:

a decoupling capacitance circuit electrically coupled between the first or second reference voltage rail and a first node; and

a filter bias circuit electrically coupled between the first node and the respective second or first reference voltage rails, the filter bias circuit comprising:

an N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a P-type MOSFET (PFET) electrically coupled in parallel between the first node and the respective second or first reference voltage rail;

a first filter electrically coupled to a gate terminal of the N-type MOSFET (NFET); and

a second filter electrically coupled to a gate terminal of the PFET; and is

When the first filter is configured as a high pass filter, the second filter has a configuration configured as a high pass filter; and

when the first filter is configured as a low-pass filter, the second filter has a configuration configured as a low-pass filter.

10. A method of decoupling voltage changes from a first voltage drop between a first reference voltage rail and a second reference voltage rail, the method comprising:

electrically coupling a decoupling capacitance circuit between the first or second reference voltage rail and a first node; and

electrically coupling a biasing circuit between the first node and the respective second or first reference voltage rails, resulting in a second voltage drop across the decoupling capacitor circuit that is less than the first voltage drop.

Technical Field

Embodiments of the invention relate to decoupling capacitance systems and methods.

Background

An integrated circuit ("IC") includes one or more semiconductor devices. One way to represent a semiconductor device is to refer to a plan view as a layout view. The layout is generated in the context of design rules. A set of design rules impose constraints on the placement of the corresponding patterns in the layout, such as geographic/spatial constraints, connectivity constraints, and the like. Typically, a set of design rules includes a subset of design rules related to spacing and other interactions between patterns in adjacent or contiguous cells, where the patterns represent conductors in a metallization layer.

Typically, a set of design rules are specific to the process/technology node by which a semiconductor device is to be manufactured based on a layout diagram. The design rule set compensates for variability of the corresponding process/technology node. This compensation increases the likelihood that the actual semiconductor device generated from the layout will become an acceptable counterpart to the virtual device upon which the layout is based.

Disclosure of Invention

According to an aspect of an embodiment of the present invention, there is provided a decoupling capacitance (decap) system, including: a decoupling capacitance circuit electrically coupled between the first or second reference voltage rail and a first node; and a bias circuit electrically coupled between the first node and the respective second or first reference voltage rail.

According to another aspect of an embodiment of the present invention, there is provided a decoupling capacitance (decap) system, including: a decoupling capacitance circuit electrically coupled between the first or second reference voltage rail and a first node; and a filter bias circuit electrically coupled between the first node and the respective second or first reference voltage rail, the filter bias circuit comprising: an N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a P-type MOSFET (PFET) electrically coupled in parallel between a first node and a respective second or first reference voltage rail; a first filter electrically coupled to a gate terminal of an N-type MOSFET (NFET); and a second filter electrically coupled to the gate terminal of the PFET; and when the first filter is configured as a high pass filter, the second filter has a configuration configured as a high pass filter; and when the first filter is configured as a low pass filter, the second filter is configured as a low pass filter.

According to yet another aspect of embodiments of the present invention, there is provided a method of decoupling from a voltage variation of a first voltage drop between a first reference voltage rail and a second reference voltage rail, the method comprising: a decoupling capacitance (decap) circuit electrically coupled between the first or second reference voltage rail and the first node; and electrically coupling a biasing circuit between the first node and the respective second or first reference voltage rails, thereby causing a second voltage drop across the decoupling capacitor circuit to be less than the first voltage drop.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1A-1C are respective block diagrams of semiconductor devices according to some embodiments.

Fig. 2A-2B are corresponding block diagrams according to some embodiments.

Fig. 3A-3J are corresponding circuit diagrams according to some embodiments.

Fig. 3K is a layout diagram according to some embodiments.

Fig. 4A-4G are corresponding circuit diagrams according to some embodiments.

Fig. 5A-5B are corresponding circuit diagrams according to some embodiments.

Fig. 6,7, and 8A-8B are respective flow diagrams according to some embodiments.

Fig. 9 is a block diagram of an Electronic Design Automation (EDA) system in accordance with some embodiments.

Fig. 10 is a block diagram of an Integrated Circuit (IC) manufacturing system and IC manufacturing flow associated therewith, in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. The term spaced relationship is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such.

In some embodiments, a decoupling capacitance (decap) system is provided that includes a decoupling capacitance circuit and a bias circuit. The decoupling capacitance circuit is coupled between a first reference voltage rail (e.g., providing VDD) or a second reference voltage rail (e.g., providing VSS) and a first node. The voltage drop across the decoupling capacitor circuit is V dcp. In some embodiments, each of the decoupling capacitor circuit and the bias circuit comprises a thin oxide Metal Oxide Semiconductor Field Effect Transistor (MOSFET). In some embodiments, the MOSFETs in the decoupling capacitor circuit have a capacitor configuration. The biasing circuit is coupled between the first node and the respective second or first reference voltage rail. In some embodiments, the MOSFETs in the bias circuit have a diode configurationAnd (4) placing. According to other methods, although not in series with the bias circuit, a decoupling capacitor circuit corresponding to the above-described decoupling capacitor circuit is provided between VDD and VSS, so that the voltage drop over the decoupling capacitor circuit (V _ other) according to other methods is VDD. In accordance with at least some embodiments in which the decoupling capacitor circuit is coupled in series with the bias circuit, one or more thin dielectric (e.g., oxide), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) in the decoupling capacitor circuit have the following advantages: is less susceptible to thin gate oxide breakdown and/or current leakage than one or more MOSFETs in a decoupling capacitor circuit according to other methods because V _ dcp is less than VDD, whereas V _uaccording to other methods is less susceptible than one or more MOSFETs in a decoupling capacitor circuit_Others＝VDD。

Fig. 1A is a block diagram of a semiconductor device 100A according to some embodiments.

The semiconductor device 100A includes a functional cell region 102 and a decoupling system cell region 108 (see fig. 2A to 2B, fig. 3A to 3B, fig. 4A to 4B, and the like). The latter, i.e., the decoupling system cell region 108, provides the function of capacitive decoupling. The term "function" is applied to the cell region 102 to indicate that the function provided by the cell region 102 is different from the function provided by the decoupled system cell region 108.

Fig. 1B is a block diagram of a semiconductor device 100B according to some embodiments.

The semiconductor device 100B of fig. 1B is similar to the semiconductor device 100A of fig. 1A. However, the functional cell region 102 of the semiconductor 100B also includes the analog cell region 104.

Fig. 1C is a block diagram of a semiconductor device 100C according to some embodiments.

The semiconductor device 100C of fig. 1C is similar to the semiconductor device 100A of fig. 1A. However, the functional cell region 102 of the semiconductor 100C further includes a Radio Frequency (RF) cell region 104.

Fig. 2A is a block diagram of a decoupling system 200A according to some embodiments.

The decoupling system 200A includes an or function circuit 202 and a decoupling capacitance (decap) system 208A. The one or more functional circuits 202 are examples of the functional unit area 102 of fig. 1A. The decap system 208A is an example of the decoupling system cell region 108 of fig. 1A.

In fig. 2A, one or more functional circuits 202 and the decap system 208A are electrically coupled in parallel between rails 214 and 216. In the following, for the sake of brevity, the adverb "electricity" will be implied by the understanding that "coupled" (and similar variants) will be used instead of "electrically coupled".

The decoupling capacitance system 208A provides the function of capacitive decoupling. More specifically, decap system 208A facilitates decoupling one or more functional circuits 202 from variations of VDD. The term "functionality" applies to the one or more circuits 202 to indicate that the one or more circuits 202 provide respective functionality that is different from the functionality provided by the decoupling system 208A.

In fig. 2A, rail 214 provides a first reference voltage. Rail 216 provides a second reference voltage. In fig. 2A (and other figures discussed herein), the first and second reference voltages are VDD and VSS, respectively. In some embodiments, the first reference voltage and the second reference voltage are voltages different from the respective VDD and VSS.

decap system 208A includes a decoupling capacitance circuit 210 coupled in series with a bias circuit 212. Substantially all of the capacitive decoupling functionality of the decoupling capacitance system 208A is provided by the decoupling capacitance circuit 210. More specifically, the decoupling capacitance circuit 210 is coupled between an input of the decap system 208A and a node 218, which is internal to the decap system 208A. The bias circuit 212 is coupled between the node 218 and the output of the decoupling capacitance system 208A.

In some embodiments, the decap system 208A is described as a voltage divider in terms of voltage drop. The voltage drop between rails 214 and 216 is VDD. Thus, the voltage drop across the decoupling capacitor system 208A is VDD. The voltage drop across the decoupling capacitor circuit 210 is V dcp. The voltage drop across the bias circuit 210 is V bs. Thus, in some embodiments, the voltage drop across decap system 208A to VDD is represented by a first type,

VDD＝V_dcp+V_bs

rewriting the first equation yields a second equation,

V_dcp＝VDD-V_bs

in some embodiments, the adjective "bias" applied to circuit 212 refers to the effect of voltage drop V _ bs, as voltage drop V _ bs reduces (or biases) voltage drop V _ dcp, which would be equal to VDD if voltage drop V _ dcp were not used for bias circuit 212 coupled in series with decoupling capacitor circuit 210 between rails 214 and 216.

According to other methods, although not in series with the bias circuit, a decoupling capacitor circuit corresponding to the decoupling capacitor circuit 210 is provided between VDD and VSS, so that the decoupling capacitor circuit (V _) according to other methods_Others) The voltage drop over is VDD. According to at least some embodiments in which the decoupling capacitor circuit 210 is coupled in series with the bias circuit 212, one or more thin-oxide metal-oxide-semiconductor field-effect transistors (MOSFETs) in the decoupling capacitor circuit 210 (see fig. 2A, etc.) have the following advantages: is less susceptible to breakdown of a thin gate dielectric (e.g., oxide) and/or current leakage than one or more MOSFETs in a decoupling capacitor circuit according to other methods, since V _ dcp is less than VDD, whereas V _uaccording to other methods_Others＝VDD。

Fig. 2B is a block diagram of a decoupling system 200B according to some embodiments.

The system 200B of fig. 2B is similar to the system 200A of fig. 2A. However, the series arrangement of the decoupling capacitance circuit 210 and the bias circuit 212 in fig. 2B is different from fig. 2A. More specifically, in fig. 2B, the bias circuit 212 is coupled between the input of the decoupling capacitance system 208B and the node 218. Decoupling capacitance circuit 210 is coupled between node 218 and the output of decoupling capacitance system 208B.

Fig. 3A is a circuit diagram of a decoupling system 308A according to some embodiments. Fig. 3B is a block diagram of a decoupling system 308B according to some embodiments. Fig. 3C-3J are corresponding circuit diagrams according to some embodiments. Fig. 3K is a layout diagram 308K according to some embodiments.

Fig. 3A-3K follow a similar numbering scheme as fig. 2A-2B. Although corresponding, some components are different. To help identify components that correspond but still differ, the numbering convention uses sequence number 3 for fig. 3A-3K, while the numbering convention for fig. 2A-2B uses sequence number 2. For example, item 308A in fig. 3A-3K is a decoupling system, and corresponding item 208A in fig. 2A is a decoupling system. Wherein: similarity is reflected on common root _ 08A; the differences are reflected in the corresponding leading digits 3 in fig. 3A to 3K. For the sake of brevity, the discussion will focus more on the differences between fig. 3A-3K and fig. 2A-2B.

And each of fig. 2A-2B includes a bias circuit 212. The embodiment of fig. 3A includes a particular type of bias circuit 212, namely bias circuit 322. Thus, the self-biasing circuit 322 has at least the same advantages as the biasing circuit 212 described above. In addition, fig. 3A illustrates the decoupling capacitance circuit 210 in more detail than fig. 2A-2B.

In fig. 3A, substantially all of the capacitive decoupling functionality of the decoupling capacitance system 308A is provided by the decoupling capacitance circuit 210. Referring to fig. 3A, decoupling capacitance circuit 210 includes one or more parallel coupled capacitor configured MOSFETs N1(1) and N1 (2). Since N1(2) is optional, it is shown using a dashed line (dot). In some embodiments, decoupling capacitor circuit 210 includes N1(1), N1(2), and one or more parallel-coupled capacitor configured MOSFETs.

In some embodiments, the capacitor configuration MOSFET includes coupling the gate terminal to a first voltage, and each of the source and drain terminals to a second voltage different from the first voltage. As shown in fig. 3A, with respect to NFET N1(1), in a capacitor configuration, the gate terminal of N1(1) is coupled to supply line 214 and each of the source and drain terminals of N1(1) is coupled to node 218 in the capacitor, according to direction 320A.

The net capacitance of the parallel coupled capacitors is the sum of the individual capacitances. For embodiments in which decoupling capacitance circuit 210 includes only N1(1) and N1(2), assuming each of N1(1) and N1(2) has substantially the same capacitance C _ N1(x), the total capacitance of circuit 210 is 2 × C _ N1 (x).

The MOSFET includes a layer of dielectric material between the gate terminal and the channel region. In some embodiments, the dielectric material is an oxide. Hereinafter, the layer of dielectric material between the gate terminal and the channel region of the MOSFET is commonly referred to as the gate oxide of the MOSFET.

In some embodiments, each of N1(1) and N1(2) is a thin oxide MOSFET, as opposed to a thick oxide MOSFET. A MOSFET of the thin oxide type has a relatively thin gate oxide, a relatively high maximum operating frequency and a relatively low maximum operating voltage. A thick oxide type MOSFET has a relatively thick gate oxide, a relatively low maximum operating frequency, and a relatively high maximum operating voltage. In some embodiments, the thin oxide MOSFET has a gate oxide thickness equal to or less than about 0.2 nanometers (nm).

In some embodiments, the gate oxide comprises one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric material, such as hafnium oxide (HfO)₂)、TiO₂、HfZrO、Ta₂O₃、HfSiO₄、ZrO₂、ZrSiO₂Or a combination thereof. Alternatively, the high-k dielectric material comprises a metal oxide. Examples of metal oxides for high k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and/or mixtures thereof, and the like.

As shown in fig. 3A, each of N1(1) and N1(2) is an N-type mosfet (nfet). As also shown in fig. 3A, each of N1(1) and N1(2) is coupled between rail 214 and node 218 in direction 320A.

In some embodiments, each of NFETs N1(1) -N1(2) is arranged according to direction 320C of fig. 3C. In fig. 3C, with respect to NFET N1(1), the source and drain terminals of N1(1) are each coupled to rail 214 and the gate terminal of N1(1) is coupled to node 218, according to direction 320C.

In some embodiments, each of NFETs N1(1) and N1(2) is instead a corresponding P-type mosfet (pfet) P1(1) and P1(2) (not shown). In some embodiments, each of P1(1) and P2(2) has a direction 320D as shown in fig. 3D. In fig. 3D, with respect to PFET P1(1), the gate terminal of P1(1) is coupled to rail 214 and each of the source and drain terminals of P1(1) are coupled to node 218 according to direction 320D. Each PFET P1(1) -P1(2) is arranged according to direction 320E of FIG. 3E. In fig. 3E, with respect to PFET P1(1), according to direction 320E, each of the source and drain terminals of P1(1) is coupled to rail 214, and the gate terminal of P1(1) is coupled to node 218.

Returning to the discussion of fig. 3A, the self-biasing circuit 322 includes one or more diode-configured MOSFETs N2(1) and N2(2) coupled in series between the node 218 and the rail 216. In some embodiments, the diode configured NFET includes coupling each of the gate and drain terminals to a first voltage and coupling the source terminal to a second voltage different from the first voltage. In some embodiments, the diode-configured PFET includes coupling a source terminal to a first voltage and coupling each of a gate terminal and a drain terminal to a second voltage different from the first voltage.

In some embodiments, each of N2(1) and N2(2) is a MOSFET of the thin oxide type. Since N2(2) is optional, it is shown using a dashed line (dot). More specifically, N2(1) is coupled between node 218 and node 319(1) internal to self-bias circuit 322. Mosfet n2(2) is coupled between node 319(1) and rail 216. Since self-biasing circuit 322 includes only N2(1), N2(1) is coupled between rails 214 and 216, rather than between rail 214 and node 319 (1). In some embodiments, self-biasing circuit 322 includes N2(1), N2(2), and one or more diode-configured MOSFETs coupled in series.

In fig. 3A, each of N2(1) and N2(2) is an NFET. As also shown in fig. 3A, each of N2(1) and N2(2) are coupled according to direction 324A. In fig. 3A, with respect to NFET N2(1), each gate and drain terminal of diode configuration N2(1) is coupled to node 218, while the source terminal of N2(1) is coupled to node 319(1), according to direction 324A. In some embodiments, the adjective "self" applied to the bias circuit 322 refers to the effect of the diode configuration of each of N2(1) and N2(2), which causes each of N2(1) and N2(2) to bias itself accordingly. The voltage drop across bias circuit 322 is V _ bs, where V _ bs is the sum of the voltage drop across N2(1) and the voltage drop across N2 (2).

In some embodiments, each of NFETs N2(1) and N2(2) is instead a corresponding P-type mosfet (pfet) (not shown) P2(1) and P2 (2). In some embodiments, each of P2(1) and P2(2) has a direction 324F shown in fig. 3F. In fig. 3F, with respect to P2(1), the source terminal of P2(1) is coupled to node 218 according to direction 324F, and each of the gate and drain terminals of P2(1) is coupled to node 319 (1).

In some embodiments, each of NFETs N2(1) and N2(2) is instead a corresponding Bipolar Junction Transistor (BJT) BJT2(1) and BJT2(2) (not shown). In some embodiments, BJT2(1) and BJT2(2) each have direction 324G shown in fig. 3G. In fig. 3G, with respect to BJT2(1) (not shown), base and collector terminals of BJT2(1) are both coupled to node 218, and emitter terminal of BJT2(1) is coupled to node 319(1), according to direction 324G. In some embodiments, BJT2(1) and BJT2(2) each have direction 324H shown in fig. 3H. In fig. 3H, with respect to BJT2(1) (not shown), according to orientation 324H, the emitter terminal of BJT2(1) is coupled to node 218, and each of the base and collector terminals of BJT2(1) is coupled to node 319 (1).

In some embodiments, each of NFETs N2(1) and N2(2) is instead a corresponding diode D1 and D2 (not shown). In some embodiments, each diode has a direction 324I shown in fig. 3I. As shown in fig. 3I, with respect to D1 (not shown), the anode of D1 is coupled to node 218, and the cathode of D1 is coupled to node 319(1), according to direction 324I. In some embodiments, each of NFETs N2(1) and N2(2) is instead a corresponding passive resistor as in fig. 3J.

In some embodiments, decap system 308A is used in general low frequency applications. In some embodiments, the capacitance of the decoupling capacitor circuit 210 is described in terms of a quality factor Q. In general, Q represents the efficiency of a capacitor in terms of its energy loss rate. Generally, the higher the Q of a capacitor, the less losses associated with the capacitor. In some embodiments, Q is represented as Q1/(ω CR), where ω is the operating frequency, C is the capacitance of the capacitor, and R is the series resistance of the capacitor. Here, Q is inversely proportional to ω, so as ω increases, Q decreases. Thus, decap system 308A is used in general low frequency applications. For high frequency applications, please refer to fig. 4A-4B and fig. 5A-5B, etc.

The inclusion of a bias circuit 322 in series with the decoupling capacitance circuit 210 according to some embodiments results in a relatively larger footprint in the decap system 308A compared to other approaches that provide a decoupling capacitance circuit between VDD and VSS (although not in series with a bias circuit) in terms of consumed area (footprint). However, in general, then the instances of the capacitor configured MOSFETs (e.g., N1(1)) present in decoupling capacitance circuit 210 are substantially (or not substantially) more numerous than the instances of the diode configured MOSFETs (e.g., N2(1) or in self-biasing circuit 322 (e.g., FIGS. 3F-3J.) in some embodiments, only N2(1) is provided in self-biasing circuit 322 of decoupling capacitance system 308A, while in many cases the capacitor configured MOSFETs (e.g., N1(1)) are provided in decoupling capacitance circuit 210 of decoupling capacitance system 308A such that the ratio of the footprint of N2(1) (area _ N2(1)) to the total area of many instances of the capacitor configured MOSFETs (area _ N1(x)) is within the range: { (1: 10)²)}≤(area_N2(1)：area_N1(x))≤{≈(1∶10⁶)}. Thus, the increase in footprint due to the inclusion of the bias circuit 322 in the decoupling capacitance system 308A is insignificant. Furthermore, the increase in footprint due to the inclusion of bias circuit 322 in decap system 308A is substantially offset by the advantages of self-bias circuit 322. Depending on the diode-configured MOSFET (e.g., N2(1)) or similar example (e.g., FIGS. 3F-3J) in the self-biasing circuit 322, in some embodiments, the self-biasing circuit 322 consumes a current I _322 in the range (≈ 1nA) ≦ I _322 ≦ (≈ 10 μ A), which is insignificant compared to the total current consumption of a semiconductor device that includes one or more functional circuits 202 (see FIGS. 2A-2B) in addition to the self-biasing circuit 322. furthermore, the increase in current consumption due to the inclusion of the biasing circuit 322 in the decapacity system 308A is substantially offset by the advantages of the self-biasing circuit 322.

In some embodiments, for gate pitches less than (≈ 100nm) (see fig. 3K), the MOSFETs in the decoupling capacitor circuit are biased to the respective cut-off regions such that substantially no conduction occurs in the channel region. Thus, in some embodiments, | Vgs | < | Vgs |, where Vgs is the voltage between the gate and source terminals, and | Vgd | < | Vgs |, where Vgd is the voltage between the gate and drain terminals, and Vth is the threshold voltage.

With respect to FIG. 3B, the system 308B of FIG. 3B is similar to the system 308A of FIG. 3A. However, the series arrangement of the decoupling capacitance circuit 210 and the self-biasing circuit 322 in fig. 3B may be different from fig. 3A. More specifically, as shown in fig. 3B, a self-bias circuit 322 is coupled between the input of the decoupling capacitance system 308B and the node 218. The decoupling capacitance circuit 210 is coupled between the node 218 and the output of the decoupling capacitance system 308B.

With respect to fig. 3K, layout 308K represents a semiconductor device. More specifically, the layout 308K represents the decoupling system 308A of fig. 3A.

As such, each shape (also referred to as a pattern) in the layout 308K represents each structure in the semiconductor device represented by the layout 308K. To simplify the discussion, the elements in layout 308K are referred to as structures themselves rather than shapes themselves. For example, each element 330(1) -330(4) in layout 308K is a gate shape, which represents an example of a gate structure in a corresponding semiconductor device. In the following discussion, the shapes 330(1) -330(4) of the layout diagram 308K are referred to as corresponding gate structures 330(1) -330(4), rather than corresponding gate shapes 330(1) -330 (4). Also, for example, element 326 in layout 308K is a shape that represents an active region in a corresponding semiconductor device. In the discussion that follows, the elements 326 of layout 308K are referred to as active regions 326, rather than active region shapes 326.

Referring to fig. 3K, the layout 308K includes: active region 326 (as indicated); and to drain/source Metal (MD) contact structures 328(1) -328 (5); gate structures 330(1) -330(4) (as described above). Active region 326 has a long axis of symmetry extending in a first direction. In fig. 3K, the first direction is substantially parallel to the X-axis. In some embodiments, fig. 3K is configured for finFET technology such that, for example, the active regions 326 represent fins. In some embodiments, active region 326 is configured for nanowire transistor technology. In some embodiments, active region 326 is configured for nanosheet transistor technology. In some embodiments, active region 326 is configured for planar transistor technology.

With respect to the X-axis, the MD contact structures 3281(1) -328(5) and the gate structures 330(1) -330(4) are interspersed with and do not overlap. The long axis of symmetry of each of the MD contact structures 3281(1) -328(5) and gate structures 330(1) -330(4) extends in a second direction that is substantially perpendicular to the first direction. In fig. 3K, the second direction is substantially parallel to the Y-axis. In some embodiments, the first direction and the second direction are perpendicular directions other than respective directions of the X-axis and the Y-axis.

Each of the MD contact structures 3281(1) -328(5) and gate structures 330(1) -330(4) is over a respective portion of the active region 236. As shown in fig. 3K, and with respect to the X-axis: gate structure 330(1) between MD contact structures 328(1) and 328 (2); gate structure 330(2) between MD contact structures 328(2) and 328 (3); gate structure 330(3) between MD contact structures 328(3) and 328 (4); the gate structure 330(4) is between the MD contact structures 328(4) and 328 (5).

Layout 308K also includes through-gate via/md (vgd) structures 332(1) -332(9) and M0 sections 314K, 318K, 319(1) K, and 316K. VGD structures 332(1) -332(9) are over respective ones of the MD contact structures 328(1) -328(5) and the gate structures 330(1) -330 (4).

The M0 sections 314K, 318K, 319(1) K, and 316K are over respective portions of the MD contact structures 328(1) -328(5) and gate structures 330(1) -330 (4). Corresponding portions of M0 sections 314K, 318K, 319(1) K, and 316K are above VGD structures 332(1) -332 (9).

In fig. 3K, M0 sections 314K, 318K, 319(1) K, and 316K are in the first metallization layer (M _1st layer) and have a long axis of symmetry extending substantially along the first direction. The layout diagram 308K employs corresponding semiconductor process technology nodes that include various design rules for generating the layout diagram. Layout diagram 308K also assumes that the design rules follow a numbering convention in which the first metallization level (M _1st level) and the corresponding first interconnect structure level (V _1st level) (not shown) are referred to as M0 and V0, respectively. In some embodiments, the numbering convention assumes that the M _1st and V _1st levels are referred to as M1 and V1, respectively, and thus the segments 314K, 318K, 319(1) K, and 316K will be referred to as the M1 segments.

Segment 314K M0 corresponds to rail 214 in FIG. 3A, with segment 314K M0 providing the voltage VDD. The portion of the M0 section 318K covering VGD structures 332(7) and 332(8) corresponds to node 218 in fig. 3A. Section 319(1) K of M0 corresponds to node 319(1) in fig. 3A. The M0 segment 316K corresponds to the rail 216 in fig. 3A, so the M0 segment 316K provides the voltage VSS.

With respect to VGD structures 332(1) -332(9) in fig. 3K, more specifically, VGD structure 332(1) is located at the intersection of M0 section 314K and gate structure 330 (1). VGD structure 332(2) is located at the intersection of M0 section 314K and gate structure 330 (2). VGD structure 332(3) is located at the intersection of M0 section 318K and MD contact structure 328 (1). VGD structure 332(4) is located at the intersection of M0 section 318K and MD contact structure 328 (2). VGD structure 332(5) is located at the intersection of M0 section 318K and MD contact structure 328 (3). VGD structure 332(6) is located at the intersection of M0 section 318K and gate structure 328 (3). VGD structure 332(7) is located at the intersection of M0 section 319(1) K and MD contacting structure 328 (4). VGD structure 332(8) is located at the intersection of M0 section 319(1) K and gate structure 328 (4). VGD structure 332(8) is located at the intersection of M0 section 316K and MD contact structure 328 (5).

In fig. 3K, VGD structures 323(1), 323(3), and 323(4), MD contact structures 328(1) and 328(2), gate structure 330(1), and corresponding portion or active region 326 collectively represent N1(1) of fig. 3A. The VGD structures 323(2), 323(5) and 323(6), the MD contact structures 328(2) and 328(3), the gate structure 330(2), and the corresponding portion or active region 326 collectively represent N1(2) of fig. 3A. The VGD structures 323(5), 323(6), 323(7), the MD contact structures 328(3) and 328(4), the gate structure 330(3), and the corresponding portion or active region 326 collectively represent N2(1) of fig. 3A. The VGD structures 323(7), 323(8), 323(9), the MD contact structures 328(4) and 328(5), the gate structure 330(4), and the corresponding portion or active region 326 collectively represent N2(2) of fig. 3A.

Fig. 3K assumes that active region 326 is configured for NMOS technology. In some embodiments, active region 326 is configured for PMOS technology. In some embodiments where active region 326 is configured for PMOS technology: the M0 segment 314K corresponds to rail 216 in FIG. 3A, with the M0 segment 314K providing the voltage VSS. The M0 segment 316K corresponds to rail 214 in fig. 3A, so the M0 segment 316K provides the voltage VDD.

Fig. 4A is a circuit diagram of a decoupling system 408A according to some embodiments. Fig. 4B is a block diagram of a decoupling system 408B according to some embodiments. Fig. 4C-4G are corresponding circuit diagrams according to some embodiments.

Fig. 4A-4G follow a similar numbering scheme as fig. 3A-3K. Although corresponding, some components are different. To help identify components that correspond but still differ, the numbering convention uses sequence number 4 for fig. 4A-4G, while the numbering convention for fig. 3A-3K uses sequence number 3. For example, item 408A in fig. 4A may be a decoupled system and the corresponding item 308A in fig. 3A is a decoupled system, where the similarity is reflected on common root _ 08A; the differences are reflected in the corresponding leading digits 4 in fig. 4A and 3 in fig. 3A. For the sake of brevity, the discussion will focus more on the differences between fig. 4A-4G and fig. 3A-3K than on the similarities.

Each of fig. 3A-3B includes a self-biasing circuit 322. The embodiment of fig. 4A includes a boost bias circuit 434 that includes the self-bias circuit 322 of fig. 3A. Thus, boost bias circuit 434 has at least the same advantages as self-bias circuit 322 described above.

In fig. 4A, the decoupling capacitor circuit 210 is shown with MOSFETs having a direction 320A, which direction 320A is the same as the direction shown in fig. 3A. Referring to fig. 3A, in some embodiments, the MOSFETs in the decoupling capacitance circuit 210 have alternative orientations as shown in fig. 3C-3E.

In fig. 4A, the bias circuit 434 includes the self-bias circuit 322 of fig. 3A and a bias current generator 436, the bias current generator 436 providing a positive boost current that flows into the node 218 to increase the voltage drop across the boost bias circuit 434. The current I _434 flowing through the boost bias circuit 434 is equal to the current flowing through the decoupling capacitor circuit 210I _210 plus the boost current I _436, such that I _434 is I _210+ I _ 436. As a result, the total amount of current flowing from node 218 through boost bias circuit 436 to rail 216 in fig. 4A is greater than the total amount of current flowing from node 218 through self-bias circuit 322 to rail 216 in fig. 3A. For low frequency applications, the effect of the current increase through boost bias circuit 436 is that the voltage drop across boost bias circuit 436, V _ bs _436, is greater than the voltage drop across self-bias circuit 322 shown in fig. 3A, such that V _ bs _436> V _ bs _322 without having to increase the size of N2 (1).

Assuming that the difference between V _ bs _322 and V _ bs _436 is represented by Δ V, which is a positive voltage, for low frequency applications, the relationship between V _ bs _322 and V _ bs _436 is represented by a third equation,

V_bs_436＝V_bs_322+ΔV

suppose VDD is V408A in fig. 4A and V308A in fig. 3A, such that VDD is V408A V308A, and the second equation for VDD is rewritten and the fourth equation is substituted accordingly,

V_dcp_408A+V_bs_436＝V_dcp_308A+V_bs_322

substituting the third expression into the fourth expression to obtain a fifth expression,

V_dcp_408A＝V_dcp_308A-ΔV

according to the fifth expression, V _ dcp _408A < V _ dcp _ 308A. Comparing the protective effects of the boost bias circuit 434 in fig. 4A and the self-bias circuit 322 in fig. 3A, the one or more thin oxide MOSFETs in the decoupling capacitor circuit 210 of the decoupling system 408A are even less susceptible to breakdown of the thin gate oxide and/or current leakage than the one or more MOSFETs of the decoupling capacitor circuit 210 of the decoupling system 308A because V _ dcp _408A < V _ dcp _ 308A.

In some embodiments, decap system 408A is used for high frequency applications. In some embodiments, the high frequency is a frequency equal to or greater than about 1 GHz. In some embodiments, the low frequency is a frequency of less than about 1 GHz. Recall that, in general, Q represents the efficiency of a capacitor in terms of energy dissipation rate, and as the Q value of the capacitor increases, the losses associated with the capacitor decrease, and high frequency applications decrease the Q value, thereby increasing the losses associated with the capacitor. Thus, without the bias current generator 436, the high frequency would cause the voltage drop across the decoupling capacitance circuit 210 (V _ dcp _408A) in the decoupling capacitance system 408A to be greater than the voltage drop at the low frequency case, where the low frequency case corresponds to the case in fig. 3A and the corresponding voltage drop V _, across the decoupling capacitance circuit 210 in the decoupling capacitance system 308Adcp _ 308A. To counteract the increase in V _ dcp _408A due to high frequency, the voltage drop V _ bs _436 across the boosted bias circuit 436 is increased (boosted) due to the boost current provided by the bias current generator 436. As a result, V _ dcp _408A is lower than the voltage drop V _, across the decoupling capacitor circuit according to other methods_OthersWherein (again) other approaches provide a decoupling capacitor circuit corresponding to the decoupling capacitor circuit 210 between VDD and VSS, even though it is not in series with the biasing circuit. Thus, an advantage of the decap capacitor system 408A is that one or more thin oxide MOSFETs in the decap capacitor circuit 210 have the advantage of being less susceptible to breakdown of the thin gate oxide and/or current leakage than one or more MOSFETs in the decap capacitor circuit according to other methods, since V _ dcp _408A is less than VDD, whereas V _ is according to other methods_Others＝VDD。

With respect to FIG. 4B, the system 408B of FIG. 4B is similar to the system 408A of FIG. 4A. However, fig. 4B differs from fig. 4A in that the series arrangement of the decoupling capacitance circuit 210 and the boost bias circuit 434 in fig. 4B may differ from that in fig. 4A. More specifically, as shown in fig. 4B, a boost bias circuit 434 is coupled between the input of decoupling capacitance system 408B and node 218. And decoupling capacitance circuit 210 is coupled between node 218 and the output of decoupling capacitance system 408B.

An exemplary version of the bias current generator 436 is shown corresponding to the current sources 436C-436G of fig. 4C-4G, respectively, according to some embodiments.

In fig. 4C, current source 436C is NFE N10, where the source terminal of N10 represents the output of current source 436C. Thus, the source terminal of N10 is coupled to node 218 in fig. 4C.

In fig. 4D, current source 436C is a current mirror comprising NFETs N10, N12, and N14. The gate terminal of N10 is coupled to the voltage Vbias. Each of the source terminal of N10, the gate terminal of N12, and the drain terminal of N14 is coupled to node 438 (1). Each of the source terminal of N12, the gate terminal of N14, and the input of an additional current source 439(1) is coupled to node 438 (2). The source terminal of N14 represents the output of current source 436D, therefore the source terminal of N14 is coupled to node 218 in fig. 4D.

In fig. 4E, current source 436E is a current mirror comprising NFETs N10, N14, N16, and N18. Each of the gate terminal of N10, the gate terminal of N16, the source terminal of N16, and the drain terminal of N18 is coupled to node 438 (3). Each of the source terminal of N10 and the drain terminal of N14 is coupled to node 438 (1). Each of the gate terminal of N18, the source terminal of N18, the gate terminal of N14, and the input of an additional current source 439(2) is coupled to node 438 (4). The source terminal of N14 represents the output of current source 436E, therefore the source terminal of N14 is coupled to node 218 in fig. 4E.

In fig. 4F, current source 436F is a current mirror including NFETs N10, N14, N16, and N20. Each of the source terminal of N10 and the drain terminal of N14 is coupled to node 438 (1). Each of the source terminal of N16 and the drain terminal of N20 is coupled to node 438 (5). Each of the gate terminal of N10, the gate terminal of N16, the source terminal of N20, and the input of an additional current source 439(3) is coupled to node 438 (6). Each of the gate terminal of N20 and the gate terminal of N14 is coupled to the voltage Vbias. The source terminal of N14 represents the output of current source 436F, therefore the source terminal of N14 is coupled to node 218 in fig. 4F.

In fig. 4G, current source 436G is a current driver that includes NFET N10 and operational amplifier (op amp) 440. The non-inverting input of operational amplifier 440 is coupled to voltage Vbias. The non-inverting input is coupled to the source terminal of N14, where the source terminal of N14 represents the output of current source 436F. Thus, the source terminal of N14 is coupled to node 218 in fig. 4F.

Fig. 5A is a circuit diagram of a decoupling system 508A according to some embodiments. Fig. 5B is a block diagram of a decoupling system 508B according to some embodiments.

Fig. 5A-5B follow a similar numbering scheme as fig. 3A-3K. Although corresponding, some components are different. To help identify components that correspond but still differ, the numbering convention uses sequence number 5 for fig. 5A-5B, while the numbering convention for fig. 3A-3K uses sequence number 3. For example, item 508A in fig. 5A may be a decoupled system and the corresponding item 308A in fig. 3A is a decoupled system, where the similarity is reflected on common root _ 08A; the differences are reflected in the corresponding leading digits 5 in fig. 5A and 3 in fig. 3A. For the sake of brevity, the discussion will focus more on the differences between fig. 5A-5B and fig. 3A-3K than on the similarities.

However, each of fig. 3A-3B includes a self-biasing circuit 322. The circuit shown in fig. 5A includes a filter bias circuit 542A. Filter bias circuit 542A is a particular type of bias circuit 212 of fig. 2A, as is self-bias circuit 322 which is a particular type of bias circuit 212. Thus, the filter circuit 542A has at least the same advantages as the bias circuit 212 described above.

With respect to fig. 5A, the decoupling system 508A has a decoupling capacitor circuit 210 and a filter bias circuit in series, which is coupled between the rails 214 and 216. More specifically, decoupling capacitor circuit 210 is coupled between rail 214 and node 218. Filter bias circuit 542A is coupled between node 218 and rail 216.

In fig. 5A, the decoupling capacitor circuit 210 is shown with MOSFETs having a direction 320A, which direction 320A is the same as the direction shown in fig. 3A. Similar to fig. 3A, in some embodiments, the MOSFETs in the decoupling capacitor circuit 210 of the decoupling system 508A have alternative orientations as shown differently in fig. 3C-3E.

In fig. 5A, the filter bias circuit 534A includes: NFET N3; PFET P3; a high pass filter 544(1) and a high pass filter 544 (2). In fig. 5A, N3 and P3 are coupled in parallel between node 218 and rail 216.

High pass filter 544(1) of bias circuit 534A includes a capacitor Cx and a resistor Rx coupled in series between rail 214 and node 218. More specifically, capacitor Cx is coupled between rail 214 and node 546(1), and resistor Rx is coupled between node 546(1) and node 218. The gate terminal of N3 is coupled to node 546 (1). High pass filter 544(1) passes (though attenuates) the positive phase of the ripple exhibited by VDD on rail 214, thereby causing the magnitude of the resultant ripple on the gate terminal of N3 to be relatively reduced. The voltage drop between the gate and source terminals of N3 is shown in fig. 5A as V _ gs _ N3.

High pass filter 544(4) of bias circuit 534A includes a capacitor Cy and a resistor Ry coupled in series between rail 214 and rail 216. More specifically, capacitor Cy is coupled between rail 214 and node 546(2), and resistor Ry is coupled between node 546(2) and rail 216. The gate terminal of P3 is coupled to node 546 (2). High pass filter 544(2) passes (though attenuates) the negative phase of the ripple exhibited by VDD on rail 214, thereby causing a relative reduction in the amplitude of the resulting ripple at the gate terminal of P3. The voltage drop between the source terminal and the gate terminal of P3 is shown in fig. 5A as V _ gs _ P3.

In fig. 5A, resistors Rx and Ry may be implemented by active devices or passive resistors, respectively, providing resistance, e.g., NFETs, PFETs, MOSFET pass gates, etc. Also in fig. 5A, the capacitors Cx and Cy can accordingly be implemented by active devices providing capacitance, e.g., MOSFETs having a capacitor configuration such as the orientation in fig. 3A and 3C-3E.

In some embodiments, decap system 508A is used for high frequency applications. Recall that, in general, Q represents the efficiency of a capacitor in terms of energy loss rate, and as the Q value of the capacitor increases, the losses associated with the capacitor decrease, and high frequency applications decrease the Q value, thus increasing the losses associated with the capacitor. Thus, without high pass filters 544(1) and 544(2), the high frequency would cause the voltage drop V _ dcp _508A across decoupling capacitance circuit 210 in decoupling capacitance system 508A to be greater than at the low frequency case, which corresponds to the low frequency case in fig. 3A and to the corresponding voltage drop V _ dcp _308A across decoupling capacitance circuit 210 in decoupling capacitance system 308A. To counteract the increase in V _ dcp _508A due to the high frequency ripple VDD on rail 214, high pass filters 544(1) and 544(2) shunt high frequencies from shunt circuit 210 to corresponding nodes 546(1) and 546 (2). As a result, V _ dcp _508A does not rise due to the high frequency ripple VDD on rail 214, which would otherwise rise for high pass filters 544(1) and 544 (2). As a result, V _ dcp _508A is lower than the voltage drop V _, over the decoupling capacitor circuit according to other methods_OthersWherein (again) other approaches provide a decoupling capacitor circuit corresponding to the decoupling capacitor circuit 210 between VDD and VSS, even though it is not in series with the biasing circuit. Due to the fact thatIn this regard, the decap system 808A has the advantage that one or more thin oxide MOSFETs in the decap circuit 210 are less susceptible to thin gate oxide breakdown and/or current leakage than one or more MOSFETs in the decap circuit according to other methods, since V _ dcp _508A is less than VDD, whereas according to other methods, V __Others＝VDD。

With respect to fig. 5B, the decoupling system 508B is similar to the system 508A of fig. 5A. However, the series arrangement of the decoupling capacitance circuit 210 and the filter bias circuit 542B in fig. 5A may be different from the series arrangement of the decoupling capacitance circuit 210 and the filter bias circuit 542A in fig. 5B. More specifically, in fig. 5B, the filter bias circuit 542B is coupled between the input of the decoupling capacitance system 508B and the node 218. And decoupling capacitance circuit 210 is coupled between node 218 and the output of decoupling capacitance system 508B.

In fig. 5B, decap circuit 210 is shown with MOSFETs having direction 320C as in fig. 3C. In some embodiments, the MOSFETs in the decoupling capacitor circuit 210 of the decoupling system 508B have alternative orientations as shown differently in fig. 3A and 3D-3E.

In fig. 5B, the filter bias circuit 534A includes: n3; p3; a low pass filter 545(1) and a low pass filter 545 (2). In fig. 5A, N3 and P3 are coupled in parallel between rail 214 and node 218.

Low pass filter 545(1) includes a resistor Ry and a capacitor Cy coupled in series between trace 214 and trace 216. More specifically, resistor Ry is coupled between trace 214 and node 546(3), and capacitor Cy is coupled between trace 214 and node 546 (3). The gate terminal of N3 is coupled to node 546 (3). Low pass filter 545(1) passes (though attenuates) the positive phase of the ripple exhibited by VSS on rail 216, thereby causing the magnitude of the resultant ripple on the gate terminal of N3 to be relatively reduced. The voltage drop between the gate and source terminals of N3 is shown in fig. 5B as V _ gs _ N3.

Low pass filter 545(2) includes resistor Rx and capacitor Cx coupled in series between node 218 and rail 216. More specifically, resistor Rx is coupled between node 218 and node 546(4), and capacitor Cx is coupled between node 546(4) and rail 216. The gate terminal of P3 couples to node 546 (4). The low pass filter 545(2) passes (though attenuates) the negative phase of the ripple exhibited by VSS on rail 216, thereby causing the resulting ripple on the gate terminal of P3 to be relatively reduced in magnitude. The voltage drop between the source terminal and the gate terminal of P3 is shown in fig. 5B as V _ gs _ P3.

In some embodiments, decap system 508A is used for high frequency applications. Recall that, in general, Q represents the efficiency of a capacitor in terms of energy dissipation rate, and as the Q value of the capacitor increases, the losses associated with the capacitor decrease, and high frequency applications decrease the Q value, thereby increasing the losses associated with the capacitor. Filters 545(1) and 545(2) are low pass filters with respect to rail 214. With respect to rail 216, low pass filters 545(1) and 545(2) act as high pass filters. Thus, without the low pass filters 545(1) and 545(2) and their associated high pass filtering behavior on rail 216, the high frequency voltage on rail 216 would cause the voltage drop V _ dcp _508B across the decoupling capacitance circuit 210 in the decoupling capacitance system 508B to be greater than the low frequency case, which corresponds to the low frequency case in fig. 3A and to the corresponding voltage drop V _ dcp _308A across the decoupling capacitance circuit 210 in the decoupling capacitance system 308A. To counteract the increase in V _ dcp _508B due to high frequency ripple in VSS on rail 216, the high pass filtering behavior of rail 216 exhibited by low pass filters 545(1) and 545(2) bypasses high frequencies from decoupling circuit 210 corresponding to nodes 546(3) and 546 (4). As a result, V _ dcp _508B does not rise due to high frequency ripple on VSS at rail 216, and conversely falls, but does not for low pass filters 545(1) and 545 (2). As a result, according to other methods, V _ dcp _508B is lower than the voltage drop V _ over the decoupling capacitor circuit according to other methods_OthersWherein (again) other approaches provide a decoupling capacitor circuit corresponding to the decoupling capacitor circuit 210 between VDD and VSS, even though it is not in series with the biasing circuit. Thus, the decap system 808A has an advantage in that one or more thin oxide MOSFETs in the decap circuit 210 have the following insusceptibility to breakdown of the thin gate oxide and/or current leakage compared to one or more MOSFETs in decap circuits according to other methodsBecause V _ dcp _508B is less than VDD, according to other methods, V __Others＝VDD。

Fig. 6 is a flow diagram of a method 600 of decoupling voltage changes according to some embodiments.

In some embodiments, the method 600 represents the operation of the decap system of fig. 1A-1C, 2A-2B, 3A-3B, 4A-4B, 5A-5B.

The flow chart of fig. 6 includes block 602-618. At block 602, a decoupling capacitance circuit is coupled between the first reference voltage rail or the second reference voltage rail and a first node. Examples of the first and second reference voltage rails are corresponding rails 214 and 216 in fig. 2A-2B, 3A-3B, 4A-4B, 5A-5B. One example of a first node is node 218 in fig. 2A-2B, 3A-3B, 4A-4B, 5A-5B. An example of a decoupling capacitance circuit coupled between the first reference voltage rail and the first node is the arrangement of decoupling capacitance circuit 210 in fig. 2A, 3A, 4A, 5A. An example of a decoupling capacitance circuit coupled between the second reference voltage rail and the first node is the arrangement of decoupling capacitance circuit 210 in fig. 2B, 3B, 4B, 5B. From block 602, flow proceeds to block 604.

At block 604, a biasing circuit is coupled between the first node and the respective second or first reference voltage rails. Examples of bias circuits coupled between the first node and the second reference voltage rail in the case of a decoupling capacitance circuit coupled to the first reference voltage rail are arrangements of bias circuit 212 in fig. 2A, self-bias circuit 322 in fig. 3A, boost bias circuit 434 in fig. 4A, filter bias circuit 542A in fig. 5A, and so forth. Examples of biasing circuits coupled between the first node and the first reference voltage rail in the case where the decoupling capacitance circuit is coupled to the second reference voltage rail are arrangements of biasing circuit 212 in fig. 2B, self-biasing circuit 322 in fig. 3B, boost biasing circuit 434 in fig. 4B, filter biasing circuit 542A in fig. 5B, and so forth. From block 604, flow proceeds to block 606.

At block 606, the second voltage drop across the bias circuit is used to reduce a third voltage drop across the decap circuit relative to a first voltage drop between the first reference voltage rail and the second reference voltage rail, with the result that the voltage drop of the third voltage is less than the first voltage drop. Examples of the first, second, and third voltage drops are the respective VDD, V _ bs, and V _ dcp of each of fig. 2A-2B, 3A-3B, 4A-4B, and 5A-5B. Fig. 2A-2B, 3A-3B, 4A-4B, 5A-5B, etc. are examples of reducing the third voltage drop (V _ dcp) using the second voltage drop (V _ bs). Accordingly, as a result, in each of fig. 2A to 2B, 3A to 3B, 4A to 4B, and 5A to 5B, the third voltage drop (V _ dcp) is smaller than the first voltage drop (VDD). From block 606, flow proceeds to block 608.

At block 608, the MOSFET is configured as a capacitor (capacitor configuration) and included in a decoupling capacitor circuit. An example of a decoupling capacitor circuit including a capacitor configured MOSFET includes NFET N (1) in the decoupling capacitor circuit 210 in each of fig. 3A, 4A, 5A-5B. From block 608, flow proceeds to block 610.

Block 610 is a separate block, which may alternatively be referred to as an "or" block. At block 610, flow proceeds to block 612 or block 618.

If the flow proceeds to block 612, then (at block 612) the bias circuit is self-biased. An example of self-biasing the bias circuit is the operation of the self-bias circuit 322 of fig. 3A-3B. From block 612, flow proceeds to block 614.

At block 614, a bias current is coupled to a first node. An example of coupling a bias current generator to the first node is the boost bias circuit 434 in each of fig. 4A-4B. In the boost bias circuit 434 of fig. 4A, the current is amplified. In fig. 4A, a bias current generator 436 (although shown in fig. 4A and not shown in fig. 4B) is coupled to node 218, so bias current generator 436 is an example of a bias current generator. From block 614, flow proceeds to block 616.

At block 616, a bias current is provided to the first node using a bias current generator to enhance the voltage drop across the boost bias circuit. In operation, the bias current generator 436 provides a current to the node 218, and thus the bias current generator 436 is an example of using a bias current generator to provide a bias current to the first node.

If the flow proceeds to block 618, the bias circuit is filtered at block 618. An example of a filter bias circuit is the operation of filter bias circuit 542A of fig. 5A. Referring to fig. 5A, which includes high pass filters 544(1) -544(2), the operation of filter bias circuit 542B of fig. 5A may be performed in fig. 5A. As shown in fig. 5B, it includes low pass filters 545(1) -545(2), etc. More specifically, in operation, high pass filters 544(1) -544(2) of filter bias circuit 542A of fig. 5A filter ripples in VDD. In operation, the low pass filters 545(1) -545(2) of the filter bias circuit 542B of fig. 5B filter the ripple in VDD. Thus, in the corresponding operation, each of the high pass filters 544(1) - (544) and 2) and the low pass filters 545(1) - (545) (2) is an example of filtering the bias circuit.

Fig. 7 is a flow chart of a method 700 of fabricating a semiconductor device according to some embodiments.

According to some embodiments, the method 700 may be implemented, for example, using an EDA system 900 (fig. 9 discussed below) and an Integrated Circuit (IC), a manufacturing system 1000 (fig. 10 discussed below). Examples of semiconductor devices that may be fabricated according to method 700 include semiconductor devices 100A-100C corresponding to fig. 1A-1C, semiconductor devices corresponding to fig. 2A-2B, 3A-3B, 4A-4B, 5A-5B, and so forth.

In FIG. 7, method 700 includes blocks 702-804. At block 702, a layout (see fig. 8A-8B) is generated that includes, among other things, one or more of the layouts disclosed herein. According to some embodiments, block 702 may be implemented, for example, using EDA system 900 (fig. 9 discussed below). From block 702, flow proceeds to block 704.

At block 704, based on the layout, at least one of: (A) one or more photolithographic exposures; or (B) fabricating one or more semiconductor masks; or (C) fabricating components in a layer of the semiconductor device. See discussion of fig. 10 below.

Fig. 8A-8B are corresponding flow diagrams of methods of generating a layout diagram according to some embodiments.

More specifically, fig. 8A-8B illustrate additional blocks included in block 702 of fig. 7 in accordance with one or more embodiments. One example of a layout generated by the method represented by the flow diagrams of fig. 8A-8B is the layout 308K of fig. 3K.

Referring to fig. 8A-8B, the flow diagram includes blocks 802-826, and block 802-814 is shown in fig. 8A. Block 816-. At block 802 of fig. 8A, an Active Area (AA) shape extending along a first direction is generated. An example of the first direction is the X-axis in fig. 3K. One example of an AA shape is active region 326 shown in fig. 3K. Flow proceeds from block 802 to block 804.

At block 804, a gate shape is generated that extends in a second direction perpendicular to the first direction and is aligned over a first corresponding portion of the AA shape. An example of the second direction is the Y-axis in fig. 3K. An example of a gate shape is gate structures 330(1) -330(4) in fig. 3K. Gate structures 330(1) -330(4) are aligned on the first corresponding portion of active region 326 and do not overlap each other. From block 804, flow passes to block 806.

At block 806, a to-transistor contact component shape (MD shape) extending in a second direction, interposed between the respective gate shapes and aligned over a second respective portion of the AA shape is generated. An example of an MD shape is the MD contact structure 3281(1) -328(5) in fig. 3K. Wherein the MD contact structures 3281(1) -328(5) are non-overlapping with each other over the second corresponding portion of the active region 326 and interposing the gate structures 330(1) -330 (4). From block 806, flow proceeds to block 808.

At block 808, conductor shapes are generated that are designated for the first metallization layer (M _1st) (M _1st shapes), that are located over the respective gate shapes and MD shapes, and that extend in a first direction. Examples of M _1st shapes are M0 sections 314K, 318K, 319(1) K, and 316K in fig. 3K. In fig. 3K, M0 sections 314K, 318K, 319(1) K, and 316K are over respective portions of MD contact structures 328(1) -328(5) and gate structures 330(1) -330 (4). In fig. 3K, segment 314K of M0 corresponds to rail 214 in fig. 3A, segment 314K of M0 provides voltage VDD. In fig. 3K, segment 316K M0 corresponds to rail 216 in fig. 3A, segment 316K M0 providing voltage VSS. From block 808, flow proceeds to block 810.

At block 810, a through-gate via/MD (vgd) shape between a respective one of the M _1st shapes and a respective one of the gate shapes or MD shapes is generated. An example of a VGD shape is the VGD structure 332(1) -332(9) in fig. 3K. In fig. 3K, VGD structures 332(1) -332(9) are over respective ones of MD contact structures 328(1) -328(5) and gate structures 330(1) -330 (4). The corresponding portions of M0 sections 314K, 318K, 319(1) K, and 316K are above VGD structures 332(1) -332 (9). From block 810, flow proceeds to block 812.

At block 812, the first and second of the VGD shapes are aligned with the first of the M _1st shapes. An example of the first one of the M _1st shapes is the M0 shape 314K in fig. 3K. The first and second examples of VGD shapes that are aligned with the first of the M _1st shapes are the corresponding VGD structures 332(1) and 332(2) in fig. 3K. In fig. 3K, VGD structures 332(1) and 332(2) are aligned over M0 section 314K. From block 812, flow proceeds to block 814.

At block 814, the first and second VGD shapes are also correspondingly aligned with the first and second gate shapes. Examples of the first and second gate shapes are gate structures 330(1) and 330(2) of fig. 3K. Examples of first and second VGD shapes that are also aligned correspondingly to the first and second gate shapes are corresponding VGD structures 332(1) and 332(2) in fig. 3K. In fig. 3K, VGD structures 332(1) and 332(2) are also aligned with gate structures 330(1) and 330(2), respectively. From block 814 in FIG. 8A, flow proceeds to block 816 in FIG. 8B.

At block 816, the third, fourth, fifth, and sixth VGD shapes are aligned with the second of the M _1st shapes. An example of a second one of the M _1st shapes is the M0 shape 318K in fig. 3K. Examples of third, fourth, fifth, and sixth VGD shapes that align with the second of the M _1st shapes are the corresponding VGD structures 332(3), 332(4), 332(5), and 332(6) in fig. 3K. In fig. 3K, VGD structures 332(3), 332(4), 332(5), and 332(6) are aligned over M0 section 318K. From block 816, flow proceeds to block 818.

At block 818, the third, fourth, and fifth VGD shapes are also correspondingly aligned with the first, second, and third MD shapes. Examples of the first, second, and third shapes of MD shapes are MD structures 328(1), 328(2), and 328(3) in fig. 3K. Examples of third, fourth, and fifth VGD shapes that are also aligned corresponding to the first, second, and third MD shapes are the corresponding VGD structures 332(3), 332(4), and 332(5) in fig. 3K. In fig. 3K, VGD structures 332(3), 332(4), and 332(5) are also aligned with MD structures 328(1), 328(2), and 328(3), respectively. From block 818, flow proceeds to block 820.

At block 820, the sixth VGD shape is also aligned with a third one of the gate shapes. An example of a third one of the gate shapes is gate structure 330(3) in fig. 3K. An example of a sixth VGD shape that is also aligned with the third gate shape is VGD structure 332(6) in fig. 3K. In fig. 3K, VGD structure 332(6) is also aligned with gate structure 330 (3). From block 820, flow proceeds to block 822.

At block 822, the seventh and eighth of the VGD shapes are aligned with the third of the M _1st shapes. An example of a third one of the M _1st shapes is the M0 shape 319(1) K in fig. 3K. The seventh and eighth examples of VGD shapes that align with the third of the M _1st shapes are the corresponding VGD structures 332(7) and 332(8) in fig. 3K. In fig. 3K, VGD structures 332(7) and 332(8) are aligned over M0 section 319(1) K. From block 822, flow passes to block 824.

At block 824, the seventh and eighth VGD shapes are also correspondingly aligned with a fourth one of the MD shapes and a fourth one of the gate shapes. A fourth example of an MD shape and a fourth example of a grid shape is corresponding to MD structure 328(4) and grid structure 330(4) in fig. 3K. Examples of seventh and eighth VGD shapes that are also aligned corresponding to the fourth one of the MD shapes and the fourth one of the gate shapes are the corresponding VGD structures 332(7) and 332(8) in fig. 3K. In fig. 3K, VGD structures 332(7) and 332(8) are also aligned with MD structure 328(4) and gate structure 330(4), respectively. From block 824, flow proceeds to block 826.

In block 826, the ninth one of the VGD shapes is aligned with the fourth one of the M _1st shapes and the fifth one of the MD shapes. Examples of the fourth of M _1st shapes and the fifth of MD shapes are the corresponding M0 section 316K and MD structure 328(5) in fig. 3K. An example of a ninth of the VGD shape is the VGD structure 332(9) in fig. 3K. In fig. 3K, VGD structure 332() is aligned over each of M0 section 316K and MD structure 328 (5).

Fig. 9 is a block diagram of an Electronic Design Automation (EDA) system 900 according to some embodiments.

In some embodiments, the EDA system 900 includes an APR system. In accordance with one or more embodiments, the methods of designing a layout described herein may be implemented, for example, using EDA system 900 in accordance with some embodiments.

In some embodiments, EDA system 900 is a general purpose computing device that includes a hardware processor 902 and a non-transitory computer readable storage medium 904. Storage medium 904 is encoded with (i.e., stores) computer program code 906 (i.e., a set of executable instructions), among other things. The instructions 906 executed by the hardware processor 902 represent (at least in part) an EDA tool that implements some or all of the methods described herein (hereinafter, the referenced processes and/or methods) in accordance with one or more embodiments.

The processor 902 is electrically coupled to a computer-readable storage medium 904 by a bus 908. The processor 902 is also electrically coupled to an I/O interface 910 through the bus 908. A network interface 912 is also electrically coupled to the processor 902 through the bus 908. The network interface 912 connects to a network 914 so that the processor 902 and the computer-readable storage medium 904 can connect to external elements through the network 914. The processor 902 is configured to execute computer program code 906 encoded in a computer readable storage medium 904 to make the system 900 available to perform some or all of the noted processes and/or methods. In one or more embodiments, processor 902 is a Central Processing Unit (CPU), multiprocessor, distributed processing system, Application Specific Integrated Circuit (ASIC), and/or suitable processing unit.

In one or more embodiments, the computer-readable storage medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or apparatus or device). The computer-readable storage medium 904 includes, for example, a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a Random Access Memory (RAM), a read-only memory (ROM), a rigid magnetic disk and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium 904 includes a compact disk read only memory (CD-ROM), a compact disk read/write (CD-R/W), and/or a Digital Video Disk (DVD).

In one or more embodiments, the storage medium 904 stores computer program code 906, the computer program code 906 being configured to make the system 900 (where such execution represents, at least in part, an EDA tool) available to perform some or all of the noted processes and/or methods. In one or more embodiments, storage medium 904 also stores information that facilitates performing some or all of the described processes and/or methods. In one or more embodiments, storage medium 904 stores a library 907 of standard cells, including such standard cells as disclosed herein. In one or more embodiments, storage medium 904 stores one or more layout maps 909 corresponding to one or more layouts disclosed herein.

The EDA system 900 includes an I/O interface 910. The I/O interface 910 is coupled to external circuitry.

In one or more embodiments, the I/O interface 910 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and/or cursor direction keys for communicating information and commands to the processor 902.

The EDA system 900 also includes a network interface 912 coupled to the processor 902. The network interface 912 allows the system 900 to communicate with a network 914, to which one or more other computer systems are connected. Network interface 912 includes a wireless network interface such as bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the described processes and/or methods are implemented in two or more systems 900.

System 900 is configured to receive information via I/O interface 910. Information received via I/O interface 910 may include one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing. Information is transferred to processor 902 via bus 908. EDA system 900 is configured to receive information related to a UI through I/O interface 910. The information is stored in the computer-readable medium 942 as a User Interface (UI).

In some embodiments, portions of the processes and/or methodsEither partially or wholly implemented as a stand-alone software application for execution by a processor. In some embodiments, some or all of the processes and/or methods are implemented as software applications that are part of additional software applications. In some embodiments, some or all of the processes and/or methods are implemented as plug-ins to software applications. In some embodiments, at least one of the mentioned processes and/or methods is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the processes and/or methods are implemented as software applications used by the EDA system 900. In some embodiments, a method such asSuch as generating a layout including standard cells. Available from CADENCE DESIGN SYSTEMS, inc.

In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of the non-transitory computer-readable recording medium include, but are not limited to, external/removable and/or internal/built-in memories or memory units, for example, such as DVDs, magnetic disks such as hard disks, semiconductor memories such as ROMs, RAMs, memory cards, and the like.

Fig. 10 is a block diagram of an Integrated Circuit (IC) manufacturing system 1000 and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, at least one of (a) at least one or more semiconductor masks in a layer of a semiconductor integrated circuit or (B) at least one component is fabricated using the fabrication system 1000 based on a layout map.

Referring to FIG. 10, IC manufacturing system 1000 includes entities such as design chamber 1020, mask chamber 1030, and IC manufacturer/manufacturer ("fab") 1050 that interact during the design, development, and manufacturing cycle and/or with each other. A service or services associated with manufacturing the IC device 1060. The entities in system 1000 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and/or wireless communication channels. Each entity interacts with and provides services to and/or receives services from one or more other entities. In some embodiments, two or more of the design chamber 1020, mask chamber 1030, and IC fab 1050 are owned by a single larger company. In some embodiments, two or more of the design chamber 1020, the mask chamber 1030, and the IC fab 1050 coexist in a common facility and use common resources.

A design room (or design team) 1020 generates an IC design layout 1022. IC design layout 1022 includes various geometric patterns designed for IC device 1060. These geometric patterns correspond to the patterns of the metal, oxide or semiconductor layers, and the various layers that make up the IC device 1060 to be fabricated combine to form various IC components. For example, portions of IC design layout 1022 include various IC components formed in a semiconductor substrate (e.g., a silicon wafer), such as active regions, gate electrodes, sources and drains, metal lines or vias for inter-level interconnects, and openings for bond pads, and various layers of materials disposed on the semiconductor substrate. Design room 1020 performs the appropriate design process to form IC design layout 1022. The design process includes one or more of logical design, physical design, or placement and routing. The IC design layout 1022 is presented in one or more data files having geometry information. For example, the IC design layout 1022 may be expressed in a GDSII file format or a DFII file format.

Mask chamber 1030 includes data preparation 1032 and mask fabrication 1044. The mask chamber 1030 manufactures one or more masks 1045 using the IC design layout 1022 to manufacture the various layers of the IC device 1060 according to the IC design layout 1022. The mask chamber 1030 performs mask data preparation 1032 in which the IC design layout 1022 is translated into a representative data file ("RDF"). Mask data preparation 1032 provides the RDF to mask fabrication 1044. Mask fabrication 1044 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1045 or a semiconductor wafer 1053. Mask layout data preparation 1032 processes the design layout 1022 to meet the requirements of the particular features of the mask writer and/or the IC fab 1050. Referring to fig. 10, mask data preparation 1032 and mask fabrication 1044 are shown as separate elements. In some embodiments, mask data preparation 1032 and mask fabrication 1044 may be collectively referred to as mask data preparation.

In some embodiments, mask data preparation 1032 includes Optical Proximity Correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be due to diffraction, interference, other processing effects, and the like. The OPC adjusts the IC design layout 1022. In some embodiments, mask data preparation 1032 includes other Resolution Enhancement Techniques (RET), such as off-axis illumination, sub-resolution assist functionality, phase shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, Inverse Lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, mask data preparation 1032 includes a Mask Rules Checker (MRC) that checks IC design layouts 1022 that have been processed in OPC using a set of mask creation rules that contain constraints on certain geometries and/or connectivity to ensure sufficient margin to address variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1022 to compensate for limitations during mask manufacturing 1044, which may undo a portion of the modifications performed by OPC to satisfy mask creation rules.

In some embodiments, mask data preparation 1032 includes a photolithographic process check (LPC), which simulates the processing to be performed by the IC fab 1050 to fabricate the IC device 1060. The process parameters in the LPC simulation to simulate the process based on the IC design layout 1022 to create a simulated LPC simulation may include parameters related to various processes of the IC fabrication cycle, parameters related to the tool used to fabricate the IC, and/or other aspects of the fabrication process. LPC accounts for various factors such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and the like, or combinations thereof. In some embodiments, after the simulated fabrication devices are created by LPC, if the simulated devices are not close enough in shape to satisfy the design rules, OPC and/or MRC are repeated to further refine the IC design layout 1022.

It should be appreciated that the above description of mask data preparation 1032 has been simplified for clarity. In some embodiments, data preparation 1032 includes additional features such as Logic Operations (LOPs) to modify IC design layout 1022 according to manufacturing rules. In addition, the processes applied to the IC design layout 1022 during data preparation 1032 may be performed in a variety of different orders.

After mask data preparation 1032 and during mask fabrication 1044, a mask 1045 or a set of masks 1045 is fabricated based on the modified IC design layout 1022. In some embodiments, mask fabrication 1044 includes performing an e-beam on the IC design layout 1022 based on one or more lithographically exposed exposures. In some embodiments, an e-beam (e-beam) or multiple e-beam mechanism is used to form the pattern 1022 on the mask (photomask or reticle) 1045 based on the modified IC design layout. The mask 1045 may be formed in various techniques. In some embodiments, mask 1045 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an Ultraviolet (UV) beam, used to expose a layer of image sensitive material (e.g., photoresist) that has been coated on the wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask version of the mask 1045 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chrome) coated in opaque regions of the binary mask. In another example, the mask 1045 is formed using a phase-shift technique. In a Phase Shift Mask (PSM) version of the mask 1045, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask may be an attenuated PSM or an alternating PSM. The mask generated by the mask fabrication 1044 is used in a variety of processes. Such masks are used, for example, in ion implantation processes to form various doped regions in semiconductor wafer 1053, in etching processes to form various etched regions in semiconductor wafer 1053, and/or in other suitable processes.

The IC fab 1050 includes a fabrication tool 1052 configured to perform various fabrication operations on a semiconductor wafer 1053 to fabricate an IC device 1060 according to one or more masks (e.g., mask 1045). In various embodiments, the manufacturing tool 1052 includes a wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etch system, wafer cleaning system, or other manufacturing process capable of performing one or more of the one or more manufacturing tools or more suitable processes, as described herein.

The IC fab 1050 uses the mask 1045 created by the mask chamber 1030 to fabricate an IC device 1060. Thus, the IC fab 1050 uses the IC design layout 1022 at least indirectly to fabricate the IC device 1060. In some embodiments, a semiconductor wafer 1053. An IC device 1060 is formed by the IC fab 1050 using the mask 1045. In some embodiments, IC fabrication includes performing one or more lithographic exposures based, at least indirectly, on the IC design layout 1022. Semiconductor wafer 1053 comprises a silicon substrate or other suitable substrate having a layer of material formed thereon. Semiconductor wafer 1053 further includes one or more of various doped regions, dielectric features, multi-layer interconnects, etc. (formed in subsequent fabrication steps).

Details regarding Integrated Circuit (IC) manufacturing systems (e.g., the system 1000 of fig. 10) and IC manufacturing flows associated therewith are found, for example, in U.S. patent No. 9,256,709 issued on day 9/2/2016, pre-grant publication No. 20150278429 issued on day 1/10/2015, U.S. pre-grant publication No. 20140040838 issued on day 6/2/2014, and U.S. patent No. 7,260,442 issued on day 21/8/2007, the entire contents of which are incorporated herein by reference.

For example, in U.S. patent No. 9,256,709, an IC design layout is generated in a design house (or design team). The IC design layout includes various geometric patterns designed for the IC device. The geometric pattern corresponds to the pattern of the metal, oxide or semiconductor layers that make up the various components of the IC device to be fabricated. The various layers combine to form various IC functions. For example, portions of an IC design layout include various IC components such as active regions, gate electrodes, source and drain, metal lines or vias for inter-level interconnects, and openings for pads formed in a semiconductor that will be formed in a semiconductor substrate (e.g., a silicon wafer) and various layers of materials disposed on the semiconductor substrate. The design room performs the appropriate design process to form the IC design layout. The design process may include logical design, physical design, and/or place and route. The IC design layout is presented in one or more data files having geometric pattern information. The mask chamber uses the IC design layout to fabricate one or more masks used to fabricate the various layers of the IC device according to the IC design layout. The mask chamber performs mask data preparation in which the IC design layout is converted into a form that can be physically written by a mask writer, wherein the design layout prepared by the mask data preparation is modified to comply with a particular mask manufacturer and/or mask vendor and then manufactured. In the present embodiment, mask data preparation and mask fabrication are illustrated as separate elements, however, mask data preparation and mask fabrication may be collectively referred to as mask data preparation. Mask data preparation typically includes Optical Proximity Correction (OPC) which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other processing effects. Mask data preparation may include other Resolution Enhancement Techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shifting masks, other suitable techniques, or combinations thereof. Mask data preparation 132 also includes a Mask Rules Checker (MRC) that checks IC design layouts that have been processed in OPC using a set of mask creation rules that may contain some geometric and connectivity constraints to ensure adequate margins.

For example, in U.S. pre-grant publication No. 20150278429, in one embodiment, an IC manufacturing system may employ maskless lithography techniques, such as electron beam lithography or optical maskless lithography. In such systems, mask fabrication is bypassed and the IC design layout is modified by data preparation appropriate for wafer processing using specific maskless lithography techniques. The data preparation modifies the design layout suitable for subsequent operations in the IC manufacturing system. The results of the data preparation are represented in one or more data files, such as files in the GDSII file format or the DFII file format. The one or more data files include information of geometric patterns, such as polygons representing the primary design pattern and/or the secondary part. In this embodiment, the one or more data files further comprise auxiliary data resulting from the data preparation. The auxiliary data will be used to enhance various operations of the IC manufacturing system, such as mask manufacturing by a mask chamber and wafer exposure by an IC manufacturer.

For example, in pre-authorization publication No. 20140040838, an IC design layout is presented in one or more data files with geometry information. In one example, the IC design layout is represented in a "GDS" format as is known in the art. In alternative embodiments, the IC design layout may be transferred between components in an IC manufacturing system in alternative file formats, such as DFII, CIF, OASIS, or any other suitable file type. The IC design layout 300 includes various geometric patterns that represent components of an integrated circuit. For example, an IC design layout may include major IC components such as active regions, gate electrodes, source and drain, metal lines, interlayer interconnect vias, and openings for pads formed in a semiconductor that will be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The IC design layout may also include some ancillary components, such as those used for imaging effects, process enhancements, and/or mask identification information.

For example, in U.S. patent No. 7,260,442, a mask manufacturing system includes: a processing tool for processing the mask; a metrology tool coupled to the processing tool for inspecting the mask and obtaining an inspection result; a controller, coupled to the process tool and the metrology tool, to generate a manufacturing model of the process tool and calibrate the manufacturing model based on the tool data, the material data, and the inspection results of the mask. The mask manufacturing system may include at least one processing tool, a metrology tool, a controller, a database, and a manufacturing execution system. The processing tool may be an exposure tool, a developer, an etcher, or a photoresist stripper. The metrology tool performs a post-etch inspection or a post-strip inspection and obtains a post-etch inspection result or a post-strip inspection result, respectively. The controller is used for run-to-run control of the process tool, including feed-forward control and feed-back control. The controller receives post-etch or post-strip inspection results from the metrology tool and retrieves device and material data from the database. A controller coupled to the manufacturing execution system generates a manufacturing model of the processing tool and calibrates the manufacturing model based on the device data, the material data, and the inspection results of the mask. The controller also monitors the operating conditions of the processing tool and adjusts the manufacturing model of the processing tool during processing.

In one embodiment, a decoupling capacitance (decap) system includes: a decoupling capacitance circuit electrically coupled between the first or second reference voltage rail and a first node; and a bias circuit electrically coupled between the first node and the respective second or first reference voltage rails. In one embodiment, the decoupling capacitor circuit includes a capacitor configured Metal Oxide Semiconductor Field Effect Transistor (MOSFET) electrically coupled between the first node and the first or second reference voltage rails. In one embodiment, the gate oxide thickness of the thick oxide MOSFET is greater than about 0.2 nm; a gate oxide thickness of the thin oxide MOSFET is equal to or less than about 0.2 nm; and the MOSFET of the capacitor configuration is a thin oxide MOSFET.

In one embodiment, the capacitor configured MOSFET has a first configuration or a second configuration; the first configuration has: a gate terminal of a MOSFET of the capacitor configuration is electrically coupled to the first node; and each of the source and drain terminals of the capacitor configured MOSFET is electrically coupled to: (A) the first reference voltage rail; or (B) the second reference voltage rail; and the second configuration has: each of the source terminal and the drain terminal of the capacitor configured MOSFET is electrically coupled to the first node; and the gate terminal of the capacitor configured MOSFET is electrically coupled to: the first reference voltage rail; or the second reference voltage rail. In one embodiment, the bias circuit is a self-bias circuit. In one embodiment, the self-biasing circuit is a diode configured Metal Oxide Semiconductor Field Effect Transistor (MOSFET). In one embodiment, the diode configured MOSFET has a first configuration or a second configuration; the first configuration has: each of a gate terminal and a drain terminal of the diode configured MOSFET is electrically coupled to the first node; and a source terminal of the diode configured MOSFET is electrically coupled to the second reference voltage rail, respectively; and the second configuration has: the source terminal of the diode configured MOSFET is electrically coupled to the first node; and each of the gate terminal and the drain terminal of the diode configured MOSFET is electrically coupled to the second reference voltage rail. In one embodiment, the self-biasing circuit is a diode configured Bipolar Junction Transistor (BJT). In one embodiment, the diode configured BJT has a first configuration or a second configuration; the second configuration comprises a second configuration. The first configuration has: each of a base terminal and a collector terminal of a diode-configured BJT electrically connected to a first node; an emitter terminal of the diode-configured BJT is electrically coupled to the first reference voltage rail or the second reference voltage rail. The second configuration has: an emitter terminal of a diode configured BJT electrically coupled to a first node; each of the base terminal and the collector terminal of the diode-configured BJT is electrically coupled to either the first reference voltage rail or the second reference voltage rail. In one embodiment, the decoupling capacitor system further comprises: a bias current generator configured to provide a bias current to the first node, thereby increasing a voltage drop across the bias circuit. In one embodiment, the bias current generator is a current mirror or a current driver. In one embodiment, the bias circuit is a filter bias circuit. In one embodiment, a filter bias circuit includes: an N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a P-type MOSFET (PFET) electrically coupled in parallel between the first node and the respective second or first reference voltage rail; a first filter electrically coupled to a gate terminal of the N-type MOSFET (NFET); and a second filter electrically coupled to a gate terminal of the PFET; and when the first filter is configured as a high pass filter, the second filter has a configuration configured as a high pass filter; and when the first filter is configured as a low pass filter, the second filter has a configuration configured as a low pass filter. In one embodiment, the configuration of the first filter as a high pass filter comprises: a first capacitor is electrically coupled between the first reference voltage rail and a second node; and a first resistor electrically coupled between the second node and the first node; the configuration of the second filter as a high pass filter includes: a second capacitor is electrically coupled between the first reference voltage rail and a third node; and a second resistor is electrically coupled between the third node and the second reference voltage rail. To configure the first filter as a high pass filter, a gate terminal of the N-type MOSFET (NFET) is electrically coupled to the second node; and to configure the second filter as a high pass filter, a gate terminal of the PFET is electrically coupled to the third node. In one embodiment, the configuration of the first filter as a low pass filter comprises: the first resistor is electrically coupled between the first reference voltage rail and a second node; and a first capacitor electrically coupled between the second node and the second reference voltage rail; the configuration of the second filter as a low-pass filter includes: a second resistor is electrically coupled between the first node and a third node; and a second capacitor electrically coupled between the third node and the second reference voltage rail; a gate terminal of the N-type MOSFET (NFET) is electrically coupled to the second node; and a gate terminal of the PFET is electrically coupled to the third node.

In one embodiment, a decoupling capacitance (decap) system includes: a decoupling capacitance circuit electrically coupled between the first or second reference voltage rail and a first node; and a filter bias circuit electrically coupled between the first node and the respective second or first reference voltage rails, the filter bias circuit comprising: an N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a P-type MOSFET (PFET) electrically coupled in parallel between the first node and the respective second or first reference voltage rail; a first filter electrically coupled to a gate terminal of the N-type MOSFET (NFET); and a second filter electrically coupled to a gate terminal of the PFET; and when the first filter is configured as a high pass filter, the second filter has a configuration configured as a high pass filter; and when the first filter is configured as a low pass filter, the second filter is configured as a low pass filter.

In one embodiment, the configuration of the first filter as a high pass filter comprises: a first capacitor is electrically coupled between the first reference voltage rail and a second node; and a first resistor electrically coupled between the second node and the first node; the configuration of the second filter as a high pass filter includes: the second capacitor is electrically coupled between the first reference voltage rail and a third node; and the second resistor is electrically coupled between the third node and the second reference voltage rail. To configure the first filter as a high pass filter, electrically coupling a gate terminal of the N-type MOSFET (NFET) to the second node; and for the first configuration of the second filter, a gate terminal of the PFET is electrically coupled to the third node. In one embodiment, the configuring of the first filter as a low pass filter comprises: a first resistor is electrically coupled between the first reference voltage rail and a second node; and a first capacitor electrically coupled between the second node and the second reference voltage rail; the configuration of the second filter as a low-pass filter includes: a second resistor is electrically coupled between the first node and a third node; and a second capacitor electrically coupled between the third node and the second reference voltage rail; a gate terminal of the N-type MOSFET (NFET) is electrically coupled to the second node; and a gate terminal of the PFET is electrically coupled to the third node.

In one embodiment, a method of decoupling from a voltage change of a first voltage drop between a first reference voltage rail and a second reference voltage rail, the method comprising: a decoupling capacitance (decap) circuit electrically coupled between the first or second reference voltage rail and the first node; and electrically coupling a biasing circuit between the first node and the respective second or first reference voltage rails, resulting in a second voltage drop across the decoupling capacitor circuit that is less than the first voltage drop.

In one embodiment, the method further comprises: the capacitor is configured with a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) as a capacitor (the capacitor is configured as a MOSFET); and wherein electrically coupling a decoupling capacitance (decap) circuit between the first or second reference voltage rail and the first node comprises: capacitively coupling the first or second reference voltage rail to the first node by electrically coupling a capacitor configured MOSFET between the first or second reference voltage rail and the first node. In one embodiment, the thick oxide MOSFET has a relatively low maximum operating frequency and a relatively high maximum operating voltage. The thin oxide MOSFET has a relatively high maximum operating frequency and a relatively low maximum operating voltage; the capacitor constituting the MOSFET includes: a MOSFET of the thin oxide type is selected as the MOSFET. In one embodiment, a capacitor constituting a MOSFET includes: employing a first configuration for the MOSFET; and adopting a first configuration for the MOSFET. Or a MOSFET in a second configuration; in a first configuration, comprising: electrically coupling a gate terminal of the MOSFET to a first node; electrically coupling each of the source and drain terminals of the MOSFET to: (A) a first reference voltage rail; (B) a second reference voltage rail; or in a second configuration comprising: a source terminal and a drain terminal of the MOSFET electrically connected to the first node. A gate electrically coupled to the MOSFET, the gate electrically coupled to: a first reference voltage rail; or a second reference voltage rail. In one embodiment, the method further comprises: the bias circuit is self-biased. In one embodiment, self-biasing the bias circuit comprises: the diode is configured with a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) as a biasing circuit. In one embodiment, configuring the diode of the MOSFET includes: adopting a first configuration; and configuring the diode in a first configuration. Or in a second configuration; in a first configuration, comprising: electrically coupling each of a gate terminal and a drain terminal of the MOSFET to a first node; electrically coupling a source terminal of the MOSFET to the second reference voltage rail. In a first configuration, comprising: electrically coupling a source terminal of the MOSFET to a first node; and electrically coupling each gate and drain terminal of the MOSFET to a second reference voltage rail. In one embodiment, the diode is configured as a bipolar junction field effect transistor (BJT); and includes a diode configured BJT in a self-bias circuit. In one embodiment, a diode configuring a BJT includes: adopting a first configuration; or in a second configuration; in a first configuration, comprising: electrically coupling each of a base terminal and a collector terminal of the BJT to a first node; an emitter terminal of the BJT is electrically coupled to either a first reference voltage rail or a second reference voltage rail. In a second configuration, comprising: electrically coupling an emitter terminal of the BJT to a first node; each of the base terminal and the collector terminal of the electrically coupled BJT is electrically coupled to either the first reference voltage rail or the second reference voltage rail. In one embodiment, the method further comprises: electrically coupling a bias current generator to a first node; and electrically coupling a bias current generator to the first node. A bias current generator is used to provide a bias current to the first node. In one embodiment, the method further comprises: the bias current generator is configured as a current mirror or current driver. In one embodiment, the method further comprises: filtering the bias circuit. In one embodiment, filtering the bias circuit comprises: an N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a P-type MOSFET (pfet) are electrically coupled in parallel between a first node and a corresponding second or first node. A reference voltage rail; electrically coupling a first filter to a gate terminal of an N-type MOSFET (NFET); and electrically coupling a second filter to a gate terminal of the PFET; similarly, configuring the first and second filters includes: configuring each of the first filter and the second filter as a high pass filter; and configuring each of the first filter and the second filter as a high pass filter. Or each of the first filter and the second filter is configured as a low-pass filter. In one embodiment, configuring each of the first filter and the second filter as a high pass filter comprises: for the first filter, electrically coupling a first capacitor between a first reference voltage rail and a second node; and for the first filter, electrically coupling a first resistor between the second node and the first node; electrically coupling a gate terminal of an N-type MOSFET (NFET) to a second node; for the second filter, a second capacitor is electrically coupled between the first reference voltage rail and a third node. For the second filter, a second resistor is electrically coupled between the third node and a second reference voltage rail. And electrically coupling a gate terminal of the PFET to the third node. In one embodiment, configuring each of the first filter and the second filter as a low pass filter comprises: for the first filter, electrically coupling a first resistor between a first reference voltage rail and a second node; and for the first filter, electrically coupling a first capacitor between the second node and a second reference voltage rail. Electrically coupling a gate terminal of an N-type MOSFET (NFET) to a second node; for the second filter, a second resistor is electrically coupled between the first node and a third node. For the second filter, a second capacitor is electrically coupled between the third node and a second reference voltage rail. And electrically coupling a gate terminal of the PFET to the third node.

In one embodiment, a method (for manufacturing a semiconductor device including a decoupling capacitance (decoupling capacitance) system, a corresponding layout diagram of which is stored on a non-transitory computer-readable medium) includes: generating a layout, comprising: generating an Active Area (AA) shape extending along a first direction; generating a gate shape extending along a second direction perpendicular to the first direction and aligned over a corresponding first portion of the AA shape; creating contact transistor component shapes (MD shapes) extending in a second direction, interspersed between corresponding gate shapes, and aligned over a second corresponding portion of the AA shapes; generating conductor shapes that are designated for the first metallization layer (M _1st shape) and extend in a first direction on the respective gate shape and MD shape corresponding to the gate shape and MD shape; and generating via-to-gate/MD (VGD) shapes between corresponding ones of the M _1st shapes and corresponding ones of the plurality of gate shapes or MD shapes; aligning the first and second VGD shapes with a first one of the M _1st shapes, designating the first M _1st shape as a first reference voltage; correspondingly aligning the first and second VGD shapes with the first and second gate shapes as well; correspondingly aligning the third, fourth, fifth and sixth of the VGD shapes with a second of the M _1st shapes; correspondingly aligning the third, fourth and fifth VGD shapes with the first, second and third MD shapes as well; aligning the sixth VGD shape with the third gate shape as well; aligning the seventh and eighth VGD shapes with a third of the M _1 shapes; correspondingly aligning the seventh and eighth VGD shapes with a fourth one of the MD shapes and a fourth one of the gate shapes as well; the ninth VGD shape is aligned with the fourth of the M _1 shapes and the fifth of the MD shapes. In one embodiment, the method further comprises, based on the map, at least one of: (A) carrying out one or more times of photoetching exposure; and (B) fabricating one or more semiconductor masks; or (C) fabricating at least one component in a layer of the semiconductor integrated circuit.

In one embodiment, a system (for generating a map, the map stored on a non-transitory computer-readable medium) includes at least one processor and at least one memory including computer program code for one or more programs; wherein the at least one memory, the computer program code, and the at least one processor are configured to cause the system to perform a method of generating a map, such as any of the methods of generating a map disclosed herein. In one embodiment, the system further comprises: at least one of: a first mask facility configured to manufacture one or more semiconductor masks based on the layout; and or a second mask apparatus configured to perform one or more lithographic exposures based on the layout; or a manufacturing facility configured to manufacture at least one component in a layer of the semiconductor device based on the layout.

In one embodiment, a non-transitory computer-readable medium includes computer-executable instructions for performing a method of generating a map, such as any of the methods of generating a map disclosed herein.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.