阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 黄娟娟 白杰 于 2021-07-05 设计创作，主要内容包括：本发明涉及半导体制造技术领域,尤其涉及一种半导体结构及其形成方法。所述半导体结构的形成方法包括如下步骤：提供衬底,所述衬底包括用于形成PMOS晶体管的第一区域和用于形成NMOS晶体管的第二区域；形成沟道层于所述衬底的所述第一区域表面；调整所述沟道层的氧化速率,以降低所述沟道层的氧化速率与所述衬底的氧化速率之间的差异；氧化所述衬底的所述第二区域表面和所述沟道层,形成覆盖于所述沟道层表面的第一过渡氧化层和覆盖于所述衬底的所述第二区域表面的第二过渡氧化层。本发明降低所述沟道层与所述衬底之间氧化速率的差异,使得覆盖于所述沟道层上的第一过渡氧化层和覆盖于所述衬底的所述第二区域表面的第二过渡氧化层保持一致的厚度。(The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same. The forming method of the semiconductor structure comprises the following steps: providing a substrate, wherein the substrate comprises a first region for forming a PMOS transistor and a second region for forming an NMOS transistor; forming a channel layer on the surface of the first region of the substrate; adjusting an oxidation rate of the channel layer to reduce a difference between the oxidation rate of the channel layer and the oxidation rate of the substrate; and oxidizing the second area surface of the substrate and the channel layer to form a first transition oxide layer covering the surface of the channel layer and a second transition oxide layer covering the surface of the second area of the substrate. According to the invention, the difference of the oxidation rates between the channel layer and the substrate is reduced, so that the first transition oxide layer covering the channel layer and the second transition oxide layer covering the surface of the second region of the substrate keep consistent thickness.)

1. A method for forming a semiconductor structure, comprising the steps of:

providing a substrate, wherein the substrate comprises a first region for forming a PMOS transistor and a second region for forming an NMOS transistor;

forming a channel layer on the surface of the first region of the substrate;

adjusting an oxidation rate of the channel layer to reduce a difference between the oxidation rate of the channel layer and the oxidation rate of the substrate;

and oxidizing the second area surface of the substrate and the channel layer to form a first transition oxide layer covering the surface of the channel layer and a second transition oxide layer covering the surface of the second area of the substrate.

2. The method of claim 1, wherein forming a channel layer on the surface of the first region of the substrate further comprises:

and forming a protective layer covering the surface of the second area of the substrate.

3. The method for forming a semiconductor structure according to claim 2, wherein the step of forming a protective layer covering the surface of the second region of the substrate comprises:

forming the protective layer overlying the substrate;

and removing the protective layer covering the surface of the first area of the substrate.

4. The method of claim 2, wherein the substrate is formed of Si and the channel layer is formed of SiGe.

5. The method for forming a semiconductor structure according to claim 4, wherein the step of adjusting the oxidation rate of the channel layer comprises:

and carrying out nitridation treatment on the channel layer to reduce the oxidation rate of the channel layer.

6. The method for forming a semiconductor structure according to claim 5, wherein the step of performing nitridation on the channel layer comprises:

and carrying out nitridation treatment on the channel layer by adopting a remote plasma nitridation process.

7. The method of forming a semiconductor structure according to claim 2, further comprising, before oxidizing the second region surface of the substrate and the channel layer, the steps of:

and removing the protective layer.

8. The method of claim 1, wherein the step of oxidizing the surface of the second region of the substrate and the channel layer comprises:

and oxidizing the surface of the second region of the substrate and the channel layer by adopting an in-situ water vapor growth process.

9. The method of claim 1, wherein the PMOS transistor and the NMOS transistor are both power transistors.

10. The method of claim 1, wherein after forming a first transitional oxide layer overlying the surface of the channel layer and a second transitional oxide layer overlying the surface of the second region of the substrate, further comprising:

and forming a first gate dielectric layer on the surface of the first transition oxidation layer and simultaneously forming a second gate dielectric layer on the surface of the second transition oxidation layer.

11. A semiconductor structure, comprising:

a substrate including a first region for forming a PMOS transistor and a second region for forming an NMOS transistor;

the channel layer is positioned on the surface of the first area of the substrate, and the oxidation rate of the channel layer is the same as that of the substrate;

the first transition oxide layer is positioned on the surface of the channel layer;

and the second transition oxide layer is positioned on the surface of the second area of the substrate.

12. The semiconductor structure of claim 11, wherein the material of the channel layer comprises SiGe and a dopant element for reducing an oxidation rate of SiGe.

13. The semiconductor structure of claim 12, wherein the dopant element is nitrogen.

14. The semiconductor structure of claim 11, further comprising:

the first gate dielectric layer covers the surface of the first transition oxidation layer;

and the second gate dielectric layer is covered on the surface of the second transition oxidation layer.

15. The semiconductor structure of claim 11, wherein the PMOS transistor and the NMOS transistor are both power transistors.

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.

Background

Dynamic Random Access Memory (DRAM) is a commonly used semiconductor structure in electronic devices such as computers, and is composed of a plurality of Memory cells, each of which typically includes a transistor and a capacitor. The transistor has a gate electrically connected to a word line, a source electrically connected to a bit line, and a drain electrically connected to the capacitor, wherein a word line voltage on the word line can control the transistor to be turned on and off, so that data information stored in the capacitor can be read or written into the capacitor through the bit line.

In a semiconductor structure such as a DRAM, a PMOS transistor and an NMOS transistor are provided. Due to the surface structure and process limitations of the PMOS transistor and the NMOS transistor, there is a difference in thickness between the gate dielectric layers in the PMOS transistor and the NMOS transistor that are formed simultaneously, thereby affecting the electrical performance of the DRAM. With the further scaling of DRAM dimensions, the slight difference in gate dielectric layer thickness between PMOS and NMOS transistors can have an order of magnitude effect on the electrical performance of semiconductor structures such as DRAM.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which are used for solving the problem of the thickness difference of gate dielectric layers of a PMOS (P-channel metal oxide semiconductor) transistor and an NMOS (N-channel metal oxide semiconductor) transistor in the conventional semiconductor structure so as to improve the electrical property of the semiconductor structure.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising the steps of:

providing a substrate, wherein the substrate comprises a first region for forming a PMOS transistor and a second region for forming an NMOS transistor;

forming a channel layer on the surface of the first region of the substrate;

adjusting an oxidation rate of the channel layer to reduce a difference between the oxidation rate of the channel layer and the oxidation rate of the substrate;

and oxidizing the second area surface of the substrate and the channel layer to form a first transition oxide layer covering the surface of the channel layer and a second transition oxide layer covering the second area surface of the substrate.

Optionally, before forming the channel layer on the surface of the first region of the substrate, the method further includes the following steps:

and forming a protective layer covering the surface of the second area of the substrate.

Optionally, the specific step of forming a protective layer covering the surface of the second region of the substrate includes:

forming the protective layer overlying the substrate;

and removing the protective layer covering the surface of the first area of the substrate.

Optionally, the substrate is made of Si, and the channel layer is made of SiGe.

Optionally, the specific step of adjusting the oxidation rate of the channel layer includes:

and carrying out nitridation treatment on the channel layer to reduce the oxidation rate of the channel layer.

Optionally, the specific step of performing nitridation on the channel layer includes:

and carrying out nitridation treatment on the channel layer by adopting a remote plasma nitridation process.

Optionally, before oxidizing the surface of the second region of the substrate and the channel layer, the method further includes the following steps:

and removing the protective layer.

Optionally, the specific step of oxidizing the surface of the second region of the substrate and the channel layer includes:

and oxidizing the surface of the second region of the substrate and the channel layer by adopting an in-situ water vapor growth process.

Optionally, the PMOS transistor and the NMOS transistor are both power transistors.

Optionally, after forming a first transition oxide layer covering the surface of the channel layer and a second transition oxide layer covering the surface of the second region of the substrate, the method further includes the following steps:

and forming a first gate dielectric layer on the surface of the first transition oxidation layer and simultaneously forming a second gate dielectric layer on the surface of the second transition oxidation layer.

In order to solve the above problem, the present invention also provides a semiconductor structure comprising:

a substrate including a first region for forming a PMOS transistor and a second region for forming an NMOS transistor;

the channel layer is positioned on the surface of the first area of the substrate, and the oxidation rate of the channel layer is the same as that of the substrate;

the first transition oxide layer is positioned on the surface of the channel layer;

and the second transition oxide layer is positioned on the surface of the second area of the substrate.

Optionally, the material of the channel layer includes SiGe and a doping element, and the doping element is used to reduce an oxidation rate of the SiGe.

Optionally, the doping element is a nitrogen element.

Optionally, the method further includes:

the first gate dielectric layer covers the surface of the first transition oxidation layer;

and the second gate dielectric layer is covered on the surface of the second transition oxidation layer.

Optionally, the PMOS transistor and the NMOS transistor are both power transistors.

According to the semiconductor structure and the forming method thereof provided by the invention, the difference of the oxidation rates between the channel layer and the substrate is reduced by adjusting the oxidation rate of the channel layer, so that a first transition oxide layer covering the channel layer and a second transition oxide layer covering the surface of the second region of the substrate can be formed simultaneously, the first transition oxide layer and the second transition oxide layer can be adjusted to keep consistent thickness, and the electrical property of the semiconductor structure is effectively improved.

Drawings

FIG. 1 is a flow chart of a method of forming a semiconductor structure in accordance with an embodiment of the present invention;

FIGS. 2A-2G are schematic cross-sectional views of the principal processes of an embodiment of the present invention in forming a semiconductor structure;

fig. 3 is a schematic diagram of a semiconductor structure in accordance with an embodiment of the present invention.

Detailed Description

The following detailed description of embodiments of the semiconductor structure and the method for forming the same according to the present invention will be made with reference to the accompanying drawings.

The specific embodiment provides a method for forming a semiconductor structure, in which a channel layer is formed in a surface region of a transistor, and the difference between the oxidation rates of the channel layer and a substrate is reduced by adjusting the oxidation rate of the channel layer, so that a first transition oxide layer covering the channel layer and a second transition oxide layer covering a second region surface of the substrate can be formed simultaneously, and the first transition oxide layer and the second transition oxide layer can be adjusted to keep consistent thicknesses. The first transition oxide layer is used as the transition between a first gate dielectric layer formed subsequently and the channel layer, and the second transition oxide layer is used as the transition between a second gate dielectric layer formed subsequently and the second region of the substrate. The forming method can be suitable for the manufacturing process of transistors of various semiconductor devices, such as the manufacturing process of power transistors, the power transistor structure obtained by the forming method effectively ensures the thickness of a gate dielectric layer, inhibits the tunneling leakage current of a grid electrode, and regulates the threshold voltage of a PMOS power transistor region through the channel layer, the first transition oxide layer and the first gate dielectric layer so as to improve the electrical property of the semiconductor structure, such as the leakage current.

Fig. 1 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention, and fig. 2A-2G are schematic cross-sectional views of main processes in forming a semiconductor structure according to an embodiment of the present invention. As shown in fig. 1 and fig. 2A to fig. 2G, the method for forming a semiconductor structure according to this embodiment includes the following steps:

step S11, providing a substrate 20, wherein the substrate 20 includes a first region 201 for forming a PMOS transistor and a second region 202 for forming an NMOS transistor, as shown in fig. 2A.

Specifically, the substrate 20 may be, but is not limited to, a silicon substrate, and the substrate 20 is exemplified as the silicon substrate in the present embodiment. In other examples, the substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 20 includes a first region 201 doped with N-type ions, and the first region 201 is used for forming a PMOS transistor. The substrate 20 further includes a second region 202 doped with P-type ions, and the second region 202 is used for forming an NMOS transistor. The first region 201 and the second region 202 are electrically isolated by an isolation structure 21. The material of the isolation structure 201 may be, but is not limited to, an oxide material, such as silicon dioxide.

Optionally, the PMOS transistor and the NMOS transistor are both power transistors.

Specifically, the PMOS power transistor and the NMOS power transistor are used to adjust parameters such as voltage and leakage current of the semiconductor structure, so that when the PMOS power transistor and the NMOS power transistor are formed, the semiconductor structure having the PMOS power transistor and the NMOS power transistor is greatly improved in terms of convenience of threshold voltage adjustment operation, leakage current, and the like by adjusting the oxidation rate of the channel layer.

In step S12, a channel layer 24 is formed on the surface of the first region 201 of the substrate 20, as shown in fig. 2C.

Optionally, before forming the channel layer 24 on the surface of the first region 201 of the substrate 20, the method further includes the following steps:

a protective layer 22 is formed covering the surface of the second region 202 of the substrate 20, as shown in fig. 2C.

Optionally, the specific step of forming the protective layer 22 covering the surface of the second region 202 of the substrate 20 includes:

forming the protective layer 22 covering the substrate 20;

removing the protection layer 22 covering the surface of the first region 201 of the substrate 20.

Optionally, the specific step of forming the protective layer 22 covering the substrate 20 includes:

and forming the protective layer 22 on the surface of the substrate 20 by using an in-situ water vapor growth process.

Specifically, after the substrate 20 having the first region 201 and the second region 202 is cleaned, the surface of the substrate 20 is oxidized by an in-situ vapor growth (ISSG) process to form the protection layer 22 covering the first region 201 and the second region 202. Taking the substrate 20 as a silicon substrate as an example, the material of the protective layer 22 formed by the in-situ water vapor growth process is silicon dioxide. Then, a first photoresist layer 23 covering the surface of the substrate 20 is formed, and the first photoresist layer 23 above the first region 201 is removed through an exposure and development process, so that the remaining first photoresist layer 23 only covers the protection layer 22 on the second region 202, and the protection layer 22 on the first region 201 is exposed, as shown in fig. 2A. Then, the protective layer 22 above the first region 201 is removed by an etching process, and after the remaining first photoresist layer 23 is removed, the structure shown in fig. 2B is obtained. The protective layer 22 located above the second region 202 is used to avoid the situation that the channel layer 24 is also formed on the second region when the channel layer 24 is subsequently grown in the first region, and further, damage to the second region 202 caused by a subsequent process can be avoided.

Optionally, the thickness of the protective layer 22 is 3nm to 10 nm. For example, the protective layer 22 may be 5nm thick.

Optionally, the specific step of forming the channel layer 24 on the surface of the first region 201 of the substrate 20 includes:

an epitaxial growth process is used to form a channel layer 24 on the surface of the first region 201 of the substrate 20, as shown in fig. 2C.

The channel layer 24 is formed by an epitaxial growth process in the present embodiment, and those skilled in the art may also form the channel layer 24 by other processes according to actual needs. The channel layer 24 is configured to reduce an interface effect between the surface of the first region 201 of the substrate 20 and a subsequently formed first transition oxide layer, so as to simplify the operation of adjusting the threshold voltage of the PMOS transistor, for example, a PMOS power transistor, and when it is required to be noted that the channel layer 24 in the present invention is only located in the first region where the PMOS transistor is located, and is not located in the second region where the NMOS transistor is located, so that the NMOS transistor is not affected, and only the threshold voltage of the PMOS transistor is adjusted, and further, the channel layer is located in the PMOS power transistor in the PMOS transistor, so that the channel layer material is selectively grown in the PMOS power transistor position as a channel, and the threshold voltage of the PMOS is adjusted.

Optionally, the substrate 20 is made of Si, the channel layer 24 may be made of SiGe, and carriers in the SiGe layer have a higher electron mobility, so that the threshold voltage of a PMOS transistor, such as a PMOS power transistor, can be well adjusted.

Step S13, adjusting the oxidation rate of the channel layer 24 to reduce the difference between the oxidation rate 24 of the channel layer 24 and the oxidation rate of the substrate 20.

Since the material of the substrate 20 is different from that of the channel layer 24, there is a difference between the oxidation rate of the substrate 20 and the oxidation rate of the channel layer 24 even under the same oxidation condition. For this reason, the present embodiment adjusts the oxidation rate of the channel layer 24 so that the difference in oxidation rate between the channel layer 24 and the substrate 20 is reduced, for example, so that the oxidation rate of the adjusted channel layer 24 and the substrate 20 are equal. The specific method for adjusting the oxidation rate of the channel layer 24 may be selected by those skilled in the art according to actual needs, such as ion implantation, and the like, and the present embodiment is not limited thereto, as long as the difference between the oxidation rates of the channel layer 24 and the substrate 20 can be reduced.

Optionally, the specific step of adjusting the oxidation rate of the channel layer 24 includes:

the channel layer 24 is nitrided to reduce the oxidation rate of the channel layer 24, as shown in fig. 2D.

Hereinafter, the material of the substrate 20 is Si, and the material of the channel layer 24 is SiGe. Since the oxidation rate of Ge is greater than that of Si, the oxidation rate of the channel layer 24 is higher than that of the substrate 20 before modification. In the present embodiment, the channel layer 24 is nitrided, and nitrogen is doped into the channel layer 24, so as to form a SiGeN layer on the surface of the channel layer 24, thereby effectively reducing the concentration of Ge on the surface of the channel layer 24, and further achieving the effect of reducing the oxidation rate of the channel layer 24.

In this embodiment, before performing the nitridation process on the channel layer 24, the surface of the channel layer 24 may be cleaned to remove the particles and the natural oxide layer on the surface of the channel layer 24, so as to prevent the particles and the natural oxide layer from blocking nitrogen atoms from entering the channel layer 24, thereby improving the effect of the nitridation process. DHF, for example, diluted HF solution, may be used as a cleaning agent to clean the channel layer 24. After the nitridation treatment of the channel layer 24, the surface of the nitrided channel layer 24 may be cleaned again by using a DHF solution, so as to avoid the influence of impurities remaining on the surface of the channel layer 24 on the subsequent processes.

Optionally, the specific step of performing nitridation on the channel layer 24 includes:

the channel layer 24 is nitrided by a Remote Plasma Nitridation (RPN) process.

Specifically, the channel layer 24 may be nitrided vertically downward by remote plasma nitridation in the direction indicated by the arrow in fig. 2D. By observing performance parameters during the nitridation process of the channel layer 24 (e.g., the concentration of nitrogen atoms that have been doped into the channel layer 24), feedback adjustment of process parameters during the remote plasma nitridation process, such as the flow rate of nitrogen source plasma and/or the process treatment time, may provide flexibility in adjusting the concentration of nitrogen elements at the surface of the channel layer 24, thereby adjusting the oxidation rate of the channel layer 24 to a value required by the process, such as adjusting the oxidation rate of the channel layer 24 to be equal to the oxidation rate of the substrate 20.

Step S14, oxidizing the surface of the second region 202 of the substrate 20 and the channel layer 24, and forming a first transition oxide layer 27 covering the surface of the channel layer 24 and a second transition oxide layer 28 covering the surface of the second region 202 of the substrate 20, as shown in fig. 2G.

Optionally, before oxidizing the surface of the second region 202 of the substrate 20 and the channel layer 24, the method further includes the following steps:

the protective layer 22 is removed.

Specifically, after adjusting the oxidation rate of the channel layer 24, a second photoresist layer 26 is formed overlying the surface of the channel layer 24, exposing the protective layer 22 on the surface of the second region 202 of the substrate 20. Then, the protective layer 22 is removed by an etching process, and the second photoresist layer 26 is stripped, so as to obtain the structure shown in fig. 2F. Since defects may be generated in the protective layer 22 during the epitaxial growth of the channel layer 24 and the nitridation of the channel layer 24, the protective layer 22 needs to be removed to avoid affecting the electrical performance of the subsequently formed NMOS transistor.

Optionally, the specific step of oxidizing the surface of the second region 202 of the substrate 20 and the channel layer 24 includes:

the surface of the second region 202 of the substrate 20 and the channel layer 24 are oxidized using an in-situ moisture growth process.

Hereinafter, the material of the substrate 20 is Si, and the material of the channel layer 24 is SiGe. And oxidizing the surface of the second region 202 of the substrate 20 and the surface of the channel layer 24 by using an in-situ water vapor growth process to form the first transition oxide layer 27 covering the surface of the channel layer 24 and the second transition oxide layer 28 covering the surface of the second region 202 of the substrate 20. Since the difference between the oxidation rate of the channel layer 24 and the oxidation rate of the substrate 20 is reduced after adjustment, the thickness difference between the first transition oxide layer 27 and the second transition oxide layer 28 formed simultaneously can be adjusted, for example, the oxidation rate of the channel layer 24 and the oxidation rate of the substrate 20 can be adjusted to be consistent, so that the thicknesses of the two layers are kept consistent, and therefore, in the subsequent electrical test process, the electrical properties of the NMOS and the PMOS can be kept consistent, the problem of magnitude influence caused by slight thickness difference is avoided, and the electrical property of the semiconductor structure is effectively improved.

Optionally, the thickness of the first transition oxide layer 27 is equal to the thickness of the second transition oxide layer 28.

For example, the thickness of the first transition oxide layer 27 and the thickness of the second transition oxide layer 28 may be 0.4 to 1.2nm, such as 0.7nm, 0.8nm, and 1 nm. The specific thickness of the first transition oxide layer 27 and the second transition oxide layer 28 can be adjusted by adjusting parameters of the in-situ water vapor growth process, such as the process time. The reduction of the thickness difference between the first transition oxide layer 27 and the second transition oxide layer 28 also helps to simplify the adjustment step of the specific thickness values of the first transition oxide layer 27 and the second transition oxide layer 28.

Optionally, after forming the first transition oxide layer 27 covering the surface of the channel layer 24 and the second transition oxide layer 28 covering the surface of the second region 202 of the substrate 20, the method further includes the following steps:

and forming a first gate dielectric layer on the surface of the first transition oxide layer 27 and simultaneously forming a second gate dielectric layer on the surface of the second transition oxide layer 28.

Specifically, the material of the first gate dielectric layer and the second gate dielectric layer may be, for example, a material with a high dielectric constant (HK), for example, a material with a dielectric constant greater than or equal to 9, so as to effectively increase the gate oxide thickness and suppress the gateIn the present invention, the first transition oxide layer 27 may reduce an interface effect between the channel layer 24 and the first gate dielectric layer, and the second transition oxide layer 28 may reduce an interface effect between the second region 202 of the substrate 20 and the second gate dielectric layer. Wherein, the material of the first gate dielectric layer and the material of the second gate dielectric layer may be both HfO, for example₂、Al₂O₃、HfSiO_z、HfON、HfAlO_z、ZrO₂、ZrSiO_z、Ta₂O₅、La₂O₃、HfLaO_z、LaAlO_z、LaSiO_zAnd any one or the combination of more than two of nitride or oxynitride of metal or alloy components in the materials, wherein, z is more than 0 and less than or equal to 1. Further, the material of the first gate dielectric layer and the material of the second gate dielectric layer may both be HfO₂、ZrO₂Or Ta₂O₅。

Furthermore, the present embodiment provides a semiconductor structure, and fig. 3 is a schematic diagram of the semiconductor structure according to the present embodiment. The semiconductor structure provided in this embodiment mode can be formed by using the method for forming a semiconductor structure shown in fig. 1 and fig. 2A to 2G. As shown in fig. 3, the semiconductor structure includes:

a substrate 20, the substrate 20 comprising a first region 201 for forming a PMOS transistor and a second region 202 for forming an NMOS transistor;

a channel layer 24 located on the surface of the first region 201 of the substrate 20, wherein the oxidation rate of the channel layer 24 is the same as that of the substrate 20;

a first transition oxide layer 27 located on the surface of the channel layer 24;

and a second transition oxide layer 28 located on the surface of the second region 202 of the substrate 20.

Optionally, the material of the channel layer 24 includes SiGe and a doping element, and the doping element is used to reduce the oxidation rate of SiGe.

Optionally, the doping element is a nitrogen element.

Wherein the doping element may be located only on the surface of the channel layer 24; alternatively, the dopant element may also be uniformly distributed throughout the channel layer 24.

Optionally, the thickness of the first transition oxide layer 27 is the same as the thickness of the second transition oxide layer 28.

For example, the thickness of the first transition oxide layer 27 and the thickness of the second transition oxide layer 28 may be 0.4 to 1.2nm, such as 0.7nm, 0.8nm, and 1 nm.

Optionally, the semiconductor structure further includes:

the first gate dielectric layer covers the surface of the first transition oxide layer 27;

and the second gate dielectric layer covers the surface of the second transition oxide layer 28.

Optionally, the material of the first gate dielectric layer is the same as the material of the second gate dielectric layer.

Optionally, the PMOS transistor and the NMOS transistor are both power transistors.

In the semiconductor structure and the forming method thereof according to the present embodiment, the difference between the oxidation rates of the channel layer and the substrate is reduced by adjusting the oxidation rate of the channel layer, so that a first transition oxide layer covering the channel layer and a second transition oxide layer covering the surface of the second region of the substrate can be simultaneously formed, and the first transition oxide layer and the second transition oxide layer can be adjusted to have the same thickness, thereby effectively improving the electrical performance of the semiconductor structure.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.