阅读说明：本技术 半导体存储器装置和该半导体存储器装置的制造方法 (Semiconductor memory device and method of manufacturing the same ) 是由 李南宰 于 2021-02-22 设计创作，主要内容包括：提供一种半导体存储器装置和该半导体存储器装置的制造方法。该半导体存储器装置包括：第一层叠结构,其包括交替层叠的层间绝缘层和第一导电图案；第二层叠结构,其包括与第一层叠结构交叠的第二导电图案,以及与第一层叠结构交叠的第三导电图案,并且第二导电图案插置在第一层叠结构和第三导电图案之间,第三导电图案的氧化速率不同于第二导电图案的氧化速率；沟道结构,其穿透第一层叠结构和第二层叠结构；以及位线,其与第一层叠结构交叠,并且第二层叠结构插置在第一层叠结构和位线之间。(A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes: a first stacked structure including interlayer insulating layers and first conductive patterns alternately stacked; a second laminated structure including a second conductive pattern overlapping the first laminated structure and a third conductive pattern overlapping the first laminated structure with the second conductive pattern interposed therebetween, the third conductive pattern having an oxidation rate different from that of the second conductive pattern; a channel structure penetrating the first and second stacked structures; and a bit line overlapping the first stacked structure with the second stacked structure interposed therebetween.)

1. A semiconductor memory device, the semiconductor memory device comprising:

a first stacked structure including interlayer insulating layers and first conductive patterns alternately stacked;

a second stacked structure including a second conductive pattern overlapping the first stacked structure and a third conductive pattern overlapping the first stacked structure with the second conductive pattern interposed therebetween, the third conductive pattern having an oxidation rate different from an oxidation rate of the second conductive pattern;

a channel structure penetrating the first and second stacked structures; and

a bit line overlapping the first stacked structure with the second stacked structure interposed therebetween.

2. The semiconductor memory device according to claim 1, wherein the second conductive pattern spaced farther from the bit line than the third conductive pattern includes a conductive material having an oxidation rate higher than that of the third conductive pattern.

3. The semiconductor memory device according to claim 1, wherein the second conductive pattern comprises silicon, and

the third conductive pattern includes a conductive material having a resistivity lower than that of the silicon.

4. The semiconductor memory device according to claim 1, wherein the second conductive pattern comprises silicon, and

the third conductive pattern includes a tungsten silicide layer.

5. The semiconductor memory device according to claim 1, further comprising a slit penetrating the second stacked structure,

wherein the slit isolates each of the second and third conductive patterns into a first select line and a second select line.

6. The semiconductor memory device according to claim 5, wherein the channel structure comprises:

a first channel structure penetrating the first select line and the first stacked structure; and

a second channel structure penetrating the second select line and the first stacked structure,

wherein the first conductive pattern extends to surround the first channel structure and the second channel structure.

7. The semiconductor memory device according to claim 6, further comprising:

a dummy channel structure penetrating the first stacked structure between the first channel structure and the second channel structure;

a dummy memory layer surrounding sidewalls of the dummy channel structure; and

an isolation insulating layer overlapping the dummy channel structure, the isolation insulating layer disposed between the first select line and the second select line.

8. The semiconductor memory device according to claim 1, further comprising:

a tunnel insulating layer surrounding sidewalls of each of the channel structures;

a data storage layer surrounding a sidewall of the tunnel insulating layer; and

a barrier insulating layer surrounding sidewalls of the data storage layer,

wherein the blocking insulating layer includes a first portion between the first stacked structure and the data storage layer, a second portion between the data storage layer and the second conductive pattern, and a third portion between the data storage layer and the third conductive pattern,

wherein the second portion of the blocking insulating layer is formed to have a width greater than a width of each of the first portion and the third portion.

9. The semiconductor memory device according to claim 8, wherein the second portion of the blocking insulating layer protrudes further toward the channel structure than the first portion and the third portion.

10. The semiconductor memory device according to claim 8, further comprising a source layer overlapping the bit line, and the first stacked structure and the second stacked structure are interposed between the bit line and the source layer,

wherein each of the channel structures penetrates the tunnel insulating layer, the data storage layer, and the blocking insulating layer, and includes a bottom surface in contact with the source layer.

11. The semiconductor memory device according to claim 8, further comprising:

a first source layer overlapping the first stacked structure; and

a second source layer disposed between the first source layer and the first stacked structure,

wherein the channel structure includes an end portion extending to an inner portion of the first source layer,

wherein the second source layer is in contact with a sidewall of the channel structure,

wherein the second source layer isolates the tunnel insulating layer, the data storage layer, and the blocking insulating layer into a first memory pattern disposed between each of the channel structures and the first stacked structure and a second memory pattern disposed between each of the channel structures and the first source layer.

12. The semiconductor memory device according to claim 8, further comprising a source layer overlapping the first stacked structure,

wherein each of the channel structures extends further into an interior of the source layer than the tunnel insulating layer, the data storage layer, and the blocking insulating layer, and includes an end portion contacting the source layer.

13. The semiconductor memory device according to claim 1, wherein each of the channel structures comprises:

a core insulating layer surrounded by the first stacked structure and the second conductive pattern;

a doped semiconductor pattern overlapping the core insulating layer, the doped semiconductor pattern being surrounded by the third conductive pattern; and

a channel layer extending along sidewalls of the core insulating layer and sidewalls of the doped semiconductor pattern.

14. The semiconductor memory device according to claim 13, wherein the channel layer comprises:

a first portion disposed between the first lamination structure and the core insulating layer;

a second portion extending from the first portion, the second portion being disposed between the second conductive pattern and the core insulating layer; and

a third portion extending from the second portion, the third portion surrounding sidewalls of the doped semiconductor pattern,

wherein the second portion protrudes further toward the core insulating layer than the first portion and the third portion.

15. The semiconductor memory device according to claim 1, wherein the second conductive pattern is formed thicker than each of the first conductive pattern and the third conductive pattern.

16. A semiconductor memory device, the semiconductor memory device comprising:

a core insulation layer including a first portion and a second portion extending from the first portion;

a doped semiconductor pattern overlapping the first portion of the core insulating layer with the second portion interposed therebetween;

a first blocking insulating layer extending along sidewalls of the core insulating layer and sidewalls of the doped semiconductor pattern, the first blocking insulating layer protruding toward the second portion of the core insulating layer;

a channel layer extending between the first barrier insulating layer and the doped semiconductor pattern and between the first barrier insulating layer and the core insulating layer;

a tunnel insulating layer disposed between the channel layer and the first blocking insulating layer;

a data storage layer disposed between the tunnel insulating layer and the first blocking insulating layer; and

a gate stack structure surrounding the first blocking insulating layer.

17. The semiconductor memory device according to claim 16, wherein the gate stack structure comprises:

a first stacked structure surrounding the first portion of the core insulating layer, the first stacked structure including first conductive patterns and interlayer insulating layers that are alternately stacked;

a second conductive pattern overlapping the first laminate structure, the second conductive pattern surrounding the second portion of the core insulating layer; and

a third conductive pattern overlapping the second conductive pattern, the third conductive pattern surrounding the doped semiconductor pattern.

18. The semiconductor memory device according to claim 17, wherein the first blocking insulating layer protrudes toward the second conductive pattern between the third conductive pattern and the first stacked structure.

19. The semiconductor memory device according to claim 17, wherein the second conductive pattern comprises silicon, and the third conductive pattern comprises a conductive material having a resistivity lower than that of the silicon.

20. The semiconductor memory device according to claim 17, wherein the second conductive pattern comprises silicon, and the third conductive pattern comprises a tungsten silicide layer.

21. The semiconductor memory device according to claim 17, wherein the second conductive pattern is formed thicker than each of the first conductive pattern and the third conductive pattern.

22. The semiconductor memory device according to claim 17, further comprising a second barrier insulating layer extending between the first conductive pattern and the interlayer insulating layer and between the first conductive pattern and the first barrier insulating layer,

wherein the first blocking insulating layer is in contact with each of the second and third conductive patterns.

23. A method of manufacturing a semiconductor memory device, the method comprising:

forming a first stacked structure including alternately stacked interlayer insulating layers and sacrificial layers;

forming a first conductive pattern overlapping the first lamination structure;

forming a second conductive pattern overlapping the first lamination structure with the first conductive pattern interposed therebetween;

forming a hole penetrating the first stacked structure, the first conductive pattern, and the second conductive pattern;

forming a plurality of layers on sidewalls of the hole, wherein the plurality of layers include a first portion extending along the sidewalls of the first stacked structure, a second portion extending along the sidewalls of the first conductive pattern, and a third portion extending along the sidewalls of the second conductive pattern, and a width of the second portion is wider than a width of each of the first portion and the third portion; and

forming a trench structure filling the hole on an inner wall of the multilayer.

24. The method of claim 23, wherein the second conductive pattern comprises a conductive material having an oxidation rate that is lower than an oxidation rate of the first conductive pattern.

25. The method of claim 23, wherein the first conductive pattern comprises silicon and the second conductive pattern comprises a conductive material having a resistivity lower than the resistivity of the silicon.

26. The method of claim 23, wherein the first conductive pattern comprises silicon and the second conductive pattern comprises a tungsten silicide layer.

27. The method of claim 23, wherein the first conductive pattern is formed thicker than each of the sacrificial layers, and

the second conductive pattern is formed to be thinner than the first conductive pattern.

28. The method of claim 23, wherein the step of forming the multilayer comprises the steps of:

forming a pad layer on a surface of the hole;

forming a blocking insulating layer by oxidizing the pad layer and the first conductive pattern using an oxidation process in which an oxidation rate of the first conductive pattern is higher than that of the pad layer and the second conductive pattern;

forming a data storage layer extending along an inner wall of the blocking insulating layer; and

a tunnel insulating layer is formed to extend along an inner wall of the data storage layer.

29. The method of claim 28, wherein a portion of the blocking insulating layer extending along the sidewalls of the first conductive pattern is formed to have a width wider than portions of the blocking insulating layer extending along the sidewalls of the first stacked structure and the sidewalls of the second conductive pattern such that inner walls of the blocking insulating layer have an uneven surface.

30. The method of claim 29, wherein each of the data storage layer and the tunnel insulating layer extends along the uneven surface.

31. The method of claim 23, wherein the central region of the aperture comprises a first central region surrounded by the first portion of the plurality of layers, a second central region surrounded by the second portion of the plurality of layers, and a third central region surrounded by the third portion of the plurality of layers,

wherein the second portion of the plurality of layers protrudes further toward the second central area of the hole than the first portion and the third portion of the plurality of layers such that an inner wall of the plurality of layers has an uneven surface.

32. The method of claim 31, wherein the step of forming the channel structure comprises the steps of:

forming a channel layer extending along the uneven surface;

filling the first and second central regions through the channel layer opening with a core insulating layer; and

filling the third central region through the channel layer opening with a doped semiconductor pattern.

33. The method of claim 32, wherein a portion of a sidewall of the doped semiconductor pattern is surrounded by the second conductive pattern.

34. The method of claim 23, further comprising the steps of:

forming a dummy hole penetrating the first stacked structure, the first conductive pattern, and the second conductive pattern in the step of forming the hole; and

in the step of forming the channel structure, forming a preliminary dummy channel structure in the dummy hole,

wherein the plurality of layers extend onto sidewalls of the dummy hole.

35. The method of claim 34, wherein the plurality of layers includes a protruding portion protruding toward a central area of the dummy aperture.

36. The method of claim 35, further comprising the steps of: forming a first slit penetrating the first and second conductive patterns, the first slit isolating each of the first and second conductive patterns into a preliminary selection line,

wherein a portion of the preliminary dummy channel structure is removed when forming the first slit.

37. The method of claim 23, further comprising the steps of:

forming a second slit penetrating the first lamination structure, the first conductive pattern, and the second conductive pattern; and

replacing the sacrificial layer with a third conductive pattern through the second slit.

Technical Field

The present disclosure relates generally to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a three-dimensional semiconductor memory device and a method of manufacturing the same.

Background

A semiconductor memory device includes memory cells capable of storing data. The three-dimensional semiconductor memory device includes memory cells arranged three-dimensionally, thereby enabling a reduction in the area of a substrate occupied by the memory cells.

In order to improve the integration of the three-dimensional semiconductor memory device, the number of stacked memory cells may be increased. As the number of stacked memory cells increases, the operational reliability of the three-dimensional semiconductor memory device may deteriorate.

Disclosure of Invention

According to an aspect of the present disclosure, there may be provided a semiconductor memory device including: a first stacked structure including interlayer insulating layers and first conductive patterns alternately stacked; a second laminated structure including a second conductive pattern overlapping the first laminated structure and a third conductive pattern overlapping the first laminated structure with the second conductive pattern interposed therebetween, the third conductive pattern having an oxidation rate different from that of the second conductive pattern; a channel structure penetrating the first and second stacked structures; and a bit line overlapping the first stacked structure with the second stacked structure interposed therebetween.

According to another aspect of the present disclosure, there may be provided a semiconductor memory device including: a core insulation layer including a first portion and a second portion extending from the first portion; a doped semiconductor pattern overlapping the first portion of the core insulating layer with the second portion interposed between the first portion and the doped semiconductor pattern; a first blocking insulating layer extending along sidewalls of the core insulating layer and sidewalls of the doped semiconductor pattern, the first blocking insulating layer protruding toward the second portion of the core insulating layer; a channel layer extending between the first barrier insulating layer and the doped semiconductor pattern and between the first barrier insulating layer and the core insulating layer; a tunnel insulating layer disposed between the channel layer and the first blocking insulating layer; a data storage layer disposed between the tunnel insulating layer and the first blocking insulating layer; and a gate stack structure surrounding the first blocking insulating layer.

According to still another aspect of the present disclosure, there may be provided a method of manufacturing a semiconductor memory device, the method including: forming a first stacked structure including alternately stacked interlayer insulating layers and sacrificial layers; forming a first conductive pattern overlapping the first lamination structure; forming a second conductive pattern overlapping the first stacked structure with the first conductive pattern interposed therebetween; forming a hole penetrating the first lamination structure, the first conductive pattern and the second conductive pattern; forming a plurality of layers on sidewalls of the hole, wherein the plurality of layers include a first portion extending along the sidewalls of the first stacked structure, a second portion extending along the sidewalls of the first conductive pattern, and a third portion extending along the sidewalls of the second conductive pattern, and a width of the second portion is wider than a width of each of the first portion and the third portion; and forming a channel structure filling the hole on the inner wall of the plurality of layers.

Drawings

In the drawings, the size may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.

Fig. 1 is a block diagram illustrating a semiconductor memory device according to one embodiment of the present disclosure.

Fig. 2 is a circuit diagram illustrating a memory block according to one embodiment of the present disclosure.

Fig. 3A and 3B are perspective views schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

Fig. 4 is a perspective view illustrating a gate stack structure of a semiconductor memory device according to one embodiment of the present disclosure.

Fig. 5 is an enlarged sectional view of the region a shown in fig. 4.

Fig. 6 is a cross-sectional view illustrating a source layer and a channel structure according to an embodiment of the present disclosure.

Fig. 7 is a cross-sectional view illustrating a source layer and a channel structure according to an embodiment of the present disclosure.

Fig. 8 is a flowchart schematically illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

Fig. 9 is a flowchart schematically illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

Fig. 10A, 10B, 10C, 10D, 11A, 11B, 11C, 11D, 12A, 12B, 12C, and 12D are cross-sectional views illustrating a method of manufacturing a memory cell array according to one embodiment of the present disclosure.

Fig. 13 is a block diagram showing a configuration of a memory system according to one embodiment of the present disclosure.

Fig. 14 is a block diagram illustrating a configuration of a computing system according to one embodiment of the present disclosure.

Detailed Description

The specific structural or functional descriptions disclosed herein are merely exemplary for purposes of describing embodiments of the concepts according to the present disclosure. Embodiments according to the disclosed concept can be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

Hereinafter, the terms "first" and "second" are used to distinguish one component from another component. For example, a first component may be termed a second component, and, similarly, a second component may be termed a first component, without departing from the scope of concepts according to the present disclosure.

Embodiments provide a semiconductor memory device capable of improving operational reliability and a method of manufacturing the semiconductor memory device.

Fig. 1 is a block diagram illustrating a semiconductor memory device 10 according to one embodiment of the present disclosure.

Referring to fig. 1, a semiconductor memory device 10 may include a peripheral circuit PC and a memory cell array 20.

The peripheral circuit PC may control a program operation for storing data in the memory cell array 20, a read operation for outputting data stored in the memory cell array 20, and an erase operation for erasing data stored in the memory cell array 20.

In one embodiment, the peripheral circuit PC may include a voltage generator 31, a row decoder 33, a control circuit 35, and a page buffer group 37.

The memory cell array 20 may include a plurality of memory blocks. The memory cell array 20 may be connected to the row decoder 33 through word lines WL and to the page buffer group 37 through bit lines BL.

The control circuit 35 can control the peripheral circuit PC in response to a command CMD and an address ADD.

The voltage generator 31 may generate various operation voltages for a program operation, a read operation, and an erase operation, such as a pre-erase voltage, an erase voltage, a ground voltage, a program voltage, a verify voltage, a pass voltage, and a read voltage, under the control of the control circuit 35.

The row decoder 33 may select a memory block under the control of the control logic 35. The row decoder 33 may apply an operating voltage to the word line WL coupled to the selected memory block.

The page buffer group 37 may be connected to the memory cell array 20 through a bit line BL. The page buffer group 37 may temporarily store data received from an input/output circuit (not shown) in a programming operation under the control of the control circuit 35. The page buffer group 37 may sense the voltage or current of the bit line BL in a read operation or a verify operation under the control of the control circuit 37. The page buffer group 37 may select the bit line BL under the control of the control circuit 35.

Structurally, the memory cell array 20 may overlap a portion of the peripheral circuit PC.

Fig. 2 is a circuit diagram illustrating a memory block according to one embodiment of the present disclosure.

Referring to fig. 2, the memory block may include a plurality of cell strings CS1 and CS2 and a plurality of word lines WL1 to WLn commonly connected to the source layer SL. The plurality of cell strings CS1 and CS2 may be connected to a plurality of bit lines BL.

Each of the plurality of cell strings CS1 and CS2 may include at least one source selection transistor SST connected to the source layer SL, at least one drain selection transistor DST connected to the bit line BL, and a plurality of memory cells MC1 through MCn connected in series between the source selection transistor SST and the drain selection transistor DST.

The gates of the plurality of memory cells MC1 through MCn may be respectively connected to a plurality of word lines WL1 through WLn that are stacked to be spaced apart from each other. A plurality of word lines WL1 to WLn may be disposed between the source select line SSL and two or more drain select lines DSL1 and DSL 2. The two or more drain select lines DSL1 and DSL2 may be spaced apart from each other on the same level.

The gate of the source selection transistor SST may be connected to a source selection line SSL. A gate of the drain select transistor DST may be connected to a drain select line corresponding to the gate of the drain select transistor DST.

The source layer SL may be connected to a source of the source selection transistor SST. A drain of the drain select transistor DST may be connected to a bit line corresponding to the drain of the drain select transistor DST.

The plurality of cell strings CS1 and CS2 may be divided into string groups connected to the two or more drain select lines DSL1 and DSL2, respectively. Cell strings connected to the same word line and the same bit line may be independently controlled by different drain select lines. In addition, cell strings connected to the same drain select line may be independently controlled by different bit lines.

In one embodiment, the two or more drain select lines DSL1 and DSL2 may include a first drain select line DSL1 and a second drain select line DSL 2. The plurality of cell strings CS1 and CS2 may include a first cell string CS1 connected to a first string group of the first drain select line DSL1, and a second cell string CS2 connected to a second string group of the second drain select line DSL 2.

Fig. 3A and 3B are perspective views schematically illustrating semiconductor memory devices 10A and 10B according to an embodiment of the present disclosure.

Referring to fig. 3A and 3B, each of the semiconductor memory devices 10A and 10B may include a peripheral circuit PC disposed on the substrate SUB and a gate stack structure GST overlapping the peripheral circuit PC.

Each gate stack structure GST may include a source selection line SSL, a plurality of word lines WL1 to WLn, and two or more drain selection lines DSL1 and DSL2 isolated from each other at the same level by the first slit S1.

The source selection line SSL and the plurality of word lines WL1 to WLn may be formed in the shape of a plate (plate) that expands in the first direction X and the second direction Y and is parallel to the top surface of the substrate SUB. The first direction X may be a direction in which an X axis of an XYZ coordinate system faces, and the second direction Y may be a direction in which a Y axis of the XYZ coordinate system faces.

A plurality of word lines WL1 to WLn may be stacked to be spaced apart from each other in the third direction Z. The third direction Z may be a direction in which the Z-axis of the XYZ coordinate system faces. A plurality of word lines WL1 to WLn may be disposed between the two or more drain select lines DSL1 and DSL2 and the source select line SSL.

The respective gate stack structures GST may be isolated from each other by the second slit S2. The first slit S1 may be formed to be shorter than the second slit S2 in the third direction Z and overlap the plurality of word lines WL1 to WLn.

Each of the first slit S1 and the second slit S2 may extend in a straight line shape, in a zigzag shape, or in a wave shape (wave shape). The width of each of the first slit S1 and the second slit S2 may be variously changed according to design rules.

Referring to fig. 3A, according to one embodiment, the source select line SSL may be disposed closer to the peripheral circuit PC than the two or more drain select lines DSL1 and DSL 2.

The semiconductor memory device 10A may include a source layer SL disposed between the gate stack structure GST and the peripheral circuit PC and a plurality of bit lines BL spaced farther from the peripheral circuit PC than the source layer SL. The gate stack structure GST may be disposed between a plurality of bit lines BL and a source layer SL.

Referring to fig. 3B, according to one embodiment, the two or more drain select lines DSL1 and DSL2 may be disposed closer to the peripheral circuit PC than the source select line SSL.

The semiconductor memory device 10B may include a plurality of bit lines BL and a source layer SL. A plurality of bit lines BL may be disposed between the gate stack structure GST and the peripheral circuit PC. The source layer SL may be spaced farther from the peripheral circuit PC than the plurality of bit lines BL. The gate stack structure GST may be disposed between a plurality of bit lines BL and a source layer SL.

Referring again to fig. 3A and 3B, the plurality of bit lines BL may be formed of various conductive materials. The source layer SL may include a doped semiconductor layer. In one embodiment, the source layer SL may include an n-type doped silicon layer.

Although not shown in the drawings, the peripheral circuit PC may be electrically connected to the plurality of bit lines BL, the source layer SL, and the plurality of word lines WL1 to WLn through an interconnect structure having various structures.

Fig. 4 is a perspective view illustrating gate stack structures GSTa, GSTb, and GSTc of a semiconductor memory device according to one embodiment of the present disclosure.

Referring to fig. 4, each of the gate stack structures GSTa, GSTb, and GSTc may include a first stack structure ST1 and a second stack structure ST 2. The first and second stacked structures ST1 and ST2 may be disposed between the plurality of bit lines BL and the source layer SLa.

The plurality of bit lines BL may overlap the first stacked structure ST1, and the second stacked structure ST2 may be disposed between the first stacked structure ST1 and the plurality of bit lines BL. The plurality of bit lines BL may overlap the source layer SLa.

The first laminate structure ST1 may include a first interlayer insulating layer ILD1 and a first conductive pattern CP1 alternately laminated. The first conductive pattern CP1 may function as a source select line SSL and a plurality of word lines WL1 to WLn.

The second stack structure ST2 may include a second conductive pattern CP2, a third conductive pattern CP3, and a second interlayer insulating layer ILD 2. The second conductive pattern CP2 may be disposed between the third conductive pattern CP3 and the first stacked structure ST1, and overlap the first stacked structure ST 1. The third conductive pattern CP3 may be disposed between the second conductive pattern CP2 and the second interlayer insulating layer ILD2, and overlap the first stacked structure ST 1. The third conductive pattern CP3 may include a contact surface contacting the second conductive pattern CP 2. The third conductive pattern CP3 may include a conductive material having an oxidation rate (oxidation rate) different from that of the second conductive pattern CP 2. In one embodiment, the second conductive pattern CP2 may include silicon, and the third conductive pattern CP3 may include a conductive material having a resistivity lower than that of silicon. In one embodiment, the third conductive pattern CP3 may include a metal silicide layer, for example, a tungsten silicide layer. By the third conductive pattern CP3 having a resistivity lower than that of the second conductive pattern CP2, the RC delay of each of the drain select lines DSL1 and DSL2 can be minimized.

The second stacked structure ST2 may be penetrated by the first slit S1. Each of the second and third conductive patterns CP2 and CP3 of the second stacked structure ST2 may be isolated as the drain select lines DSL1 and DSL2 by the first slit S1. In one embodiment, each of the gate stack structures GSTa, GSTb, and GSTc may include a first drain selection line DSL1 and a second drain selection line DSL2 isolated from each other by a first slit S1.

The gate stacked structures GSTa, GSTb, and GSTc may be isolated from each other by the second slits S2 formed deeper than the first slits S1. A spacer insulating layer SP may be formed on sidewalls of each of the second slits S2, and a vertical structure 60 may be formed in each of the second slits S2. In one embodiment, the vertical structure 60 may contact the source layer SLa and include a conductive material filling each of the second slits S2. However, the present disclosure is not limited thereto. In one embodiment, the vertical structure 60 may comprise an insulating material.

The first and second stack structures ST1 and ST2 of each of the gate stack structures GSTa, GSTb, and GSTc may be penetrated by the plurality of channel structures CH. The plurality of channel structures CH may be arranged in a plurality of channel columns (channel columns). The channel structures arranged in each channel column may include channel structures aligned in a direction in which the bit line BL extends. In one embodiment, the channel structures disposed in each channel column may include first channel structures CH11 and CH12 and second channel structures CH21 and CH 22. The first channel structures CH11 and CH12 may be disposed at one side of the first slit S1, and the second channel structures CH21 and CH22 may be disposed at the other side of the first slit S1. In other words, the first slit S1 may be disposed between the first channel structures CH11 and CH12 and the second channel structures CH21 and CH 22.

In one embodiment, the first channel structures CH11 and CH12 may extend to penetrate the first drain select line DSL1 and the first stacked structure ST 1. The second channel structures CH21 and CH22 may extend to penetrate the second drain select line DSL2 and the first stacked structure ST 1. Each of the first conductive pattern CP1 and the first interlayer insulating layer ILD1 may extend to surround the first channel structures CH11 and CH12 and the second channel structures CH21 and CH 22.

Each bit line may be electrically connected to any one of the first channel structures CH11 and CH12 and any one of the second channel structures CH21 and CH22 via drain contact plugs DCT.

The dummy channel structure DCH may be disposed between the first channel structures CH11 and CH12 and the second channel structures CH21 and CH 22. The dummy channel structure DCH may penetrate the first stack structure ST 1. The first slit S1 may overlap the dummy channel structure DCH.

Each channel structure CH may include a core insulating layer CO, a doped semiconductor pattern DP, and a channel layer CL. The dummy channel structure DCH may include a dummy core insulating layer CO 'and a dummy channel layer CL'.

The core insulating layer CO may be surrounded by the first lamination structure ST1 and the second conductive pattern CP 2. In one embodiment, the core insulating layer CO may include a first portion PA surrounded by the first lamination structure ST1 and a second portion PB extending from the first portion PA and surrounded by the second conductive pattern CP 2. The dummy core insulating layer CO' may extend parallel to the first portion PA of the core insulating layer CO.

The doped semiconductor pattern DP may overlap the core insulating layer CO and be surrounded by the third conductive pattern CP3 and the second interlayer insulating layer ILD 2. In one embodiment, the doped semiconductor pattern DP may overlap the first portion PA of the core insulating layer CO, and the second portion PB of the core insulating layer CO is interposed between the doped semiconductor pattern DP and the first portion PA of the core insulating layer CO. In one embodiment, the doped semiconductor pattern DP may include an n-type doped silicon layer.

The doped semiconductor pattern DP may be surrounded by at least a portion of the third conductive pattern CP3, and thus, a Gate Induced Drain Leakage (GIDL) current may be increased during an erase operation of the semiconductor memory device. The GIDL current may be generated due to a difference between an erase voltage applied to the bit line BL and a gate voltage applied to the third conductive pattern CP 3.

The distance between the doped semiconductor pattern DP and the word line WLn closest to the doped semiconductor pattern DP among the plurality of word lines WL1 to WLn may be controlled by adjusting the thickness D2 of the second conductive pattern CP 2. The second conductive pattern CP2 may be formed to be thicker to improve off characteristics of drain select transistors connected to the first drain select line DSL1 and the second drain select line DSL 2. In one embodiment, the thickness D2 of the second conductive pattern CP2 may be formed to be thicker than the thickness D1 of each of the first conductive patterns CP1 and the thickness D3 of the third conductive pattern CP 3. In one embodiment, the thickness D2 of the second conductive pattern CP2 may be two or more times the thickness D1 of each of the first conductive patterns CP 1.

The channel layer CL may extend along sidewalls of the core insulating layer CO and sidewalls of the doped semiconductor pattern DP. The channel layer CL may include a first portion PP1, a second portion PP2 extending from the first portion PP1, and a third portion PP3 extending from the second portion PP 2. The first part PP1 may be disposed between the first lamination structure ST1 and the core insulation layer CO. The first portion PP1 may extend between the source layer SLa and the core insulating layer CO, and contact the source layer SLa. The second part PP2 may be disposed between the second conductive pattern CP2 and the core insulating layer CO. The third portion PP3 may surround the sidewall of the doped semiconductor pattern DP. The dummy channel layer CL' may extend parallel to the first portion PP1 of the channel layer CL. Each of the channel layer CL and the dummy channel layer CL' may include a semiconductor layer. In one embodiment, each of the channel layer CL and the dummy channel layer CL' may include a silicon layer.

The sidewall of each channel structure CH may be surrounded by the memory layer ML. The sidewalls of the dummy channel structure DCH may be surrounded by the dummy memory layer ML'. The dummy memory layer ML' may extend from a sidewall of the dummy channel structure DCH to penetrate the second stack structure ST 2. The dummy memory layer ML' may extend onto sidewalls of the isolation insulating layer 50. The isolation insulating layer 50 may be disposed between the first drain select line DSL1 and the second drain select line DSL 2. The isolation insulating layer 50 may fill the first slit S1 and overlap the dummy channel structure DCH. The dummy memory layer ML' may include the same material layer as the memory layer ML.

Although not shown in the drawings, an upper insulating layer through which the drain contact plug DCT penetrates may be disposed between the plurality of bit lines BL and the second stack structure ST 2.

Fig. 5 is an enlarged sectional view of the region a shown in fig. 4.

Referring to fig. 5, the memory layer ML may include a tunnel insulating layer TI, a data storage layer DL, and a first blocking insulating layer BI 1.

The tunnel insulating layer TI may surround sidewalls of each channel structure CH shown in fig. 4. The tunnel insulating layer TI may include an insulating material through which charges can tunnel. In one embodiment, the tunnel insulating layer TI may include a silicon oxide layer.

The data storage layer DL may surround a sidewall of the tunnel insulating layer TI. The data storage layer DL may include a material layer capable of storing data. In one embodiment, data storage layer DL may be formed of a layer of material capable of storing data altered by tunneling using Fowler-Nordheim (F-N). To this end, the data storage layer DL may include a nitride layer capable of trapping charges therein. However, the present disclosure is not limited thereto, and the data storage layer DL may include a phase change material, nanodots, and the like.

The first barrier insulating layer BI1 may surround a sidewall of the data storage layer DL. The first barrier insulating layer BI1 may extend along sidewalls of the core insulating layer CO and sidewalls of the doped semiconductor pattern DP. The first barrier insulating layer BI1 may include a first portion P1, a second portion P2, and a third portion P3. The first portion P1 is disposed between the data storage layer DL and the first stacked structure ST1 shown in fig. 4. The second portion P2 extends from the first portion P1 and is disposed between the data storage layer DL and the second conductive pattern CP 2. The third portion P3 extends from the second portion P2 and is disposed between the data storage layer DL and the third conductive pattern CP 3.

The first barrier insulating layer BI1 may include an oxide. The width W2 of the second portion P2 of the first barrier insulating layer BI1 may be formed to be wider than each of the width W1 of the first portion P1 and the width W3 of the third portion P3. The second portion P2 may protrude further toward the channel layer CL of the channel structure than the first portion P1 and the third portion P3. In one embodiment, the first barrier insulating layer BI1 may protrude toward the second portion PB of the core insulating layer CO located between the doped semiconductor pattern DP and the first portion PA of the core insulating layer CO. The second portion P2 may protrude toward the second conductive pattern CP2 positioned between the third conductive pattern CP3 and the first stacked structure ST1 shown in fig. 4.

By the protruding second portion P2 of the first barrier insulating layer BI1, an uneven surface may be defined at an inner wall of the first barrier insulating layer BI1 contacting the data storage layer DL. Each of the data storage layer DL disposed between the first barrier layer BI1 and the channel layer CL and the tunnel insulation layer TI disposed between the data storage layer DL and the channel layer CL may be deposited along the uneven surface of the first barrier insulation layer BI 1.

The channel layer CL may extend between the first barrier insulating layer BI1 and the doped semiconductor pattern DP and between the first barrier insulating layer BI1 and the core insulating layer CO. The second portion PP2 of the channel layer CL may be formed along the uneven surface of the first barrier insulating layer BI1 to protrude further toward the core insulating layer CO than the first portion PP1 and the third portion PP 3.

The doped semiconductor pattern DP may be aligned on the protruding second portion PP2 of the channel layer CL. Accordingly, in the embodiments of the present disclosure, a deviation (variation) in the position of the doped semiconductor pattern DP beyond a target range may be reduced.

The first conductive patterns CP1 may surround the memory layer ML between the respective first interlayer insulating layers ILD 1. The first conductive pattern CP1 may include a conductive material having a resistivity lower than that of silicon. In one embodiment, the first conductive pattern CP1 may include a metal layer.

A second barrier insulating layer BI2 may also be formed between the first conductive pattern CP1 and the first barrier insulating layer BI 1. The second barrier insulating layer BI2 may include an insulating material having a higher dielectric constant than that of the first barrier insulating layer BI 1. In one embodiment, the second barrier insulating layer BI2 may include a metal oxide layer. In one embodiment, the metal oxide layer may include an aluminum oxide layer. The second barrier insulating layer BI2 may extend along an interface between the first conductive pattern CP1 and the first interlayer insulating layer ILD 1.

The second and third conductive patterns CP2 and CP3 may be in contact with the first barrier insulating layer BI 1. In other words, the second barrier insulating layer BI2 may be omitted between the channel layer CL and the drain select line including the second and third conductive patterns CP2 and CP 3.

The semiconductor memory devices shown in fig. 4 and 5 can be applied to the semiconductor memory device 10A shown in fig. 3A. The semiconductor memory device shown in fig. 4 and 5 may be inverted in the vertical direction to be applied to the semiconductor memory device 10B shown in fig. 3B.

As shown in fig. 4, the channel layer CL may penetrate the memory layer ML and include a bottom surface contacting the source layer SLa. However, the embodiments of the present disclosure are not limited thereto.

Fig. 6 is a cross-sectional view illustrating the source layer SLb and the channel structure CH according to one embodiment of the present disclosure. The structure shown in fig. 6 can be applied to the semiconductor memory device 10A shown in fig. 3A.

Referring to fig. 6, the source layer SLb may include a first layer SL1 (i.e., a first source layer) and a second layer SL2 (i.e., a second source layer), or include a first layer SL1, a second layer SL2, and a third layer SL3 (i.e., a third source layer). The first layer SL1 may overlap the first lamination structure ST 1. The second layer SL2 may be disposed between the first layered structure ST1 and the first layer SL 1. The third layer SL3 may be disposed between the second layer SL2 and the first lamination ST 1.

Each of the first layer SL1, the second layer SL2, and the third layer SL3 may include a semiconductor layer. Each of the first, second, and third layers SL1, SL2, and SL3 may include at least one of a p-type impurity and an n-type impurity. In one embodiment, each of the first layer SL1, the second layer SL2, and the third layer SL3 may include an n-type doped silicon layer.

The first stack structure ST1 may include first interlayer insulating layers ILD and first conductive patterns CP1 alternately stacked as described with reference to fig. 4, and may be penetrated by the channel structure CH.

The end EP of the channel structure CH may penetrate the third layer SL3 and the second layer SL2 and extend to the inside of the first layer SL 1. In one embodiment, the channel layer CL and the core insulating layer CO may penetrate the third layer SL3 and the second layer SL2 and extend to the inside of the first layer SL 1.

Each of the first blocking insulating layer BI1, the data storage layer DL, and the tunnel insulating layer TI may be isolated into the first and second memory patterns ML1 and ML 2. The second layer SL2 may protrude further toward the channel layer CL than the first layer SL1 and the third layer SL3, and be in contact with the channel layer CL.

The first blocking insulating layer BI1, the data storage layer DL, and the tunnel insulating layer TI of the first memory pattern ML1 may extend between the third layer SL3 and the channel layer CL and between the first stacked structure ST1 and the channel layer CL. The first blocking insulating layer BI1, the data storage layer DL, and the tunnel insulating layer TI of the second memory pattern ML2 may extend between the first layer SL1 and the channel layer CL.

The second barrier insulating layer BI2 may be disposed between the first barrier insulating layer BI1 and the first conductive pattern CP1 of the first memory pattern ML 1.

Fig. 7 is a cross-sectional view illustrating the source layer SLc and the channel structure CH according to one embodiment of the present disclosure. The structure shown in fig. 7 can be applied to the semiconductor memory device 10B shown in fig. 3B.

Referring to fig. 7, the source layer SLc may overlap the first stacked structure ST1, and include a doped semiconductor layer. In one embodiment, the source layer SLc may include n-type doped silicon. The first stacked structure ST1 may be disposed between the source layer SLc and the second stacked structure ST2 described with reference to fig. 4.

The first stack structure ST1 may include first interlayer insulating layers ILD and first conductive patterns CP1 alternately stacked as described with reference to fig. 4, and may be penetrated by the channel structure CH.

The end portion EP' of the channel structure CH may penetrate the first blocking insulating layer BI1, the data storage layer DL, and the tunnel insulating layer TI of the memory layer ML and extend to the inside of the source layer SLc. In one embodiment, the channel layer CL and the core insulating layer CO may extend to the inside of the source layer SLc. A portion of the channel layer CL constituting the end portion EP' of the channel structure CH may contact the source layer SLc.

Fig. 8 is a flowchart schematically illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

Referring to fig. 8, the method of manufacturing the semiconductor memory device may include a step S1 of forming a peripheral circuit on a substrate and a step S3 of forming a memory cell array on the peripheral circuit.

In step S1, a peripheral circuit may be provided on the substrate. The peripheral circuit may include a plurality of transistors. A junction of the transistor may be formed in a partial region of the substrate, and a gate electrode of the transistor may be formed on the substrate.

In step S3, a memory cell array may be formed on the peripheral circuit. Step S3 may include a step of forming the source layer SL shown in fig. 3A, a step of forming the gate stack structure GST shown in fig. 3A, and a step of forming the bit line BL shown in fig. 3A.

Although not shown in the drawings, a conductive pattern for an interconnect structure may be formed on the peripheral circuit and a memory cell array may be formed on the interconnect structure before step S3.

Fig. 9 is a flowchart schematically illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

Referring to fig. 9, a method of manufacturing a semiconductor memory device may include: the step S11 of forming a first chip including a peripheral circuit, the step S13 of forming a second chip including a memory cell array, the step S15 of bonding the first chip and the second chip, the step S17 of removing an auxiliary substrate of the second chip, and the step S19 of forming a source layer.

In step S11, the peripheral circuit may be provided on the main substrate. The first chip may include a first interconnect structure connected to peripheral circuitry.

In step S13, a memory cell array may be formed on the auxiliary substrate. Step S13 may include a step of forming the gate stack structure GST shown in fig. 3B and a step of forming the bit line BL shown in fig. 3B. The structure including the gate stack structure GST and the bit line BL shown in fig. 3B may be inverted in a vertical direction to be formed on the auxiliary substrate. The second chip may further include a second interconnect structure connected to the memory cell array.

In step S15, the second chip may be aligned on the first chip such that the first interconnect structures and the second interconnect structures face each other, and some of the first interconnect structures and some of the second interconnect structures may be bonded to each other.

In step S17, the auxiliary substrate of the second chip may be removed. The channel structure of the memory cell array may be exposed.

In step S19, a source layer may be formed in contact with the channel structure. Therefore, the semiconductor memory device 10B shown in fig. 3B can be provided.

Fig. 10A, 10B, 10C, 10D, 11A, 11B, 11C, 11D, 12A, 12B, 12C, and 12D are cross-sectional views illustrating a method of manufacturing a memory cell array according to one embodiment of the present disclosure. The method of manufacturing a memory cell array, which will be described later with reference to fig. 10A, 10B, 10C, 10D, 11A, 11B, 11C, 11D, 12A, 12B, 12C, and 12D, may be included in step S3 shown in fig. 8 or step S13 shown in fig. 9.

Fig. 10A to 10D are sectional views illustrating a step of forming the preliminary stacked structure 110 and a step of forming channel structures 140A penetrating the preliminary stacked structure 110 and respectively surrounded by the memory layers 130A.

Referring to fig. 10A, the step of forming the preliminary laminated structure 110 may include a step of forming a first laminated structure 110A and a step of forming a second laminated structure 110B on the first laminated structure 110A.

The step of forming the first stacked structure 110A may include a step of alternately stacking the first interlayer insulating layer 101 and the sacrificial layer 103. Each of the sacrificial layers 103 may include a material having an etch selectivity with respect to the first interlayer insulating layer 101. In one embodiment, the first interlayer insulating layer 101 may include silicon oxide, and the sacrificial layer 103 may include silicon nitride.

The step of forming the second stacked structure 110B may include a step of sequentially stacking the first conductive pattern 111, the second conductive pattern 113, and the second interlayer insulating layer 115. Each of the first conductive pattern 111, the second conductive pattern 113, and the second interlayer insulating layer 115 may overlap the first laminate structure 110A. The first conductive pattern 111 may be disposed between the second conductive pattern 113 and the first laminate structure 110A, and the second conductive pattern 113 may be disposed between the second interlayer insulating layer 115 and the first conductive pattern 111.

The second conductive pattern 113 may include a conductive material having an oxidation rate lower than that of the first conductive pattern 111. In one embodiment, the first conductive pattern 111 may include silicon, and the second conductive pattern 113 may include a conductive pattern having a resistivity lower than that of silicon. In one embodiment, the second conductive pattern 113 may include a metal silicide layer, for example, a tungsten silicide layer.

The first conductive pattern 111 may be formed to be thicker than each of the sacrificial layers 103. The thickness of the second conductive pattern 113 may be variously controlled. In one embodiment, the second conductive pattern 113 may be formed to be thinner than the first conductive pattern 111.

After the preliminary stacked structure 110 is formed, a mask layer 121 may be formed on the preliminary stacked structure 110. The mask layer 121 may include a nitride layer.

Referring to fig. 10B, a hole 125A may be formed by etching the mask layer 121 and the preliminary stacked structure 110. The hole 125A may penetrate the preliminary laminated structure 110. In the step of forming the holes 125A, dummy holes 125B penetrating the preliminary stacked structure 110 may be formed simultaneously with the holes 125A.

The holes 125A and the dummy holes 125B may be defined by etching the mask layer 121 and the preliminary stacked structure 110. The mask layer 121 and the preliminary stacked structure 110 may be etched by using a photoresist pattern (not shown) as an etch barrier. The photoresist pattern may be formed through a photolithography process.

After the holes 125A and the dummy holes 125B are formed, the photoresist pattern may be removed.

Referring to fig. 10C, a multi-layer (multi-layer)130L may be formed to cover the surfaces of the holes 125A and the dummy holes 125B. The multilayer 130L may extend onto the mask layer 121. The multi-layer 130L may include a first blocking insulating layer 133, a data storage layer 135, and a tunnel insulating layer 137 shown in fig. 11C.

The multilayer 130L may include a first portion Pa, a second portion Pb, a third portion Pc, and a fourth portion Pd. The first portion Pa, the second portion Pb, and the third portion Pc of the multilayer 130L may be disposed on a sidewall of each of the hole 125A and the dummy hole 125B. The first portion Pa may extend along a sidewall of the first lamination structure 110A. The second portion Pb may extend from the first portion Pa and extend along sidewalls of the first conductive pattern 111. The third portion Pc may extend from the second portion Pb and extend along sidewalls of the second conductive pattern 113, sidewalls of the second interlayer insulating layer 115, and sidewalls of the mask layer 121. The fourth portion Pd may extend from the third portion Pc and extend along the top surface of the mask layer 121. The second portion Pb of the multi-layer 130L may be formed to have a width wider than those of the other portions Pa, Pc, and Pd.

The central region of each of the holes 125A and the dummy holes 125B may include a first central region C1 surrounded by the first portion Pa, a second central region C2 surrounded by the second portion Pb, and a third central region C3 surrounded by the third portion Pc. The second portion Pb may protrude further toward the second central area C2 than the first portion Pa and the third portion Pc such that an inner wall of the multi-layer 130L facing the central area of each of the hole 125A and the dummy hole 125B has an uneven surface.

Fig. 11A to 11D are enlarged sectional views. Fig. 11A to 11C illustrate one embodiment of the step of forming the multilayer 130L.

Referring to fig. 11A, the step of forming the multi-layer 130L shown in fig. 10C may include a step of forming a liner layer (liner layer)131 on a surface of each of the hole 125A and the dummy hole 125B shown in fig. 10B. The pad layer 131 may be formed using a deposition with good step coverage (step coverage). In one embodiment, the liner layer 131 may be formed using Atomic Layer Deposition (ALD). The liner layer 131 may include a material having an oxidation rate lower than that of the first conductive pattern 111. In one embodiment, the pad layer 131 may include a nitride layer.

Referring to fig. 11B, the step of forming the multi-layer 130L shown in fig. 10C may include a step of forming a blocking insulating layer 133 by oxidizing the pad layer 131 and the first conductive pattern 111 shown in fig. 11A through an oxidation process.

In the oxidation process, a portion of the first conductive pattern 111 may be oxidized. The oxidation process may include a radical oxidation process in which the oxidation rate of the first conductive pattern 111 is higher than that of the pad layer 131 and the second conductive pattern 113 shown in fig. 11A. The inner wall of the barrier insulating layer 133 defined by the oxidation process according to the embodiment of the present disclosure may have an uneven surface. The blocking insulating layer 133 may include an oxidized region of the pad layer 131 and a region in which a portion of the first conductive pattern 111 is oxidized as shown in fig. 11B.

The blocking insulating layer 133 may include a first portion 133a, a second portion 133b extending from the first portion 133a, and a third portion 133c extending from the second portion 133 b. The first portion 133a may extend along sidewalls of the first stacked structure 110A, the second portion 133b may extend along sidewalls of the first conductive pattern 111, and the third portion 133C may extend along sidewalls of the second conductive pattern 113, sidewalls of the second interlayer insulating layer 115, and a surface of the mask layer 121. Due to the difference in oxidation rate between the liner layer 131 and the first conductive pattern 111 shown in fig. 11A, the width Wb of the second portion 133b of the blocking insulating layer 133 may be formed to be wider than the width Wa of the first portion 133a and the width Wc of the third portion 133 c.

During the oxidation process, a portion of the sacrificial layer 103, a portion of the second conductive pattern 113, and a portion of the mask layer 121 may be oxidized. The oxidation rate of the first conductive pattern 111 is higher than that of each of the sacrificial layer 103, the second conductive pattern 113, and the mask layer 121. Accordingly, although a portion of the sacrificial layer 103, a portion of the second conductive pattern 113, and a portion of the mask layer 121 are oxidized, the width Wb of the second portion 133b may be formed to be wider than the width Wa of the first portion 133a and the width Wc of the third portion 133 c.

Referring to fig. 11C, the step of forming the multi-layer 130L shown in fig. 10C may include the step of sequentially depositing a data storage layer 135 and a tunnel insulating layer 137 along the uneven surface of the blocking insulating layer 133. The data storage layer 135 may extend along an inner wall of the blocking insulating layer 133, and the tunnel insulating layer 137 may extend along an inner wall of the data storage layer 135.

Referring to fig. 10D, a channel structure 140A may be formed in the hole 125A opened through the multi-layer 130L shown in fig. 10C. In the step of forming the channel structure 140A, a preliminary dummy channel structure 140B filling the dummy hole 125B shown in fig. 10C may be formed simultaneously with the channel structure 140A.

The top surface of the mask layer 121 may be exposed by removing the fourth portion Pd of the multilayer 130L shown in fig. 10C. The multi-layer 130L may be isolated into a memory layer 130A and a dummy memory layer 130B. The second portion Pb may be defined as a protruding portion that defines an uneven surface at an inner wall of each of the memory layer 130A and the dummy memory layer 130B.

The memory layers 130A may remain on the sidewalls of the respective holes 125A shown in fig. 10C, respectively. The dummy memory layer 130B may remain on the sidewalls of the dummy hole 125B shown in fig. 10C. The channel structures 140A may be respectively disposed on the inner walls of the respective memory layers 130A and fill the holes 125A. The preliminary dummy channel structure 140B may be disposed on an inner wall of the dummy memory layer 130B and fill the dummy hole 125B.

Fig. 11C and 11D illustrate one embodiment of the steps of forming channel structure 140A and preliminary dummy channel structure 140B.

Referring to fig. 11C, the step of forming the channel structure 140A and the preliminary dummy channel structure 140B may include a step of forming a channel layer 141 along the uneven surface of the multilayer 130L and a step of filling the first and second central regions C1 and C2 opened through the channel layer 141 with the core insulating layer 143.

The channel layer 141 may include a protruding portion 141PP covering the second portion Pb of the multilayer 130L shown in fig. 10C.

The core insulating layer 143 may be formed by depositing an insulating layer by Atomic Layer Deposition (ALD). Accordingly, the core insulating layer 143 can fill the second central region C2 without any void, so that process defects due to the void can be minimized.

The insulation layer of the core insulation layer 143 may extend to the inside of the third central region C3. A portion of the insulating layer formed in the third central region C3 may be removed by an etching process. In one embodiment, the etching process may be performed by a wet etching process or a dry etching process. When the portion of the insulating layer is etched, the protruding portion 141PP of the channel layer 141 may serve as an etch stop layer. Therefore, the remaining height of the core insulating layer 143 can be uniformly controlled.

Referring to fig. 11D, the third central region C3 opened on the core insulating layer 143 may be filled with the doped semiconductor pattern 145. The doped semiconductor pattern 145, the channel layer 141 shown in fig. 11C, and the multi-layer 130L shown in fig. 11C may be planarized to expose the top surface of the mask layer 121. Thus, as shown in fig. 10D, a memory layer 130A and a dummy memory layer 130B isolated from each other and a channel structure 140A and a preliminary dummy channel structure 140B isolated from each other may be formed.

A portion of the sidewall of the doped semiconductor pattern 145 may be surrounded by the second conductive pattern 113. The top surface of the doped semiconductor layer 145 is not covered by the first and second stacked structures 110A and 110B, but may be open. Accordingly, even without using the thermal diffusion process, the impurity may be directly implanted into the doped semiconductor pattern 145. Impurities are directly implanted into the doped semiconductor pattern 145, so that junction overlap (junction overlap) of the memory cell string obtained due to the doped semiconductor pattern 145 can be stably formed. In one embodiment, an impurity may also be implanted into a local region of the channel layer 141 in contact with the doped semiconductor pattern 145.

Fig. 12A through 12D are cross-sectional views illustrating one embodiment of subsequent processes performed after the channel structure 140A and the preliminary dummy channel structure 140B illustrated in fig. 10D.

Referring to fig. 12A, after removing the mask layer 121 illustrated in fig. 10D, a first upper insulating layer 151 may be formed. The first upper insulating layer 151 may cover the channel structure 140A and the preliminary dummy channel structure 140B shown in fig. 10D.

Subsequently, a first slit 153 penetrating the first upper insulating layer 151 and the second stacked structure 110B may be formed. Each of the first conductive pattern 111 and the second conductive pattern 113 of the second stacked structure 110B may be isolated into the preliminary selection line SELa by the first slit 153. The first slit 153 may be defined by etching the first upper insulating layer 151, the second interlayer insulating layer 115, the second conductive pattern 113, and the first conductive pattern 111. The first upper insulating layer 151, the second interlayer insulating layer 115, the second conductive pattern 113, and the first conductive pattern 111 may be etched by using a photoresist pattern (not shown) as an etch barrier. The photoresist pattern may be formed through a photolithography process. After the first slit 153 is formed, the photoresist pattern may be removed.

The first conductive pattern 111 is selectively etched using an etch selectivity between the first conductive pattern 111 and the oxide layer, so that the position of the first slit 153 may be controlled on the first lamination structure 110A.

The first slit 153 may overlap the preliminary dummy channel structure 140B shown in fig. 10D. In forming the first slits 153, portions of the preliminary dummy channel structure 140B overlapping the first slits 153 may be removed. The preliminary dummy channel structure 140B shown in fig. 10D may include the doped semiconductor pattern 145, the channel layer 141, and the core insulating layer 143 as shown in fig. 11D. In forming the first slits 153, the doped semiconductor pattern 145 of the preliminary dummy channel structure 140B may be removed, and a portion of the channel layer 141 of the preliminary dummy channel structure 140B may be removed. After removing a portion of the channel layer 141, a portion of the channel layer 141 remaining in the dummy hole may be defined as a dummy channel layer 141'. In forming the first slit 153, a portion of the core insulating layer 143 of the preliminary dummy channel structure 140B may be removed. After removing a portion of the core insulating layer 143, a portion of the core insulating layer 143 remaining in the dummy hole may be defined as a dummy core insulating layer 143'. The dummy core insulating layer 143 ' and the dummy channel layer 141 ' may define a dummy channel structure 140B '.

The first slit 153 may expose a portion of the dummy memory layer 130B protruding further than the dummy channel structure 140B'. Subsequently, an isolation insulating layer 155 filling the first slit 153 may be formed. The isolation insulating layer 155 may cover a portion of the dummy memory layer 130B protruding further than the dummy channel structure 140B' and extend to cover the first upper insulating layer 151.

Referring to fig. 12B, a second upper insulating layer 157 may be formed on the isolation insulating layer 155. Subsequently, a second slit 161 may be formed, which penetrates the second upper insulating layer 157, the insulating isolation layer 155, the first upper insulating layer 151, the second stacked structure 110B, and the first stacked structure 110A shown in fig. 12A. Each of the first conductive pattern 111 and the second conductive pattern 113 of the second stacked structure 110B may be isolated as the selection line SELb by the first slit 153 and the second slit 161. The second slit 161 may be defined by etching the second upper insulating layer 157, the isolation insulating layer 155, the first upper insulating layer 151, the second stacked structure 110B, and the first stacked structure 110A shown in fig. 12A using a photoresist pattern (not shown) formed by a photolithography process as an etch barrier. After the second slit 161 is formed, the photoresist pattern may be removed.

Subsequently, the sacrificial layer 103 of the first stacked structure 110A shown in fig. 12A may be selectively removed through the second slit 161. Accordingly, a horizontal space 163 may be defined between the first interlayer insulating layers 101.

Referring to fig. 12C, a third conductive pattern 165 may be formed in the horizontal space shown in fig. 12B. Before forming the third conductive pattern 165, a second blocking insulating layer may be formed on a surface of each horizontal space 163. The second barrier insulating layer may include an insulating material having a dielectric constant higher than that of the first barrier insulating layer 133 shown in fig. 11D. In one embodiment, the second barrier insulating layer may include an aluminum oxide layer.

As described with reference to fig. 12B and 12C, the sacrificial layer 103 may be replaced with the third conductive pattern 165 through the second slit 161. In the case of forming the selection line SELb having a relatively thick thickness, various process defects may occur in replacing the sacrificial layer having a thick thickness with the conductive pattern. According to an embodiment of the present disclosure, the first conductive pattern 111 and the third conductive pattern 113 are not replaced by the third conductive pattern 165, but may be patterned into a selection line SELb having a relatively thick thickness through an etching process. Accordingly, it is possible to fundamentally prevent process defects occurring in the process of replacing the sacrificial layer having a different thickness with the conductive pattern.

Referring to fig. 12D, subsequent processes, such as a process of forming a spacer insulating layer 171 on sidewalls of the second slits 161 shown in fig. 12C, a process of filling the second slits 161 opened through the spacer insulating layer 171 with vertical structures 173, and a process of forming drain contact plugs 175 connected to the channel structures 140A, may be performed.

In one embodiment, the vertical structure 173 may include a conductive material. In one embodiment, the drain contact plug 175 may penetrate the second upper insulating layer 157 and the isolation insulating layer 155 and extend to the inside of the first upper insulating layer 151.

Fig. 13 is a block diagram showing a configuration of a memory system 1100 according to one embodiment of the present disclosure.

Referring to fig. 13, a memory system 1100 includes a memory device 1120 and a memory controller 1110.

The memory device 1120 may include a select line penetrated by a hole, a memory layer formed on a sidewall of the hole, and a doped semiconductor pattern filling a portion of the hole. The selection line may include a stacked structure of conductive patterns having different oxidation rates. The memory layer may include a protruding portion protruding toward a central region of the hole on a sidewall of the conductive pattern having a relatively high oxidation rate. The doped semiconductor pattern may be aligned on the protruding portion of the memory layer. In an erase operation of the memory device 1120, a Gate Induced Drain Leakage (GIDL) current may be generated in the doped semiconductor pattern.

Memory device 1120 may be a multi-chip package configured with multiple flash memory chips.

The memory controller 1110 controls the memory device 1120, and may include a Static Random Access Memory (SRAM)1111, a Central Processing Unit (CPU)1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as an operation memory for the CPU 1112, the CPU 1112 performs an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol for a host connected to the memory system 1100. The error correction block 1114 detects and corrects errors contained in data read from the memory device 1120. The memory interface 1115 interfaces with the memory device 1120. The memory controller 1110 may also include a Read Only Memory (ROM) or the like for storing encoded data for interfacing with a host.

Fig. 14 is a block diagram illustrating a configuration of a computing system according to one embodiment of the present disclosure.

Referring to fig. 14, a computing system 1200 according to an embodiment of the present disclosure may include a CPU 1220, a Random Access Memory (RAM)1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. Computing system 1200 may be a mobile device.

Memory system 1210 may include a memory device 1212 and a memory controller 1211. The memory device 1212 may include a select line penetrated by a hole, a memory layer formed on a sidewall of the hole, and a doped semiconductor pattern filling a portion of the hole. The selection line may include a stacked structure of conductive patterns having different oxidation rates. The memory layer may include a protruding portion protruding toward a central region of the hole on a sidewall of the conductive pattern having a relatively high oxidation rate. The doped semiconductor pattern may be aligned on the protruding portion of the memory layer. In an erase operation of the memory device 1120, a Gate Induced Drain Leakage (GIDL) current may be generated in the doped semiconductor pattern.

According to the present disclosure, by using conductive patterns having different oxidation rates, the width of a partial region of the blocking insulating layer extending along the sidewalls of the conductive patterns having a higher oxidation rate may be formed to be wider than the width of other regions of the blocking insulating layer, and the partial region of the blocking insulating layer may protrude.

According to the present disclosure, by using the protruding local region of the blocking insulating layer, it is possible to reduce deviation of the position of the doped semiconductor pattern from a target range. Accordingly, a Gate Induced Drain Leakage (GIDL) current for an erase operation may be stably generated, so that operational reliability of the semiconductor memory device may be improved.

Cross Reference to Related Applications

This application claims priority from korean patent application No.10-2020-0058646, filed on 5/15/2020 and incorporated herein by reference in its entirety.