阅读说明：本技术 包括存储器单元串的存储器阵列及用于形成存储器阵列的方法 (Memory array including memory cell strings and method for forming memory array ) 是由 J·D·霍普金斯 N·M·洛梅利 于 2021-05-11 设计创作，主要内容包括：本申请涉及包括存储器单元串的存储器阵列及用于形成所述存储器阵列的方法。一种包括存储器单元串的存储器阵列包括横向间隔开的存储器块,所述横向间隔开的存储器块分别包括竖直堆叠,所述竖直堆叠包括交替的绝缘层及导电层。存储器单元的沟道材料串结构延伸穿过所述绝缘层及所述导电层。所述沟道材料串结构分别包括在下部部分上方且与下部部分接合的上部部分。个别所述沟道材料串结构包括在所述上部及下部部分接合的垂直截面中的至少一个外部折弯表面。公开包含方法的其它实施例。(The present application relates to memory arrays including strings of memory cells and methods for forming the same. A memory array including a string of memory cells includes laterally spaced memory blocks each including a vertical stack including alternating insulating and conductive layers. A channel material string structure of a memory cell extends through the insulating layer and the conductive layer. The channel material string structures each include an upper portion above and joined with a lower portion. Individual ones of the channel material string structures include at least one outer inflection surface in vertical cross-section where the upper and lower portions join. Other embodiments are disclosed, including methods.)

1. A method for forming a memory array comprising a string of memory cells, comprising:

forming a lower portion of a stack on a substrate that will include vertically alternating first and second layers, the stack including laterally spaced memory block regions, a material of the first layer having a different composition than a material of the second layer;

forming pillars in the lower portion, the pillars respectively positioned horizontally, wherein individual channel material string structures are to be formed, the pillars comprising a sacrificial material;

forming the vertically alternating first and second layers of the upper portion of the stack over the lower portion and the pillars;

forming channel openings into the stack and extending to individual ones of the pillars, respectively;

removing the sacrificial material of the posts through the channel openings to extend the channel openings deeper into the stack; and

a channel material string structure is formed in the elongated channel opening and in void spaces therein resulting from the removing.

2. The method of claim 1, wherein the channel material string structures each include an upper portion above and joined with a lower portion, the respective channel material string structures including at least one outer bend surface in a vertical cross-section of the upper and lower portion joins.

3. The method of claim 1, wherein the sacrificial material comprises a metallic material.

4. The method of claim 3, wherein the metallic material comprises elemental tungsten.

5. A method for forming a memory array comprising a string of memory cells, comprising:

forming a conductor layer including a conductor material on a substrate;

forming a lower portion of a stack comprising vertically alternating first and second layers over the conductor layer, the stack comprising laterally spaced memory block regions, the material of the first layer being of a different composition than the material of the second layer, the lowermost first layer comprising a first sacrificial material;

forming pillars in the lowermost first layer, the pillars respectively positioned horizontally, wherein individual channel material string structures are to be formed, the pillars comprising a second sacrificial material;

forming the vertically alternating first and second layers of the upper portion of the stack over the lower portion and the pillars;

forming channel openings into the stack and extending to individual ones of the pillars, respectively;

removing the second sacrificial material of the pillars through the channel openings to extend the channel openings deeper into the stack;

forming a channel material string structure in the elongated channel opening and in void spaces therein resulting from the removing;

forming horizontal elongated trenches into the stack, the horizontal elongated trenches respectively between the laterally immediately adjacent memory block regions and extending into the first sacrificial material in the lowermost first layer;

isotropically etching the first sacrificial material from the lowermost first layer through the trench; and

after the isotropic etching, forming a conductive material in the lowermost first layer that directly electrically couples together the channel material of the individual channel material string structures and the conductor material of the conductor layer.

6. The method of claim 5, wherein the second sacrificial material has a different composition than the first sacrificial material, the first layer of material that forms or will form over the first sacrificial material, and the second layer of material that forms or will form over the first sacrificial material.

7. The method of claim 5, wherein the channel material string structures each include an upper portion above and joined with a lower portion, the respective channel material string structures including at least one outer bend surface in a vertical cross-section of the upper and lower portion joins.

8. The method of claim 5, wherein the pillars each comprise an uppermost surface above the lowermost first layer.

9. The method of claim 5, wherein individual of the pillars have a bottom surface in or at a top of the conductor layer.

10. The method of claim 9, wherein the bottom surface is directly against the conductor material.

11. The method of claim 5, wherein the lowermost first layer does not directly abut the conductor material of the conductor layer during the isotropic etching.

12. The method of claim 5, wherein a lowermost surface of the channel material string structure never directly abuts the conductor material of any of the conductor layers.

13. The method of claim 5, wherein the conductive material in the lowermost first layer is directly against sidewalls of the channel material string structures.

14. The method of claim 5, wherein the conductive material in the lowermost first layer is directly against an uppermost surface of the conductor material of the conductor layer.

15. A memory array comprising a string of memory cells, comprising:

laterally spaced memory blocks each comprising a vertical stack comprising alternating insulating layers and conductive layers through which channel material string structures of memory cells extend; and

the channel material string structures each include an upper portion above and joined to a lower portion, the respective channel material string structures including at least one outer bending surface in vertical cross-section of the upper and lower portion junctions.

16. The memory array of claim 15, wherein the at least one folding surface is horizontal or within 10 ° of horizontal.

17. The memory array of claim 16, wherein the at least one folding surface is horizontal.

18. The memory array of claim 16, wherein the at least one folding surface is not horizontal.

19. The memory array of claim 15, wherein the at least one folding surface is more than 10 ° from horizontal.

20. The memory array of claim 19, wherein the at least one folding surface is at least 22.5 ° from horizontal.

21. The memory array of claim 20, wherein the at least one folding surface is at least 45 ° from horizontal.

22. The memory array of claim 15, comprising only one bending surface in the vertical cross-section in the individual channel material string structures.

23. The memory array of claim 15, comprising two bending surfaces in the vertical cross-section in the individual channel material string structures.

24. The memory array of claim 23, wherein the two bending surfaces are tilted differently from vertical with respect to each other.

25. The memory array of claim 24, wherein one of the two angled surfaces is horizontal and the other of the two angled surfaces is not horizontal.

26. The memory array of claim 23 wherein the two angled surfaces are equally inclined from vertical with respect to each other.

27. The memory array of claim 26, wherein the two folding surfaces are horizontal.

28. The memory array of claim 26, wherein neither of the two angled surfaces is horizontal.

Technical Field

Embodiments disclosed herein relate to memory arrays and to methods for forming memory arrays.

Background

Memory is one type of integrated circuit system and is used in computer systems to store data. The memory may be fabricated as one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which can also be referred to as bit lines, data lines, or sense lines) and access lines (which can also be referred to as word lines). Sense lines can conductively interconnect memory cells along columns of the array, and access lines can conductively interconnect memory cells along rows of the array. Each memory cell is uniquely addressable by a combination of a sense line and an access line.

The memory cells may be volatile, semi-volatile, or nonvolatile. Non-volatile memory cells can store data for long periods of time without power. Non-volatile memory is typically designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. Regardless, the memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the state is considered to be either "0" or "1". In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors include a pair of conductive source/drain regions with a semiconductive channel region therebetween. A conductive gate is adjacent to and separated from the channel region by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. The field effect transistor may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

Flash memory is one type of memory and is used in large numbers in modern computers and devices. For example, modern personal computers may have the BIOS stored on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in the form of a solid state drive in place of a traditional hard disk drive. As yet another example, flash memory is popular in wireless electronic devices because flash memory enables manufacturers to support new communication protocols as they become standardized and to provide manufacturers with the ability to remotely upgrade devices for enhanced features.

NAND can be the basic architecture of integrated flash memory. The NAND cell devices include at least one select device coupled in series with a series combination of memory cells (and the series combination is commonly referred to as a NAND string). The NAND architecture may be configured in a three-dimensional arrangement that includes vertically stacked memory cells that individually include reversibly programmable vertical transistors. Control circuitry or other circuitry may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells that each include a transistor.

The memory arrays may be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks), and memory planes, for example, as shown and described in any of U.S. patent application publication nos. 2015/0228651, 2016/0267984, and 2017/0140833. The memory block may at least partially define a longitudinal profile of an individual word line in an individual word line layer of vertically stacked memory cells. The connections to these word lines may occur in so-called "staircase structures" at the ends or edges of the array of vertically stacked memory cells. The stair-step structure includes individual "steps" (alternatively referred to as "steps" or "stairs") that define contact regions for individual word lines that are contacted by vertically extending conductive vias to provide electrical access to the word lines.

Disclosure of Invention

In one aspect, the present application provides a method for forming a memory array comprising a string of memory cells, comprising: forming a lower portion of a stack on a substrate that will include vertically alternating first and second layers, the stack including laterally spaced memory block regions, a material of the first layer having a different composition than a material of the second layer; forming pillars in the lower portion, the pillars respectively positioned horizontally, wherein individual channel material string structures are to be formed, the pillars comprising a sacrificial material; forming the vertically alternating first and second layers of the upper portion of the stack over the lower portion and the pillars; forming channel openings into the stack and extending to individual ones of the pillars, respectively; removing the sacrificial material of the posts through the channel openings to extend the channel openings deeper into the stack; and forming a channel material string structure in the elongated channel opening and in void spaces therein resulting from the removing.

In another aspect, the present application provides a method for forming a memory array comprising a string of memory cells, comprising: forming a conductor layer including a conductor material on a substrate; forming a lower portion of a stack comprising vertically alternating first and second layers over the conductor layer, the stack comprising laterally spaced memory block regions, the material of the first layer being of a different composition than the material of the second layer, the lowermost first layer comprising a first sacrificial material; forming pillars in the lowermost first layer, the pillars respectively positioned horizontally, wherein individual channel material string structures are to be formed, the pillars comprising a second sacrificial material; forming the vertically alternating first and second layers of the upper portion of the stack over the lower portion and the pillars; forming channel openings into the stack and extending to individual ones of the pillars, respectively; removing the second sacrificial material of the pillars through the channel openings to extend the channel openings deeper into the stack; forming a channel material string structure in the elongated channel opening and in void spaces therein resulting from the removing; forming horizontal elongated trenches into the stack, the horizontal elongated trenches respectively between the laterally immediately adjacent memory block regions and extending into the first sacrificial material in the lowermost first layer; isotropically etching the first sacrificial material from the lowermost first layer through the trench; and forming conductive material in the lowermost first layer after the isotropic etching, the conductive material directly electrically coupling together the channel material of the individual channel material string structures and the conductor material of the conductor layer.

In yet another aspect, the present application further provides a memory array comprising a string of memory cells, comprising: laterally spaced memory blocks each comprising a vertical stack comprising alternating insulating layers and conductive layers through which channel material string structures of memory cells extend; and the channel material string structures respectively comprise an upper portion above and joined with a lower portion, the respective channel material string structures comprising at least one outer bending surface in a vertical cross-section of the upper and lower portion junctions.

Drawings

FIG. 1 is a diagrammatic, cross-sectional view of a portion of a substrate in process in accordance with an embodiment of the invention and is taken through line 1-1 in FIG. 2.

Fig. 2 is a diagrammatic cross-sectional view taken through line 2-2 in fig. 1.

Fig. 3-10 and 14-38 are diagrammatic sequential cross-sectional, expanded, enlarged and/or partial views of the construction of fig. 1 and 2, or portions thereof, in a process according to some embodiments of the invention.

Figures 11-13 and 39-53 are diagrammatic, cross-sectional views of portions of a substrate in process according to some embodiments of the invention.

Detailed Description

Embodiments of the present invention encompass methods for forming a memory array, such as an array of NAND or other memory cells, which may have at least some peripheral control circuitry under the array (e.g., CMOS under the array). Embodiments of the present invention encompass so-called "gate last" or "replacement gate" processes, so-called "gate first" processes, and other processes, whether now existing or developed in the future, that are independent of the formation time of the transistor gate. Embodiments of the present invention also encompass memory arrays (e.g., NAND architectures) that are independent of the method of fabrication. A first example method embodiment is described with reference to fig. 1-53, which may be considered a "gate last" or "replacement gate" process and begins with fig. 1 and 2.

Fig. 1 and 2 show a construction 10 having an array or array region 12 in which vertically extending strings of transistors and/or memory cells are to be formed. Construction 10 includes a base substrate 11 having any one or more of conductive/conductor/conductive, semi-conductive/semi-conductive, or insulating/insulator/insulating (i.e., electrically herein) materials. Various materials have been formed vertically above the base substrate 11. The material may be alongside, vertically inward of, or vertically outward of the material depicted in fig. 1 and 2. For example, other partially or fully fabricated components of the integrated circuit system may be provided somewhere above, around, or within the base substrate 11. Control and/or other peripheral circuitry for operating components within an array of vertically-extending strings of memory cells (e.g., array 12) may also be fabricated, and may or may not be entirely or partially within the array or sub-array. Furthermore, multiple sub-arrays may also be fabricated and operated independently, sequentially, or otherwise with respect to each other. In this document, "subarrays" may also be considered as arrays.

In some embodiments and as shown, a conductor material 17 (e.g., WSi) is included_xTop conductively doped polysilicon) has been formed over the substrate 11. The conductor layer 16 may comprise portions of control circuitry (e.g., peripheral array lower circuitry and/or common source line or plate) for controlling read and write access to transistors and/or memory cells to be formed within the array 12.

A lower portion 18L of the stack 18, when present, has been formed over the substrate 11 and the conductor layer 16 (suffixed to include all such components designated with the same numerical value, which may or may not have other suffixes). The stack 18 will include vertically alternating conductive layers 22 and insulating layers 20. Example lower portion 18L is shown to include two insulating layers 20 and two conductive layers 22. More insulating layers 20, more conductive layers 22, fewer insulating layers 20, or fewer conductive layers 22 may be provided in the lower portion 18L (not shown) alternately. Conductive layer 22 (alternatively referred to as the first layer) may not include a conductive material, and insulating layer 20 (alternatively referred to as the second layer) may not include an insulating material or be insulating when processed in connection with the "back gate" or "replacement gate" example method embodiments described initially herein. Example conductive layer 22 includes a first material 26 (e.g., silicon nitride) that may be fully or partially sacrificial. Example insulating layers 20 include a second material (e.g., 24, 27; e.g., one or more insulating oxides, including, for example, silicon dioxide) that has a different composition than the composition of first material 26 and may be fully or partially sacrificial. In one embodiment, the lowermost first layer 22z comprises a first sacrificial material 77 (e.g., polysilicon or silicon nitride, and may be of the same or different composition as the material of the first layer 22 over and/or to be formed over it). In one embodiment, the next lowest first layer 22x comprises conductively doped polysilicon 47.

Example thicknesses for each of layers 20 and 22 are 20 to 60 nanometers. In one embodiment and as shown, the lowermost first layer 22z is not directly against the conductor material 17 of the conductor layer 16, for example where the lowermost second layer 20z is vertically between the conductor material 17 of the conductor layer 16 and the lowermost first layer 22 z. Alternatively, the lowermost first layer may be directly against the conductor material of the conductor layer (not shown). In one embodiment, the lowermost second layer 20z is directly against the top 19 of the conductor material 17 of the conductor layer 16. A silicon nitride layer (not shown) may be between second material 24 and first sacrificial material 77, and thus be part of insulating layer 20 z. A silicon nitride layer (not shown) may be between second material 27 and first layer material 47, and thus be part of insulating layer 20 x.

The stack 18 includes laterally spaced memory block regions 58 that will include the laterally spaced memory blocks 58 in the finished circuitry construction. In this document, "block" generally includes "sub-blocks". Memory block regions 58 and resulting memory blocks 58 (not shown) may be considered to be longitudinally extending and oriented, for example, along direction 55. The memory block 58 may not be discernable at this point of processing.

In one embodiment, horizontally extending lines 13 have been formed in the next lowest first layer 22x (and in one embodiment, in layer 20 x). Lines 13 are respectively between laterally adjacent memory block regions 58. The line 13 includes a second sacrificial material 15 that in one embodiment has a different composition than the first sacrificial material 77. In some embodiments, the "second sacrificial material" is referred to merely as a "sacrificial material". In some embodiments, the second sacrificial material 15 has a different composition than the first layer of material (e.g., 47) formed or to be formed over the first sacrificial material 77 and the second layer of material (e.g., 27) formed or to be formed over the first sacrificial material 77. In one embodiment, the second sacrificial material 15 has a different composition than the material 47 of the next lowest conductive first layer 22 x. In one embodiment, the second sacrificial material 15 comprises a metallic material, such as elemental tungsten over a thin layer of TiN. In one embodiment, insulator material 24 (e.g., silicon dioxide) may be formed in trenches formed in materials 47 and 27 as shown prior to forming material 47, and thus laterally between materials 47 and 15 as shown. Regardless, the wires 13 may taper laterally inward (not shown), moving deeper into the lower stacking portion 18L. Line 13 may be considered to have a bottom surface 59. In one embodiment and as shown, the individual bottom line surfaces 59 are anywhere above the next lowest first layer 22 z.

In one embodiment, the post 60 has been formed in the lower portion 18L. The pillars 60 are positioned horizontally (i.e., in x, y coordinates) where individual channel material string structures will be formed. By way of example only and for the sake of brevity, the pillars 60 are shown arranged in groups or columns of staggered rows of four and five pillars 60 per row. In one embodiment, the pillars 60 comprise a second sacrificial material 15. The struts 60 may taper radially inward (not shown) moving deeper into the lower stacking portion 18L. The pillar 60 may be considered as having a bottom surface 64 and an uppermost surface 63. In embodiments where both the posts 60 and the lines 13 are formed, they may be formed simultaneously or at different times.

In one embodiment, the pillar bottom surface 64 and the line bottom surface 59 are at different depths relative to each other. In one such embodiment, the pillar bottom surfaces 64 are deeper than the wire bottom surfaces 59, and in one such latter embodiment, they are in the conductor layer 16 (e.g., directly against the conductor material 17). In one embodiment, the uppermost surfaces 63 of the posts are above the lowermost first layer 22z, respectively.

Referring to fig. 3 and 4, vertically alternating first layers 22 and second layers 20 of upper portion 18U of stack 18 have been formed over lower portion 18L (and, when present, lines 13 and/or pillars 60). An example upper portion 18U is shown beginning at the second layer 20 above the lower portion 18L, but this could alternatively begin at the first layer 22 (not shown). In any event, only a small number of layers 20 and 22 are shown, with the upper portion 18U (and thus the stack 18) more likely including tens, a hundred, or more, etc. of layers 20 and 22. Further, other circuitry, which may or may not be part of the peripheral and/or control circuitry, may be between the conductor layer 16 and the stack 18. By way of example only, the plurality of vertically alternating layers of conductive material and insulating material of such circuitry may be below the lowermost conductive layer 22 and/or above the uppermost conductive layer 22. For example, one or more select gate layers (not shown) may be between the conductive layer 16 and the lowermost conductive layer 22, and one or more select gate layers may be above the uppermost conductive layer 22. Alternatively or additionally, at least one of the depicted uppermost and lowermost conductive layers 22 may be an option gate layer.

Channel openings 25 have been formed (e.g., by etching) through insulating layer 20 and conductive layer 22 in upper portion 18U to lower portion 18L and, respectively, to posts 60, when present. Alternatively, if the pillars 60 are not present, the channel openings 25 may extend to (be incorporated into or below) the lowermost first layer 22 z. Regardless, the channel opening 25 may taper radially inward (not shown), moving deeper into the upper stack portion 18U.

Referring to fig. 5 and 6, pillars 60 (not shown) have been removed (e.g., by isotropic etching) through channel openings 25, thereby effectively extending channel openings 25 into the individual void spaces 61 created by the removal of pillars 60 and to the lowermost first layer 22 z. Those skilled in the art will be able to select a suitable isotropic etch chemistry that will selectively etch the post material 15 relative to other exposed materials.As examples, tungsten material 15 may use a mixture of ammonia and hydrogen peroxide or a mixture of sulfuric acid and hydrogen peroxide versus SiO₂And Si₃N₄Selectively etching isotropically.

Referring to fig. 7-10, transistor channel material 36 has been formed vertically along the first and second layers in the respective channel openings 25 and void spaces 61. The channel material 36 will be electrically coupled directly to the conductive material 17 in the conductor layer 16. The individual memory cells of the example memory array formed may include a gate region (e.g., a control gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, a memory structure is formed that includes a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge transport material. The storage material (e.g., floating gate material, such as doped or undoped silicon, or charge trapping material, such as silicon nitride, metal dots, etc.) of individual memory cells is vertically along the individual charge blocking regions. An insulating charge transport material (e.g., a band gap engineered structure having a nitrogen-containing material [ e.g., silicon nitride ] sandwiched between two insulator oxides [ e.g., silicon dioxide ]) is laterally between the channel material and the memory material. Fig. 10 and 11 show an embodiment in which charge blocking material 30, storage material 32 and charge transport material 34 have been formed in respective channel openings 25 vertically along insulating layer 20 and conductive layer 22. Transistor materials 30, 32, and 34 (e.g., memory cell materials) may be formed by, for example, depositing respective thin layers thereof over stack 18 and within respective channel openings 25, followed by planarizing such transistor materials back to at least the top surface of stack 18. Channel material 36 and materials 30, 32, and 34 can be collectively considered to comprise individual channel material string structures 53 that extend through first layer 22 and second layer 20 in upper portion 18U to lowermost first layer 22z in lower portion 18L.

Channel material 36 may be considered to have its lowermost surface 71. In one embodiment, the channel material string structures 53 have memory cell material (e.g., 30, 32, and 34) along them, and wherein the second layer of material (e.g., 24) is horizontally between immediately adjacent channel material string structures 53. Due to the proportions, materials 30, 32, 34, and 36 are shown collectively in fig. 13 and 14 and are designated only as material 37. Example channel material 36 includes appropriately doped crystalline semiconductor material such as one or more of silicon, germanium, and so-called III/V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness for each of materials 30, 32, 34, and 36 is 25-100 angstroms. A punch etch may be performed to remove materials 30, 32, and 34 from the base (not shown) of the channel opening 25 to expose the conductor layer 16 such that the channel material 36 is directly against the conductor material 17 of the conductor layer 16. Such punch etching may occur separately with respect to each of materials 30, 32, and 34 (as shown), or may occur with respect to only some (not shown). Alternatively and by way of example only, no stamping etch may be performed, and channel material 36 may be directly electrically coupled to conductor material 17 of conductor layer 16 only by separate conductive interconnects (not shown). The channel opening 25 is shown as comprising a radially central solid dielectric material 38 (e.g., a spin-on dielectric, silicon dioxide, and/or silicon nitride). Alternatively, and by way of example only, the radially central portion within the channel opening 25 may include void space (not shown) and/or be free of solid material (not shown).

In one embodiment, the channel material string structures 53 may be considered to include upper portions 70 over and joined with lower portions 72, respectively. Individual channel material string structures 53 include at least one external bend surface 75 (fig. 10) in vertical cross-section (e.g., the vertical cross-sections of fig. 8 and 10), wherein upper portion 70 and lower portion 72 are joined (i.e., "bend surface" herein is characterized by an abrupt change in direction [ at least 15 ° ] as compared to the outer surface of the channel material string structure directly above and below the bend surface). As a result of the radially inward taper of the channel opening 25 moving deeper into the upper stacking portion 18U, one or more folding surfaces 75 may be formed, as compared to the larger uppermost radial extent of the void space 61 left by the removal of the post 60 (as shown). Alternatively and/or additionally, for example as described below, one or more bending surfaces 75 may result from misalignment of channel opening 25 relative to prior pillars 60 (not shown in fig. 7-10).

In one embodiment, at least one outer inflection surface 75 is horizontal (as shown) or within 10 ° of horizontal. Example individual channel material string structures 53 include two angled surfaces 75 and, in one embodiment, are vertically angled relative to each other (each horizontal in one example and thus each angled 90 ° from vertical).

FIG. 11 illustrates an example alternate embodiment configuration 10 a. The same reference numerals have been used for the above-described embodiments where appropriate, with some construction differences being indicated with the suffix "a" or with different reference numerals. Individual channel material string structures 53a include only one bending surface 75a, which may occur, for example, due to slight misalignment of channel opening 25 with respect to prior pillars 60. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

FIG. 12 shows an example alternate embodiment construction 10 b. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "b" or with different numerals. Individual channel material string structures 53b include at least one bending surface 75b that is not horizontal (e.g., two bending surfaces 75b are shown, one horizontal and the other not horizontal). In one embodiment, non-horizontal angled surface 75b is greater than 10 ° from horizontal, in one such implementation at least 22.5 ° from horizontal, and in one such embodiment at least 45 ° from horizontal (exhibiting about 66 ° from horizontal, and thus about 24 ° from each of the example extremes; the vertical surface of channel material string structure 53 is above and below angled surface 75 b). Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

Fig. 13 shows an example alternative embodiment construction 10c in which individual channel material string structures 53c include angled surfaces 75c (one to the left) at 45 ° from horizontal. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "b" or with different numerals. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

Referring to fig. 14 and 15, horizontally elongated trenches 40 have been formed into stack 18 (e.g., by anisotropic etching) and are respectively between and extend to lines 13 between laterally immediately adjacent memory block regions 58.

Referring to fig. 16 and 17, the second sacrificial material 15 (not shown) of the lines 13 (not shown) has been removed by the trenches 40 (by an isotropic etch using a mixture of ammonia and hydrogen peroxide or a mixture of sulfuric acid and hydrogen peroxide if the material 15 comprises tungsten). Finally, an intervening material (not shown) is formed in the trenches 40 and void spaces left by the removal of the second sacrificial material 15 of the lines 13.

Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments. In some embodiments, other and/or additional processing occurs, e.g., as described below.

Referring to fig. 18 and 19, the trenches 40 have optionally been lined with a liner material 35 (e.g., 35 is hafnium oxide, aluminum oxide, silicon dioxide, silicon nitride, etc.). Liner material 35 may be partially or completely sacrificial and is desirably a composition other than the composition of materials 24 and 26. After deposition of the liner material 35, the liner material has been substantially removed from the horizontal surfaces, e.g., by its maskless anisotropic spacer-like etch.

Referring to fig. 20 and 21, trench 40 has been extended to conductor material 17 of conductor layer 16 (e.g., by etching through materials 27, 77, and 24).

Referring to fig. 22-24, a first sacrificial material 77 (not shown) has been isotropically etched (e.g., using liquid or gaseous H) from the lowermost first layer 22z through the trenches 40₃PO₄As a primary etchant, where material 77 is silicon nitride and the other materials exposed include one or more oxides or polysilicon, or using tetramethylammonium hydroxide [ TMAH ]]Where material 77 is polysilicon). If the first layer of material 26 and the first sacrificial material 77 are of the same composition, the sidewalls of the first layer of material 26 have been masked by a liner material 35, which is a linerThe material prevents etching of material 26 when etching first sacrificial material 77.

In one embodiment, sidewalls of channel material of the channel material string structure in the lowermost first layer are exposed. Fig. 25 and 26 show an example such subsequent processing in which, in one embodiment, material 30 (e.g., silicon dioxide), material 32 (e.g., silicon nitride), and material 34 (e.g., silicon dioxide or a combination of silicon dioxide and silicon nitride) have been etched in layer 20z to expose sidewalls 41 of channel material 36 of channel material string structures 53 in the lowermost first layer 22 z. Any of the materials 30, 32, and 34 in layer 22z may be considered a sacrificial material therein. As an example, consider an embodiment in which material 35 is one or more insulating oxides (other than silicon dioxide), materials 47 and 36 are polysilicon, and memory cell materials 30, 32, and 34 are one or more of a silicon dioxide layer and a silicon nitride layer, respectively. In such an example, the depicted construction can be produced by using a modified or different chemistry to selectively sequentially etch silicon dioxide and silicon nitride relative to another chemistry. As an example, a 100:1 (by volume) solution of water and HF would selectively etch silicon dioxide relative to silicon nitride, while a 1000:1 (by volume) solution of water and HF would selectively etch silicon nitride relative to silicon dioxide. Thus, and in such an example, such etch chemistries may be used in an alternating fashion where it is desired to achieve the example configuration shown by fig. 25 and 26. Those skilled in the art will be able to select other chemistries for etching other different materials where the configuration shown in fig. 25 and 26 is desired.

Referring to fig. 27 and 28, and in one embodiment, conductive material 42 has been deposited into the void spaces in the lowermost first layer 22z left by the removal of the first sacrificial material 77. In one such embodiment, the conductive material 42 is directly against the exposed sidewalls 41 of the channel material 36 of the channel material string structures 53 in the lowermost first layer 22z and, in one embodiment, directly against the uppermost surface 19 of the conductor material 17 of the conductor layer 16. This is but one example whereby conductive material 42 has been deposited to directly electrically couple together channel material 36 of individual channel material string structures 53 and conductor material 17 of conductor layer 16 (e.g., through channel material sidewalls 41). Example conductive materials 42 are conductively-doped semiconductor materials (e.g., conductively-doped polysilicon) and metal materials. The conductive material 42 may be directly against the first layer of material 47. Conductive material 42 may not be directly against first layer of material 47 (not shown), for example, if a silicon nitride layer (not shown and mentioned above) is between second material 27 (not shown) and first layer of material 47. The first layer of material 47 may or may not be in the finished construction and, if so, may be circuit inactive or circuit active.

Referring to fig. 29 and 30, conductive material 42 has been removed from trenches 40, such as by a timed isotropic or anisotropic etch that may be selectively conducted relative to materials 24, 26, 17 and 47. This may result in the removal of the liner material 35 as shown, or this material may be removed separately. Alternatively, the liner material 35 may have been removed earlier (not shown). The reason for removing the liner material 35 is to provide access to the material 26 in the second layer 22 for its removal in a replacement gate process. When exposed (not shown), the etching of conductive material 42 may result in some etching of conductive material 17. Example etch chemistries are anisotropic (HBr) and isotropic (TMAH) where material 42 is conductively doped polysilicon, material 24 is silicon dioxide, and material 26 is silicon dioxide.

Referring to fig. 31 and 32, an optional selective oxidation has been performed, thus forming an oxide layer 45 (e.g., silicon dioxide).

Referring to fig. 33-38, material 26 (not shown) of conductive layer 22 has been removed (e.g., using liquid or gaseous H) such as by isotropically etching away through trench 40 desirably selective to other exposed materials₃PO₄As the main etchant, where material 26 is silicon nitride and the other materials include one or more oxides or polysilicon). In an example embodiment, material 26 (not shown) in conductive layer 22 is sacrificial and has been replaced with conductive material 48, and has thereafter been removed from trenches 40, thus forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and/or memory cells 56.

Can be shapedFormation of a thin insulating liner (e.g., Al) prior to formation of conductive material 48₂O₃And not shown). The approximate locations of transistors and/or memory cells 56 are indicated in parenthesis in fig. 38, while some are indicated in dashed outline in fig. 33, 35, and 37, with transistors and/or memory cells 56 being substantially ring-shaped or ring-shaped in the depicted example. Alternatively, the transistors and/or memory cells 56 may not completely surround with respect to the individual channel openings 25 such that each channel opening 25 may have two or more vertically extending strings 49 (e.g., in individual conductive layers, a plurality of transistors and/or memory cells surround the individual channel openings, where there may be multiple word lines per channel opening in the individual conductive layers, and not shown). Conductive material 48 can be considered to have ends 50 corresponding to control gate regions 52 of individual transistors and/or memory cells 56 (fig. 38). In the depicted embodiment, the control gate regions 52 comprise individual portions of individual conductive lines 29. Materials 30, 32, and 34 may be considered memory structure 65 located laterally between control gate region 52 and channel material 36. In one embodiment and as shown with respect to the example "gate last" process, conductive material 48 of conductive layer 22 is formed after forming channel openings 25 and/or trenches 40. Alternatively, such as with respect to a "gate first" process, the conductive material of the conductive layer may be formed prior to forming the channel opening 25 and/or the trench 40 (not shown).

A charge blocking region, such as charge blocking material 30, is between the storage material 32 and the respective control gate region 52. The charge barrier may have the following functions in the memory cell: in a program mode, the charge blocking member may prevent charge carriers from flowing from the storage material (e.g., floating gate material, charge trapping material, etc.) to the control gate, and in an erase mode, the charge blocking member may prevent charge carriers from flowing from the control gate to the storage material. Thus, the charge barriers may be used to block charge migration between the control gate region and the storage material of the individual memory cell. The example charge blocking region as shown includes an insulator material 30. By way of further example, the charge blocking region may comprise a laterally (e.g., radially) outer portion of a memory material (e.g., material 32), wherein such memory material is insulative (e.g., in the absence of any different composition material between the insulative memory material 32 and the conductive material 48). Regardless, as an additional example, the interface of the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region in the absence of any separate composition insulator material 30. Furthermore, the interface of conductive material 48 and material 30 (if present) in combination with insulator material 30 may function together as a charge blocking region and may alternatively or additionally function as a laterally outer region of an insulating memory material, such as silicon nitride material 32. Example material 30 is one or more of hafnium oxide and silicon dioxide.

In one embodiment and as shown, the lowermost surface 71 of the channel material 36 of the channel material string structure 53 never directly abuts against any of the conductor materials 17 of the conductor layer 16.

Intervening material 57 has been formed in trenches 40 and void spaces left by removal of second sacrificial material 15 of lines 13, and thus laterally between and longitudinally along laterally immediately adjacent memory blocks 58. Intervening material 57 may provide lateral electrical isolation (insulation) between laterally immediately adjacent memory blocks. This may include one or more of insulating, semiconductive, and conductive materials, and in any event, may help prevent shorting of conductive layers 22 relative to one another in the finished circuitry construction. Example insulating material is SiO₂、Si₃N₄、Al₂O₃And undoped polysilicon. Intervening material 57 may include through-array vias (not shown). Some of the material in trench 40 formed prior to forming the material designated as intervening material 57 may remain and thus comprise a portion of intervening material 57. Regardless, in one embodiment, at least a majority of intervening material 57 is formed in the trenches and void spaces after conductive material 42 is formed.

Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.

FIGS. 39, 40 and 41 show example resulting constructions 10a, 10b and 10c, respectively, that can be produced by FIGS. 11, 12 and 13, respectively. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

FIGS. 42 and 43 show an example alternate embodiment construction 10d in process according to an embodiment of the present disclosure. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "d" or with different numerals. Fig. 42 corresponds to fig. 2 in the processing sequence. Construction 10d has individual wires 13d with bottom surfaces 59 that are lower than tops 73 of the lowermost first layer 22 z. Further, in one such embodiment and as shown, the wires 13d each include laterally opposing protrusions 54 in the lowermost first layer 22z longitudinally therealong. Processing similar to and/or alternative to that shown and described above may occur to produce construction 10d as shown in fig. 43 (which corresponds in sequence and view to the construction of fig. 35 of the first described embodiment). Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

An alternative method is described with reference to fig. 44 to 48. The same reference numerals have been used, where appropriate, for the above-described embodiments, with some construction differences being indicated with the suffix "e" or with different reference numerals. Fig. 44 corresponds to fig. 2 in the processing sequence. Example configuration 10e conductor material 17 with conductor layer 16 including lower conductor material 44 of a different composition than upper conductor material 43 (e.g., WSi)_x) An upper conductor material 43 (e.g., n-type or p-type conductively doped polysilicon) directly above (e.g., directly against). The second layer 20x, which is directly above the lowermost first layer 22z, comprises undoped polysilicon 51 (and second layer materials/layers 27 and 24). A silicon nitride layer (not shown) may be between second material 27 and undoped polysilicon 51, and thus be part of insulating layer 20 x. A horizontal elongated groove 79 has been formed in the lower portion 18L and extends to the conductor layer 16.

Referring to fig. 45 and 46, the exposed portions of the conductor material 43 and undoped polysilicon 51 of the conductor layer 16 have been oxidized, thereby forming an insulating oxide 45 (e.g., silicon dioxide; e.g., longitudinally along what would be line 13 e).

Thereafter and with reference to fig. 47, horizontally extending lines 13e have been formed in the grooves 79 and respectively between the laterally immediately adjacent memory block regions 58. The example line 13e includes a second sacrificial material 15. In one embodiment, the bottom surface 59 of the individual wire 13e is in the conductor layer 16, and in one such embodiment, not directly against its conductor material (e.g., due to the presence of the insulating oxide 45).

Processing similar to and/or alternative to that shown and described above may occur to produce construction 10e as shown in fig. 48 (which corresponds in sequence and view to the construction of fig. 35 of the first described embodiment). Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

Alternative methods to those shown and described with reference to fig. 44-48 are described with reference to fig. 49-53. Like numerals from the above-described embodiments have been used where appropriate, with certain construction differences being indicated with the suffix "f" or with different numerals. Fig. 49 and 50 correspond collectively to fig. 44 and 46 in the processing sequence. The undoped polysilicon 51 has been recessed laterally (e.g., by isotropic etching) to form laterally opposite notches 78 longitudinally along the respective grooves 79. In one embodiment, as shown, laterally opposing notches 78 have also been formed in conductor material 17.

Referring to fig. 51 and 52, horizontally extending lines 13f (including second sacrificial material 15) have been formed in recesses 79 and between laterally immediately adjacent memory block regions 58, respectively. The wires 13f include laterally opposing projections 66 longitudinally therealong in laterally opposing recesses 78, respectively. In one embodiment, the line 13f includes a bottom surface 59 in the conductor layer 16. In one embodiment in which laterally opposite notches 78 have also been formed in the conductor material 43, the wires 13f also include laterally opposite projections 54 longitudinally therealong in the laterally opposite notches 78 in the conductor material 43, respectively.

Processing similar to and/or alternative to that shown and described above may occur to produce the construction 10f as shown in fig. 53 (which corresponds in sequence and view to the construction of fig. 35 of the first described embodiment). Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

In some embodiments, a method for forming a memory array (e.g., 12) including a string (e.g., 49) of memory cells (e.g., 56) includes forming a lower portion (e.g., 18L) of a stack (e.g., 18), which will include vertically alternating first (e.g., 22) and second (e.g., 20) layers. The stack includes laterally spaced memory block regions (e.g., 58). The material of the first layer has a different composition than the material of the second layer. Pillars (e.g., 60) are formed in the lower portion and are respectively positioned horizontally, wherein individual channel material string structures (e.g., 53) are to be formed. The posts comprise a sacrificial material (e.g., 15). Vertically alternating first and second layers of an upper portion (e.g., 18U) of the stack are formed over the lower portion and the pillars. Channel openings (e.g., 25) are formed into the stack and extend to the individual pillars, respectively. The sacrificial material of the pillars is removed through the trench openings to extend the trench openings deeper into the stack. A trench material string structure is formed in the elongated trench opening and in the void space therein created by the removal of the pillars. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

In some embodiments, a method for forming a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes forming a conductor layer (e.g., 16) including a conductor material (e.g., 17) on a substrate (e.g., 11). A lower portion (e.g., 18L) of a stack (e.g., 18) including vertically alternating first (e.g., 22) and second (e.g., 20) layers is formed over the conductor layer. The stack includes laterally spaced memory block regions (e.g., 58). The material of the first layer has a different composition than the material of the second layer. The lowermost first layer (e.g., 22z) includes a first sacrificial material (e.g., 77). Pillars (e.g., 60) are formed in the lowermost first layer and are respectively positioned horizontally, wherein individual channel material string structures (e.g., 53) are to be formed. The posts comprise a second sacrificial material (e.g., 15). Vertically alternating first and second layers of an upper portion (e.g., 18U) of the stack are formed over the lower portion and the pillars. Channel openings (e.g., 25) are formed into the stack and extend to the individual pillars, respectively. The second sacrificial material of the pillars is removed through the channel openings to extend the channel openings deeper into the stack. A trench material string structure is formed in the elongated trench opening and in the void space therein created by the removal of the pillars. Horizontally elongated trenches (e.g., 40) are formed into the stack and between laterally immediately adjacent memory block regions and extending into the first sacrificial material in the lowermost first layer, respectively. The first sacrificial material is isotropically etched from the lowermost first layer through the trench. After the isotropic etch, a conductive material (e.g., 42) is formed in the lowermost first layer that directly electrically couples together the channel material of the individual channel material string structures and the conductor material of the conductor layer. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

Alternative embodiment configurations may result from the method embodiments described above or otherwise. Regardless, embodiments of the present invention encompass memory arrays that are independent of the method of fabrication. Nonetheless, such memory arrays may have any of the attributes as described herein in method embodiments. Likewise, the method embodiments described above may incorporate, form, and/or have any of the attributes described with respect to the device embodiments.

In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes a conductor layer (e.g., 16) including a conductor material (e.g., 17). The memory array includes laterally spaced memory blocks (e.g., 58) that each include a vertical stack (e.g., 18) that includes alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). The channel material string structure (e.g., 53) of the memory cell extends through the insulating layer and the conductive layer. The channel material string structures each include an upper portion (e.g., 70) above and joined with a lower portion (e.g., 72). The individual channel material string structures include at least one outer inflection surface (e.g., 75a, 75b, 75c) in vertical cross-section where the upper and lower portions join. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

The above processes or configurations may be considered relative to an array of components that form or are within a single stack or single deck of such components, either above or as part of an underlying base substrate (although a single stack/deck may have multiple layers). Control and/or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the final construction, and in some embodiments may be underneath the array (e.g., CMOS underneath the array). Regardless, one or more additional such stacks/levels may be provided or fabricated above and/or below the stacks/levels shown in the figures or described above. Further, the arrays of components may be the same or different relative to each other in different stacks/levels, and the different stacks/levels may have the same thickness or different thicknesses relative to each other. Intervening structures may be disposed between vertically immediately adjacent stacks/layers (e.g., additional circuitry and/or dielectric layers). Also, different stacks/layers may be electrically coupled with respect to each other. Multiple stacks/levels may be fabricated separately and sequentially (e.g., one on top of the other), or two or more stacks/levels may be fabricated substantially simultaneously.

The assemblies and structures discussed above may be used in integrated circuits/circuitry and may be incorporated in electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic system may be any of a wide range of systems: such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular telephones, personal computers, automobiles, industrial control systems, aircraft, and so forth.

In this document, "vertical," higher, "" upper, "" lower, "" top, "" bottom, "" above, "" below, "" in. "horizontal" refers to the general direction along the main substrate surface (i.e., within 10 degrees) that a substrate may be opposing during fabrication, and vertical is a direction generally orthogonal thereto. Reference to "exactly horizontal" is along the direction of the main substrate surface (i.e., not at an angle thereto) in which the handle substrate may be opposing during fabrication. Further, "vertical" and "horizontal" as used herein are generally vertical directions relative to each other and are independent of the orientation of the substrate in three-dimensional space. Additionally, "vertically extending" and "vertically extending" refer to directions that are inclined at least 45 ° from exactly horizontal. Furthermore, with regard to field effect transistors "vertically extending", "horizontally extending" etc. are references to the orientation of the channel length of the transistor along which, in operation, current flows between source/drain regions. For a bipolar junction transistor, "vertically extending," "horizontally extending," etc., are orientations with reference to the length of the substrate along which, in operation, current flows between the emitter and collector. In some embodiments, any component, feature, and/or region that extends vertically or within 10 ° of vertical.

Further, "directly above," "directly below," and "directly below" require at least some lateral overlap (i.e., horizontally) of the two recited regions/materials/components with respect to each other. Also, the use of "over" without "right before merely requires that some portion of the stated region/material/component above the other stated region/material/component be vertically outward from the other stated region/material/component (i.e., independent of whether there is any lateral overlap of the two stated regions/material/components). Similarly, the use of "under" and "below" without "positive" above merely requires that some portion of the stated region/material/component under/below another stated region/material/component be vertically inward of the other stated region/material/component (i.e., regardless of whether there is any lateral overlap of the two stated regions/materials/components).

Any of the materials, regions, and structures described herein may be uniform or non-uniform, and in any event may be continuous or discontinuous over any material that it overlies. When one or more example compositions are provided for any material, the material can comprise, consist essentially of, or consist of such one or more compositions. Additionally, unless otherwise noted, each material may be formed using any suitable existing or future-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

Additionally, "thickness" (the preceding non-directional adjectives), used alone, is defined as the average straight-line distance perpendicularly through a given material or region from the nearest surface of the immediately adjacent material or region having a different composition. In addition, the various materials or regions described herein can have a substantially constant thickness or have a variable thickness. If having a variable thickness, the thickness refers to an average thickness unless otherwise indicated, and the material or region will have some minimum thickness and some maximum thickness due to the variable thickness. As used herein, "different compositions" only requires that those portions of two recited materials or regions that may be directly against each other be chemically and/or physically different, such as where such materials or regions are not homogeneous. If two recited materials or regions are not directly against each other, then "different compositions" merely requires that those portions of the two recited materials or regions that are closest to each other be chemically and/or physically different, in cases where such materials or regions are not homogeneous. In this document, a material, region or structure is "directly against" another material, region or structure when the stated materials, regions or structures are in at least some physical contact with respect to each other. In contrast, the absence of "directly" preceding "above," "on," "adjacent," "along," and "against" encompass "directly against" as well as configurations in which intervening materials, regions, or structures are in no physical contact with one another.

Herein, zone-material-components are "electrically coupled" with respect to each other if, in normal operation, an electrical current is able to flow continuously from one zone-material-component to another zone-material-component, and the flow is primarily by movement of the subatomic positive and/or negative charge when it is sufficiently generated. Another electronic component may be between and electrically coupled to the zone-material-component. In contrast, when a region-material-component is referred to as "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-component.

Any use of "rows" and "columns" herein is for convenience in distinguishing one series or orientation of features from another, and components have been or may be formed along the "rows" and "columns". "Row" and "column" are used synonymously with respect to any series of regions, components, and/or features, regardless of function. Regardless, the rows can be straight and/or curved and/or parallel and/or non-parallel with respect to one another, as can the columns. Further, the rows and columns may intersect at 90 ° or at one or more other angles (i.e., other than straight angles) relative to each other.

The composition of any of the conductive/conductor/conductive materials herein can be a metallic material and/or a conductively doped semiconductive/semiconductor/semiconductive material. A "metallic material" is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

Any use of "selectivity" with respect to etching (etching/ablating), removing/removing, depositing/forming, is herein such an action of one recited material in a ratio of at least 2:1 by volume relative to another recited material acted upon. Additionally, any use of selectively depositing, selectively growing, or selectively forming is a deposition, growth, or formation of one material relative to another or more stated materials by a ratio of at least 2:1 by volume up to at least a first 75 angstroms.

Unless otherwise indicated, use of "or" herein encompasses either and both.

Conclusion

In some embodiments, a method for forming a memory array comprising a string of memory cells comprises: a lower portion of a stack is formed on a substrate that will include vertically alternating first and second layers. The stack includes laterally spaced apart memory block regions. The material of the first layer has a different composition than the material of the second layer. Pillars are formed in the lower portion and are respectively positioned horizontally, wherein individual channel material string structures are to be formed. The posts comprise a sacrificial material. Vertically alternating first and second layers of an upper portion of the stack are formed over the lower portion and the pillars. Channel openings are formed into the stack and extend to the individual pillars, respectively. The sacrificial material of the pillars is removed through the trench openings to extend the trench openings deeper into the stack. A channel material string structure is formed in the elongated channel opening and in void spaces therein resulting from the removal.

In some embodiments, a method for forming a memory array including strings of memory cells includes forming a conductor layer including a conductor material on a substrate. A lower portion of a stack including vertically alternating first and second layers is formed over a conductor layer. The stack includes laterally spaced apart memory block regions. The material of the first layer has a different composition than the material of the second layer. The lowermost first layer comprises a first sacrificial material. Pillars are formed in the lowermost first layer and are respectively positioned horizontally, wherein individual channel material string structures will be formed. The pillars comprise a second sacrificial material. Vertically alternating first and second layers of an upper portion of the stack are formed over the lower portion and the pillars. Channel openings are formed into the stack and extend to the individual pillars, respectively. The second sacrificial material of the pillars is removed through the channel openings to extend the channel openings deeper into the stack. A channel material string structure is formed in the elongated channel opening and in void spaces therein resulting from the removal. Horizontal elongated trenches are formed into the stack and between laterally immediately adjacent memory block regions and extending into the first sacrificial material in the lowermost first layer, respectively. The first sacrificial material is isotropically etched from the lowermost first layer through the trench. After the isotropic etching, a conductive material is formed in the lowermost first layer that directly electrically couples together the channel material of the individual channel material string structures and the conductor material of the conductor layer.

In some embodiments, a method for forming a memory array including strings of memory cells includes forming a conductor layer including a conductor material on a substrate. A lower portion of a stack including vertically alternating first and second layers is formed over a conductor layer. The stack includes laterally spaced apart memory block regions. The material of the first layer has a different composition than the material of the second layer. The lowermost first layer comprises a first sacrificial material. The next lowest first layer comprises conductively doped polysilicon. Horizontally extending lines are formed in the second lowest first layer, the horizontally extending lines being respectively between laterally immediately adjacent memory block regions. The line includes a second sacrificial material having a different composition than the material of the first layer formed or to be formed over the first sacrificial material, the material of the second layer formed or to be formed over the first sacrificial material, and the material of the next lowest first layer. Vertically alternating first and second layers of an upper portion of the stack are formed over the lower portion and the line. A channel material string structure is formed that extends through the first and second layers in the upper portion to a lowermost first layer in the lower portion. Horizontal elongated trenches are formed into the stack, the horizontal elongated trenches respectively between and extending to lines between laterally immediately adjacent memory block regions. The second sacrificial material of the line is removed through the trench. An intervening material is formed in the trenches and void spaces left by the removal of the second sacrificial material of the lines.

In some embodiments, a method for forming a memory array including strings of memory cells includes forming a conductor layer including a conductor material on a substrate. A lower portion of a stack including vertically alternating first and second layers is formed over a conductor layer. The stack includes laterally spaced apart memory block regions. The material of the first layer has a different composition than the material of the second layer. The lowermost first layer comprises a first sacrificial material. The second layer of material of the second layer directly above the lowermost first layer comprises undoped polysilicon. A horizontal elongated groove is formed in the lowermost portion and extends to the conductor layer. The exposed portions of the conductor material and the undoped polysilicon of the conductor layer are oxidized. After oxidation, horizontally extending lines are formed in the grooves between laterally immediately adjacent memory block regions, respectively. The line comprises a second sacrificial material. Vertically alternating first and second layers of an upper portion of the stack are formed over the lower portion and the line. A channel material string structure is formed that extends through the first and second layers in the upper portion to a lowermost first layer in the lower portion. Horizontal elongated trenches are formed into the stack, the horizontal elongated trenches respectively between and extending to lines between laterally immediately adjacent memory block regions. The second sacrificial material of the line is removed through the trench. An intervening material is formed in the trenches and void spaces left by the removal of the second sacrificial material of the lines.

In some embodiments, a method for forming a memory array including strings of memory cells includes forming a conductor layer including a conductor material on a substrate. A lower portion of a stack including vertically alternating first and second layers is formed over a conductor layer. The stack includes laterally spaced apart memory block regions. The material of the first layer has a different composition than the material of the second layer. The lowermost first layer comprises a first sacrificial material. The second layer of material of the second layer directly above the lowermost first layer comprises undoped polysilicon. A horizontal elongated groove is formed in the lowermost portion and extends to the conductor layer. The undoped polysilicon is recessed laterally to form laterally opposite notches longitudinally along the respective grooves. After recessing, horizontally extending lines are formed in the grooves between the laterally immediately adjacent memory block regions, respectively. The wires include laterally opposing projections longitudinally therealong in the laterally opposing recesses, respectively. The line comprises a second sacrificial material. Vertically alternating first and second layers of an upper portion of the stack are formed over the lower portion and the line. A channel material string structure is formed that extends through the first and second layers in the upper portion to a lowermost first layer in the lower portion. Horizontal elongated trenches are formed into the stack, the horizontal elongated trenches respectively between and extending to lines between laterally immediately adjacent memory block regions. The second sacrificial material of the line is removed through the trench. An intervening material is formed in the trenches and void spaces left by the removal of the second sacrificial material of the lines.

In some embodiments, a memory array including a string of memory cells includes laterally spaced memory blocks each including a vertical stack including alternating insulating and conductive layers. The channel material string structure of the memory cell extends through the insulating layer and the conductive layer. The channel material string structures each include an upper portion above and joined to a lower portion. The individual channel material string structures include at least one outer inflection surface in a vertical cross-section where the upper and lower portions join.

In accordance with the provisions, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the devices disclosed herein include example embodiments. The claims are, therefore, to be accorded the full scope as literally set forth and appropriately interpreted in accordance with the doctrine of equivalents.