阅读说明：本技术 三维闪存以及制造该三维闪存的方法 (Three-dimensional flash memory and method of manufacturing the same ) 是由 宋润洽 于 2020-04-02 设计创作，主要内容包括：公开了一种三维闪存以及制造该三维闪存的方法。根据一个实施方式,三维闪存可以具有用于实现集成的结构,并可以通过有效率地形成字线的制造方法来制造。(A three-dimensional flash memory and a method of manufacturing the same are disclosed. According to one embodiment, a three-dimensional flash memory may have a structure for realizing integration and may be manufactured by a manufacturing method of efficiently forming word lines.)

1. A three-dimensional flash memory implementing integration, the three-dimensional flash memory comprising:

at least one memory cell string vertically extending and including at least one channel layer and at least one charge storage layer surrounding the at least one channel layer; and

a plurality of word lines orthogonally connected to the at least one memory cell string and stacked, and extending in a horizontal direction, wherein the plurality of word lines extend at lengths different from each other to form a stepped shape including a stepped portion and a planar portion,

wherein the at least one memory cell string is formed in both the planar portion and the step portion.

2. The three-dimensional flash memory of claim 1, wherein the contact of each of the plurality of word lines is formed only in a minimized partial region of each of the plurality of steps of the step portion.

3. The three-dimensional flash memory of claim 2, wherein the minimized partial region comprises a region corresponding to a cross-sectional area of the contact of each of the plurality of word lines.

4. The three-dimensional flash memory of claim 1, wherein for each step of the step portion, the at least one memory cell string formed in the step portion is located in a same column as a contact of each word line formed in the step portion.

5. A three-dimensional flash memory implementing integration, the three-dimensional flash memory comprising:

at least one memory cell string extending in a direction and including at least one channel layer and at least one charge storage layer surrounding the at least one channel layer; and

a plurality of word lines vertically connected to the at least one memory cell string,

wherein the contact of each of the plurality of word lines is formed only in a minimized partial area of an entire area of each of the plurality of word lines.

6. The three-dimensional flash memory of claim 5, wherein the plurality of word lines provide a space where at least one other memory cell string is formed that is not arranged in the same array as the at least one memory cell string, since the contact of each of the plurality of word lines is formed only in a minimized partial area in an entire area of each of the plurality of word lines.

7. The three-dimensional flash memory of claim 6, wherein the plurality of word lines are shared by the at least one memory cell string and the at least one other memory cell string due to the at least one other memory cell string being formed in the space.

8. The three-dimensional flash memory of claim 6, wherein the minimized partial area at which the contact of each of the plurality of word lines is formed comprises an area in the same row as an entire area of each of the plurality of word lines.

9. A method of fabricating a three-dimensional flash memory for efficiently forming word lines, the method comprising:

preparing a plurality of word lines stacked in a horizontal direction by dividing the plurality of word lines into an upper word line group and a lower word line group, wherein the upper word line group and the lower word line group have different horizontal sizes and are sequentially stacked in a staircase shape such that at least a portion of an upper surface of each of the upper word line group and the lower word line group is exposed;

forming a photoresist on at least a portion of the upper surface of the upper word line group and at least a portion of the upper surface of the lower word line group; and

an etching operation is simultaneously performed on each of the upper word line group and the lower word line group on which the photoresist is formed.

10. The method of claim 9, wherein the lower set of word lines has a larger horizontal dimension than the upper set of word lines.

11. The method of claim 9, wherein preparing the plurality of word lines by dividing the plurality of word lines into an upper word line group and a lower word line group comprises determining a horizontal size of the lower word line group to include an etch stop distance to prevent etching of a lowermost word line in the upper word line group when an etching operation is performed on the lower word line group.

12. The method of claim 9, wherein preparing the plurality of word lines by dividing the plurality of word lines into an upper word line group and a lower word line group comprises disposing an etch stop protective layer between the upper word line group and the lower word line group to prevent an uppermost word line in the lower word line group from being etched when an etching operation is performed on the upper word line group.

13. The method of claim 9, wherein performing the etching operation simultaneously on each of the upper word line group and the lower word line group is repeatedly performed based on a number of steps by which the word lines included in the upper word line group are stacked and a number of steps by which the word lines included in the lower word line group are stacked.

Technical Field

The following embodiments relate to a three-dimensional flash memory and a method of manufacturing the same.

Background

Flash memory is an electrically erasable programmable read-only memory (EEPROM) whose data input and output are electrically controlled by F-N tunneling (Fowler-Nordheim tunneling) or hot electron injection.

In recent flash memories, a three-dimensional structure has been applied in which cells are vertically stacked to increase integration in order to provide high performance and achieve a low price required by consumers. Referring to fig. 1 and 2 (which illustrate a three-dimensional flash memory according to the related art), a three-dimensional flash memory 100 has a structure including at least one memory cell string 110, a plurality of electrode layers 120, and a plurality of insulating layers 130, the at least one memory cell string 110 including a channel layer 111 extending in a vertical direction and a charge storage layer 112 formed to surround the channel layer 111, the plurality of electrode layers 120 being connected to the at least one memory cell string 110 in a horizontal direction and stacked, the plurality of insulating layers 130 being alternately formed between the plurality of electrode layers 120. Hereinafter, since each of the plurality of electrode layers 120 is used as a word line, the plurality of electrode layers 120 will be described as a plurality of word lines 120.

Here, a contact 121 to be connected to an external wiring will be formed on each of the plurality of word lines 120, and thus, the plurality of word lines 120 have a stair-step structure including a step portion 122 and a flat portion 123, as shown.

Here, only the contacts 121 of the plurality of word lines 120 are formed in the stepped portions 122, respectively, and only the at least one memory cell string 110 is formed in the planar portion 123. That is, the at least one memory cell string 110 having a memory function will be formed only on the planar portion 123, and thus, a large area of the three-dimensional flash memory 100 is wasted. Further, the larger the number of steps of the three-dimensional flash memory 100 is, the higher the ratio of the area of the step portion 122 to the total memory area is, thereby reducing the overall integration degree.

Therefore, it is necessary to provide a three-dimensional flash memory technology to improve the integration by efficiently using the stepped portion 122.

In addition, the contacts 121 of the plurality of word lines 120 are formed on the total stepped region of the plurality of word lines 120, respectively, and thus, a large amount of area of the three-dimensional flash memory 100 is wasted. In addition, the larger the number of steps of the three-dimensional flash memory 100 is, the higher the ratio of the area of the contact 121 with respect to the total memory area is, thereby reducing the overall integration.

Therefore, it is necessary to propose a three-dimensional flash memory technology to achieve integration by reducing an area for forming a contact.

Referring to fig. 10a to 10d regarding a method of manufacturing a three-dimensional flash memory according to the related art, according to the method, as shown in fig. 10a, a photoresist 1030 is formed on a mold structure in which a plurality of word lines 1010 and a plurality of insulating layers 1020 are alternately stacked, and the photoresist 1030 is trimmed, and then, as shown in fig. 10b, an etching operation is performed on an uppermost word line 1011 among the plurality of word lines 1010 to form a portion of a stepped shape. Next, in a method of manufacturing a three-dimensional flash memory according to the related art, as shown in fig. 10c, the photoresist 1030 is trimmed, and then, as shown in fig. 10d, an etching operation is performed on the word line 1011 and the word line 1012 (surfaces thereof are exposed) to form two portions having a stepped shape. In the method of manufacturing a three-dimensional flash memory according to the related art, the word line 1010 having a staircase shape may be completed by repeating the trimming operation and the etching operation as shown up to fig. 10j and then removing the photoresist 1030 as shown in fig. 10 k.

However, in the method of manufacturing the three-dimensional flash memory according to the related art, there is a disadvantage that the etching operation needs to be repeatedly performed less than the number of steps of the word line 1010 once.

Therefore, it is desirable to provide a technique for simplifying the manufacturing process of the word line by reducing the number of repetitions of the etching operation.

Disclosure of Invention

Technical problem

According to an embodiment, a three-dimensional flash memory and a method of manufacturing the same are provided to achieve integration by efficiently using a stepped portion.

Specifically, according to an embodiment, a three-dimensional flash memory and a method of manufacturing the same are proposed, in which at least one memory cell string is formed in both a planar portion and a stepped portion included in a stepped shape of a plurality of word lines.

Further, according to an embodiment, a three-dimensional flash memory and a method of manufacturing the same are proposed to achieve integration by reducing an area for forming a contact.

In particular, according to an embodiment, a three-dimensional flash memory and a method of manufacturing the same are proposed, in which a contact of each of the plurality of word lines is formed only in a minimized partial area (minimized partial area) in an entire area of each of the plurality of word lines.

Further, according to an embodiment, a method of manufacturing a three-dimensional flash memory is provided, in which a manufacturing process is simplified by reducing the number of repetitions of an etching operation for a word line.

Specifically, according to an embodiment, a method of manufacturing a three-dimensional flash memory is proposed, in which a plurality of word lines are prepared by dividing the plurality of word lines into an upper word line group and a lower word line group which are sequentially stacked in a staircase shape, and then an etching operation is simultaneously performed on each of the upper word line group and the lower word line group, thereby significantly reducing the number of repetitions of the etching operation on the word lines.

Further, according to an embodiment, a three-dimensional flash memory manufactured according to the above-described method of manufacturing a three-dimensional flash memory is proposed.

Specifically, according to an embodiment, there is provided a three-dimensional flash memory having a structure including a portion having a different height from other portions in a staircase shape when the staircase shape having an equal pitch width and an equal pitch height is formed by using a plurality of word lines.

Further, according to an embodiment, there is provided a three-dimensional flash memory having a structure including a portion having a different width from other portions in a stepped shape when the stepped shape having an equal pitch width and an equal pitch height is formed by using a plurality of word lines.

Further, according to an embodiment, there is provided a three-dimensional flash memory having a structure including a portion having a different height and a portion having a different width from other portions in a stepped shape when the stepped shape having an equally spaced width and an equally spaced height is formed by using a plurality of word lines.

Solution to the problem

According to one embodiment, a three-dimensional flash memory for implementing integration includes: at least one memory cell string vertically extending and including at least one channel layer and at least one charge storage layer surrounding the at least one channel layer; and a plurality of word lines orthogonally connected to the at least one memory cell string and stacked in parallel and extending in a horizontal direction, wherein the plurality of word lines extend in different lengths from each other to form a stepped shape including a stepped portion and a planar portion, wherein the at least one memory cell string is formed in both the planar portion and the stepped portion.

The contact of each of the plurality of word lines may be formed only in a minimized partial region of each of the plurality of steps of the step portion.

The minimized partial region may include a region corresponding to a cross-sectional area of a contact of each of the plurality of word lines.

The at least one memory cell string formed in the step part may be located in the same column as a contact of each word line formed in the step part for each step of the step part.

According to an embodiment, a three-dimensional flash memory for implementing integration includes: at least one memory cell string extending in a direction and including at least one channel layer and at least one charge storage layer surrounding the at least one channel layer; and a plurality of word lines vertically connected to the at least one memory cell string, wherein a contact of each of the plurality of word lines is formed only in a minimized partial area of an entire area of each of the plurality of word lines.

Since the contact of each of the plurality of word lines is formed only in a minimized partial area of the entire area of each of the plurality of word lines, the plurality of word lines may provide a space where at least one additional memory cell string, which is not arranged in the same array as the at least one memory cell string, is formed.

Since the at least one additional memory cell string is formed in the space, the plurality of word lines may be shared by the at least one memory cell string and the at least one additional memory cell string.

The minimized partial region where the contact of each of the plurality of word lines is formed may include a region located in the same row as the entire region of each of the plurality of word lines.

According to one embodiment, a method of fabricating a three-dimensional flash memory for efficiently forming word lines includes: preparing a plurality of word lines stacked in a horizontal direction by dividing the plurality of word lines into an upper word line group and a lower word line group, wherein the upper word line group and the lower word line group have different horizontal sizes and are sequentially stacked in a stepped shape such that at least a portion of an upper surface of each of the upper word line group and the lower word line group is exposed; forming a photoresist on at least a portion of an upper surface of the upper word line group and at least a portion of an upper surface of the lower word line group; and simultaneously performing an etching operation on each of the upper word line group and the lower word line group on which the photoresist is formed.

The lower word line group may have a larger horizontal size than the upper word line group.

Preparing the plurality of word lines by dividing the plurality of word lines into an upper word line group and a lower word line group may include determining a horizontal size of the lower word line group to include an etch stop distance to prevent etching of a lowermost word line in the upper word line group when an etching operation is performed on the lower word line group.

Preparing the plurality of word lines by dividing the plurality of word lines into an upper word line group and a lower word line group may include disposing an etch stop protective layer between the upper word line group and the lower word line group to prevent an uppermost word line in the lower word line group from being etched when an etching operation is performed on the upper word line group.

The simultaneous performing of the etching operation on each of the upper word line group and the lower word line group may be repeatedly performed based on the number of steps by which the word lines included in the upper word line group are stacked and the number of steps by which the word lines included in the lower word line group are stacked.

Advantageous effects of the disclosure

According to an embodiment, a three-dimensional flash memory and a method of manufacturing the same may be proposed to achieve integration by efficiently using a stepped portion.

In particular, according to an embodiment, a three-dimensional flash memory and a method of manufacturing the same may be proposed, in which at least one memory cell string is formed in both a planar portion and a stepped portion included in a stepped shape of a plurality of word lines.

Further, according to the embodiment, a three-dimensional flash memory and a method of manufacturing the same may be proposed to achieve integration by reducing an area for forming a contact.

In particular, according to an embodiment, a three-dimensional flash memory and a method of manufacturing the same may be proposed, in which a contact of each of the plurality of word lines is formed only in a minimized partial area in an entire area of each of the plurality of word lines.

Further, according to the embodiment, a method of manufacturing a three-dimensional flash memory may be proposed in which a manufacturing process is simplified by reducing the number of repetitions of an etching operation for a word line.

In particular, according to an embodiment, a method of manufacturing a three-dimensional flash memory may be suggested, according to which a plurality of word lines are prepared by dividing the plurality of word lines into an upper word line group and a lower word line group which are sequentially stacked in a staircase shape, and then an etching operation is simultaneously performed on each of the upper word line group and the lower word line group, thereby significantly reducing the number of repetitions of the etching operation on the word lines.

Further, according to an embodiment, a three-dimensional flash memory manufactured according to the above-described method of manufacturing a three-dimensional flash memory may be provided.

In particular, according to an embodiment, a three-dimensional flash memory having a structure including a portion having a different height from other portions in a staircase shape when the staircase shape having an equal pitch width and an equal pitch height is formed by using a plurality of word lines may be proposed.

Further, according to the embodiment, a three-dimensional flash memory having a structure including a portion having a different width from other portions in a stepped shape when the stepped shape having an equally spaced width and an equally spaced height is formed by using a plurality of word lines may be proposed.

Further, according to an embodiment, a three-dimensional flash memory having a structure including a portion having a different height and a portion having a different width from other portions in a staircase shape when the staircase shape having an equally spaced width and an equally spaced height is formed by using a plurality of word lines may be proposed.

Drawings

Fig. 1 is a plan view of a three-dimensional flash memory according to the related art.

Fig. 2 is a sectional view of a three-dimensional flash memory according to the related art.

Fig. 3 is a plan view of a three-dimensional flash memory according to an embodiment.

FIG. 4 is a cross-sectional view of a three-dimensional flash memory according to an embodiment.

Fig. 5 is a flow chart of a method of manufacturing a three-dimensional flash memory according to an embodiment.

Fig. 6a to 6i are diagrams for describing a method of manufacturing a three-dimensional flash memory according to an embodiment.

Fig. 7 is a plan view of a three-dimensional flash memory according to an embodiment.

Fig. 8a and 8b are cross-sectional views of a three-dimensional flash memory according to an embodiment.

Fig. 9 is a flowchart of a method of manufacturing a three-dimensional flash memory according to an embodiment.

Fig. 10a to 10k are diagrams for describing a method of manufacturing a three-dimensional flash memory according to the related art.

FIG. 11 is a flow chart of a method of fabricating a three-dimensional flash memory according to an embodiment.

Fig. 12a to 12k are diagrams for describing a method of manufacturing a three-dimensional flash memory according to an embodiment.

Fig. 13a to 13c illustrate a three-dimensional flash memory manufactured using the method of manufacturing a three-dimensional flash memory described with reference to fig. 11.

Detailed Description

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the inventive concept is not limited by the embodiments. Further, like reference numerals shown in each drawing denote like elements.

The terms used in the present specification are those used to appropriately express the embodiments of the inventive concept, and the terms may be changed according to the intention, precedent instance, or convention of one of ordinary skill in the art. Accordingly, terms used in the specification should be defined based on the description of the inventive concept.

Fig. 3 is a plan view of a three-dimensional flash memory according to an embodiment, and fig. 4 is a cross-sectional view of a three-dimensional flash memory according to an embodiment.

Referring to fig. 3 and 4, the three-dimensional flash memory 300 may include at least one memory cell string 310, 320, 330 extending vertically and a plurality of word lines 340 connected orthogonally to the at least one memory cell string 310, 320, 330 and stacked and extending in a horizontal direction.

The at least one memory cell string 310, 320, 330 may include at least one channel layer 311 and at least one charge storage layer 312 surrounding the at least one channel layer 311. The at least one channel layer 311 may include single crystal silicon or polycrystalline silicon extending in a vertical direction, and may be formed using a selective epitaxial growth process or a phase change epitaxy process in which a substrate (not shown) is used as a seed. In addition, the at least one channel layer 311 may have a hollow pipe shape and further include a buried layer (not shown) therein.

The at least one charge storage layer 312 may include an element having a storage function of storing charges from currents flowing through the plurality of word lines 340, and may have, for example, an oxide-nitride-oxide (ONO) structure. Hereinafter, although the at least one charge storage layer 312 is described as including only vertical elements, the inventive concept is not limited thereto and the at least one charge storage layer 312 may further include horizontal elements.

Further, although not shown in the drawings, at least one tunneling insulating layer (not shown) surrounding the at least one memory cell string 310, 320, 330 and vertically extending may be disposed outside the at least one memory cell string 310, 320, 330. The at least one tunneling insulating layer may include an insulating material having a high-k characteristic (e.g., such as Al)₂O₃、HfO₂、TiO₂、La₂O₅、BaZrO₃、Ta₂O₅、ZrO₂、Gd₂O₃Or Y₂O₃Insulating material of).

The plurality of word lines 340 have a function of applying a voltage to the at least one memory cell string 310, 320, 330, and may include a conductive material such as W, Ti, Ta, Cu, or Au. The plurality of word lines 340 may extend in lengths different from each other to form a stepped shape including stepped portions 350 and planar portions 360. For example, among the plurality of word lines 340, the first word line 341 in the lowermost portion may have the longest horizontal length, the second word line 341 positioned above the first word line 341 may have the second longest horizontal length, and the third word line 343 in the uppermost portion may have the shortest horizontal length, thereby forming a stepped shape including the stepped portion 350 and the planar portion 360.

Specifically, the three-dimensional flash memory 300 according to the embodiment is characterized in that the at least one memory cell string 310, 320, 330 is formed in both the planar portion 360 and the stepped portion 350. For example, the first memory cell string 310 and the second memory cell string 320 may be formed in the stepped portion 350, and the third memory cell string 330 may be formed in the planar portion 360. Therefore, unlike the three-dimensional flash memory according to the related art, in which at least one memory cell string is formed only in the plane part 360, the overall integration of the three-dimensional flash memory 300 according to the embodiment may be improved.

Here, the contacts 341-1, 342-1 of the plurality of word lines 340 may be formed only in a minimized partial region in each of the plurality of steps 351, 352 constituting the step portion 350. Hereinafter, the minimized partial region may refer to a region corresponding to a cross-sectional area of each of the contacts 341-1 and 341-2 of the plurality of word lines 340, for example, a region having an area equal to a cross-sectional area of each of the contacts 341-1 and 341-2 of the plurality of word lines 340 among a total area of each of the plurality of steps 351 and 352.

Further, for each of the plurality of steps 351 and 352 constituting the stepped portion 350, at least one memory cell string 310, 320 formed in the stepped portion 350 may be located in the same column as the contacts 341-1, 342-1 of the word lines 341, 342 formed in the stepped portion 350. For example, the first memory cell string 310 formed in the step 351 of the first word line 341 and the contact 341-1 of the first word line 341 may be located in the same column, and the second memory cell string 320 formed in the step 352 of the second word line 342 and the contact 342-1 of the second word line 342 may be located in the same column.

Since the at least one memory cell string 310, 320 formed in the stepped portion 350 and each contact 341-1, 342-1 of each word line 341, 342 formed in the stepped portion 350 are located in the same column for each of the plurality of steps 351, 352 constituting the stepped portion 350, the external wiring 370 connected to each contact 341-1, 342-1 of the word line 341, 342 formed in the stepped portion 350 and the drain line 380 connected to the at least one memory cell string 310, 320 formed in the stepped portion 350 may also be located in the same column.

In addition, the three-dimensional flash memory 300 may further include a plurality of interlayer insulating layers 390 between the plurality of word lines 340. However, the inventive concept is not limited thereto, and a plurality of air gaps, which space the plurality of word lines 340 from each other, may be disposed instead of the plurality of interlayer insulating layers 380.

As described above, the three-dimensional flash memory 300 according to the embodiment may include at least one memory cell string 310, 320 also in the stepped portion 350 of the plurality of word lines 340, and thus, may include more memory cell strings 310, 320, 330 than the structure according to the related art (in which the memory cell string is not formed in the stepped portion 350). Accordingly, the integration of the three-dimensional flash memory 300 can be significantly increased.

Fig. 5 is a flow chart of a method of manufacturing a three-dimensional flash memory according to an embodiment. Fig. 6a to 6i are diagrams for describing a method of manufacturing a three-dimensional flash memory according to an embodiment. Hereinafter, as a main body for performing the method of manufacturing the three-dimensional flash memory, an automated and mechanized manufacturing system may be used, and the three-dimensional flash memory manufactured in the operations (S510 to S540) described below has the structure described with reference to fig. 3 and 4.

Referring to fig. 5, a manufacturing system according to an embodiment prepares a semiconductor structure 600 in which a plurality of word lines 610 and a plurality of insulating layers 620 are alternately stacked, as shown in fig. 6a, in operation S510.

Next, in operation S520, the manufacturing system forms at least one memory cell string 630 extending vertically (the at least one memory cell string 630 including at least one channel layer and at least one charge storage layer surrounding the at least one channel layer) in the entire region of the semiconductor structure 600 except for minimized partial regions 601, 602, 603 in which contacts 611, 612, 613 of the plurality of word lines 610 are to be formed, respectively.

Hereinafter, the minimized partial regions 601, 602, 603 may refer to regions corresponding to the cross-sectional areas of the contacts 611, 612, 613 of the plurality of word lines 610, respectively, for example, regions having an area equal to the cross-sectional areas of the contacts 611, 612, 613 of the plurality of word lines 610 in the entire region of each of the plurality of steps 614, 615, 616 to be included in the stepped shape.

For example, by considering the arrangement of the minimized partial regions 601, 602, 603, the manufacturing system may form at least one vertical hole 604, 605, 606 in a vertical direction in the entire region of the semiconductor structure 600 except for the minimized partial regions 601, 602, 603 such that the minimized partial regions 601, 602, 603 are respectively included in a plurality of steps 614, 615, 616 to be included in a staircase shape (which the plurality of word lines 610 will have), as shown in fig. 6b and 6c, and then form at least one memory cell string 630 in the at least one vertical hole 604, 605, 606, as shown in fig. 6d and 6 e.

Here, in the operation of forming the at least one vertical hole 604, 605, 606, the manufacturing system may form the at least one vertical hole 604, 605, 606 for each of the plurality of steps 604, 605, 606 in a vertical direction such that the at least one vertical hole 604, 605, 606 is located in the same column as the minimized partial areas 601, 602, 603 respectively included in the plurality of steps 614, 615, 616 to be formed in operation S530 (to be described later).

Next, in operation S530, as shown in fig. 6f and 6g, the manufacturing system etches a specific region including the minimized partial regions 601, 602, 603 in a step shape. For example, the manufacturing system may form a stepped shape by etching a specific region including the minimized partial regions 601, 602, 603 in a stepped shape, the stepped shape including a stepped portion 640 and a planar portion 650, the stepped portion 640 including a plurality of steps 614, 615, 616.

Operation S530 may be performed by repeatedly performing a trimming operation and an etching operation based on the number of steps of the plurality of steps 614, 615, 616 to be formed, and the etching method used in operation S530 may be an etching method that allows the at least one memory cell string 630 and the plurality of word lines 610 to be simultaneously etched. That is, the manufacturing system may use an etching method that allows the material of the at least one memory cell string 630 and the material of the plurality of word lines 610 to be simultaneously etched at the same depth in operation S530.

Next, in operation S540, the manufacturing system may form respective contacts 611, 612, 613 of the plurality of word lines 610 in the minimized partial areas 601, 602, 603, as shown in fig. 6h and 6 i. Here, the manufacturing system may form the external wiring connected to the respective contacts 611, 612, 613 of the plurality of word lines 610 and the drain line connected to the at least one memory cell string 630 at the same time as the contacts 611, 612, 613 of the plurality of word lines 610 are formed.

Fig. 7 is a plan view of a three-dimensional flash memory according to an embodiment, and fig. 8a and 8b are sectional views of the three-dimensional flash memory according to an embodiment.

Referring to fig. 7 to 8b, a three-dimensional flash memory 700 according to an embodiment includes at least one memory cell string 720 and a plurality of word lines 730 extending in a direction on a substrate 710. In the three-dimensional flash memory 700, a drain line may be disposed on the at least one memory cell string 720 and connected to the at least one memory cell string 720, and each of the plurality of word lines 730 may be connected to an external wiring through a contact 731. Hereinafter, the drain lines and the external wirings are only shown in fig. 7, and are omitted in fig. 8a and 8 b.

The at least one memory cell string 720 may include at least one channel layer 721 and at least one charge storage layer 722 surrounding the at least one channel layer 721. The at least one channel layer 721 may include single crystal silicon or polycrystalline silicon, and may be formed using a selective epitaxial growth process or a phase change epitaxial process in which the substrate 710 serves as a seed.

The at least one charge storage layer 722 may include an element that stores charges from a current flowing through the plurality of word lines 730, and may have, for example, an oxide-nitride-oxide (ONO) structure. Although the at least one charge storage layer 722 is described below as including only vertical elements extending in a direction orthogonal to the substrate 710, the inventive concept is not limited thereto, and the at least one charge storage layer 722 may further include horizontal elements parallel to the plurality of word lines 730 and contacting the plurality of word lines 730.

The plurality of word lines 730 are connected to the at least one memory cell string 720 in a vertical direction and may be alternately arranged with respect to the plurality of insulating layers 740. The plurality of word lines 730 may include a conductive material such as tungsten, titanium, tantalum, and the plurality of insulating layers 740 may include various insulating materials.

The plurality of word lines 730 are formed in a stepped shape and may be connected to an external wiring via each contact 731 formed in the stepped shape. In particular, the contacts 731 of the plurality of word lines 730 are characterized in that they are respectively formed only in a minimized partial area of the entire area of each of the plurality of word lines 730. The contact 731 of each of the plurality of word lines 730 formed in a minimized partial region as described below refers to the contact 731 formed only in a region corresponding to a cross section of the contact 731 in the entire region of each of the plurality of word lines 730.

Further, the minimized partial region in which the contact 731 of each of the plurality of word lines 730 is formed may be a region located in the same row in the entire region of each of the plurality of word lines 730. That is, when the contact 731 is formed only in a region corresponding to a cross section of the contact 731 in the entire region of each of the plurality of word lines 730, the contact 731 may be formed in a region located in the same row in each of the plurality of word lines 730.

As described above, since the contact 731 of each of the plurality of word lines 730 is formed only in a minimized partial region of the entire region of each of the plurality of word lines 730, the space 751 at which at least one other memory cell string 750, which is not arranged in the same array as the at least one memory cell string 720, is formed, may be provided. Accordingly, the three-dimensional flash memory 700 may include more memory cell strings 720, 750, and thus have a higher integration level. Hereinafter, the same array as the at least one memory cell string 720 refers to a group of memory cell strings including the at least one memory cell string 720 and memory cell strings arranged in the same column as the at least one memory cell string 720, and thus, the at least one other memory cell string 750 not arranged in the same array as the at least one memory cell string 720 may refer to a memory cell string arranged in a different column from the at least one memory cell string 720.

Here, since the at least one other memory cell string 750 is formed in the space 751, the plurality of word lines 730 may be shared by the at least one memory cell string 720 and the at least one other memory cell string 750. Hereinafter, the plurality of word lines 730 shared by the at least one memory cell string 720 and the at least one other memory cell string 750 represent that the plurality of word lines 730 are used to provide current to both the at least one memory cell string 720 and the at least one other memory cell string 750.

According to the three-dimensional flash memory 700 according to the embodiment, since the contact 731 of each of the plurality of word lines 730 is formed only in a minimized partial region of the entire region of each of the plurality of word lines 730 as described, the space 751 is provided where the at least one other memory cell string 750, which is not arranged in the same array as the at least one memory cell string 720, is formed, and thus, the three-dimensional flash memory 700 may include a large number of memory cell strings 720, 750. Accordingly, the integration degree of the three-dimensional flash memory 700 may be significantly increased.

Fig. 9 is a flowchart of a method of manufacturing a three-dimensional flash memory according to an embodiment. Hereinafter, as a main body for performing the method of manufacturing the three-dimensional flash memory, an automated and mechanized manufacturing system may be used, and the three-dimensional flash memory manufactured in the operations (S910 to S940) described below has the structure described with reference to fig. 7 to 8 b.

Referring to fig. 9, the manufacturing system according to the embodiment prepares a mold structure in which a plurality of word lines and a plurality of insulating layers are alternately stacked in operation S910.

Next, in operation S920, the manufacturing system forms at least one memory cell string (the at least one memory cell string includes at least one channel layer and at least one charge storage layer surrounding the at least one channel layer) extending in a direction in a region of the mold structure except for a minimized partial region in which contacts of the plurality of word lines are to be formed.

For example, the manufacturing system may form a vertical hole in a remaining region except a minimized partial region where a contact of each of the plurality of word lines is to be formed, such that a substrate included in the mold structure is exposed, and then may deposit at least one charge storage layer in the vertical hole and fill at least one channel layer in the vertical hole, thereby forming at least one memory cell string.

Here, the minimized partial region in which the contact of each of the plurality of word lines is to be formed may be a region corresponding to a cross section of the contact among the entire region of each of the plurality of word lines, and may be a region located in the same row on the region of each of the plurality of word lines.

Further, in operation S920, in order to provide a space in which at least one other memory cell string that is not arranged in the same array as the at least one memory cell string is to be formed, the manufacturing system may form the at least one memory cell string extending in a direction in the remaining region and then form the at least one other memory cell string in the space in the direction.

Accordingly, in operation S920, the at least one other memory cell string may extend in a direction such that the plurality of word lines are shared between the at least one memory cell string and the at least one other memory cell string.

As described above, the manufacturing system leaves only a minimized partial area of the entire area of each of the plurality of word lines as an area for forming the contact in operation S920, and thus, the memory cell string may be formed in the entire area except the minimized partial area, thereby further improving the integration of the memory cell string.

Next, in operation S930, the manufacturing system etches a minimized partial region in which a contact of each of the plurality of word lines is to be formed in a staircase shape.

Next, in operation S940, the manufacturing system forms a contact for each of the plurality of word lines in the etched region.

FIG. 11 is a flow chart of a method of fabricating a three-dimensional flash memory according to an embodiment. Fig. 12a to 12k are diagrams for describing a method of manufacturing a three-dimensional flash memory according to an embodiment. Hereinafter, as a main body for performing the method of manufacturing the three-dimensional flash memory, an automated and mechanized manufacturing system may be used.

Referring to fig. 11 to 12k, the manufacturing system prepares a plurality of word lines 1210 stacked in a horizontal direction by dividing the plurality of word lines 1210 into an upper word line group 1220 and a lower word line group 1230 in operation S1110, as shown in fig. 12 a.

The upper word line group 1220 and the lower word line group 1230 may be prepared by sequentially stacking them having different horizontal sizes in a stair shape such that at least portions of upper surfaces 1221 and 1231 thereof are exposed. For example, the upper group 1220 and the lower group 1230 of wordlines may be separately provided by stacking them in sequence, wherein the horizontal dimension of the lower group 1230 of wordlines is greater than the horizontal dimension of the upper group 1220 of wordlines, such that at least a portion of the upper surfaces 1221, 1231 is exposed.

Here, the operation S1110 refers not only to an operation of preparing only the plurality of word lines 1210, but also to an operation of preparing a mold structure including a plurality of insulating layers 1223, 1233 and vertical strings 1240, the plurality of insulating layers 1223, 1233 being alternately included between the plurality of word lines 1210, the vertical strings 1240 including the channel layer 1241 and the charge storage layer 1242. Accordingly, the upper word line group 1220 may include upper word lines 1222 and upper insulating layers 1223 alternately included between the upper word lines 1222, the lower word line group 1230 may include lower word lines 1232 and lower insulating layers 1233 alternately included between the lower word lines 1232, and the upper word line group 1220 and the lower word line group 1230 may share one vertical string 1240.

For example, in operation S1110, the manufacturing system may prepare the plurality of wordlines 1210 having a stepped form and divided into upper wordline groups 1220 and lower wordline groups 1230 as shown in fig. 12a by etching portions 1211, 1212 of a mold structure in which a plurality of wordlines 1222, 1232 and a plurality of insulating layers 1223, 1233 are alternately stacked and a vertical string 1240 is formed in a vertical direction as shown in fig. 12b and 12 c.

As another example, in operation S1110, the manufacturing system may prepare the plurality of word lines 1210 having a stepped form and divided into the upper word line group 1220 and the lower word line group 1230 as shown in fig. 12a by stacking the upper mold structure (in the upper mold structure, the upper word lines 1222 and the upper insulation layers 1223 having a smaller horizontal size than the lower word lines 1232 are alternately stacked and the upper vertical string is formed in the vertical direction) on the lower mold structure (in the lower mold structure, the lower word lines 1232 and the lower insulation layers 1233 are alternately stacked and the lower vertical string is formed in the vertical direction) as shown in fig. 12d and 12 e.

Specifically, in operation S1110, the manufacturing system may determine the horizontal size of the lower word line group 1230 to include an etch stop distance 1250 to prevent the lowermost word line of the upper word line group 1220 from being etched when an etching operation is performed on the lower word line group 1230 in operation S1130 described later. This will be described in more detail below.

Further, in operation S1110, the manufacturing system may arrange an etch stop protective layer 1260 between the upper word line group 1220 and the lower word line group 1230 to prevent an uppermost word line in the lower word line group 1230 from being etched when an etching operation is performed on the upper word line group 1220 in operation S1130 described later. This will also be described in more detail below.

Next, in operation S1120, the fabrication system forms photoresists 1270, 1280 on at least a portion of the upper surface 1221 of the set of upper wordlines 1220 and at least a portion of the upper surface 1231 of the set of lower wordlines 1230, as shown in fig. 12 f.

Next, in operation S1130, the manufacturing system performs an etching operation on the upper word line group 1220 and the lower word line group 1230 having the photoresists 1270, 1280 formed thereon at the same time, as shown in fig. 12 h.

Here, the manufacturing system may trim the photoresists 1270 and 1280 by the widths of the equal pitches, and the stepped shape to be formed by the plurality of word lines 1210 will have the widths of the equal pitches, as shown in fig. 12g, before operation S1130.

Operation S1130 may be repeatedly performed based on the number of steps by which the upper word lines 1222 included in the upper word line group 1220 are stacked and the number of steps by which the lower word lines 1232 included in the lower word line group 1230 are stacked, and thus, a three-dimensional flash memory including the word lines 1210 having a stepped shape may be manufactured.

Likewise, when repeatedly performing operation S1130, the manufacturing system may additionally repeat the operation of trimming the photoresist 1270, 1280, as shown in fig. 12h to 12j, thereby allowing the word line 1210 to have a stepped shape.

As described above, since the horizontal size of the lower word line group 1230 is determined to include the etch stop distance 1250, as shown in fig. 12h, when the etch operation is performed on the lower word line group 1230, the erroneous etching of the lowermost word line 1224 in the upper word line group 1220 may be prevented.

Further, as described above, since the etch stop protective layer 1260 is between the upper word line group 1220 and the lower word line group 1230, as shown in fig. 12h, when an etching operation is performed on the upper word line group 1220, it is possible to prevent an erroneous etching of the uppermost word line 1234 in the lower word line group 1230.

Although determining the horizontal size of the lower word line group 1230 to include both the etch stop distance 1250 and disposing the etch stop protective layer 1260 between the upper word line group 1220 and the lower word line group 1230 are described as being performed in operation S1110, the inventive concept is not limited thereto and any one of them may be performed.

When only the determination of the horizontal size of the lower word line group 1230 to include the etch stop distance 1250 is performed in operation S1110, the completed three-dimensional flash memory is shown in fig. 13 a. When only the arrangement of the etch stop protective layer 1260 between the upper and lower word line groups 1220 and 1230 is performed in operation S1110, the completed three-dimensional flash memory is shown in fig. 13 b. When determining the horizontal size of the lower word line group 1230 to include both the etch stop distance 1250 and the arrangement of the etch stop protective layer 1260 between the upper word line group 1220 and the lower word line group 1230 are performed in operation S1110, the completed three-dimensional flash memory is shown in fig. 13 c. This will be described in more detail below.

Next, in operation S1140, the fabrication system may remove the photoresists 1270, 1280, as shown in fig. 12k, to complete the fabrication of the three-dimensional flash memory including the word line 1210 having the step shape.

Fig. 13a to 13c illustrate a three-dimensional flash memory manufactured using the method of manufacturing a three-dimensional flash memory described with reference to fig. 11.

Referring to fig. 13a, a three-dimensional flash memory 1310 according to an embodiment includes word lines having steps and manufactured in operations S1110 to S1130 described above with reference to fig. 11 to 12 f. Specifically, since the manufacturing system determines the horizontal size of the lower word line group to include the etch stop distance 1311 in operation S1110, when a stepped shape having an equally spaced width and an equally spaced height is formed using the plurality of word lines 1320, the three-dimensional flash memory 1310 includes a portion 1321 having a width different from other portions of the stepped shape.

That is, the portion 1321 having a different width from other portions may be formed by the etch stop distance 1311 to prevent unnecessary etching of the lowermost wordline 1322 included in the upper wordline group among the plurality of wordlines 1320 in the process of performing the etching operation on the plurality of wordlines 1320.

Referring to fig. 13b, a three-dimensional flash memory 1330 according to another embodiment includes word lines having a staircase shape and manufactured in operations S1110 to S1130 described above with reference to fig. 11 to 12 f. Specifically, since the manufacturing system arranges the etch stop protective layer 1331 between the upper word line group and the lower word line group in operation S1110, when a stepped shape having an equally spaced width and an equally spaced height is formed using the plurality of word lines 1340, the three-dimensional flash memory 1310 includes a portion 1341 having a height different from other portions of the stepped shape.

That is, the portion 1341 having a height different from other portions may be formed of the etch protective layer 1331 to prevent unnecessary etching of the uppermost word line 1342 included in the lower word line group among the plurality of word lines 1340 in the process of performing the etching operation on the plurality of word lines 1340.

Referring to fig. 13c, a three-dimensional flash memory 1350 according to an embodiment includes word lines having a staircase shape and manufactured in operations S1110 to S1130 described above with reference to fig. 11 to 12 f. Specifically, since the manufacturing system arranges the etch stop protective layer 1352 between the upper word line group and the lower word line group while determining the horizontal size of the lower word line group to include the etch stop distance 1351 in operation S1110, when a stepped shape having an equally spaced width and an equally spaced height is formed using the plurality of word lines 1360, the three-dimensional flash memory 1350 includes a portion 1361 having a width different from other portions of the stepped shape and a portion 1362 having a height different from other portions of the stepped shape.

The portions 1361 having different widths may be formed of the etch stop distances 1351 to prevent unnecessary etching of the lowermost word line 1363 included in the upper word line group among the plurality of word lines 1360 in the process of performing the etching operation on the plurality of word lines 1360, and the portions 1362 having different heights may be formed of the etch stop protective layers 1352 to prevent unnecessary etching of the uppermost word line 1364 included in the lower word line group among the plurality of word lines 1360 in the process of performing the etching operation on the plurality of word lines 1360.

As described above, according to the method of manufacturing a three-dimensional flash memory of the present embodiment, when manufacturing a three-dimensional flash memory including word lines of six steps in total, only two etching operations are performed (five etching operations are performed in the method of manufacturing a three-dimensional flash memory according to the related art), and thus, the number of repetitions of the etching operations can be significantly reduced, and thus, the manufacturing process can be simplified.

While the inventive concept has been particularly shown and described with reference to examples thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims. For example, even when the above-described techniques are performed in a different order than the above-described methods and/or components such as the above-described systems, structures, devices, and circuits are combined or combined in a form different from the above-described methods or replaced or substituted by other components or their equivalents, appropriate results can be obtained.

Accordingly, other implementations, other embodiments, and claims and equivalents also fall within the scope of the claims described below.