阅读说明：本技术 三维nand结构制造的方法与设备 (Method and apparatus for three-dimensional NAND structure fabrication ) 是由 小泽武仁 穆昆德·斯里尼瓦桑 北岛知彦 姜昌锡 姜声官 吉尔·Y·李 苏米特·辛格·罗伊 于 2020-04-21 设计创作，主要内容包括：本文提供了用于形成多个非易失性储存单元的方法和设备。在某些实施方式中,方法例如包括形成多个非易失性储存单元,包括在基板上形成金属层交替的堆叠,金属层包括第一金属层和不同于第一金属层的第二金属层；去除第一金属层以在第二金属层的交替层之间形成空间；以及沉积第一材料层以部分地填充空间以在其中留有气隙或沉积第二材料层以填充空间这两步骤之一。(Methods and apparatus for forming a plurality of non-volatile storage cells are provided herein. In some embodiments, a method, for example, includes forming a plurality of non-volatile storage cells, including forming an alternating stack of metal layers on a substrate, the metal layers including a first metal layer and a second metal layer different from the first metal layer; removing the first metal layer to form spaces between alternating layers of the second metal layer; and one of depositing a first material layer to partially fill the space to leave an air gap therein or depositing a second material layer to fill the space.)

1. A method for forming a plurality of non-volatile storage cells, comprising:

forming a stack of alternating metal layers on a substrate, the metal layers including a first metal layer and a second metal layer different from the first metal layer;

removing the first metal layer to form a plurality of spaces between the alternating layers of the second metal layer; and

depositing a first layer of material to partially fill the space to leave a plurality of air gaps therein or depositing a second layer of material to fill the space.

2. The method of claim 1, wherein one of depositing the first material layer to partially fill the space to leave air gaps therein or depositing the second material layer in the space is performed using one of chemical vapor deposition or atomic layer deposition.

3. The method of claim 1, wherein the first metal layer and the second metal layer are deposited using at least one of chemical vapor deposition and physical vapor deposition.

4. The method of claim 1, wherein removing the first metal layer is performed using one of: dry chemical etch process with F chemistry including fluorine compounds including SF₆、CF₄、CHF₄、CH₃F、C₂F₆、C₄F₈Or NF₃At least one of (a); or a wet etch process.

5. The method of claim 1, further comprising the steps of:

forming at least one storage hole in the stack of alternating layers of the first metal layer and the second metal layer, and in a silicon nitride (SiN) and polysilicon (poly-Si) layer, the first metal layer deposited on the SiN and polysilicon layer; and

depositing in the at least one storage well:

an aluminum oxide (AlO) layer;

a first silicon oxide layer on top of the AlO layer;

a SiN layer on top of the first silicon oxide layer;

a second silicon oxide layer on top of the SiN layer;

a polysilicon layer on top of the second silicon dioxide layer to form a polysilicon channel; and

a core silicon oxide for filling the polysilicon channel.

6. The method of any of claims 1 to 5, wherein forming the at least one storage hole is performed using a dry chemical etch process with F chemistry, the F chemistry comprising a plurality of fluorine compounds, the fluorine compounds comprising SF₆、CF₄、CHF₄、CH₃F、C₂F₆、C₄F₈Or NF₃At least one of (1).

7. The method of claim 5, further comprising, prior to removing the first metal layer to form spaces between the alternating layers of the second metal layer:

forming at least two slits through the first metal layer, the second metal layer, and the SiN and polysilicon layers using an F-based chemistry, the F-based chemistry including a plurality of fluorine compounds, the fluorine compounds including SF₆、CF₄、CHF₄、CH₃F、C₂F₆、C₄F₈Or NF₃At least one of (a);

removing the SiN and polysilicon layers from the substrate using one of a wet etch process or a chemical dry etch process;

removing the AlO layer, the first silicon oxide layer on top of the AlO layer, the SiN layer on top of the first silicon oxide layer, and the second silicon oxide layer on top of the SiN layer from the at least one storage hole in the area occupied by the SiN and polysilicon layers prior to removal of the SiN and polysilicon layers using a chemical dry etch process; and

depositing a phosphorus-doped polysilicon layer on the substrate in the positions of the removed AlO layer, the removed first silicon oxide layer, the removed SiN layer and the removed second silicon oxide layer to cover a part of the polysilicon channel.

8. The method of any of claims 1-5 or 7, further comprising, after removing the first metal layer to form a number of spaces between the alternating layers of the second metal layer and before one of depositing the first material layer to partially fill the spaces to leave a number of air gaps therein or depositing the second material layer to fill the spaces:

removing the AlO layer, the first silicon oxide layer on top of the AlO layer, and the SiN layer on top of the first silicon oxide layer from the at least one storage hole in the area occupied by the first metal layer before removing the first metal layer using the chemical dry etch process.

9. The method of claim 1, wherein the first metal layer is at least one of tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), titanium (Ti), Ti nitride (TiN), TaN, WN, MoN, ZrN, WOx, RuOx, and IrOx,

wherein the second metal layer is one of W, Mo, Ta, Ru, Nb, Os, Zr, Ir, Re, and Ti,

wherein the first material layer is silicon oxide, and

wherein the second material layer is a low-k oxide.

10. The method of any of claims 1-5 or 9, wherein the low-k oxide is one of silicon oxide or silicon dioxide having a dielectric constant less than or equal to 3.9.

11. A semiconductor storage device, comprising:

a substrate comprising an alternating stack of material layers, the material layers comprising a first material layer and a second material layer, the first material layer being at least one of a metal, a metal nitride, or a conductive metal compound, and the second material layer being at least one of a metal, a metal alloy, or a metal having a dopant comprising one or more metallic elements,

wherein the first material layer is different from the second material layer.

12. The semiconductor storage device according to claim 11, wherein the first material layer is at least one of tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), titanium (Ti), Ti nitride (TiN), TaN, WN, MoN, ZrN, WOx, RuOx, and IrOx, and

wherein the second material layer is one of W, Mo, Ta, Ru, Nb, Os, Zr, Ir, Re, and Ti.

13. The semiconductor storage device according to any one of claims 11 or 12, further comprising:

a silicon nitride (SiN) and polysilicon (poly-Si) layer deposited on the substrate, the first material layer being deposited on the SiN and polysilicon layer; and

at least one storage hole in the stack of alternating layers of the first material layer and the second material layer and in the polysilicon layer,

wherein the at least one storage well has deposited therein:

an aluminum oxide (AlO) layer;

a first silicon oxide layer on top of the AlO layer;

a SiN layer on top of the first silicon oxide layer;

a second silicon oxide layer on top of the SiN layer;

a polysilicon layer on top of the second silicon dioxide layer to form a polysilicon channel; and

a core silicon oxide for filling the polysilicon channel.

14. A system for forming a plurality of non-volatile storage cells, comprising:

an apparatus configured to deposit a stack of alternating layers of silicon nitride (SiN) and poly-silicon (poly-Si) and a plurality of metal layers on a substrate, the metal layers including a first metal layer and a second metal layer different from the first metal layer;

a device configured to remove the first metal layer to form a number of spaces between the alternating layers of the second metal layer; and

an apparatus configured to perform one of depositing a first layer of material to partially fill the space to leave a number of air gaps therein or depositing a second layer of material to fill the space.

15. The system of claim 14, wherein one of depositing the first material layer to partially fill the space to leave air gaps therein or depositing the second material layer in the space is performed using one of chemical vapor deposition or atomic layer deposition.

Technical Field

Embodiments of the present disclosure relate generally to substrate processing equipment and techniques, and more particularly, to methods and apparatus for three-dimensional (3D) NAND structure fabrication.

Background

To address the challenges encountered in scaling (scaling) planar (2D) NAND storage devices to achieve higher densities at lower cost per bit, ultra-high density three-dimensional (3D) stacked storage structures have been introduced. The above-described 3D storage structure is sometimes referred to as having a Bit Cost Scalable (BiCS) architecture and includes vertically aligned strings of storage cells. Typically, vertically aligned memory cells are formed from an array of alternating conductor and insulator layers, with the conductive layers corresponding to the word lines of the memory structure.

As the number of vertically stacked storage cells in a 3D NAND device increases (e.g., as chip density increases), the aspect ratio of the storage cell string also increases, thereby presenting a number of manufacturing problems. The inventors have observed that the difficulty of etching/filling and stress control increases, for example, as the stack increases. The inventors have further observed that thinning the layers in the stack to keep the aspect ratio of the string of storage cells within a controllable range results in a more challenging downstream etch process.

Accordingly, the inventors provide methods and apparatus for 3D NAND structure fabrication.

Disclosure of Invention

Methods and apparatus for forming a plurality of non-volatile storage cells are provided herein. In some embodiments, a method includes forming an alternating stack of metal layers on a substrate, the metal layers including a first metal layer and a second metal layer different from the first metal layer; removing the first metal layer to form spaces between alternating layers of the second metal layer; and one of depositing a first material layer to partially fill the space to leave an air gap therein or depositing a second material layer to fill the space.

According to some embodiments of the present disclosure, there is provided a semiconductor storage device including a substrate including an alternating stack of material layers, the material layers including a first material layer and a second material layer, the first material layer being at least one of a metal, a metal nitride, or a conductive metal compound, and the second material layer being at least one of a metal, a metal alloy, or a metal with a dopant including one or more metal elements, wherein the first material layer is different from the second material layer.

According to an aspect of the present disclosure, a system for forming a plurality of non-volatile storage cells is provided. The system includes a device configured to deposit layers of silicon nitride (SiN) and polysilicon (poly-Si) and an alternating stack of metal layers on a substrate, the metal layers including a first metal layer and a second metal layer different from the first metal layer; a device configured to remove the first metal layer to form spaces between alternating layers of the second metal layer; and an apparatus configured to one of deposit a first layer of material to partially fill the space to leave an air gap therein or deposit a second layer of material to fill the space.

Other and further embodiments of the present disclosure are described below.

Drawings

Embodiments of the present disclosure, briefly summarized above and discussed in more detail below, may be understood by reference to the illustrative embodiments of the disclosure that are depicted in the drawings. However, the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

Fig. 1 is a schematic diagram of a system for forming a plurality of non-volatile storage cells in a 3D NAND storage device, according to at least one embodiment of the present disclosure.

Fig. 2 is a flow chart of a method of forming a plurality of non-volatile storage cells in a 3D NAND storage device according to at least one embodiment of the present disclosure.

Fig. 3A-3P are schematic cross-sectional views of a portion of a 3D NAND storage device according to at least one embodiment of the present disclosure.

Fig. 4A-4C are schematic cross-sectional views of a portion of a 3D NAND storage device according to at least one embodiment of the present disclosure.

Fig. 5 is a schematic cross-sectional view of a portion of a 3D NAND storage device according to at least one embodiment of the present disclosure.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

Detailed Description

Embodiments described herein generally relate to 3D NAND storage devices with improved word line isolation and methods of forming the same. In particular, alternating layers of material (e.g., first and second metal layers of different types of metals) are used for 3D NAND cell film stacking to form the storage hole. One of the metal layers (e.g., the first metal) may then be removed (e.g., etched) to form a space, and then the space is filled with one or more materialsInter-low-k oxides (e.g., SiO)₂Etc.) or an air gap. The same etch chemistry can be used to etch away both metal layers. Thus, High Aspect Ratio (HAR) etching can be performed with higher throughput. For example, a dry chemical etch comprising hydrofluoric acid (HF) may be used to etch a substrate with high selectivity (e.g.,>100: 1) to etch away both metals. Furthermore, the embodiments described herein eliminate the Word Line (WL) metal fill step, which is sometimes used with conventional methods of forming 3D NAND storage devices and is a critical step in Replacing Metal Gate (RMG), such as with an oxygen-nitrogen (ON) die. As described herein, WL metal may be deposited as a mold stack and filled with silicon oxide after TiN removal; SiO 2₂The filling is an easier and more cost-effective process than the conventional process for WL metal filling. In addition, SiO may be used₂Incompletely filled voids are not detrimental to the fabricated 3D NAND memory devices described herein because voids can act as air gaps (can be formed without adding any additional steps), which is in contrast to voids formed during conventional RMG processes (which can result in severe SiO due to fluorine (F) gas remaining in the voids₂Degradation) is reversed. In addition, the mechanical stress of the mold stack for forming 3D NAND storage devices can be adjusted by the deposition conditions of the metal using Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD), with current SiO₂Silicon nitride (Si)₃N₄) The overall stack height can be thinner than with multiple layers, for example, because RMG need not be used.

FIG. 1 is a schematic diagram of a system 100 for forming a plurality of non-volatile storage cells in a 3D NAND storage device (e.g., storage device 300 of FIGS. 3A-3P). Fig. 2 is a flow chart of a method 200 for forming a plurality of non-volatile storage cells in a storage device according to an embodiment of the present disclosure. Figures 3A-3P are schematic cross-sectional views of a portion of a 3D NAND storage device during stages of manufacture (e.g., using method 200) in accordance with at least one embodiment of the present disclosure.

Fig. 3A shows a storage device 300, the storage device 300 may be a bit-cost scalable (BiCS) device comprising a string(s) of vertically stacked storage cell layers 302 (e.g., conductive layers that act as word lines) (e.g., second material layers) alternately disposed between a plurality of layers 304 (e.g., first material layers) formed on a substrate 301, which substrate 301 may be a semiconductor in some embodiments.

The substrate 301 may be any suitable starting material for forming integrated circuits, such as a silicon (Si) wafer or a germanium (Ge) wafer. The semiconductor substrate 301 may be a silicon semiconductor substrate having one or more layers (e.g., film stacks) formed thereon for forming structures such as the storage device 300 on the substrate 301. The substrate 301 may comprise a material such as crystalline silicon (e.g., Si < 100)>Or Si < 111>)、Si₃N₄Strained silicon, silicon germanium, doped or undoped poly-silicon (poly-Si), doped or undoped silicon, patterned or unpatterned wafers, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride (SiN, Si)₃N₄Etc.), doped silicon, germanium, gallium arsenide, glass, sapphire, a metal layer disposed on silicon, and the like. The substrate 301 may be a circular wafer, for example a 200mm, 300mm or 450mm diameter wafer, or a rectangular or square panel.

In some embodiments, the memory cell layer 302 and the layer 304 may be formed on a Common Source Line (CSL) layer, and the Common Source Line (CSL) layer may be formed on an Etch Stop Layer (ESL). In the above embodiments, the CSL layer and the ESL layer may be made of a material such as tungsten (W), silicon nitride (SiN), poly-Si, or a combination thereof. In some embodiments, a Mask Layer (ML), e.g., a silicon oxide layer, may be deposited on top of the storage cell layer 302 or layer 304 to form a top or final material layer. The ML is patterned prior to etching the stack to cover areas that are not removed during the stack etch process.

Layers 304 are disposed between storage unit layers 302. Layer 304 may be formed using any suitable material (e.g., metal nitride, or conductive metal compound), such as W, molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), titanium (Ti), Ti nitride (N), TaN, WN, MoN, ZrN、WOx、RuOx、IrO_xAnd so on. Layer 304 is provided to facilitate the formation (or building) of storage cell layer 302 on semiconductor substrate 301. After the storage cell layer 302 is formed, the layer 304 is removed using one or more suitable processes and filled with one or more suitable materials, as will be described in more detail below.

Each storage cell layer 302 corresponds to a wordline of the memory device 300, each wordline extending into a page to form additional storage cells of the memory device 300 that are not visible. Thus, each storage cell layer 302 is configured to store one or more bits of data. As such, each storage cell layer 302 may be formed using any suitable material, such as a metal, a metal alloy, a metal having a dopant including one or more metal elements, such as W, tungsten silicide (WSi), tungsten poly-Si (W/poly-Si), a tungsten alloy, Ta, Ti, Nb, Os, Zr, Ir, Re, copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), aluminum (Al), hafnium (Hf), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), silver (Au), platinum (Pt), alloys thereof, nitride compounds thereof (such as titanium nitride (TiN) and tantalum nitride (TaN)), combinations thereof, and the like. The storage unit layer 302 and the layer 304 are formed of different materials for each substrate 301. For example, in at least some embodiments, storage cell layer 302 may be formed of W and layer 304 may be formed of TiN; other combinations of materials may also be used.

With continued reference to fig. 3A, at 202, the storage cell layers 302 and 304 may be deposited on the semiconductor substrate 301 using any suitable deposition process and/or apparatus 130 (fig. 1), examples of which apparatus 130 may include a Chemical Vapor Deposition (CVD) apparatus 130a, a Physical Vapor Deposition (PVD) apparatus 130b, or an Atomic Layer Deposition (ALD) apparatus 130 c. For example, in one embodiment, the layer 304 (e.g., TiN) may be deposited using, for example, the PVD apparatus 130b, which may be a stand-alone apparatus or part of a cluster tool configured to, for example, perform a PVD process. Exemplary equipment that may be configured to perform the above-described processes may include, for exampleA series of independent PVD devices available from Applied Materials, inc. Likewise, storage cell layer 302 (e.g., W) may be deposited using, for example, CVD apparatus 130a may be a stand-alone apparatus or part of a cluster tool configured to, for example, perform a CVD process. Exemplary equipment that may be configured to perform the above-described processes may include, for exampleAn APF series of stand-alone CVD apparatus available from Applied Materials, inc. Alternatively or additionally, layer 304 may be deposited using, for example, CVD apparatus 130a, and storage cell layer 302 may be deposited using, for example, PVD apparatus 130 b.

Subsequently, a WL step may be formed by etching the storage cell layer 302, the layer 304, and ML (fig. 3B). For example, any suitable etching apparatus 110 (FIG. 1) and/or method may be employed to form the WL ladder, such as Deep Reactive Ion Etching (DRIE), which is a highly anisotropic etching process used to create high aspect ratio holes and trenches in a wafer or other substrate. Etching gases suitable for use in the above-described etching process may include fluoride (SF)₆、CF₄、CHF₄、CH₃F、C₂F₆、C₄F₈And NF₃) Chloride (HCl, Cl)₂、BCl₃) Bromide (Br)₂HBr), or an oxygen-containing gas (such as O)₃、O₂、CO₂、CO、H₂O、NO、NO₂、N₂O, CO, and the like) and may optionally include an inert gas such as argon (Ar) or helium (He).

After the WL step is formed, an interlayer dielectric deposition (ILD) process may be performed to deposit a material layer 305 over storage cell layer 302 and layer 304. The ILD process may use a dielectric material to be filled in the region where the step is formed. In at least some embodiments, a thick silicon oxide (about 1.2 times thicker than the stack height of storage cell layer 302 and layer 304) is deposited and planarized by Chemical Mechanical Polishing (CMP).

Subsequently, referring to fig. 3C, at least one storage hole 306 is formed using the etching apparatus 110(Or a plurality of storage holes 306, e.g., three storage holes 306) in the ML, in the stack of alternating storage cell layers 302 and 304, in the CSL, and partially in the ESL. Alternatively or additionally, the storage hole 306 may be formed to extend into the substrate 301. The vertically stacked string of storage cell layers 302 and 304 is shown arranged in four vertical columns. The etching apparatus 110 may be configured to use sulfur hexafluoride (SF) having an ion acceleration voltage of 0.5-10 kV₆) A chemical substance. A hard mask deposition process may be first performed before etching is performed, and the hard mask layer deposited before etching may be removed after etching is completed and the storage hole 306 is formed. Other etching equipment and/or processes may be used to form the storage holes 306.

Referring to fig. 3D and 3E, after the storage holes 306 are formed, one or more additional material layers may be deposited in the storage holes 306. For example, as shown in the detailed indicator region of fig. 3E, an aluminum oxide (AlO) layer (layer 307) (e.g., a continuous layer) is first deposited on the sides defining the storage hole 306 and along the ESL at the bottom of the storage hole 306. Subsequently, a silicon oxide layer (layer 309) is deposited on top of the AlO layer and along the bottom of the storage hole 306. Subsequently, a trap (trap) -silicon nitride (SiN) layer (layer 311) is deposited on top of layer 309 and along the bottom of the storage hole 306. Subsequently, another silicon oxide layer 313 is deposited on top of layer 311 and along the bottom of storage hole 306. Subsequently, a polysilicon layer (layer 315) is deposited on top of the silicon oxide layer 313 and along the bottom of the storage hole 306 to form a polysilicon channel at the bottom of the storage hole 306. Subsequently, core silicon oxide (layer 317) such as SiO, SiOC, etc. is deposited to fill the polysilicon channel (see, e.g., fig. 3E). Any suitable deposition process and/or apparatus may be used to deposit the layers 307-317. For example, the CVD apparatus 130a and PVD apparatus 130b of FIG. 1 may be used to perform CVD and PVD, respectively, to deposit the layer 307-317. Alternatively or additionally, the ALD apparatus 130c may be a stand-alone apparatus or a cluster tool that may be used to perform the ALD process to deposit the layers 307-. Exemplary apparatus that may be configured to perform the above-described processes include, for example, ALD apparatusSeries, available from Applied Materials, Inc.And (4) obtaining.

After depositing layer 317 to fill the polysilicon channel, an additional layer 321 (e.g., a polysilicon layer) may be deposited on top of layer 317 to cover layer 317, and an additional ML layer may be deposited on top of layer 321 to cover layer 321, as shown in fig. 3F and 3G.

Subsequently, with respect to fig. 3H, two additional slits or holes 308 may be formed (e.g., using the etching process described above) in ML, in the stack of alternating storage cell layers 302 and 304, in CSL, in ESL, and partially in substrate 301. However, unlike the storage wells 306, the wells 308 are used to remove the CSL and the layer 304. For example, after forming the hole 308, the CSL is removed using the above-described etching process (e.g., wet etching and/or chemical dry etching), as are the layers 309-313 deposited in the storage hole 306 within the CSL (see, e.g., fig. 3I and 3J).

Subsequently, the region comprising the CSL and the layers 307-313 is filled with a phosphorus doped poly (n + -type silicon) layer (e.g., layer 323) while the hole 308 remains intact, e.g., unfilled or minimally filled with layer 323 (fig. 3K).

Subsequently, at 204, layer 304 is removed using the etching process described above (e.g., wet etching or chemical dry etching using etching apparatus 110). More specifically, as shown in fig. 3L, layer 304 (e.g., a TiN layer) is removed by selectively oxidizing layer 304 to form spaces 325 between alternating layers of storage cell layer 302 (e.g., a W layer).

The removal of layer 304 may be accomplished using any suitable etching or patterning process to selectively remove layer 304 from storage device 300 without undesirably damaging storage cell layer 302.

For example, layer 304 may be removed with high selectivity using any isotropic etch process that is selective to at least storage cell layer 302. For example, in certain embodiments, layer 304 may be removed with a reactive species via a process from the inclusion of oxygen (O)₂) And nitrogen trifluoride (NF3), such as the etching apparatus 120 of fig. 1. The isotropic etching process may be performed in any suitable isotropic etching apparatus. Useful for removing layer 304A highly selective isotropic dry etch process is described in U.S. Pat. No. 9,165,786, issued 8/5/2014, entitled "Integrated oxide and nitride Access for beta channel contact in 3D architecture". The dry etching process may be performed using a suitable dry etching apparatus. Exemplary equipment that can be configured to perform the above-described processes include, for exampleA series of etching apparatus (fig. 1) available from Applied Materials, inc. (Santa Clara, california).

Alternatively or additionally, to remove layer 304, a silicon oxide layer (not shown) may be deposited on layer 304 using selective oxidation apparatus 140 using Rapid Thermal Oxidation (RTO), radical oxidation, or Remote Plasma Oxidation (RPO), such as Decoupled Plasma Oxidation (DPO). In certain embodiments, plasma oxidation or radical oxidation may be used when a low thermal budget and/or reduced oxygen diffusion is desired. As used herein, a low thermal budget means a thermal budget for a furnace process of less than tens of minutes at a peak temperature of 850 ℃. For example, when RPO is used at 204, one or more suitable plasma reactors, such as an RPO reactor available from Applied Materials, inc.

Alternatively, a high thermal budget process (i.e., high oxygen diffusion) may also be utilized. For example, high thermal budget processes (such as wet, dry, or RTO) may provide conformal oxidation, faster oxidation rates, and thicker oxidation.

The type of selective oxidation device 140 and/or etching device 120 used to remove the carbon layer 304 may depend on one or more factors including, but not limited to, time constraints, desired oxidation rates, and the like.

Regardless of the selective oxidation apparatus 140 and/or the etching apparatus 120 (or the etching process using the etching apparatus 110) used, after the layer 304 is removed from the storage device 300, the suspended film stack with only the storage cell layer 302 remains on the substrate 301 for further processing, see fig. 3L.

In some embodiments, at 206, referring to fig. 3M, a material layer 327 (such as a low-k (dielectric constant) oxide material, silicon oxide, silicon dioxide, etc.) may be deposited to fill the space 325 (e.g., without air gaps). The material layer 327 may be deposited using, for example, the CVD apparatus 130a or the ALD apparatus 130c of fig. 1. The low-k oxide material may include, but is not limited to, silicon oxide, silicon dioxide, and the like. The material layer 327 may have a dielectric constant of 3.9 and less than 3.9.

Conversely, referring to fig. 3N, at 204, in certain embodiments, a material layer 327 may be deposited to partially fill the space 325, thereby leaving an air gap 329 therein. The material layer 327 may be deposited using, for example, the CVD apparatus 130a or the ALD apparatus 130c of fig. 1. Space 325 may be partially filled such that air gap 329 may occupy any particular volume of space 325.

After completing one of the processes at 206, the storage device 300 will have a stack of alternating storage cell layers 302 and material layers 327 (e.g., low-k oxide material) with or without air gaps 329 (fig. 3N). Once formed, the 3D NAND storage device 300 can be further processed to deposit, for example, gate silicon oxide for forming the gates.

For example, after processing at 206 is completed, the holes 308 may be filled (e.g., planarized) with one or more suitable materials, including but not limited to TiN, W, SiN, oxides, or combinations thereof (fig. 3O). Likewise, after planarization has been performed, one or more back end of the line (BEOL) processes (e.g., WL step contact formation) may be performed to complete the fabrication of the 3D NAND memory device 300 (fig. 3P).

Fig. 4A-4C are schematic cross-sectional views of a portion of 3D NAND storage devices 400a-400C according to at least one embodiment of the present disclosure. The 3D NAND storage devices 400a-400c are substantially similar to the 3D NAND storage device 300. Accordingly, only those features unique to the 3D NAND storage devices 400a-400c are described herein.

As shown in FIG. 4A, one or more layers (e.g., layers 407b-415b or layers 407c-415c) that fill the storage holes may be removed from the storage cell layer 402 prior to 206 (e.g., depositing material layers (e.g., material layers 427b and 427c) to fill the spaces 425a (e.g., with or without air gaps 429c as described above).

For example, as shown in the detailed area in fig. 4B, instead of applying a continuous layer 407B of AlO, a discontinuous layer 407B may be formed to cover the storage cell layer 402B (and not the layer 404B) only on the sides defining the storage hole and along the ESL at the bottom of the storage hole. A storage cell layer 402b having a discontinuous layer 407b may be made by removing 407b of the layer from the storage hole prior to 206 in the area adjacent to the material layer 427b to be deposited. By using the discontinuous layer 407b, the intercell interference between the adjacent storage cell layers 402 can be reduced. For illustration purposes, the 3D NAND storage device 400b is shown without an air gap.

Similarly, discontinuous layer 407C and discontinuous layers of silicon oxide and SiN (e.g., layers 409C and 411C) may be used to form 3D NAND storage device 400C (fig. 4C). A storage cell layer 402c having discontinuous layers 407c-411c may be fabricated by removing layers 407c-411c from storage holes in areas adjacent to the material layer 427c to be deposited prior to 206. A storage cell layer 402c with discontinuous layers 407c-411c may prevent data loss between adjacent storage cell layers 402c via layer 411c (e.g., trap SiN). For illustrative purposes, the 3D NAND storage device 400 is shown with an air gap 429 c.

Fig. 5 is a schematic cross-sectional view of a portion of a 3D NAND storage device 500 in accordance with at least one embodiment of the present disclosure. The inventors have found that the present disclosure is not limited to charge trap based NAND flash memory storage devices. For example, a memory cell having resistive ram (reram) or phase change storage (PCM) may be formed using the methods described herein. More specifically, as shown in FIG. 5, a resistive memory material (such as Ta of ReRAM)₂O₅、TiO₂Etc. or Ge of PCM_xSb_yTe_z(GST), etc.) may be deposited between storage cell layer 502 and layer 515 and may be made of the same material as layer 515 (e.g., to form a polysilicon channel).

The methods described herein may be used to form a 3D NAND storage device, and by forming a plurality of storage cell layers 302 with layers 304 that reduce, if not eliminate, cross-talk (e.g., leakage of trapped charge) between adjacent storage cells of the storage cell layers 302 of the storage device 300, the layers 304 may be removed and replaced with a material 327 (e.g., a low-k oxide material, silicon oxide, etc.) that may or may not include air gaps 329 therein. Furthermore, since both storage cell layers 302 and 304 may be etched using an oxygen-based etch process, high aspect ratio storage hole etching and gap filling are less challenging than conventional processes. In addition, when storage cell layers 302 and 304 are formed from one or more of the above-described materials, the mechanical stress of the mold stack may be accommodated by the deposition conditions of the above-described materials, which in turn may reduce (if not eliminate) the likelihood of mode collapse and may allow the overall stack height of storage device 300/400 to be relatively thin compared to conventional storage devices. Furthermore, because the storage cell layer 302 is made of one or more of the above-mentioned metals (e.g., W), the conventional replacement metal gate process sometimes used to build word line steps is eliminated.

While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof.