阅读说明：本技术 一种信号传输损耗补偿电路、集成电路及传输系统 (Signal transmission loss compensation circuit, integrated circuit and transmission system ) 是由 冒鑫 马怀昌 谢芳 薛恺 裔鹏 王继春 于 2021-07-23 设计创作，主要内容包括：一种信号传输损耗补偿电路,该电路与数字信号传输线并接,用于对通过该传输线传输的数字信号进行损耗补偿。所述补偿电路包括直流电平补偿电路、和沿口调整电路。所述沿口调整电路连接所述数字信号传输线,用于调整数字信号沿口,调节数据转换速率。所述直流电平补偿电路连接所述数字信号线端口,以及所述沿口调整电路输出端,用于增大所述数字信号高电平时的直流电平值。(A signal transmission loss compensation circuit is connected in parallel with a digital signal transmission line and is used for performing loss compensation on a digital signal transmitted through the transmission line. The compensation circuit comprises a direct current level compensation circuit and a bead adjustment circuit. The edge adjusting circuit is connected with the digital signal transmission line and used for adjusting the digital signal edge and adjusting the data conversion rate. The direct current level compensation circuit is connected with the port of the digital signal line and the output end of the edge adjusting circuit and is used for increasing the direct current level value of the digital signal at the high level.)

1. A signal transmission loss compensation circuit, which is connected in parallel with a digital signal transmission line, for performing loss compensation on a digital signal transmitted through the transmission line,

the compensation circuit comprises a direct current level compensation circuit and a bead adjusting circuit,

the above-mentionedBead adjusting circuitThe digital signal transmission line is connected and used for adjusting a digital signal edge and adjusting the data conversion rate;

the above-mentionedDC level compensation circuitConnecting the digital signal line ports, andbead adjusting circuitAnd the output end is used for increasing the direct current level value when the digital signal is at the high level.

2. The signal transmission loss compensation circuit of claim 1, wherein the compensation circuit further comprises an over-voltage protection circuit,

the overvoltage protection circuit, the direct current level compensation circuit and the bead adjusting circuit are connected in sequence,

the above-mentionedOvervoltage protection circuitAnd the digital signal transmission line is connected in parallel and used for protecting the signal transmission loss compensation circuit from being damaged by external high voltage.

3. The signal transmission loss compensation circuit of claim 2, wherein said digital signal transmission line is a serial bus.

4. The signal transmission loss compensation circuit of claim 3, wherein the serial bus is a USB serial bus.

5. The signal transmission loss compensation circuit of claim 3, wherein the signal transmission loss compensation circuit is configured to compensate for the loss of the signalOvervoltage protection circuitThe device comprises a first MOS tube and a second MOS tube which are respectively connected with one of a digital signal wire pair of a serial port bus.

6. The signal transmission loss compensation circuit according to claim 3,characterized in that theBead adjusting circuitThe method comprises the following steps of (1),

a first equalization comparator, a first AND logic gate, a first delay unit, a third MOS transistor, a fourth MOS transistor, a first current source and a third current source, an

A second equalization comparator, a second AND logic gate, a second delay unit, a fifth MOS transistor, a sixth MOS transistor, a fifth current source and a sixth current source,

the input ends of the first equalization comparator and the second equalization comparator are connected in a cross way and are respectively connected with the digital signal line pair of the serial port bus,

the output end of the first equalization comparator is simultaneously connected with the input ends of the first AND logic gate and the first delay unit, the output end of the second equalization comparator is simultaneously connected with the input ends of the second AND logic gate and the second delay unit,

the output end of the first delay unit is connected with the other input end of the second AND logic gate, the output end of the second delay unit is connected with the other input end of the first AND logic gate,

the output end of the first AND logic gate is connected with the grid ends of the third MOS transistor and the sixth MOS transistor in parallel, the output end of the second AND logic gate is connected with the grid ends of the fourth MOS transistor and the fifth MOS transistor in parallel,

the third MOS tube and the fourth MOS tube are connected in series and then are respectively connected with the first current source and the third current source, and the fifth MOS tube and the sixth MOS tube are connected in series and then are respectively connected with the second current source and the fourth current source.

7. The signal transmission loss compensation circuit of claim 3, wherein the signal transmission loss compensation circuit is configured to compensate for the loss of the signalDC level compensation circuitComprises a first logic judgment circuit and a first level compensation circuit,

the output end of the first logic judgment circuit is connected with the input end of the first level compensation circuit,

the input end of the first logic judgment circuit is connected with the logic output end of the bead adjusting circuit,

and the output end of the first level compensation circuit is connected with the digital signal line pair of the serial port bus.

8. The signal transmission loss compensation circuit of claim 5,

the first level compensation circuit comprises a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor and a fifth current source,

the first logic judgment circuit comprises a first NOR logic gate, a second NOR logic gate and a third NOR logic gate, wherein,

a fifth current source is connected in parallel with the seventh MOS transistor, the eighth MOS transistor and the ninth MOS transistor,

the output of the first equalization comparator and the output of the first delay unit are connected to the input end of the first NOR gate, the output of the first NOR gate is connected with the gate end of the eighth MOS tube,

the output of the second equalization comparator and the output of the second delay unit are connected to the input end of the second NOR gate, the output of the second NOR gate is connected with the gate end of the seventh MOS tube,

the output of the first NOR gate and the output of the second NOR gate are connected with the input end of the third NOR gate, the output of the third NOR gate is connected with the gate end of the seventh MOS tube,

the source ends of the seventh MOS tube and the eighth MOS tube are respectively connected with the digital signal line pair of the serial port bus.

9. A digital signal transmission system is characterized in that the system comprises a first digital signal port, a second digital signal port and a digital signal transmission line connected with the first digital signal port and the second digital signal port,

the signal transmission loss compensation circuit of claim 1, further comprising a compensation circuit connected across the digital signal transmission line.

10. An integrated circuit connected across a digital signal transmission line for transmission loss compensation of a digital signal, comprising the signal transmission loss compensation circuit of claim 1.

Technical Field

The invention belongs to the technical field of data transmission, and particularly relates to a signal transmission loss compensation circuit, an integrated circuit and a transmission system.

Background

USB (Universal Serial Bus) is an interface technology standard widely used in the PC field. The USB interface has the advantages of simple interface, convenient application and high transmission speed. Since the release of the USB standard, through the development of many years, the USB interface has become an interface standard with very wide application.

In the USB2.0 standard, there are 3 transmission modes, which are low-speed mode, full-speed mode, and high-speed mode. Their transmission rates are 1.5Mbps, 12Mbps, and 480Mbps, respectively. In low-speed and full-speed modes, the output voltage swing is 3.3V, in high-speed mode the output voltage swing is 0.4V, and the data ports D + and D-support a maximum voltage of 5V. The low-speed mode and the full-speed mode have low speed, so that the loss is low in a general transmission process and no additional processing is needed. As shown in fig. 1, when a high-speed signal is transmitted, if the transmission distance is too long, the channel attenuation increases, the eye pattern of the receiving end receiving the data signal becomes very poor, the integrity of the data signal is affected, and in the worst case, data errors may be caused.

Disclosure of Invention

The invention aims to provide a signal transmission loss compensation circuit to overcome the defects of the existing serial port bus data transmission scheme.

In one embodiment of the present invention, a signal transmission loss compensation circuit structure includes: the device comprises an overvoltage protection circuit, a bead adjusting circuit and a direct current level compensating circuit. The overvoltage protection circuit, the direct current level compensation circuit and the bead adjusting circuit are sequentially connected.

The above-mentionedBead adjusting circuitThe digital signal transmission line is connected and used for accelerating the conversion rate of the digital signal edge;

the above-mentionedDC level compensation circuitConnecting the digital signal line ports, andbead adjusting circuitAnd the output end is used for increasing the direct current level value when the digital signal is at the high level.

The above-mentionedOvervoltage protection circuitAnd the digital signal transmission line is connected in parallel and used for protecting the signal transmission loss compensation circuit from being damaged by external high voltage.

The signal transmission attenuation compensation circuit is different from the traditional relay driver, does not cut off a data signal path, is directly mounted on a data signal line pair, reduces the design complexity and eliminates the transmission delay of the traditional relay driver. Meanwhile, the bead compensation intensity and the direct-current level compensation intensity can be adjusted, and the method is suitable for compensation application under various signal transmission loss conditions.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

fig. 1 is a comparison graph of eye diagrams of 480Mbps data signals attenuated by different lengths of transmission cables in the prior art.

Fig. 2 is a schematic diagram of a relay driver circuit in a prior art solution.

Fig. 3 is a schematic diagram of an application of the data transmission system according to one embodiment of the present invention.

Fig. 4 is a schematic diagram of a signal transmission loss compensation circuit according to one embodiment of the present invention.

Fig. 5 is a diagram illustrating timing of control signals of a signal transmission loss compensation circuit according to an example of the present invention.

Fig. 6 is a differential eye diagram compensated for a high transmission loss data signal in accordance with an example of the invention.

100-a system for data transmission, comprising,

101-data ports 1, 102-data ports 2, 103-high speed signal transmission attenuation compensation circuit,

104-a first connection point, 105-a second connection point,

201-edge adjusting circuit, 202-DC level compensating circuit, 203-overvoltage protection circuit,

204-DP port, 205-DM port,

301-first NMOS transistor, 302-second NMOS transistor, 303-equalization comparator 1,

304-equalization comparators 2, 305-first combinatorial logic.

Detailed Description

To solve the problem of data signal loss during transmission, the prior art solution is shown in fig. 2. A relay driver is inserted into a data transmission channel, the relay driver high-speed data transmission channel includes 2 sets of oppositely-directed transceivers, each set of transceivers includes an equalizing receiver, and a transmitter. The relay driver cuts off the direct connection between the data port 1 and the data port 2, and in order to ensure that the port states of the data ports 1 and2 can be completely converted and transmitted, a complicated state detection control system for the data ports 1 and2 needs to be designed. Meanwhile, due to the addition of the relay driver, the signal delay between the data port 1 and the data port 2 is increased. In addition, the bidirectional transceiver needs to strictly comply with the USB electrical standard, and the power consumption is large.

The invention provides a signal transmission loss compensation circuit structure which is used for solving the problems that transmission delay is increased due to the fact that two data ports are cut off to be directly connected in the prior art scheme shown in figure 2, the scheme design is complex, and power consumption is large.

According to one or more embodiments, a signal transmission loss compensation circuit structure comprises an overvoltage protection circuit, a bead adjustment circuit and a direct-current level compensation circuit.

Wherein, the overvoltage protection circuit is connected with the data ports D + and D-, and the internal DP and DM ports.

The edge adjusting circuit is connected with DP and DM ports and used for accelerating the conversion rate of D + and D-edges.

The direct current level compensation circuit is connected with DP and DM ports, and the edge adjusting circuit outputs control signals for increasing direct current levels when D + and D-high level signals exist.

Further, the overvoltage protection circuit comprises NMOS tubes MN0 and MN 1. MN0 drain terminal is connected with data port D +, source terminal is connected with internal DP port, grid terminal is connected with control signal EN. MN1 drain terminal is connected with data port D-, source terminal is connected with internal DM port, grid terminal is connected with control signal EN. The overvoltage protection NMOS tube MN0 and the overvoltage protection NMOS tube MN1 are 5V devices, and the control signal EN is an internal preset voltage enabling signal.

Further, the edge adjustment circuit comprises an equalization comparator 1, an equalization comparator 2, AND logic gates AND1 AND2, Delay units Delay1 AND Delay2, NMOS transistors MN3, MN4, MN5, MN6, current sources I1, I2, I3, AND I4. Wherein, the positive input end of the equalization comparator 1 is connected with a DP port, and the negative input end is connected with a DM port; the positive input end of the equalization comparator 2 is connected with the DM port, and the negative input end is connected with the DP port; one input end of the AND logic gate AND1 is connected with the output end OP of the equalization comparator 1, AND the other input end is connected with the output OMD of the Delay unit Delay 2; the input end of the Delay unit Delay1 is connected with the output end OP of the equalization comparator 1, AND the output end is connected with the input end of the AND logic gate AND 2; the input end of the Delay unit Delay2 is connected with the output end OM of the equalization comparator 2, AND the output end is connected with the input end of the AND logic gate AND 1; the source end of the NMOS tube MN3 is connected with a DP port, the drain end is connected with a current source I1, AND the gate end is connected with the output end of the AND logic gate AND 1; one end of the current source I1 is connected with a power supply, and the other end is connected with the drain end of the MN 3; the drain end of the NMOS tube MN4 is connected with a DP port, the source end is connected with a current source I3, AND the gate end is connected with the output end of an AND logic gate AND 2; the other end of the current source I3 is grounded; the source end of the NMOS tube MN5 is connected with a DM port, the drain end is connected with a current source I2, AND the gate end is connected with the output end of an AND logic gate AND 2; the other end of the current source I2 is connected with a power supply; the drain end of the NMOS tube MN6 is connected with a DM port, the source end is connected with a current source I4, AND the gate end is connected with the output end of an AND logic gate AND 1; the current source I4 has its other end connected to ground.

Further, the equalization comparator 1 and the equalization comparator 2 have high frequency compensation while the comparator threshold voltage is adjustable; the current sources I1, I2, I3 and I4 are adjustable in current magnitude; the Delay units Delay1 and Delay2 have adjustable Delay time, and the Delay time needs to be less than the shortest data period.

Further, the dc level compensation circuit includes NMOS transistors MN7, MN8, MN9, a current source I5, a resistor R0, and NOR gates NOR1, NOR2, and NOR 3. The source end of the NMOS transistor MN7 is connected with a DP port, the drain end of the NMOS transistor MN7 is connected with the output end of the current source I5, and the gate end of the NMOS transistor MN is connected with the output end of the NOR logic gate NOR 2; the source end of the NMOS transistor MN8 is connected with a DM port, the drain end of the NMOS transistor MN8 is connected with the output end of the current source I5, and the gate end of the NMOS transistor MN is connected with the output end of the NOR logic gate NOR 1; the other end of the current source I5 is connected with a power supply; the drain terminal of the NMOS transistor MN9 is connected with the output terminal of the current source I5, the source terminal of the NMOS transistor MN is connected with one end of a resistor R0, and the gate terminal of the NMOS transistor MN is connected with the output terminal PD _ DC of the NOR gate NOR 3; the other end of the resistor RO is connected with the ground; the NOR gate NOR1 has its input terminal connected to the output terminal OP of the equalization comparator 1 in claim 3 and its other input terminal connected to the output terminal OPD of the Delay unit Delay1 in claim 3; the input end of the NOR logic gate NOR2 is connected with the output end OM of the equalization comparator 2 in claim 3, and the other input end is connected with the output end OMD of the Delay unit Delay2 in claim 3; the input end of the NOR logic gate NOR3 is connected to the output end DM _ ON of the NOR logic gate NOR1, and the other input end is connected to the output end DP _ ON of the NOR logic gate NOR 2.

Furthermore, in the dc level compensation circuit, the current source I5 is an adjustable current source; the R0 resistor value is between 50 ohms and 250 ohms.

As described above, in the embodiment of the present invention, the signal transmission loss compensation circuit has the following advantages:

1, the physical connection of a cable between two data ports is completely reserved, a complex data port communication state detection design is not needed, the transmission delay of a traditional relay driver is avoided, and meanwhile, a single signal transmission loss compensation circuit supports the common use of a plurality of ports on a data bus;

2, a bidirectional transceiver is not needed, only one group of compensation circuits are needed, and the power consumption area is reduced;

and 3, the bead compensation intensity and the direct-current level compensation intensity can be adjusted, and the method is suitable for application under different transmission loss conditions.

In accordance with one or more embodiments, as shown in fig. 3, a data transmission system 100 is provided, in which a signal transmission loss compensation circuit structure 103 is connected across a data port 1 and a data port 2, and is directly connected to connection points 104 and 105 of a data port 1101 and a data port 2102.

As shown in fig. 4, the signal transmission loss compensation circuit structure 103 at least includes an overvoltage protection circuit 203, a bead adjustment circuit 201, and a dc level compensation circuit 202.

The overvoltage protection circuit 203 is connected with the USB buses D +104 and D-105, and the internal DP port 204 and the DM port 205. The overvoltage protection circuit 203 is used for protecting internal devices from high voltage on the USB ports D + and D-.

The edge adjusting circuit 201 is connected to the DP port 204 and the DM port 205, and is used to reduce the D + and D-rise-fall time, so as to achieve the function of compensating the edge.

The dc level compensation circuit 202 connects the DP port 204 and the DM port 205, and the edge adjustment circuit outputs a control signal for increasing the dc voltage at the D + and D-high level signals.

Specifically, as shown in fig. 4, the overvoltage protection circuit 203 includes an NMOS transistor 301 and an NMOS transistor 302. The drain terminal of the NMOS tube 301 is connected to the USB bus D +104, the source terminal is connected to the internal bus DP204, and the gate terminal is connected to the control signal EN. The drain terminal of the NMOS tube 301 is connected to the USB bus D-105, the source terminal is connected to the internal port DM205, and the gate terminal is connected to the control signal EN. Overvoltage protection NMOS pipe 301 and 302 are 5V devices, control signal EN is inside preset voltage enable signal, through setting up EN voltage value guarantees inside device safety.

Specifically, the bead adjustment circuit 201 includesEqualizing comparator 1 303，Equalizing comparator 2304, AND logic gates AND1 AND2, Delay units Delay1 AND Delay2, NMOS transistors MN3, MN4, MN5, MN6, current sources I1, I2, I3, I4. Wherein the content of the first and second substances,

the above-mentionedEqualizing comparator 1303 positive input is connected with the DP port 204, and negative input is connected with the DM port 205;

the above-mentionedEqualizing comparator 2304 positive input is connected with the DM port 205, and negative input is connected with the DP port 204;

one input end of the AND logic gate AND1 is connected to the output end OP of the equalization comparator 1303, AND the other input end is connected to the Delay unit Delay2 to output the OMD;

the input end of the Delay unit Delay1 is connected with the output end OP of the equalization comparator 1303, AND the output end is connected with the input end of the AND gate AND 2;

the input end of the Delay unit Delay2 is connected with the output end OM of the equalization comparator 2304, AND the output end is connected with the input end of the AND logic gate AND 1;

the source end of the NMOS tube MN3 is connected with the DP port 204, the drain end is connected with the current source I1, AND the gate end is connected with the output end of the AND logic gate AND 1; one end of the current source I1 is connected with a power supply, and the other end is connected with the drain end of the MN 3;

the drain end of the NMOS tube MN4 is connected with the DP port 204, the source end is connected with a current source I3, AND the gate end is connected with the output end of an AND logic gate AND 2;

the other end of the current source I3 is grounded;

the source end of the NMOS transistor MN5 is connected with the DM port 205, the drain end is connected with a current source I2, AND the gate end is connected with the output end of an AND logic gate AND 2;

the other end of the current source I2 is connected with a power supply;

the drain end of the NMOS transistor MN6 is connected with the DM port 205, the source end is connected with a current source I4, AND the gate end is connected with the output end of an AND logic gate AND 1;

the current source I4 has its other end connected to ground.

The equalization comparator 1303 and the equalization comparator 2304 can find the intersection point of the differential signals DP204 and DM205, while the equalization comparator 1303 and the equalization comparator 2304 have adjustable high frequency compensation and comparator threshold voltage. The high-frequency compensation is adjusted to compensate signals with different attenuation amplitudes; and adjusting the initial time of the edge compensation and the ending time of the direct current level compensation by adjusting the threshold voltage of the comparator. As shown at T1 in fig. 5, i.e., the lead and lag times relative to the intersection of signals D + and D-are introduced by setting the comparator threshold offset voltage. The AND logic gates AND1 AND2, AND the Delay units Delay1 AND Delay2 process the comparison results of the equalization comparator 1303 AND the equalization comparator 2304, AND generate high-level pulse signals EN _ UP _ DP AND EN _ UP _ DM that are Delay times T2 of the Delay units Delay1 AND Delay 2. The signals EN _ UP _ DP and EN _ UP _ DM control the on-off of NMOS tubes MN3, MN4, MN5 and MN6, and reduce the rising time and the falling time of signals of the DP port 204 and the DM port 205.

The current sources I1, I2, I3 and I4 are adjustable in current magnitude and used for adjusting the bead compensation intensity; the Delay units Delay1 and Delay2 have adjustable Delay times, and the Delay times must be less than the minimum period of the compensated data signal.

Specifically, the dc level compensation circuit 202 includes NMOS transistors MN7, MN8, MN9, a current source I5, a resistor R0, and a combinational logic 305. Wherein the combinational logic 305 includes NOR logic gates NOR1, NOR2, NOR 3. The source end of the NMOS transistor MN7 is connected with a DP port 204, the drain end of the NMOS transistor MN7 is connected with the output end of the current source I5, and the gate end of the NMOS transistor MN is connected with the output end of the NOR logic gate NOR 2; the source end of the NMOS transistor MN8 is connected with the DM port 205, the drain end is connected with the output end of the current source I5, and the gate end is connected with the output end of the NOR logic gate NOR 1; the other end of the current source I5 is connected with a power supply; the drain terminal of the NMOS transistor MN9 is connected with the output terminal of the current source I5, the source terminal of the NMOS transistor MN is connected with one end of a resistor R0, and the gate terminal of the NMOS transistor MN is connected with the output terminal PD _ DC of the NOR gate NOR 3; the other end of the resistor RO is connected with the ground; the NOR logic gate NOR1 has an input terminal connected to the output terminal OP of the equalization comparator 1303 and another input terminal connected to the output terminal OPD of the Delay unit Delay 1; one input end of the NOR logic gate NOR2 is connected to the output end OM of the equalization comparator 2304, and the other input end is connected to the output end OMD of the Delay unit Delay 2; the input end of the NOR logic gate NOR3 is connected to the output end DM _ ON of the NOR logic gate NOR1, and the other input end is connected to the output end DP _ ON of the NOR logic gate NOR 2.

The combinational logic 305 generates control signals DP _ ON and DM _ ON. The control signal controls the NMOS transistors MN7 and MN8 to turn on and off, and the adjustable current source I5 makes current flow into the DP port 204 and the DM port 205 by turning on MN7 or MN 8. And increasing the voltage amplitude of the high-level ports D +104 and D-105, and compensating the direct-current level loss of the ports D +104 and D-105.

The current source I5 is an adjustable current source, and the current value of the current source I5 can adjust the direct current level compensation intensity, so that the targeted compensation of transmission attenuation of different degrees is met; the R0 resistor value is between 50 ohms and 250 ohms.

In summary, the present invention provides a signal transmission loss compensation circuit structure, which at least includes an overvoltage protection circuit, a bead adjustment circuit, and a dc level compensation circuit. The overvoltage protection circuit is connected with the data buses D + and D-, the DP port and the DM port and is used for protecting internal devices from being damaged by high voltage on the data ports D + and D-; the edge port adjusting circuit is connected with the DP port and the DM port and used for reducing the rising and falling time of the data ports D + and D-and compensating the edge port conversion rate; the direct current level compensation circuit is connected with the DP port and the DM port, and the edge adjusting circuit outputs a control signal for increasing the direct current level when the D + and D-high level signals of the data port are increased. When the signal transmission loss compensation circuit is connected to the data ports D + and D-, the overvoltage protection MOS tubes MN0 and MN1 are conducted by setting the voltage of an internal preset control signal EN. At the moment, the equalizing comparators 1 and2 in the edge adjusting circuit detect the intersection points of the high-speed differential signals D + and D-in real time. When the D + level is higher than the D-, a high-level pulse signal EN _ UP _ DP is generated to control MN3 and MN6 to be conducted, and when the D-level is higher than the D +, a high-level pulse signal EN _ UP _ DM is generated to control MN4 and MN5 to be conducted, and a current source flows into or out of data D + and D-ports to accelerate the edge conversion rate of the data D + and D-. And the direct current level compensation circuit is used for compensating the amplitude of high level signals on the D + and the D-after the edge compensation.

The signal transmission loss compensation circuit structure adopts the structural design of directly mounting on the data buses D + and D-, keeps the direct connection of the data port 1 and the data port 2, simplifies the system application and design, has no transmission delay of a traditional relay driver, and can play a compensation role on all ports on a data channel; the design of the strength of the adjustable bead compensation and the direct-current level compensation meets the application under the condition of different degrees of transmission loss; an overvoltage protection circuit is adopted, and the interior of the signal transmission loss compensation circuit structure can be designed by adopting a high-speed device, so that the requirement of high-speed signal rate is met. The present invention overcomes various disadvantages of the prior art and has a high industrial value.

It should be noted that while the foregoing has described the spirit and principles of the invention with reference to several specific embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, nor is the division of aspects, which is for convenience only as the features in these aspects cannot be combined. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.