阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 林琨祐 林恩平 葛育菱 廖志腾 于 2021-06-11 设计创作，主要内容包括：方法包括：提供具有第一半导体材料的衬底；创建覆盖衬底的nFET区域的掩模；蚀刻衬底的pFET区域以形成沟槽；在沟槽中外延生长第二半导体材料,其中,第二半导体材料与第一半导体材料不同；以及图案化nFET区域和pFET区域,以在nFET区域中产生第一鳍,并且在pFET区域中产生第二鳍,其中,第一鳍包括第一半导体材料,并且第二鳍包括位于底部上方的顶部,其中,顶部包括第二半导体材料,并且底部包括第一半导体材料。本申请的实施例还涉及半导体器件及其形成方法。(The method comprises the following steps: providing a substrate having a first semiconductor material; creating a mask overlying the nFET region of the substrate; etching the pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin comprises a first semiconductor material and the second fin comprises a top portion located over a bottom portion, wherein the top portion comprises a second semiconductor material and the bottom portion comprises the first semiconductor material. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.)

1. A method of forming a semiconductor structure, comprising:

providing a substrate having a first semiconductor material;

creating a mask overlying the nFET region of the substrate;

etching the pFET region of the substrate to form a trench;

epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and

patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin comprises the first semiconductor material and the second fin comprises a top portion over a bottom portion, wherein the top portion comprises the second semiconductor material and the bottom portion comprises the first semiconductor material.

2. The method of claim 1, wherein the substrate is a silicon substrate and the second semiconductor material comprises silicon germanium.

3. The method of claim 1, further comprising:

after epitaxially growing the second semiconductor material, a top surface of the nFET region and the pFET region is planarized.

4. The method as claimed in claim 1, wherein patterning the nFET region and the pFET region comprises:

forming a fin hardmask over the nFET region and the pFET region; and

the nFET region and the pFET region are etched through the fin hardmask by the same process to produce the first fin and the second fin.

5. The method of claim 4 wherein etching the nFET region and the pFET region comprises:

anisotropically etching the nFET region and the pFET region through the fin hardmask;

isotropically etching the nFET region and the pFET region through the fin hardmask after the anisotropic etching;

treating a structure resulting from the anisotropic etching and the isotropic etching with a process gas mixture; and

repeating the anisotropic etching, the isotropic etching, and the processing to produce the first fin in the nFET region and the second fin in the pFET region, wherein the anisotropic etching, the isotropic etching, and the processing apply different gases.

6. The method of claim 5, wherein the anisotropic etch comprises applying HBr, Cl₂Ar or mixtures thereof.

7. The method of claim 5, wherein the isotropic etching comprises applying NF₃、CHF₃、CF₄Or mixtures thereof.

8. The method of claim 5, wherein the treating comprises applying O₂、CO₂、SF₆、CH₃F or mixtures thereof.

9. A semiconductor structure, comprising:

a substrate;

a first fin extending from the substrate; and

a second fin extending from the substrate, wherein the second fin includes a top portion above a bottom portion, the bottom portions of the first and second fins include crystalline silicon, the top portion of the second fin includes a semiconductor material having a higher charge carrier mobility than silicon, a top surface of the second fin and a top surface of the first fin are substantially coplanar, and the bottom portion of the second fin extends deeper into the substrate than the first fin.

10. A semiconductor structure, comprising:

a substrate;

two first fins adjacent to each other and extending from a first region of the substrate;

two second fins adjacent to each other and extending from a second region of the substrate; and

an isolation structure over the substrate and adjacent to the first and second fins, wherein each of the second fins includes a top portion over a bottom portion, the bottom portions of the first and second fins include crystalline silicon, the top portions of the second fins include silicon germanium, a top surface of the second fins and a top surface of the first fins are substantially coplanar, each of the second fins being taller than the first fins.

Technical Field

Embodiments of the present application relate to semiconductor structures and methods of forming the same.

Background

The electronics industry is increasingly demanding smaller and faster electronic devices that are capable of supporting more and more sophisticated and sophisticated functions. To meet these demands, there is a continuing trend in the Integrated Circuit (IC) industry to manufacture low cost, high performance, and low power consumption ICs. To date, these goals have been largely achieved by reducing IC size (e.g., minimum IC component size), thereby increasing production efficiency and reducing associated costs. However, such scaling also increases the complexity of the IC manufacturing process. Accordingly, similar advances in IC manufacturing processes and technologies are needed to achieve continued advances in IC devices and their performance.

FinFET devices have been introduced to increase gate-channel coupling, reduce off-state current, and reduce Short Channel Effects (SCE) over planar transistors. As device scaling continues, such as approaching 5nm and 3nm process nodes, conventional silicon-based finfets also approach their performance limits. For example, extremely compact gate dimensions and extremely small device volumes make doping and strain engineering for performance very challenging for FinFET devices. Improvements in FinFET fabrication are highly desirable.

Disclosure of Invention

Some embodiments of the present application provide a method of forming a semiconductor structure, comprising: providing a substrate having a first semiconductor material; creating a mask overlying the nFET region of the substrate; etching the pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin comprises the first semiconductor material and the second fin comprises a top portion over a bottom portion, wherein the top portion comprises the second semiconductor material and the bottom portion comprises the first semiconductor material.

Other embodiments of the present application provide a semiconductor structure comprising: a substrate; a first fin extending from the substrate; and a second fin extending from the substrate, wherein the second fin includes a top portion above a bottom portion, the bottom portions of the first and second fins include crystalline silicon, the top portion of the second fin includes a semiconductor material having a higher charge carrier mobility than silicon, a top surface of the second fin and a top surface of the first fin are substantially coplanar, and the bottom portion of the second fin extends deeper into the substrate than the first fin.

Still other embodiments of the present application provide a semiconductor structure comprising: a substrate; two first fins adjacent to each other and extending from a first region of the substrate; two second fins adjacent to each other and extending from a second region of the substrate; and an isolation structure over the substrate and adjacent to the first and second fins, wherein each of the second fins includes a top portion over a bottom portion, the bottom portions of the first and second fins include crystalline silicon, the top portions of the second fins include silicon germanium, a top surface of the second fins and a top surface of the first fins are substantially coplanar, each of the second fins is taller than the first fins.

Drawings

The invention is best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1A and 1B illustrate a flow diagram of a method of forming a semiconductor device in accordance with various aspects of the present invention.

Fig. 2A, 3, 4, 5A, 5B, 5C, 6, 7, 9B, 10, and 11 illustrate cross-sectional views of portions of a semiconductor device in intermediate steps of fabrication according to embodiments of the method of fig. 1A-1B, according to some embodiments.

Fig. 2B illustrates a top view of a portion of a semiconductor device according to some embodiments.

Fig. 8 and 9A illustrate perspective views of portions of semiconductor devices according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Further, when a value or range of values is described using "about," "approximately," etc., the term includes values within certain variations (such as +/-10% or other variations) of the described values, unless otherwise specified, as would be understood by one of ordinary skill in the art in view of the particular techniques disclosed herein. For example, the term "about 5 nm" may include size ranges of 4.5nm to 5.5nm, 4.0nm to 5.0nm, and the like.

The present application relates generally to semiconductor structures and fabrication processes, and more particularly to CMOS (complementary metal oxide semiconductor) devices having p-channel FinFET transistors and n-channel FinFET transistors. It is an object of the present invention to provide a method of forming a p-channel fin and an n-channel fin on the same substrate, wherein the n-channel fin comprises a first semiconductor material and the p-channel fin comprises a second semiconductor material having a higher charge carrier (e.g., hole) mobility than the first semiconductor material. In an embodiment of the invention, the first semiconductor material is monocrystalline silicon and the second semiconductor material is a silicon germanium alloy. In an embodiment, p-channel fins are used to form p-type finfets and n-channel fins are used to form n-type finfets. The use of p-channel fins further enhances the performance of p-type finfets compared to approaches where n-type finfets and p-type finfets use the same material in their channels. Embodiments of the present invention also optimize the etching of the p-channel fin and the n-channel fin by the same etching process to form the p-channel fin and the n-channel fin with closely matched critical dimensions and closely matched fin heights. This further improves the planarity of the isolation structure between the p-channel fin and the n-channel fin. The planarity of the isolation structures in turn improves subsequent manufacturing processes, such as gate formation. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein.

Fig. 1A is a flow chart of a method 10 for fabricating a semiconductor device according to various aspects of the present invention. The present invention contemplates additional processing. Additional operations may be provided before, during, and after method 10, and some of the operations described may be removed, replaced, or eliminated with respect to additional embodiments of method 10.

Method 10 is described below in conjunction with fig. 2A-11, with fig. 2A-11 showing various views of a semiconductor device (or semiconductor structure) 100 at various steps of fabrication according to method 10, according to some embodiments. In some embodiments, device 100 is part of an IC chip, system on a chip (SoC), or portion thereof, including various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs or PFETs), n-type field effect transistors (NFETs or NFETs), finfets, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Complementary Metal Oxide Semiconductor (CMOS) transistors, Bipolar Junction Transistors (BJTs), laterally diffused mos (ldmos) transistors, high voltage transistors, high frequency transistors, memory devices, other suitable components, or combinations thereof. Fig. 2A-11 have been simplified for clarity in order to better understand the inventive concepts of the present invention. Additional components may be added to device 100 and some of the components described below may be replaced, modified, or eliminated in other embodiments of device 100.

In operation 12, the method 10 (fig. 1A) is provided or provided with a substrate 102, such as shown in fig. 2A. In the depicted embodiment, the substrate 102 is a silicon substrate, such as a silicon wafer with crystalline silicon. Alternatively, the substrate 102 may include: another elemental semiconductor such as germanium; compound semiconductors including silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium phosphide, aluminum gallium arsenide, gallium indium phosphide, and gallium indium arsenide phosphide; or a combination thereof.

In operation 14, the method 10 (fig. 1A) forms a patterned mask 103 over the substrate 102, such as shown in fig. 2A and 2B. According to an embodiment, fig. 2A shows the patterned mask 103 and the substrate 102 in a cross-sectional view in the "X-Z" plane, while fig. 2B shows the patterned mask 103 and the substrate 102 in a top view in the "X-Y" plane. The patterned mask 103 covers the substrate 102 in the nFET region and exposes the substrate 102 in the pFET region. In the present invention, an n-type transistor, such as an n-type FinFET, will be formed in the nFET region, and a p-type transistor, such as a p-type FinFET, will be formed in the pFET region. N-type transistors and p-type transistors may be coupled to form a CMOS device. In the present embodiment, the patterned mask 103 is shown as having parallel rectangular strips. In alternative embodiments, the patterned mask 103 may have other shapes and configurations. The patterned mask 103 may be formed using one or more photolithography processes, including double patterning or multiple patterning processes. In various embodiments, the patterned mask 103 may comprise silicon oxide, silicon nitride, photoresist, or other suitable material.

In operation 16, the method 10 (fig. 1A) etches the substrate 102 through the patterned mask 103, forming trenches 102' in the substrate 102, such as shown in fig. 3 according to an embodiment. Trenches 102' (one shown in fig. 3) are formed in the pFET region while the substrate 102 remains intact or substantially intact in the nFET region under the patterned mask 103. The etching process may include dry etching, wet etching, Reactive Ion Etching (RIE), and/or other suitable processes. For example, the dry etching process may be performed with an oxygen-containing gas, a fluorine-containing gas (e.g., CF)₄、SF₆、CH₂F₂、CHF₃And/or C₂F₆) Chlorine-containing gas (e.g., Cl)₂、CHCl₃、CCl₄And/or BCl₃) Bromine-containing gas (e.g., HBr and/or CHBR)₃) Iodine-containing gas, other suitable gases and/or plasmas and/or combinations thereof. For example, the wet etch process may include etching in dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; containing hydrofluoric acid (HF), nitric acid (HNO)₃) And/or acetic acid (CH)₃COOH); or other suitable wet etchant. In an embodiment, the etching process is anisotropic such that the boundary between the nFET region and the pFET region is well maintained during operation 16. In some embodiments, the depth of the trench 102' is controlled to be in a range of about 40nm to about 70nm in the "Z" direction from the top surface of the substrate 102. This range is intended to provide a suitable semiconductor thickness for forming the fins, as will be discussed later. In this embodiment, the depth of the trench 102' may be controlled using a timer and depends on the etch rate of the material in the substrate 102 during the etch process.

In operation 18, method 10 (fig. 1A) is in trench 102', according to an embodimentA semiconductor material is epitaxially grown to form a semiconductor layer 104 over the substrate 102 in the pFET region, such as shown in fig. 4. In the present embodiment, the semiconductor material in the semiconductor layer 104 has a higher charge carrier mobility (or simply mobility) than the material in the substrate 102. In the present embodiment, the substrate 102 includes crystalline silicon, and the semiconductor layer 104 includes silicon germanium (SiGe) having a higher hole mobility than the crystalline silicon. This applies to creating high performance pfets in the pFET region and high performance nfets in the nFET region. In a further embodiment, the silicon germanium in the semiconductor layer 104 has a constant or near constant atomic percent (at.%) germanium. In a further embodiment, the silicon germanium in the semiconductor layer 104 has a constant or near constant atomic percentage of germanium in the range of about 15 at.% to about 30 at.%. In other words, the semiconductor layer 104 includes Si_1-xGe_xWherein x is in the range of 15 at.% to 30 at.%. The range of Ge at.% is intended to provide suitable performance enhancement when portions of the semiconductor layer 104 are used as FinFET transistor channels. In another embodiment, the semiconductor layer 104 includes silicon germanium (SiGe) with a gradient of Ge at.%. For example, Ge at.% in the semiconductor layer 104 may be gradually increased as the semiconductor layer 104 is grown to adjust the crystal quality. In such an example, when growing the semiconductor layer 104 is complete, the lower portion of the semiconductor layer 104 (proximate to the substrate 102) has a lower Ge at.% than the upper portion of the semiconductor layer 104. In various embodiments, depending on the material in the substrate 102, the material in the semiconductor layer 104 may include silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium arsenide and indium antimonide, silicon germanium, gallium arsenide phosphide, aluminum indium phosphide, aluminum gallium arsenide, indium gallium arsenide, gallium indium phosphide, or combinations thereof. In an embodiment, epitaxially growing the semiconductor layer 104 is accomplished by a Molecular Beam Epitaxy (MBE) process, a Chemical Vapor Deposition (CVD) process, a Metal Organic Chemical Vapor Deposition (MOCVD) process, other suitable epitaxial growth processes, or a combination thereof.

After growth of the semiconductor layer 104 is complete, operation 18 removes the patterned hard mask 103 and planarizes the top surface of the device 100, for example, using Chemical Mechanical Planarization (CMP). As shown in fig. 4, the top surface of the semiconductor layer 104 (in the pFET region) and the top surface of the substrate 102 in the nFET region are coplanar or substantially coplanar. In an embodiment, the height (or thickness) h1 of the semiconductor layer 104 along the Z direction is in a range from about 40nm to about 70 nm. This height range is intended to provide sufficient sidewall surface area for the pFET fin channel, which is approximately twice the product of height h1 and the fin channel length (or gate length Lg). It also aims to provide a good aspect ratio (which is the ratio of the height h1 to the width of the pFET fin) for the pFET fin to achieve stable manufacturability. If the height h1 is too small (such as less than 40nm), the pFET fin created by the semiconductor layer 104 may not have sufficient surface area for conducting current, which would result in pFET performance degradation. If the height h1 is too large (such as greater than 70nm), the aspect ratio of the pFET fin created by the semiconductor layer 104 may be undesirably high and the pFET fin may be prone to collapse during fabrication.

In operation 20, the method 10 (fig. 1A) forms a hard mask 105 for etching the substrate 102 and the semiconductor layer 104 to form the fin. The hard mask 105 is also referred to as a fin hard mask 105. Operation 20 involves the various steps shown in fig. 5A, 5B, and 5C. Referring to fig. 5A, operation 20 forms hard mask layers 105A, 105B, and 105C over the top surfaces of the substrate 102 and the semiconductor layer 104. In an embodiment, the hard mask layer 105A includes an oxide that may be formed by oxidizing the top surfaces of the substrate 102 and the semiconductor layer 104 or by deposition, such as Chemical Vapor Deposition (CVD); the hard mask layer 105B includes a material such as silicon nitride (Si) which can be formed by CVD₃N₄) A nitride of (a); and the hard mask layer 105C includes a material such as silicon dioxide (SiO) that can be formed by CVD₂) An oxide of (a). Still referring to fig. 5A, operation 20 further forms a patterned mask 105D over the hard mask layer 105C. The patterned mask 105D may be formed using one or more photolithography processes, including a double patterning or multiple patterning process. Typically, double patterning or multiple patterning processes combine lithographic and self-aligned processes, allowing for the creation of patterns, for example, with pitches less than those obtainable using a single, direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over the hard mask layer 105C and patterned using a photolithographic process. Using self-aligning toolsThe process forms spacers beside the patterned sacrificial layer. The sacrificial layer is then removed and the remaining spacers or mandrels become the patterned mask 105D. In various embodiments, the patterned mask 105D may comprise silicon oxide, silicon nitride, or other suitable materials.

Referring to fig. 5B, in some embodiments, operation 20 forms a capping layer 105E over the patterned mask 105D and the hard mask layer 105C. In an embodiment, capping layer 105E comprises silicon nitride or other suitable material and is deposited using Atomic Layer Deposition (ALD). The thickness of the capping layer 105E is controlled to adjust the dimensions of the combined hard mask 105 (e.g., the combined dimensions of the hard masks 105D and 105E in the "X" direction) to meet the target fin width. In some embodiments, the capping layer 105E is omitted in operation 20. Referring to fig. 5C, the hard mask layers 105C, 105B, and 105A are etched using the combined hard masks 105D and 105E as an etching mask, and the combined hard masks 105D and 105E are consumed by the etching process or removed after the etching process is completed. At this stage, the fin hardmask 105 includes patterned hardmask 105A, 105B, and 105C.

In operation 22, the method 10 (fig. 1A) etches the substrate 102 and the semiconductor layer 104 to form an nFET fin 108n in the nFET region and a pFET fin 108p in the pFET region. The resulting structure is shown in fig. 6, according to an embodiment. The fin hard mask 105 serves as an etch mask when the substrate 102 and the semiconductor layer 104 are etched. An etch process that provides the same etch rate for the semiconductor layer 104 and the substrate 102 is desirable for operation 22 to produce fins 108n and 108p having the same dimensions. However, because the semiconductor layer 104 and the substrate 102 comprise different materials, in practice they typically etch at different rates in the same etch process. For example, when the semiconductor layer 104 comprises SiGe and the substrate 102 comprises crystalline Si, the semiconductor layer 104 may etch faster than the substrate 102 in a typical dry etching process. Thus, when a common etch process is used to etch the nFET and pFET regions, the pFET fin 108p may be narrower and taller than the nFET fin 108 n. When the difference between the dimensions (such as height and width) of the pFET fin 108p and the nFET fin 108n is large (such as greater than 30%), this presents challenges to subsequent fabrication processes and may reduce production yield. In the present embodiment, operation 22 implements an iterative etching process comprising multiple steps of dry etching and chemical processing such that nFET fins 108n and pFET fins 108p having closely matched dimensions (such as closely matched fin widths w1 and w2 in the "X" direction and closely matched fin heights h3 and h4 in the "Z" direction) may be formed simultaneously. This generally improves production yield while producing fins 108n and 108p with acceptable matching dimensions (e.g., a mismatch of less than 25%). Furthermore, this embodiment saves manufacturing costs and produces a fin hard mask 105 with better pattern uniformity by forming the fin hard mask 105 using one lithography process, as compared to methods of etching the pFET fin 108p and the nFET fin 108n in different etching processes (e.g., forming a mask covering the pFET region while etching the nFET region, and vice versa, which requires forming the fin hard mask 105 for the nFET region and the pFET region, respectively).

FIG. 1B shows a flowchart of operation 22 using an iterative etch process, according to an embodiment. Referring to fig. 1B, operation 22 includes step 30, where step 30 simultaneously performs an anisotropic etch on the pFET region and the nFET region. In an embodiment, the anisotropic etch uses HBr gas, Cl₂The dry etching process is performed with a gas, Ar gas, other suitable gas, or a mixture thereof. The gas flow rate, etch time, and other etch parameters (such as temperature and pressure) of the anisotropic etch are controlled to produce the initial structure of the pFET fin 108p and the nFET fin 108 n. For example, step 30 may etch the pFET region and the nFET region several nanometers deep. Operation 22 then proceeds to step 32, where step 32 simultaneously performs an isotropic etch on the pFET region and the nFET region. In an embodiment, the isotropic etch uses NF₃Gas, CHF₃Gas, CF₄The dry etching process is performed with a gas, other suitable gas, or a mixture thereof. The gas flow rate, etch time, and other etch parameters (such as temperature and pressure) of the isotropic etch are controlled to maintain a good profile in the fins 108n and 108p and to compensate (to some extent) for the different etch depths in the anisotropic etch (step 30) between the nFET region and the pFET region. The operation 22 then proceeds to step 34, where step 34 examines (or monitors) the fins 108n and 108pHeight. If the fins 108n and 108p have not reached the target fin height, the operation 22 proceeds to step 36 where step 36 treats the sidewalls of the fins 108n and 108p with certain chemistries. For example, step 36 may apply a composition comprising O₂、CO₂、SF₆、CH₃F. Other suitable gases or mixtures thereof. This process creates some polymer on the sidewalls of the fins 108n and 108p to help control the profile of the fins 108n and 108p during the subsequent etching process. After the process is complete, operation 22 proceeds to step 30 to begin another iteration of the anisotropic and isotropic etch process. Operation 22 may repeat steps 30, 32, 34, and 36 until fins 108n and 108p reach the target fin height.

In an embodiment, the fins 108n and 108p may end up at slightly different heights (e.g., the fin heights are within 25% of each other) even with the iterative etch process implemented in operation 22. The regions that are etched slower than the other regions in operation 22 control when operation 22 is stopped. For example, when the substrate 102 comprises crystalline Si and the semiconductor layer 104 comprises SiGe, the nFET region etches slower than the pFET region. Thus, the operation 22 in step 34 uses the height of the nFET fin 108n as a control. In other words, when step 34 determines that the height of the nFET fin 108n has reached the target fin height, operation 22 proceeds to step 38 to complete the etch. Step 38 may also perform a cleaning process on the fins 108n and 108 p. In the embodiment depicted in fig. 6, the pFET fin 108p is ultimately slightly taller than the nFET fin because the pFET region etches faster.

Referring to fig. 6, each nFET fin 108n has a width w2 along the "X" direction and a height h4 along the "Z" direction from the top surface of the remaining substrate 102 to the bottom surface of the fin hardmask 105. The nFET fin 108n results from etching the substrate 102 through operation 22 and therefore has the same material as the substrate 102. Each pFET fin 108p has a width w1 along the "X" direction and a height h3 along the "Z" direction from the top surface of the remaining substrate 102 to the bottom surface of the fin hardmask 105. Each pFET fin 108p includes a top portion resulting from etching the semiconductor layer 104 through operation 22 and a bottom portion resulting from etching the substrate 102 through operation 22. For ease of discussion, the top of the pFET fin 108p is referred to as the top 104 and the bottom of the pFET fin 108p is referred to as the bottom 106. The top portion 104 has the same material as the semiconductor layer 104 and the bottom portion 106 has the same material as the substrate 102. The top 104 has a height h1, the bottom 106 has a height h2, and the height h3 is the sum of the height h1 and the height h 2. Because the pFET region etches faster in this embodiment, the top surface of the remaining portion of the substrate 102 in the pFET region is lower than the top surface of the remaining portion of the substrate 102 in the nFET region by the step height h 5. Even though fig. 6 depicts two nFET fins 108n adjacent to two pFET fins 108p, the invention is not so limited. In various embodiments, one or more nFET fins 108n may be present in the nFET region and one or more pFET fins 108p may be present in the pFET region.

In the present embodiment, the bottom 106 of the nFET fin 108n and the pFET fin 108p comprise crystalline Si, and the top 104 of the pFET fin 108p comprises SiGe. The width w2 may be slightly larger than the width w1, e.g., about 5% to about 10%, because SiGe etches faster than Si in operation 22. For example, the width w1 may be in the range of about 6.1nm to about 7.1nm, and the width w2 may be in the range of about 6.5nm to about 7.5 nm. These fin width ranges are designed in view of proper gate channel control when the fins are used as FinFET channels. Further, the height h1 is in the range of about 40nm to about 70nm, as discussed with reference to FIG. 4. In an embodiment, the height h4 is in a range from about 100nm to about 115 nm. As will be discussed, the height h4 may vary between nFET fins 108n depending on the spacing (or center-to-center distance) between adjacent nFET fins 108 n. This range is intended to provide sufficient fin sidewall surface area for conducting current and to provide a stable aspect ratio for manufacturability of the nFET fin 108n (h4: w 2). Height h3 is greater than height h4 because SiGe etches faster than Si in operation 22. In the present embodiment, height h3 is slightly larger than height h4 due to the iterative etching and processing process performed in operation 22. For example, height h3 is 25% or less, such as 20% or less, greater than height h 4. For example, in an embodiment, the height h3 may be in the range of about 115nm to about 125 nm. Further, in various embodiments, the step height h5 may be in the range of about 10nm to about 30 nm. Operation 22 may be adjusted to minimize step height h 5.

In operation 24, the method 10 (fig. 1A) forms an isolation structure 110 laterally isolating the respective fins 108n and 108p over the remaining portion of the substrate 102. The resulting structure is shown in fig. 7, according to an embodiment. For example, the isolation structure 110 surrounds the bottom of the fins 108n and 108p to separate and isolate the fins 108n and 108p from each other. The isolation structure 110 may comprise silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., comprising silicon, oxygen, nitrogen, carbon, or other suitable isolation compositions), or combinations thereof. The isolation structure 110 may include different structures, such as a Shallow Trench Isolation (STI) structure and/or a Deep Trench Isolation (DTI) structure. In some embodiments, the isolation structure 110 comprises a multi-layer structure. For example, the isolation structure 110 may include a thermally formed oxide liner layer on the surface of the substrate 102 and the fins 108n and 108p and a silicon nitride layer disposed over the oxide liner layer. In an embodiment, the trenches between the fins 108n and 108p are filled by using one or more insulating materials (e.g., by using a CVD process or a spin-on-glass process); performing a Chemical Mechanical Polishing (CMP) process to remove excess insulating material, remove fin hardmask 105, and/or planarize a top surface of the insulating material; and etching back the insulating material to form the isolation structure 110. In the present embodiment, the etch-back of the isolation structure 110 is controlled such that a top surface of the isolation structure 110 in the pFET region is flush with or slightly higher than a bottom surface of the top 104 of the pFET fin 108 p. The top surface of the isolation structure 110 may also have a step due to the step profile in the substrate 102. In other words, the top surface of the isolation structure 110 in the nFET region may be slightly higher than the top surface of the isolation structure 110 in the pFET region by the step height h 6. In some embodiments where height h5 is in the range of about 10nm to about 30nm, height h6 is in the range of about 1nm to about 6 nm. Such a range of height h6 is generally within a desirable range that is conducive to good production yields. Operation 22 may be adjusted to minimize step height h5, which results in minimizing step height h 6.

In operation 26, the method 10 (fig. 1A) proceeds to further fabrication steps to form FinFET devices over the nFET fin 108n and the pFET fin 108 p. For example, operation 26 may: forming dummy gates over the fins 108n and 108 p; forming source/drain regions by etching the fins 108n and 108p in the source/drain regions and epitaxially growing source/drain features over remaining portions of the fins 108n and 108p in the source/drain regions; replacing the dummy gate with a high-k metal gate; forming an interlayer dielectric layer; forming contacts to the source/drain features and the high-k metal gate; forming a multilayer interconnection structure; and performing other fabrication. In that regard, fig. 8 illustrates a perspective view of the device 100 after completion of operation 24, and fig. 8 illustrates two nFET fins 108n and two pFET fins 108p extending from the substrate 102 and through the isolation structure 110. Each of the pFET fins 108p includes a top portion 104 and a bottom portion 106. Fig. 9A illustrates a perspective view of device 100 after further fabrication of device 100 is performed in operation 26, in accordance with an embodiment. Fig. 9B shows a cross-sectional view of device 100 along line "B-B" in fig. 9A. As shown in fig. 9A and 9B, operation 26 forms an n-type FinFET over the nFET fin 108n and a p-type FinFET over the pFET fin 108p, where portions of the fins 108n and 108p serve as channels for the respective finfets. In the embodiment shown in fig. 9A and 9B, the common high-k metal gate 112 joins the fins 108n and 108p to form a CMOS device. In alternative embodiments, the n-type FinFET and the p-type FinFET may have different high-k metal gates.

Referring to fig. 9A and 9B, in this embodiment, the device 100 includes a high-k metal gate 112, a gate spacer 114 on sidewalls of the high-k metal gate 112, a fin sidewall spacer 116, an n-type source/drain feature 118n over a remaining portion of the fin 108n (after a source/drain trench etch process), and a p-type source/drain feature 118p over a remaining portion of the fin 108p (after a source/drain trench etch process). Device 100 may include various other elements not shown in fig. 9A and 9B. Referring to fig. 9B, in a p-type FinFET, a high-k metal gate 112 is disposed over the top 104 of the pFET fin 108p that provides high carrier mobility. The top 104 of the pFET fin 108p connects the two p-type source/drain features 118p and serves as a transistor channel. Because the top portion 104 uses a high mobility semiconductor material, the performance of the p-type FinFET is improved. In the present embodiment, the top portion 104 of the pFET fin 108p is partially etched in the source/drain regions, and source/drain features 118p are disposed directly on the remaining portions of the top portion 104 in the source/drain regions. In an alternative embodiment, the top 104 of the pFET fin 108p is completely etched in the source/drain regions, and the source/drain features 118p are disposed directly on the bottom 106 in the source/drain regions.

The source/drain features 118n and 118p may be formed by any suitable epitaxial process, such as vapor phase epitaxy, molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. In some embodiments, the source/drain features 118n comprise silicon and may be doped with carbon, phosphorous, arsenic, other n-type dopants, or combinations thereof (e.g., forming Si: C epitaxial source/drain features, Si: P epitaxial source/drain features, or Si: C: P epitaxial source/drain features). In some embodiments, the source/drain features 118p comprise silicon germanium or germanium, and may be doped with boron, other p-type dopants, or combinations thereof (e.g., to form Si: Ge: B epitaxial source/drain features). In some embodiments, the epitaxial source/drain features 118n and 118p are doped during deposition by adding impurities to the source material of the epitaxial process (i.e., in-situ). In some embodiments, the epitaxial source/drain features 118n and 118p are doped by an ion implantation process following the deposition process. In some embodiments, an annealing process (e.g., Rapid Thermal Annealing (RTA) and/or laser annealing) is performed to activate the dopants in the epitaxial source/drain features 118n and 118 p. In some embodiments, the epitaxial source/drain features 118n and 118p are formed in a different process sequence, including: for example, when the epitaxial source/drain features 118n are formed in the nFET region, the pFET region is masked; and masking the nFET regions when the epitaxial source/drain features 118p are formed in the pFET regions.

In an embodiment, high-k metal gate 112 includes a high-k gate dielectric layer 112A and a gate electrode layer 112B. The gate electrode layer 112B may include a work function layer and a bulk metal layer. The high-k metal gate 112 may include additional layers, such as a dielectric interfacial layer between the top portion 104 and the high-k gate dielectric layer 112A. In various embodiments, the dielectric interfacial layer may comprise a dielectric material, such as silicon oxide, silicon oxynitride, or silicon germanium oxide, and may be deposited by chemical oxidation, thermal oxidation, atomic layer deposition(ALD), Chemical Vapor Deposition (CVD), and/or other suitable methods. The dielectric interfacial layer may include different dielectric materials for n-type finfets and for p-type finfets. For example, the dielectric interfacial layer may include silicon oxide for n-type finfets and silicon germanium oxide for p-type finfets. High-k gate dielectric layer 112A may comprise hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Lanthanum oxide (La)₂O₃) Titanium oxide (TiO)₂) Yttrium oxide (Y)₂O₃) Strontium titanate (SrTiO)₃) Other suitable metal-oxides, or combinations thereof; and may be formed by ALD and/or other suitable methods. The work function layer (part of gate electrode layer 112B) may include a metal selected from the group of, but not limited to, titanium aluminum nitride (TiAlN), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), aluminum (Al), or combinations thereof; and may be deposited by CVD, PVD, and/or other suitable processes. The bulk metal layer (part of the gate electrode layer 112B) may include a metal such as aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and/or other suitable materials; and may be deposited using plating, CVD, PVD, or other suitable process.

Each of the fin sidewall spacers 116 and the gate spacers 114 may be a single layer or a multi-layer structure. In some embodiments, each of spacers 116 and 114 comprises a dielectric material, such as silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), other dielectric materials, or combinations thereof. In an example, the first dielectric layer (e.g., SiO with a substantially uniform thickness) is deposited over the device 100₂Layer) as a cushion layer; and depositing a second dielectric layer (e.g., Si) over the first dielectric layer₃N₄Layer) as a body D-shaped spacer; and then anisotropically etched to remove portions of the dielectric layer to form spacers 116 and 114. Further, the fin sidewall spacers 116 may be partially removed during an etch process that forms recesses in the fins 108n and 108p prior to growing the source/drain features 118n and 118 p. In some embodiments, the fin sidewall spacers 116 may be completely removed by such an etching process.

Fig. 10 shows a cross-sectional view of a portion of device 100 according to an embodiment. For example, the portion of device 100 in fig. 10 may be part of a ring oscillator circuit, where high performance p-type finfets may be used to improve the performance of the circuit. Referring to fig. 10, the device 100 includes a repeating pattern of dual nFET fins 108n and dual pFET fins 108 p. More specifically, the device 100 includes a repeating pattern of one pair of nFET fins 108n, another pair of nFET fins 108n, one pair of pFET fins 108p, and another pair of pFET fins 108 p. In some embodiments, two nFET fins 108n in the same pair are used to form a single n-type FinFET, and two pFET fins 108p in the same pair are used to form a single p-type FinFET. The spacing (center-to-center distance) between the two nFET fins 108n in the same pair is S2, and the spacing between the two pFET fins 108p in the same pair is S4. In an embodiment, S4 is substantially equal to S2. The center-to-center distance between two adjacent pairs of nFET fins 108n and the other nFET fin 108n is S1. The center-to-center distance between two adjacent pairs of pFET fins 108p and another pFET fin 108p is S5. The center-to-center distance between two adjacent pairs of nFET fins 108n and pFET fins 108p is S3. In an embodiment, distances S1, S3, and S5 are substantially the same. FIG. 10 also shows the respective depths D1, D2, D3, D4, D5, D6, and D7, each of which is measured from the top surface of the fins 108n/108p to the top surface of the substrate 102 after the operation 22 is completed. The depth D1 is measured between the two nFET fins 108n of the same pair. The depth D2 is measured between two adjacent pairs of nFET fins 108 n. The depths D3, D4, and D5 are measured at various points between the pair of nFET fins 108n and the pair of pFET fins 108 p. The depth D6 is measured between two adjacent pFET fin 108p pairs. The depth D7 is measured between the two pFET fins 108p of the same pair.

Fig. 10 shows the effect of the spacings S1 to S5 on the depths D1 to D7. Specifically, as the two fins in the same device region (two fins in the nFET region or two fins in the pFET region) are closer together, the etch depth between the two fins is smaller. For example, each of the intervals S1 and S5 is larger than the intervals S2 and S4, and each of the depths D2 and D6 is larger than the intervals D1 and D7. Furthermore, even though S2 and S4 are substantially the same, depth D7 is greater than depth D1 because semiconductor layer 104 is etched at a faster rate than substrate 102, as discussed above. In some embodiments, the depth D7 is about 25% or less, such as about 5% to about 20%, than the depth D1. For the same reason, even though S1 and S5 are substantially the same, the depth D6 is larger than the depth D2. In some embodiments, the depth D6 is about 25% or less, such as about 5% to about 20%, than the depth D2. For this embodiment, the difference between D6 and D2 represents the step height h5 (fig. 6). The depths D3, D4, and D5 gradually increase in sequence as the measurement point moves from the nFET fin 108n to the pFET fin 108 p. In other words, D4 is larger than D3, and D5 is larger than D4. Further, in this embodiment, the depth D2 is equal to or less than the depth D3, and the depth D5 is equal to or less than the depth D6. The gradual change in depth from D3 to D5 represents a step between the nFET region and the pFET region as shown in fig. 6.

In an embodiment, the pFET fin 108p has a width in the range of about 6.1nm to about 7.1nm, and the nFET fin 108n has a width greater than the pFET fin 108p, and may be in the range of about 6.5nm to about 7.5 nm. These fin width ranges are intended to achieve desired FinFET performance, such as DIBL (drain induced barrier lowering) and increased fin density. Further, each of S2 and S4 is in the range of about 23nm to about 28nm, and each of S1, S3, and S5 is in the range of about 68nm to about 73 nm. These pitch ranges are intended to increase the density of the fins (or devices) while avoiding fin-to-fin bridging problems. Further, the depth D1 is in the range of about 100nm to about 105 nm; depth D2 is in the range of about 101nm to about 106 nm; depth D3 is in the range of about 105nm to about 110 nm; depth D4 is in the range of about 113nm to about 118 nm; each of the depths D5 and D6 is in the range of about 120nm to about 125 nm; and the depth D7 is in the range of about 115nm to about 120 nm. These depth ranges achieve good depth uniformity, which provides good topography when performing CMP on the isolation structures 110.

Fig. 11 shows a cross-sectional view of a portion of a device 100 according to another embodiment. For example, the portion of device 100 in fig. 11 may be part of an SRAM circuit, where high performance p-type finfets may be used to improve the performance of the circuit. Referring to fig. 11, the device 100 includes a repeating pattern of dual nFET fins 108n and single pFET fins 108 p. More specifically, the device 100 includes a repeating pattern of a single pFET fin 108p, another single pFET fin 108p, a pair of nFET fins 108n, another pair of nFET fins 108n, a single pFET fin 108p, and another single pFET fin 108 p. In some embodiments, two nFET fins 108n in the same pair are used to form a single n-type FinFET, and each pFET fin 108p is used to form a single p-type FinFET. The spacing (center-to-center distance) between two nFET fins 108n of the same pair is S8, the spacing between two adjacent pFET fins 108p is S6, the spacing between the pFET fins 108p and the adjacent nFET fins 108n is S7, and the spacing between two adjacent pairs of two nFET fins 108n is S9. In embodiments, S7 is substantially equal to S9, and S8 is less than S6, and S6 is less than S7. Fig. 11 also shows the respective depths D8, D9, D10, and D11, each of which is measured from the top surface of the fins 108n/108p to the top surface of the substrate 102 after the operation 22 is completed. The depth D8 is measured between two adjacent pFET fins 108 p. The depth D9 is measured between the pFET fin 108p and the adjacent nFET fin 108 n. The depth D10 is measured between the two nFET fins 108n of the same pair. The depth D11 is measured between two adjacent pairs of nFET fins 108 n.

Fig. 11 shows the effect of the spacings S6 to S9 on the depths D8 to D11. Specifically, as the two fins in the same device region (two fins in the nFET region or two fins in the pFET region) are closer together, the etch depth between the two fins is smaller. For example, the spacing S9 is greater than the spacing S8, and the depth D11 is greater than the depth D10 (both measured between the nFET fins 108 n). Furthermore, even though S7 and S9 are substantially the same, the depth D9 is greater than the depth D11 because the depth D9 is between the pFET fin 108p and the nFET fin 108n and etches the semiconductor layer 104 at a faster rate than the substrate 102, as discussed above. Further, in various embodiments, depth D8 may be greater than, equal to, or less than depth D9, depending on spacings S6 and S7. When the spacing S6 is about equal to the spacing S7 (e.g., within 10% of each other), the depth D8 may be equal to or greater than the depth D9 because the depth D8 is measured between the two pFET fins 108p and the depth D9 is measured between the pFET fins 108p and the nFET fins 108 n. In some embodiments, the depth D11 is about 10% or less than the depth D10. In some embodiments, the depth D8 is about 20% or less, such as about 5% to about 12%, than the depth D11. For this embodiment, the difference between D8 and D11 represents the step height h5 (fig. 6).

In an embodiment, the pFET fin 108p has a width in the range of about 6.1nm to about 7.1nm, and the nFET fin 108n has a width greater than the pFET fin 108, and may be in the range of about 6.5nm to about 7.5 nm. These fin width ranges are intended to achieve desired FinFET performance, such as DIBL (drain induced barrier lowering) and increased fin density. Further, spacing S6 is in the range of about 33nm to about 38 nm; spacing S7 is in the range of about 40nm to about 45 nm; spacing S8 is in the range of about 23nm to about 28 nm; and spacing S9 is in the range of about 40nm to about 45 nm. These pitch ranges are intended to increase the density of the fins (or devices) while avoiding fin-to-fin bridging problems. Further, the depth D8 is in the range of about 120nm to about 125 nm; depth D9 is in the range of about 117nm to about 122 nm; depth D10 is in the range of about 100nm to about 105 nm; and the depth D11 is in the range of about 108nm to about 113 nm. These depth ranges achieve good depth uniformity, which provides good topography when performing CMP on the isolation structures 110.

Although not intended to be limiting, embodiments of the invention provide one or more of the following advantages. For example, embodiments of the present invention form pFET fins and nFET fins over the same substrate, where the pFET fins comprise a material having a higher hole mobility than the material in the nFET fins. This improves the performance of p-type finfets formed from pFET fins. Further, embodiments of the present invention etch the pFET fins and the nFET fins using a common process that implements iterative etching and processing. Such a process reduces or minimizes the size difference of the pFET fins and the nFET fins and results in good planarity of the subsequently formed isolation structures. Embodiments of the present invention can be easily integrated into existing semiconductor manufacturing processes.

In one exemplary aspect, the invention is directed to a method comprising: providing a substrate having a first semiconductor material; creating a mask overlying the nFET region of the substrate; etching the pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin comprises the first semiconductor material and the second fin comprises a top portion over a bottom portion, wherein the top portion comprises the second semiconductor material and the bottom portion comprises the first semiconductor material.

In an embodiment of the method, the substrate is a silicon substrate and the second semiconductor material comprises silicon germanium. In an embodiment, the method further comprises: after the epitaxial growth of the second semiconductor material, the top surfaces of the nFET region and the pFET region are planarized.

In an embodiment, patterning the nFET region and the pFET region includes: forming a fin hardmask over the nFET region and the pFET region; and etching the nFET region and the pFET region through the fin hardmask by the same process to produce a first fin and a second fin. In a further embodiment, etching the nFET region and the pFET region includes: anisotropically etching the nFET region and the pFET region through the fin hardmask; after the anisotropic etch, isotropically etching the nFET region and the pFET region through the fin hard mask; treating the structure resulting from the anisotropic etching and the isotropic etching with a treatment gas mixture; and repeating the anisotropic etching, isotropic etching, and processing to create a first fin in the nFET region and a second fin in the pFET region, wherein the anisotropic etching, isotropic etching, and processing apply different gases. In some embodiments, the anisotropic etch comprises applying HBr, Cl₂Ar or mixtures thereof. In some embodiments, the isotropic etching includes applying NF₃、CHF₃、CF₄Or mixtures thereof. In some embodiments, the treating comprises applying O₂、CO₂、SF₆、CH₃F or mixtures thereof.

In an embodiment, the method further comprises: an isolation structure is formed between the first fin and the second fin, wherein a first bottom surface of the isolation structure adjacent to the first fin is about 10nm to about 30nm higher than a second bottom surface of the isolation structure adjacent to the second fin.

In another exemplary aspect, the present invention is directed to a structure comprising: a substrate; a first fin extending from the substrate; and a second fin extending from the substrate. The second fin includes a top portion over a bottom portion. The bottom of the first fin and the second fin comprise crystalline silicon. The top of the second fin comprises a semiconductor material having a higher charge carrier mobility than silicon. The top surface of the second fin and the top surface of the first fin are substantially coplanar. The bottom of the second fin extends deeper into the substrate than the first fin.

In an embodiment of the structure, the first fin extends from a first portion of the substrate and the second fin extends from a second portion of the substrate, wherein the first portion is higher than the second portion. In a further embodiment, the first portion is about 10nm to about 30nm higher than the second portion. In another embodiment of the structure, the top of the second fin includes silicon germanium.

In an embodiment, the structure further comprises: an isolation structure adjacent to the first fin and the second fin, wherein a top surface of the isolation structure is substantially flush with a bottom surface of a top of the second fin. In some embodiments, the structure further comprises: a first gate structure over the isolation structure and engaging the first fin; and a second gate structure over the isolation structure and engaging a top of the second fin.

In yet another exemplary aspect, the present invention is directed to a structure comprising: a substrate; two first fins adjacent to each other and extending from a first region of the substrate; two second fins adjacent to each other and extending from a second region of the substrate; and an isolation structure located over the substrate and adjacent to the first fin and the second fin. Each of the second fins includes a top portion over a bottom portion. The bottom of the first fin and the second fin comprise crystalline silicon. The top of the second fin includes silicon germanium. The top surface of the second fin and the top surface of the first fin are substantially coplanar. Each of the second fins is taller than the first fins.

In an embodiment of the structure, a first portion of the isolation structure extends laterally between the two first fins, a second portion of the isolation structure extends laterally between the two second fins, a first spacing between the two first fins is approximately equal to a second spacing between the two second fins, and a depth of the first portion of the isolation structure is less than a depth of the second portion of the isolation structure. In a further embodiment, the third portion of the isolation structure extends laterally between one of the two first fins and one of the two second fins, and the third portion of the isolation structure has a depth greater than a depth of the second portion of the isolation structure.

In an embodiment of the structure, a first portion of the isolation structure extends laterally between the two first fins, a second portion of the isolation structure extends laterally between the two second fins, a first spacing between the two first fins is smaller than a second spacing between the two second fins, and a depth of the first portion of the isolation structure is less than a depth of the second portion of the isolation structure. In a further embodiment, the third portion of the isolation structure extends laterally between one of the two first fins and one of the two second fins, and the third portion of the isolation structure has a depth that is greater than a depth of the first portion of the isolation structure and less than a depth of the second portion of the isolation structure.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.