阅读说明：本技术 半导体器件及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 杨丰诚 林孟汉 王圣祯 贾汉中 林仲德 于 2021-01-18 设计创作，主要内容包括：根据实施例,利用多重图案化工艺形成存储器阵列。在实施例中,在多层堆叠件内形成第一沟槽,并且沉积第一导电材料到第一沟槽中。在沉积第一导电材料后,在多层堆叠件内形成第二沟槽,并且将第二导电材料沉积到第二沟槽中。蚀刻第一导电材料和第二导电材料。本申请的实施例提供了半导体器件及其制造方法。(According to an embodiment, a memory array is formed using a multiple patterning process. In an embodiment, a first trench is formed within the multilayer stack and a first conductive material is deposited into the first trench. After depositing the first conductive material, a second trench is formed within the multilayer stack and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched. Embodiments of the present application provide a semiconductor device and a method of manufacturing the same.)

1. A method of manufacturing a semiconductor device, the method comprising:

etching a first trench in a multilayer stack, the multilayer stack comprising alternating dielectric layers and sacrificial layers;

depositing a first conductive material to fill the first trench;

etching a second trench in the multilayer stack after the depositing of the first conductive material;

depositing a second conductive material to fill the second trench; and

etching the first conductive material and the second conductive material.

2. The method of claim 1, wherein the depositing the first conductive material deposits a first seed layer and a first bulk conductive material.

3. The method of claim 2, wherein the depositing a second conductive material deposits a second seed layer in physical contact with the first seed layer.

4. The method of claim 3, wherein after said etching the first and second conductive materials, the first and second seed layers have a shape between the two dielectric layers, the shape being an "H" shape.

5. The method of claim 1, further comprising planarizing the first conductive material prior to the etching the second trench, wherein the first conductive material completely crosses a top of the first trench after the planarizing the first conductive material.

6. The method of claim 1, wherein after said etching first and second conductive materials, said first conductive material has a greater width than said second conductive material.

7. The method of claim 1, further comprising:

depositing a ferroelectric material into the first trench and the second trench after the etching of the first conductive material and the second conductive material;

depositing a channel material into the first trench; and

depositing a dielectric material into the first trench after the depositing a channel material.

8. A method for manufacturing a semiconductor device, the method comprising:

forming an alternating stack of a first dielectric material and a sacrificial material;

forming a first portion of a first wordline within the alternating stack of first dielectric material and sacrificial material, the forming the first portion of the first wordline comprising:

etching a first trench in the alternating stack of first dielectric material and sacrificial material;

forming a first recess by recessing a portion of the sacrificial material exposed within the first trench; and

depositing a first conductive material into the first recess to fill the first trench; and

after the forming the first portion of the first word line, forming a second portion of the first word line within the alternating stack of the first dielectric material and the sacrificial material, the forming the second portion of the first word line comprising:

etching a second trench in the alternating stack of first dielectric material and sacrificial material;

forming a second recess by removing a remaining portion of the sacrificial material; and

depositing a second conductive material into the second recess to fill the second trench.

9. The method of claim 8, further comprising etching the first conductive material and the second conductive material.

10. A semiconductor device, comprising:

a ferroelectric material extending away from the substrate;

a channel material on a first side of the ferroelectric material;

a first dielectric material extending away from a second side of the ferroelectric material opposite the first side;

a second dielectric material extending away from the second side of the ferroelectric material;

a first conductive material extending away from the second side of the ferroelectric material between the first and second dielectric materials, the first conductive material comprising a first bulk material and a first seed layer; and

a second conductive material extending away from the first conductive material between the first and second dielectric materials, the second conductive material comprising a second bulk material and a second seed layer, the second seed layer in physical contact with the first seed layer, the second conductive material having a greater width than the first conductive material.

Technical Field

Embodiments of the present application relate to a semiconductor device and a method of manufacturing the same.

Background

Semiconductor memories are used in integrated circuits for electronic applications including radios, televisions, cell phones, and personal computing devices. Semiconductor memories include two main categories. One is a volatile memory; the other is a non-volatile memory. Volatile memory includes Random Access Memory (RAM), which can be further divided into two subcategories, Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). Both SRAM and DRAM are volatile because they lose stored information when not powered.

On the other hand, the nonvolatile memory may store data thereon. One type of nonvolatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). The advantages of FeRAM include fast write/read speed and small size.

Disclosure of Invention

In some embodiments, a method of manufacturing a semiconductor device, the method comprising: etching a first trench in a multilayer stack, the multilayer stack comprising alternating dielectric layers and sacrificial layers; depositing a first conductive material to fill the first trench; etching a second trench in the multilayer stack after the depositing of the first conductive material; depositing a second conductive material to fill the second trench; and etching the first conductive material and the second conductive material.

In some embodiments, a method for manufacturing a semiconductor device, the method comprising: forming an alternating stack of a first dielectric material and a sacrificial material; forming a first portion of a first wordline within the alternating stack of first dielectric material and sacrificial material, the forming the first portion of the first wordline comprising: etching a first trench in the alternating stack of first dielectric material and sacrificial material; forming a first recess by recessing a portion of the sacrificial material exposed within the first trench; and depositing a first conductive material into the first recess to fill the first trench; and forming a second portion of the first word line within the alternating stack of the first dielectric material and the sacrificial material after the forming the first portion of the first word line, the forming the second portion of the first word line comprising: etching a second trench in the alternating stack of first dielectric material and sacrificial material; forming a second recess by removing a remaining portion of the sacrificial material; and depositing a second conductive material into the second recess to fill the second trench.

In some embodiments, a semiconductor device includes: a ferroelectric material extending away from the substrate; a channel material on a first side of the ferroelectric material; a first dielectric material extending away from a second side of the ferroelectric material opposite the first side; a second dielectric material extending away from the second side of the ferroelectric material; a first conductive material extending away from the second side of the ferroelectric material between the first and second dielectric materials, the first conductive material comprising a first bulk material and a first seed layer; and a second conductive material extending away from the first conductive material between the first and second dielectric materials, the second conductive material comprising a second bulk material and a second seed layer, the second seed layer in physical contact with the first seed layer, the second conductive material having a greater width than the first conductive material.

Embodiments of the present application provide three-dimensional memory devices and methods.

Drawings

Aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 is a block diagram of a random access memory according to some embodiments.

Fig. 2A-2B are various views of a memory array according to some embodiments.

Figures 3A-13D are various views of intermediate stages in the manufacture of a memory array, according to some embodiments.

Fig. 14A-14B are various views of a memory array according to some other embodiments.

Fig. 15A-15B are various views of a memory array according to some other embodiments.

Fig. 16A-16B are various views of a memory array according to some other embodiments.

17A-17B are various views of a memory array according to some other embodiments.

Fig. 18A-18B are various views of a memory array according to some other embodiments.

Fig. 19A-20B are various views of intermediate stages in the manufacture of a memory array, according to some other embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to various embodiments, the word lines of the memory array are formed by a multiple patterning process, wherein a first portion of the word lines and a first subset of the transistors for the memory array are formed in a first patterning process, and wherein a second portion of the word lines and a second subset of the transistors for the memory array are subsequently formed in a second patterning process. Thus, the aspect ratio of the columns of the memory array can be increased while avoiding twisting or collapse of the features during formation.

FIG. 1 is a block diagram of a random access memory 50 according to some embodiments. The random access memory 50 includes a memory array 52, a row decoder 54, and a column decoder 56. Memory array 52, row decoder 54, and column decoder 56 may each be part of the same semiconductor die, or may be part of different semiconductor dies. For example, memory array 52 may be part of a first semiconductor die, while row decoder 54 and column decoder 56 may be part of a second semiconductor die.

Memory array 52 includes memory cells 58, word lines 62, and bit lines 64. The memory cells 58 are arranged in rows and columns. Word line 62 and bit line 64 are electrically connected to memory cell 58. Word lines 62 are conductive lines that extend along rows of memory cells 58. Bit line 64 is a conductive line that extends along a column of memory cells 58.

The row decoder 54 may be, for example, a static Complementary Metal Oxide Semiconductor (CMOS) decoder, a pseudo-N-type metal oxide semiconductor (NMOS) decoder, or the like. During operation, row decoder 54 selects a desired memory cell 58 in a row of memory array 52 by activating a word line 62 for the row. The column decoder 56 may be, for example, a static CMOS decoder, a pseudo-NMOS decoder, etc., and may include write drivers, sense amplifiers, combinations thereof, etc. During operation, column decoder 56 selects a bit line 64 for a desired memory cell 58 from a column of memory array 52 in a selected row and uses bit line 64 to read data from or write data to the selected memory cell 58.

Fig. 2A and 2B are various views of a memory array 52 according to some embodiments. Fig. 2A is a circuit diagram of the memory array 52. Fig. 2B is a three-dimensional view of a portion of memory array 52.

The memory array 52 is a flash memory array such as a non-volatile (NOR) flash memory array; high speed memory arrays such as DRAM or SRAM; nonvolatile memories such as resistive ram (rram) or magnetic ram (mram), and the like. Each memory cell 58 is a flash memory cell that includes a Thin Film Transistor (TFT) 68. The gate of each TFT 68 is electrically connected to a respective word line 62, a first source/drain region of each TFT 68 is electrically connected to a respective bit line 64, and a second source/drain region of the TFT 68 is electrically connected to a respective source line 66 (which is electrically grounded). Memory cells 58 in the same row of memory array 52 share a common word line 62, while memory cells in the same column of memory array 52 share a common bit line 64 and a common source line 66.

The memory array 52 includes multiple arrangements of conductive lines (e.g., word lines 62), with a dielectric layer 72 located between adjacent ones of the word lines 62. The word lines 62 are in a first direction D parallel to a major surface of an underlying substrate (not shown in fig. 2B, but discussed in more detail below with reference to fig. 3A-20B)₁And an upper extension. The word lines 62 may have a stair step arrangement such that the lower word lines 62 are longer than the upper word lines 62 and extend laterally beyond the ends of the upper word lines 62. For example, in fig. 2B, multiple stacked layers of word lines 62 are shown, with the uppermost word line 62A being the shortest line and the lowermost word line 62B being the longest line. The respective lengths of the word lines 62 increase in a direction extending toward the underlying substrate. In this manner, portions of each word line 62 may be accessed from above the memory array 52 such that conductive contacts may be formed to exposed portions of each word line 62.

The memory array 52 also includes a plurality of arranged conductive lines, such as bit lines 64 and source lines 66. The bit line 64 and the source line 66 are in a direction perpendicular to the first directionD₁And a second direction D of the main surface of the underlying substrate₂And an upper extension. A dielectric layer 74 is disposed between and separates adjacent ones of the bit line 64 and source line 66. The boundaries of each memory cell 58 are defined by a pair of bit lines 64 and source lines 66 and intersecting word lines 62. A dielectric plug 76 is disposed between and separates adjacent pairs of bit lines 64 and source lines 66. Although fig. 2A and 2B show a particular position of the bit line 64 relative to the source line 66, it should be noted that in other embodiments, the position of the bit line 64 and the position of the source line 66 may be reversed.

The memory array 52 also includes ferroelectric stripes 84 and semiconductor stripes 82. The ferroelectric strip 84 contacts the word line 62. Semiconductor strips 82 are disposed between ferroelectric strips 84 and dielectric layer 74.

The semiconductor strips 82 provide channel regions for the TFTs 68 of the memory cells 58. For example, when an appropriate voltage [ e.g., higher than the corresponding threshold voltage (V) of the corresponding TFT 68 ] is applied through the corresponding word line 62_thThe area where the semiconductor strip 82 intersects the word line 62 may allow current to flow from the bit line 64 to the source line 66 (e.g., at D)₁In the direction).

Ferroelectric strips 84 are the data storage layers that can be polarized in one of two different directions by applying an appropriate voltage difference across ferroelectric strips 84. Depending on the polarization direction of a particular region of the ferroelectric strip 84, the threshold voltage of the corresponding TFT 68 changes and a digital value (e.g., 0 or 1) may be stored. For example, when the region of the ferroelectric strip 84 has a first electrical polarization direction, the corresponding TFT 68 may have a relatively low threshold voltage, and when the region of the ferroelectric strip 84 has a second electrical polarization direction, the corresponding TFT 68 may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as a threshold voltage shift. A larger threshold voltage shift may make it easier (e.g., less prone to error) to read the digital value stored in the corresponding memory cell 58. Accordingly, the memory array 52 may also be referred to as a ferroelectric random access memory (FERAM) array.

To perform a write operation on a particular memory cell 58, a write voltage may be applied to the area of ferroelectric stripe 84 corresponding to memory cell 58. For example, the write voltage may be applied by applying appropriate voltages to the word line 62, bit line 64, and source line 66 corresponding to the memory cell 58. The direction of polarization of a region of the ferroelectric strip 84 can be changed by applying a write voltage across the region of the ferroelectric strip 84. Accordingly, the respective threshold voltage of the respective TFT 68 may be switched from a low threshold voltage to a high threshold voltage (or vice versa) such that a digital value may be stored in the memory cell 58. Because word lines 62 and bit lines 64 intersect in memory array 52, a single memory cell 58 can be selected and written.

To perform a read operation on a particular memory cell 58, a read voltage (a voltage between the low and high threshold voltages) is applied to the word line 62 corresponding to the memory cell 58. The TFT 68 of the memory cell 58 may or may not be turned on depending on the polarization direction of the corresponding region of the ferroelectric strip 84. Accordingly, bit line 64 may or may not discharge through source line 66 (e.g., ground), thereby determining the digital value stored in memory cell 58. Because word lines 62 and bit lines 64 intersect in memory array 52, a single memory cell 58 may be selected and read from a single memory cell 58.

Fig. 3A-15B are various views of an intermediate stage in the fabrication of a memory array 52 according to some embodiments. A portion of a memory array 52 is shown. For clarity of illustration, some components are not shown, such as a staircase arrangement of word lines (see FIG. 2B). Fig. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A are perspective views of the memory array 52. Fig. 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, and 15B are cross-sectional views taken along a reference section B-B in fig. 12A.

In fig. 3A and 3B, a substrate 102 is provided. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, an insulator Semiconductor (SOI) substrate, or the like, which may be doped (e.g., doped with a dopant of p-type or n-type) or undoped. The substrate 102 may be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 102 may include silicon; germanium; a compound semiconductor containing silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor containing silicon germanium, gallium arsenide phosphide, indium aluminum arsenide, gallium arsenide, indium gallium arsenide, gallium indium phosphide and/or gallium indium phosphide arsenic; or a combination thereof. The substrate 102 may comprise a dielectric material. For example, the substrate 102 may be a dielectric substrate or may include a dielectric layer on a semiconductor substrate. Possible dielectric materials for the dielectric substrate include oxides such as silicon oxide; nitrides such as silicon nitride and the like; carbides such as silicon carbide and the like; and the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, and the like. In some embodiments, substrate 102 is formed of silicon carbide.

A multi-layer stack 104 is formed over the substrate 102. The multi-layer stack 104 includes overlapping first and second dielectric layers 104A and 104B. The first dielectric layer 104A is formed of a first dielectric material and the second dielectric layer 104B is formed of a second dielectric material. The dielectric materials may each be selected from candidate dielectric materials for the substrate 102. In the illustrated embodiment, the multi-layer stack 104 includes five first dielectric layers 104A and four second dielectric layers 104B. It should be noted that the multi-layer stack 104 may include any number of first dielectric layers 104A and any number of second dielectric layers 104B.

The multi-layer stack 104 will be patterned in subsequent processing. As such, the dielectric material of the first dielectric layer 104A and the dielectric material of the second dielectric layer 104B both have a high etch selectivity compared to the etching of the substrate 102. The patterned first dielectric layer 104A will be used to isolate the subsequently formed TFTs. The patterned second dielectric layer 104B is a sacrificial layer (or dummy layer) that will be removed in subsequent processing and replaced by the word line of the TFT. As such, the second dielectric material of the second dielectric layer 104B also has a high etch selectivity compared to the etching of the first dielectric material of the first dielectric layer 104A. In embodiments where the substrate 102 is formed of silicon carbide, the first dielectric layer 104A may be formed of an oxide, such as silicon oxide, and the second dielectric layer 104B may be formed of a nitride, such as silicon nitride. Other combinations of dielectric materials with feasible etch selectivity with respect to each other may also be used.

Each layer of the multi-layer stack 104 may be formed by a viable deposition process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), and the like. The thickness of each layer may range from about 15nm to about 90 nm. In some embodiments, the first dielectric layer 104A is formed to a different thickness than the second dielectric layer 104B. For example, the first dielectric layer 104A may be formed to have a first thickness t₁And the second dielectric layer 104B may be formed to have a second thickness T₂A second thickness T₂Is greater than the first thickness T₁Small [ big/small ]]From about 0% to about 100%. The multilayer stack 104 may have an overall height H₁Between about 1000nm and about 10000nm (e.g., about 2000 nm).

As will be discussed in more detail below, fig. 4A-11B illustrate a process of patterning a trench in the multilayer stack 104 and forming a TFT in the trench. Specifically, the TFT is formed using a multiple patterning process. The multiple patterning process may be a double patterning process, a quadruple patterning process, or the like. Fig. 4A to 11B illustrate a double patterning process. In a double patterning process, a first trench 106 is patterned in the multilayer stack 104 using a first etch process (see fig. 4A and 4B), and a first subset of elements of the TFT are formed in the first trench 106. Then, a second trench 120 is patterned in the multi-layer stack 104 using a second etch process (see fig. 8A and 8B), and a second subset of TFTs is formed in the second trench 120. Forming TFTs using multiple patterning processes allows for each patterning process to be performed at a low pattern density, which may help reduce defects while still allowing the memory array 52 to have sufficient memory cell density, while also helping to prevent problems with aspect ratios that become too high and cause structural instability.

In addition, although the above-described embodiments illustrate the memory array 52 formed at the front end of the production line but directly on the substrate 102 (e.g., semiconductor substrate), this is merely exemplary and is not intended to limit the embodiments. Instead, the memory array 52 may be formed in the front end of the manufacturing line or the back end of the manufacturing line, and may be formed as an embedded memory array or a stand-alone structure. Any suitable type of formation for memory array 52 may be used and all such types of formation are fully intended to be included within the scope of the embodiments.

In fig. 4A and 4B, a first trench 106 is formed in the multi-layer stack 104. In the illustrated embodiment, the first trench 106 extends through the multi-layer stack 104 and exposes the substrate 102. In another embodiment, the first trench 106 extends through some, but not all, of the layers in the multi-layer stack 104. The first trench 106 may be formed using viable photolithography and etching techniques, such as with an etch process that is selective to the multi-layer stack 104 (e.g., a process that etches the dielectric material of the first dielectric layer 104A and the dielectric material of the second dielectric layer 104B at a faster rate than the material of the substrate 102). The etching may be any feasible etching process, such as reactive ion etching (PIE), neutral atom beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. In embodiments where the substrate 102 is formed of silicon carbide, the first dielectric layer 104A is formed of silicon oxide, and the second dielectric layer 104B is formed of silicon nitride, the first trench 106 may be formed by using hydrogen (H) with hydrogen₂) Or oxygen (O)₂) Gas-mixed fluorine-based gases (e.g. C)₄F₆) Is formed by dry etching.

A portion of the multi-layer stack 104 is disposed between each pair of first trenches 106. Each portion of the multilayer stack 104 can have a width W₁Between about 50nm and about 500nm (e.g., about 240nm), and has a height H as described with respect to FIGS. 3A and 3B₁. Further, each portion of the multilayer stack 104 is separated by a separation distance S₁And separated by a separation distance that may be between about 50nm and about 200nm (e.g., about 80 nm). The Aspect Ratio (AR) of each portion of the multi-layer stack 104 is the height H₁The ratio to the width of the narrowest feature of the portion of the multi-layer stack 104, which is the width W in that processing step₁. In accordance with some embodiments of the present invention,when first trench 106 is formed, each portion of multilayer stack 104 has an aspect ratio of between about 5 and about 15. Forming each portion of the multi-layer stack 104 with an aspect ratio less than about 5 may not allow the memory array 52 to have a sufficient memory cell density. Forming each portion of the multi-layer stack 104 with an aspect ratio less than about 15 may cause distortion or collapse of the multi-layer stack 104 during subsequent processing.

In fig. 5A and 5B, the first trench 106 is expanded to form a first sidewall recess 110. Specifically, the portions of the sidewalls of the second dielectric layer 104B exposed by the first trenches 106 are recessed inward from the first sidewall recesses 110. Although the sidewalls of the second dielectric layer 104B are shown as being linear, the sidewalls may be concave or convex. The first sidewall recess 110 may be formed by a viable etch process, such as an etch process that is selective to the material of the second dielectric layer 104B (e.g., a process that selectively etches the material of the second dielectric layer 104B at a faster rate than the material of the first dielectric layer 104A and the material of the substrate 102). The etching may be isotropic. In embodiments where the substrate 102 is formed of silicon carbide, the first dielectric layer 104A is formed of silicon oxide, and the second dielectric layer 104B is formed of silicon nitride, the first trench 106 may be formed by using phosphoric acid (H)₃PO₄) Is used to extend. However, any other suitable etching process, such as dry selective etching, may also be employed.

After formation, the first sidewall recess 110 has a depth D that extends beyond the sidewalls of the first dielectric layer 104A₃. To a desired depth D in the first sidewall recess 110₃Thereafter, the etching of the first sidewall recess 110 may be stopped using a timed etch process. For example, when phosphoric acid is used to etch the second dielectric layer 104B, the first sidewall recess 110 may be made to have a depth D ranging between about 10nm to about 60nm (e.g., about 40nm)₃. Forming the first sidewall recess 110 reduces the width of the second dielectric layer 104B. Continuing with the previous example, after etching, the second dielectric layer 104B may have a width W in the range of about 50nm to about 450nm (such as about 160nm)₂. As described above, the Aspect Ratio (AR) of each portion of the multi-layer stack 104 is the height H₁And a multi-layer stack 104, the width of the narrowest part of the portion being the width W in the processing step₂. Thus, forming the first sidewall recesses 110 increases the aspect ratio of each portion of the multi-layer stack 104. According to some embodiments, the aspect ratio of each portion of the multi-layer stack 104 remains within the ranges described above, such as within a range of about 5 to about 15, after the first sidewall recesses 110 are formed. Thus, the advantages of such aspect ratios (as described above) may still be realized.

In fig. 6A and 6B, a first conductive feature 112A is formed in the first sidewall recess 110 to fill and/or overfill the first trench 106, thereby completing the process of replacing the first portion of the second dielectric layer 104B. Each of the first conductive features 112A may include one or more layers such as a seed layer, a glue layer, a barrier layer, a diffusion layer, a fill layer, and the like. In some embodiments, although in other embodiments, the seed layer 112A may be omitted_SHowever, each of the first conductive features 112A includes a seed layer 112A_S(or glue layer) and main layer 112A_M. Each seed layer 112A_SEach along a corresponding main layer 112A located in the first sidewall recess 110_MExtend on three sides (e.g., top, side, and bottom) of the material. Seed layer 112A_SFormed of a first conductive material that can be used to aid in growth or to aid in adhesion of subsequently deposited materials, such as titanium nitride, tantalum nitride, titanium, tantalum, molybdenum, ruthenium, rhodium, hafnium, iridium, niobium, rhenium, tungsten, combinations of these, oxides of these, and the like. Main layer 112A_MMay be formed of a second conductive material such as a metal, e.g., tungsten, cobalt, aluminum, nickel, copper, silver, gold, molybdenum, ruthenium, molybdenum nitride, alloys thereof, and the like. Seed layer 112A_SIs a material having good adhesion to the material of the first dielectric layer 104A, the main layer 112A_MIs made of a material opposite to the seed layer 112A_SThe material of (2) has good adhesion. In embodiments where the first dielectric layer 104A is formed of an oxide, such as silicon oxide, the seed layer 112A_SMay be formed of titanium nitride, and the main layer 112A_MMay be formed of tungsten. Seed layer 112A_SAnd a main layer 112A_MCan be formed by acceptable depositionA process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), etc.

Once the first conductive feature 112A has been deposited so as to fill and/or overfill the first trench 106, the first conductive feature 112A can be planarized to remove excess material outside the first trench 106 so that the first conductive feature 112A can completely straddle the top of the first trench 106 after the first conductive feature 112A is planarized. In one embodiment, the first conductive feature 112A may be planarized using a method such as a Chemical Mechanical Planarization (CMP) process. However, any suitable planarization process, such as a water milling process, may also be employed.

In fig. 7A and 7B, a second trench 120 is formed in the multilayer stack 104. In the illustrated embodiment, the second trench 120 extends through the multi-layer stack 104 and exposes the substrate 102. In another embodiment, the second trench 120 extends through some, but not all, of the layers in the multi-layer stack 104. The second trench 120 may be formed using viable photolithography and etching techniques, such as with an etch process that is selective to the multi-layer stack 104 (e.g., a process that etches the dielectric material of the first dielectric layer 104A and the dielectric material of the second dielectric layer 104B at a faster rate than the material of the substrate 102). The etch may be any feasible etch process and, in some embodiments, may be similar to the etch used to form the first trench 106 described with reference to fig. 4A and 4B.

A portion of the multi-layer stack 104 is disposed between each second trench 120 and each first trench 106. Each portion of the multi-layer stack 104 may have a width W in a range of about 50nm to about 500nm₃And has a height H as described with reference to FIGS. 3A and 3B₁. Moreover, each portion of the multi-layer stack 104 is separated by a distance S₂The distance may be in the range of about 50nm to about 200nm apart. The Aspect Ratio (AR) of each portion of the multi-layer stack 104 is the height H₁The ratio to the width of the narrowest feature of the portion of the multi-layer stack 104, which is the width W in that processing step₃. According to some embodiments, when forming the second trench 120, the aspect of each portion of the multi-layer stack 104The ratio is in the range of about 5 to about 15. Forming each portion of the multi-layer stack 104 with an aspect ratio less than about 5 may not allow the memory array 52 to have a sufficient memory cell density. Forming each portion of the multi-layer stack 104 with an aspect ratio less than about 15 may cause distortion or collapse of the multi-layer stack 104 during subsequent processing.

In fig. 8A and 8B, the second trench 120 is expanded to form a second sidewall recess 124. Specifically, the remaining portion of the second dielectric layer 104B is removed to form the second sidewall recesses 124. Thus, the second sidewall recesses 124 expose portions of the first conductive features 112A (e.g., the seed layer 112A)_S) Or exposing the main layer 112A in embodiments where the seed layer 112AS is not present_M. The second sidewall recesses 124 may be formed by a viable etch process, such as an etch process that is selective to the material of the second dielectric layer 104B (e.g., a process that selectively etches the material of the second dielectric layer 104B at a faster rate than the material of the first dielectric layer 104A and the material of the substrate 102). The etch may be any feasible etch process and, in some embodiments, may be similar to the etch used to form the first sidewall recesses 110 described with reference to fig. 5A and 5B. After formation, the second sidewall recess 124 has a depth D that extends beyond the sidewalls of the first dielectric layer 104A₄. In some embodiments, depth D₄Depth D similar to that described with reference to FIGS. 5A and 5B₃. In another embodiment, the depth D₄Different (greater or less) than the depth D described with reference to fig. 5A and 5B₃。

In fig. 9A and 9B, the second conductive feature 112B is formed in the second sidewall recess 124 to fill and/or overfill the second trench 120, thus completing the process for replacing the second portion of the second dielectric layer 104B, which results in the inner layers (e.g., glue or seed layers) of the first and second conductive features 112A and 112B being buried within the word line 112. The second conductive features 112B may be formed from a material selected from the same set of candidate materials for the first conductive features 112A, and may be formed using a method selected from the same set of candidate methods for forming the material of the first conductive features 112A. First conductive member 112A and second conductive memberThe electrical components 112B may be formed of the same material, or may comprise different materials. In some embodiments, although in other embodiments, the seed layer 112B may be omitted_SHowever, each of the second conductive features 112B includes a seed layer 112B_SAnd a main layer 112B_M. Seed layer 112B of second conductive feature 112B_SAnd a main layer 112B_MMay be respectively thicker than the seed layer 112A of the first conductive feature 112A_SAnd a main layer 112A_MAre the same in thickness. In some embodiments, the seed layer 112A_SAnd a seed layer 112B_SFormed of similar materials, in this case, seed layer 112A_SAnd a seed layer 112B_SMay be combined during formation so that there is no discernable interface between them. In another embodiment (described further below), seed layer 112A_SAnd a seed layer 112B_SFormed of different materials, in this case, the seed layer 112A_SAnd a seed layer 112B_SMay not coalesce during formation so that there is a discernible interface between them.

Once the second conductive feature 112B has been deposited so as to fill and/or overfill the second trench 120, the second conductive feature 112B can be planarized to remove excess material outside the second trench 120, such that the second conductive feature 112B can completely straddle the top of the second trench 120 after the second conductive feature 112B is planarized. In one embodiment, the second conductive feature 112B may be planarized using a method such as a CMP process. However, any suitable planarization process, such as a water milling process, may also be employed.

The first and second conductive features 112A and 112B are collectively referred to as word lines 112 of the memory array 52. The adjacent pairs of first and second conductive members 112A and 112B are in physical contact with each other and are electrically coupled to each other. Thus, each pair of first and second conductive features 112A and 112B functions as a single word line 112.

Fig. 10A-10B illustrate an etch-back process to remove excess portions of the first and second conductive features 112A and 112B and expose the second dielectric layer 104B. In one embodiment, the etch-back process may be performed using, for example, an anisotropic etch process. However, any suitable etching process may be utilized.

In one embodiment, an etch-back process is performed until the material of the first and second conductive features 112A, 112B not covered by the first dielectric layer 104A is removed. As such, the remaining material of the first and second conductive features 112A, 112B has a similar width (e.g., 80nm) as the remaining portion of the first dielectric layer 104A. However, any suitable dimensions may be used.

In addition, as can be clearly seen in fig. 10B, the first conductive feature 112A and the second conductive feature 112B within the word line 112 may have widths equal to each other, such as about 40nm each. In addition, a seed layer (e.g., seed layer 112A)_SAnd 112B_S) May have an "H" shape and also have a thickness T along the top and bottom of the first and second conductive features 112A, 112B₃And also has a thickness T buried within the word line 112₄Wherein the seed layer 112A_SAnd 112B_SAre combined so that the seed layer 112A_SAnd 112B_SEach contribute to the thickness. In one embodiment, the thickness T₃Can be in the range ofTo aboutAnd a thickness T₄Can be in the range ofTo aboutIn the meantime. However, any suitable thickness may be used.

FIG. 10C illustrates another embodiment in which the first conductive feature 112A in the word line 112 may have a different width than the second conductive feature 112B in the word line 112. For example, in one embodiment,the second trenches 120 may be formed offset from a midpoint between two of the first trenches 106 (e.g., by intentional misalignment of the mask). As such, although the word lines 112 may have generally the same width, the second sidewall recesses 124 may have a greater width than the first sidewall recesses 110, which causes the second conductive features 112B within the word lines 112 to have a greater width than the first conductive features 112A. For example, the width W of the first conductive feature 112A₄Can be in the range ofAnd the combinationAnd the width W of the second conductive feature 112B₅Can be in the range ofAnd aboutHowever, any suitable width may be used.

Fig. 11A to 11B illustrate a Thin Film Transistor (TFT) film stack formed in the first trench 106 and the second trench 120. Specifically, two ferroelectric strips 114, one semiconductor strip 116, and one dielectric layer 118 are formed in each first trench 106 and each second trench 120. In this embodiment, no other layer is formed in the first trench 106 and the second trench 120. In another embodiment (discussed further below), additional layers are formed in the first trench 106 and the second trench 120.

Ferroelectric tape 114 is a data storage tape formed of an acceptable ferroelectric material for storing digital values, such as hafnium oxide (HfZrO); hafnium aluminum oxide (HfAlO), zirconium oxide (ZrO); oxide f (hfo) doped with lanthanum (La), silicon (Si), aluminum (Al), or the like; undoped hafnium oxide (HfO); and so on. The material of the ferroelectric strip 114 may be formed by a viable deposition process such as ALD, CVD, Physical Vapor Deposition (PVD), and the like.

The semiconductor strips 116 are formed of an acceptable semiconductor material for providing a channel region of the TFT, such as zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), Indium Tin Oxide (ITO), Indium Gallium Zinc Tin Oxide (IGZTO), polysilicon, amorphous silicon, and the like. The material of the semiconductor strips 116 may be formed by a viable deposition process such as ALD, CVD, PVD, and the like.

The dielectric layer 118 is formed of a dielectric material. Acceptable dielectric materials include oxides (e.g., silicon oxide and aluminum oxide), nitrides (e.g., silicon nitride), and the like, or combinations thereof (e.g., silicon oxynitride, silicon carbonitride, and the like). The material of the dielectric layer 118 may be formed by a viable deposition process such as ALD, CVD, flowable CVD (fcvd), and the like.

The ferroelectric strips 114, semiconductor strips 116, and dielectric layer 118 may be formed by a combination of deposition, etching, and planarization. For example, a ferroelectric layer may be conformally deposited on the multi-layer stack 104 and in the first trench 106 (e.g., on sidewalls of the first conductive feature 112A and sidewalls of the first dielectric layer 104A). Then, a semiconductor layer can be conformally deposited on the ferroelectric layer. The semiconductor layer may then be anisotropically etched to remove horizontal portions of the semiconductor layer, thereby exposing the ferroelectric layer. A dielectric layer may then be conformally deposited on the remaining vertical portion of the semiconductor layer and on the exposed portion of the ferroelectric layer. A planarization process is then applied to the layers to remove excess material over the multi-layer stack 104. The planarization process may be a Chemical Mechanical Polishing (CMP), an etch back process, a combination thereof, or the like. The portion of the ferroelectric layer, the portion of the semiconductor layer, and the portion of the dielectric layer remaining in the first trench 106 form a ferroelectric stripe 114, a semiconductor stripe 116, and a dielectric layer 118, respectively. The planarization process exposes the multi-layer stack 104 such that the top surface of the multi-layer stack 104, the top surface of the ferroelectric strip 114, the top surface of the semiconductor strip 116, and the top surface of the dielectric layer 118 are coplanar (within process variations) after the planarization process.

In fig. 12A and 12B, dielectric plugs 132 are formed through the dielectric layer 118 and the semiconductor stripes 116. The dielectric plugs 132 are spacers to be disposed between adjacent TFTs and to physically and electrically separate the adjacent TFTs. In the illustrated embodiment, the dielectric plug 132 does not extend through the ferroelectric strip 114. Different regions of the ferroelectric strip 114 can be individually polarized, so the ferroelectric strip 114 can be used to store values even if adjacent regions are not physically and electrically separated. In another embodiment, dielectric plug 132 is also formed through ferroelectric strip 114. The dielectric plug 132 also extends through any remaining portions of the first dielectric layer 104A and the second dielectric layer 104B.

As an example of forming the dielectric plugs 132, openings for the dielectric plugs 132 may be formed through the dielectric layer 118 and the semiconductor strips 116. These openings may be formed using available photolithography and etching techniques. One or more dielectric materials are then formed in these openings. Possible dielectric materials include oxides such as silicon oxide; nitrides such as silicon nitride and the like; carbides such as silicon carbide; and the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, and the like. The dielectric material may be formed by one possible deposition process, such as ALD, CVD, and the like. In some embodiments, silicon oxide or silicon nitride is deposited in these openings. A planarization process is then applied to the layers to remove excess dielectric material over the topmost first dielectric layer 104A. The planarization process may be a Chemical Mechanical Polishing (CMP), an etch back process, a combination thereof, or the like. The remaining dielectric material forms a dielectric plug 132 in the opening.

In addition, fig. 12A and 12B illustrate the formation of bit lines 134 and source lines 136 through dielectric layer 118. The bit line 134 and source line 136 also extend through any remaining portions of the first dielectric layer 104A and the second dielectric layer 104B. The bit line 134 and source line 136 serve as source/drain regions of the TFT. The bit lines 134 and source lines 136 are conductive columns formed in pairs, with each semiconductor stripe 116 contacting a respective bit line 134 and a respective source line 136. Each TFT includes a bit line 134, a source line 136, a word line 112, and regions where the semiconductor strips 116 and ferroelectric strips 114 intersect the word line 112. Each dielectric plug 132 is disposed between a bit line 134 of one TFT and a source line 136 of the other TFT. In other words, the bit line 134 and the source line 136 are disposed at opposite sides of each dielectric plug 132. Thus, each dielectric plug 132 physically and electrically separates adjacent TFTs.

As one example of forming bit line 134 and source line 136, openings for bit line 134 and source line 136 may be formed through dielectric layer 118. These openings may be formed using available photolithography and etching techniques. Specifically, these openings are formed on opposite sides of the dielectric plug 132. One or more conductive materials, such as glue layers and bulk conductive materials, are then formed in these openings, acceptable conductive materials including metals such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, titanium nitride, tantalum nitride, combinations of these, and the like. The conductive material may be formed by a feasible deposition process such as ALD or CVD, a feasible plating process such as electroplating or electroless plating, or the like. In some embodiments, tungsten is deposited in the opening. A planarization process is then applied to the layers to remove excess conductive material over the topmost first dielectric layer 104A. The planarization process may be a Chemical Mechanical Polishing (CMP), an etch back process, a combination thereof, or the like. The remaining conductive material forms bit lines 134 and source lines 136 in the openings.

In fig. 13A, 13B, 13C and 13D, an interconnect structure 140 is formed over the intermediate structure, wherein fig. 13B shows a cross-sectional view of the structure of fig. 13A, fig. 13C shows a top view of the structure of fig. 13A at the height of the first metal line 164, and fig. 13D shows a top view of the structure of fig. 13A at the height of the metallization pattern 142. For clarity of illustration, only some of the features of interconnect structure 140 are shown in FIG. 13A. The interconnect structure 140 may include a metallization pattern 142, for example, in a dielectric material 144. The dielectric material 144 may include one or more dielectric layers, such as one or more layers of low dielectric constant (LK) or ultra low dielectric constant (ELK) dielectric material. Metallization pattern 142 may be metal interconnects (e.g., metal lines and vias) formed in one or more dielectric layers. The interconnect structure 140 may be formed by a damascene process, such as a single damascene process, a dual damascene process, and the like.

In one particular embodiment shown, the metallization pattern 142 of the interconnect structure 140 includes a first via 162 (e.g., via0), a first metal line 164 (e.g., a first top metal line), a second via 166 (e.g., via1), and a second metal line 168 (e.g., a second top metal line) in contact with the bit line 134 and the source line 136. Each of these components may be formed by: depositing a portion of dielectric material 144 (not separately shown in fig. 13A for clarity), patterning within the portion of dielectric material 144, filling the clusters with one or more conductive materials, and planarizing the conductive material with dielectric material 144. However, any suitable number of vias and conductive lines may be used, and all such connection layers are fully intended to be included within the scope of the embodiments.

In some embodiments, metallization pattern 142 includes bit line interconnect 142B (electrically coupled to bit line 134) and source line interconnect 142S (electrically coupled to source line 136). Adjacent bit lines 134 are connected to different bit line interconnects 142B, which helps to avoid shorting of adjacent bit lines 134 when their common word line 112 is activated. Likewise, adjacent source lines 136 are connected to different source line interconnects 142S, which helps to avoid shorting of adjacent source lines 136 when common word lines 112 of these adjacent source lines 136 are activated.

As shown in fig. 13C, a first via 162 within metallization pattern 142 of interconnect structure 140 is electrically coupled to bit line 134 and source line 136. In this embodiment, the bit lines 134 and the source lines 136 are formed in a staggered layout, with adjacent bit lines 134 and adjacent source lines 136 along the first direction D₁(see fig. 2B) are laterally offset from each other. Thus, each word line 112 is disposed laterally between a dielectric plug 132 and a bit line 134 or between a dielectric plug 132 and a source line 136. Each of the first via 162 connected to the bit line 134 and the first via 162 connected to the source line 136 is along the second direction D₂(see fig. 2B), such as along columns of the memory array 52. The first vias 162 connected to the bit lines 134 are connected to alternate bit lines 134 along columns of the memory array 52. The first vias 162 connected to the source line interconnect 142S are connected to alternate source lines 136 along columns of the memory array 52. Laterally offsetting bit lines 134 and source lines 136 eliminates the need for lateral interconnects along columns of memory array 52 becauseWhile allowing the metallization pattern 142 overlying the bit line 134 and source line 136 to be straight conductive segments. In one embodiment, the bit lines 134 and the source lines 136 may not be formed in a staggered layout, but rather lateral interconnections are implemented in the interconnect structure 140.

In particular, fig. 13D shows straight conductive segments within the upper metallization pattern 142 (e.g., second metal line 168). It can be seen that since the underlying connections have been formed in a staggered fashion, the bit line interconnects 142B and the source line interconnects 142S can be placed in a straight line without the need for lateral interconnects. This alignment operation greatly increases the line density in the metallization layers.

Fig. 14A-14B are various views of memory array 52 according to some other embodiments. A portion of a memory array 52 is shown. For clarity of illustration, some components are not shown, such as a staircase arrangement of word lines (see FIG. 2B). Fig. 14A is a perspective view of the memory array 52, and fig. 14B is a sectional view showing a section similar to the reference section B-B in fig. 12A.

In this embodiment, the ferroelectric stripe 114 is omitted and replaced with a plurality of dielectric layers 150 as data storage stripes, thereby allowing a NOR (NOR) flash memory array to be built. Specifically, a first dielectric layer 150A is formed on the substrate 102 and in contact with sidewalls of the word lines 112. A second dielectric layer 150B is formed on the first dielectric layer 150A. A third dielectric layer 150C is formed on the second dielectric layer 150B. The first dielectric layer 150A, the second dielectric layer 150B, and the third dielectric layer 150C are each formed of a dielectric material. Possible dielectric materials include oxides such as silicon oxide; nitrides such as silicon nitride and the like; carbides such as silicon carbide; and the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, and the like. In some embodiments, the first and third dielectric layers 150A, 150C are formed of a first dielectric material (e.g., an oxide such as silicon oxide) and the second dielectric layer 150B is formed of a second, different dielectric material (e.g., a nitride such as silicon nitride). The dielectric material may be formed by one possible deposition process, such as ALD, CVD, and the like. For example, the first dielectric layer 150A, the second dielectric layer 150B, and the third dielectric layer 150C may be formed by a combination of deposition, etching, and planarization in a manner similar to that described above with reference to the ferroelectric strip 114.

Fig. 15A and 15B are various views of a memory array 52 provided by some other embodiments. A portion of a memory array 52 is shown. For clarity of illustration, some components are not shown, such as a staircase arrangement of word lines (see FIG. 2B). Fig. 15A is a perspective view of the memory array 52, and fig. 15B is a sectional view showing a section similar to the reference section B-B in fig. 12A.

In this embodiment, conductive strips 160 are formed between ferroelectric strips 114 and semiconductor strips 116. The formation of conductive strips 160 helps to avoid or reduce the formation of interlayer oxides on the ferroelectric strips 114 during the formation of the semiconductor strips 116. Avoiding or reducing the formation of interlayer oxide may increase the lifetime of the memory array 52.

Conductive strips 160 may be formed of a metal such as ruthenium, tungsten, titanium nitride, tantalum nitride, molybdenum, and the like. The conductive material of the conductive strip 160 may be formed by a feasible deposition process such as ALD or CVD, a feasible plating process such as electroplating or electroless plating, or the like. The thickness of conductive strip 160 may be in the range of about 1nm to about 20 nm. The conductive strips 160 may be formed in a similar manner to the semiconductor strips 116 and may be formed during the formation of the semiconductor strips 116. The dielectric plug 132 may (or may not) be formed through the conductive strip 160.

Fig. 16A and 16B are various views of a memory array 52 provided by some other embodiments. A portion of a memory array 52 is shown. For clarity of illustration, some components are not shown, such as a staircase arrangement of word lines (see FIG. 2B). Fig. 16A is a perspective view of the memory array 52, and fig. 16B is a sectional view showing a section similar to the reference section B-B in fig. 12A.

In this embodiment, the seed layer 112A_SAnd a seed layer 112B_SFormed of different materials to help reduce overall resistivity. For example, the seed layer 112A_SMay be formed of a first glue material (e.g., titanium nitride), and seed layer 112B_SCan be made of different resistorsA second glue material (e.g., tantalum nitride). Thus, the seed layer 112A_SAnd a seed layer 112B_SMay not merge during formation such that they are separate and distinct from each other.

Fig. 17A and 17B are various views of a memory array 52 provided by some other embodiments. A portion of a memory array 52 is shown. For clarity of illustration, some components are not shown, such as a staircase arrangement of word lines (see FIG. 2B). Fig. 17A is a perspective view of memory array 52, and fig. 17B is a cross-sectional view taken along reference section B-B in fig. 17A.

In this embodiment, the metallization pattern 142 of the interconnect structure 140 includes only the source line interconnect 142S. Another interconnect structure 170 is formed on a side of the substrate 102 opposite the interconnect structure 140. Interconnect structure 170 may be formed in a similar manner as interconnect structure 140. The interconnect structure 170 may include, for example, a metallization pattern 172 in a dielectric material 174. Conductive vias 180 may be formed through the substrate 102 and the ferroelectric strip 114 to electrically couple the metallization pattern 172 to the bit lines 134 and/or the source lines 136. For example, metallization pattern 172 includes bit line interconnect 172B (which is electrically coupled to source line 136 through conductive via 180).

Also, in this embodiment, the bit lines 134 and the source lines 136 are formed in a staggered layout, so adjacent bit lines 134 and adjacent source lines 136 are along the first direction D₁(see fig. 2B) are laterally aligned with each other. Thus, each word line 112 is laterally disposed between a pair of bit lines 134 or between a pair of source lines 136. Because bit lines 134 and source lines 136 are not formed in a staggered layout, lateral interconnections to a subset of source line interconnects 142S are implemented in interconnect structure 140, while lateral interconnections to a subset of bit line interconnects 172B are implemented in interconnect structure 170. For example, the source line interconnect 142S is a straight conductive segment formed at an intermediate level of the interconnect structure 140. Lateral interconnects 146 between the first subset of source line interconnects 142S and the first subset of source lines 136 are formed at a lower level of the interconnect structure 140 than the source line interconnects 142S. Straight line interconnect 148 between the second subset of source line interconnects 142S and the second subset of source lines 136 and source line interconnect 142S is formed at a lower level of the interconnect structure 140. Likewise, bit line interconnect 172B is a straight conductive segment formed at an intermediate level of interconnect structure 170. Lateral interconnects 176 between the first subset of bit line interconnects 172B and the first subset of bit lines 134 are formed at a lower level of the interconnect structure 170 than the bit line interconnects 172B. The straight line interconnects 178 between the second subset of bit line interconnects 172B and the second subset of bit lines 134 are formed at a lower level of the interconnect structure 140 than the bit line interconnects 172B.

It should be noted that in other embodiments, the layout of the interconnect structures 140, 170 may be reversed. For example, metallization pattern 142 of interconnect structure 140 may include bit line interconnects, and metallization pattern 172 of interconnect structure 170 may include source line interconnects.

Fig. 18A-20B are various views of intermediate stages in the fabrication of a memory array 52 according to some other embodiments. A portion of a memory array 52 is shown. For clarity of illustration, some components are not shown, such as a staircase arrangement of word lines (see FIG. 2B). Fig. 18A and 19A are perspective views of the memory array 52. Fig. 18B and 19B are sectional views taken along a reference section B-B in fig. 19A. Fig. 20A and 20B are top views of a portion of memory array 52.

In fig. 18A and 18B, a structure similar to that described with respect to fig. 13A and 13B is obtained, but the ferroelectric stripe 114, the semiconductor stripe 116, and the dielectric layer 118 are not formed in this processing step. In contrast, the first trench 106 (see fig. 4A and 4B) and the second trench 120 (see fig. 8A and 8B) are each filled with a dielectric layer 192. The dielectric layer 192 is formed of a dielectric material. Possible dielectric materials include oxides such as silicon oxide; nitrides such as silicon nitride and the like; carbides such as silicon carbide; and the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, and the like. The dielectric material may be formed by one possible deposition process, such as ALD, CVD, and the like. In some embodiments, silicon oxide is deposited in the first trench 106 and the second trench 120. A planarization process may be applied to the layers to remove excess dielectric material over the topmost first dielectric layer 104A. The planarization process may be a Chemical Mechanical Polishing (CMP), an etch back process, a combination thereof, or the like. For example, a first planarization process may be performed after filling the first trench 106 to form the dielectric layer 192, and a second planarization process may be performed after filling the second trench 120 to form the dielectric layer 192.

In fig. 19A and 19B, a TFT film stack is formed extending through the dielectric layer 192. The TFT thin film stacks each include a ferroelectric stripe 114, a semiconductor stripe 116, and a dielectric layer 118. Bit line 134 and source line 136 are then formed at least through dielectric layer 118.

The ferroelectric strips 114, semiconductor strips 116, and dielectric layer 118 may be formed by a combination of deposition, etching, and planarization. For example, an opening may be formed through the dielectric layer 192. These openings may be formed using available photolithography and etching techniques. The ferroelectric layer may be conformally deposited in the openings through dielectric layer 192. Then, a semiconductor layer can be conformally deposited on the ferroelectric layer. The semiconductor layer may then be anisotropically etched to remove horizontal portions of the semiconductor layer, thereby exposing the ferroelectric layer. A dielectric layer may then be conformally deposited on the remaining vertical portion of the semiconductor layer and on the exposed portion of the ferroelectric layer. A planarization process is then applied to the layers to remove excess material above the topmost first dielectric layer 104A. The planarization process may be a Chemical Mechanical Polishing (CMP), an etch back process, a combination thereof, or the like. The portion of the ferroelectric layer, the portion of the semiconductor layer, and the portion of the dielectric layer remaining in the opening through dielectric layer 192 form ferroelectric stripe 114, semiconductor stripe 116, and dielectric layer 118, respectively. The planarization process exposes the uppermost first dielectric layer 104A such that the top surface of the uppermost first dielectric layer 104A, the top surface of the ferroelectric strip 114, the top surface of the semiconductor strip 116, and the top surface of the dielectric layer 118 are coplanar (within process variations) after the planarization process.

As one example of forming the bit line 134 and the source line 136, an opening for the bit line 134 and an opening for the source line 136 may be formed through the dielectric layer 118, and optionally also through the ferroelectric bar 114 and the semiconductor bar 116. These openings may be formed using available photolithography and etching techniques. Specifically, these openings are formed such that they are opposite the sides of the remaining portion of the dielectric layer 118. In some embodiments, the openings extend only through the dielectric layer 118, such that the bit lines 134 and source lines 136 extend only through the dielectric layer 118 (as shown in FIG. 19A). In some embodiments, the openings also extend through the ferroelectric and semiconductor strips 114, 116, such that the bit lines 134 and source lines 136 also extend through the ferroelectric and semiconductor strips 114, 116. One or more conductive materials are then formed in these openings. Possible conductive materials include metals such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, and the like. The conductive material may be formed by a feasible deposition process such as ALD or CVD, a feasible plating process such as electroplating or electroless plating, or the like. In some embodiments, tungsten is deposited in the opening. A planarization process is then applied to the layers to remove excess conductive material over the topmost first dielectric layer 104A. The planarization process may be a Chemical Mechanical Polishing (CMP), an etch back process, a combination thereof, or the like. The remaining conductive material forms bit lines 134 and source lines 136 in the openings. Then, similar techniques as described above may be used to form interconnects above (or below) bit lines 134 and above (or below) source lines 136, such that bit lines 134 and source lines 136 may be coupled to the bit line interconnects and the source line interconnects, respectively.

By utilizing the above-described process to form the word lines 112, the word lines 112 can be formed with a reduced likelihood of wiggling or even collapse. In particular, by using two separate etching processes and then filling the trench between the etching processes, the width of the remaining structure at any point in the process should be kept wide enough to provide sufficient structural support to help prevent wiggling and collapse. In addition, such a reduction effect can be achieved at low cost, and an additional mask is not required.

According to one embodiment, a method of manufacturing a semiconductor device includes: etching a first trench in a multilayer stack, the multilayer stack comprising alternating dielectric layers and sacrificial layers; depositing a first conductive material to fill the first trench; etching a second trench in the multilayer stack after the depositing a first conductive material; depositing a second conductive material to fill the second trench; and etching the first conductive material and the second conductive material. In one embodiment, the depositing the first conductive material is depositing a first seed layer and a first bulk conductive material. In one embodiment, the depositing the second conductive material is depositing a second seed layer in physical contact with the first seed layer. In one embodiment, after said etching the first and second conductive materials, the first and second seed layers have a shape between the two dielectric layers, the shape being an "H" shape. In one embodiment, the method further comprises planarizing the first conductive material prior to the etching the second trench, wherein the first conductive material completely crosses the top of the first trench after the planarizing the first conductive material. In one embodiment, after the etching the first conductive material and the second conductive material, the first conductive material has a greater width than the second conductive material. In one embodiment, the method further comprises: depositing a ferroelectric material into the first trench and the second trench after the etching of the first conductive material and the second conductive material; depositing a channel material into the first trench; and depositing a dielectric material into the first trench after the depositing a channel material.

According to another embodiment, a method of manufacturing a semiconductor device includes: forming an alternating stack of a first dielectric material and a sacrificial material; forming a first portion of a first wordline within the alternating stack of first dielectric material and sacrificial material, the forming the first portion of the first wordline comprising: etching a first trench in the alternating stack of first dielectric material and sacrificial material; forming a first recess by recessing a portion of the sacrificial material exposed within the first trench; and depositing a first conductive material into the first recess to fill the first trench; and forming a second portion of the first word line within the alternating stack of the first dielectric material and the sacrificial material after the forming the first portion of the first word line, the forming the second portion of the first word line comprising: etching a second trench in the alternating stack of first dielectric material and sacrificial material; forming a second recess by removing a remaining portion of the sacrificial material; and depositing a second conductive material into the second recess to fill the second trench. In one embodiment, the method further comprises etching the first conductive material and the second conductive material. In one embodiment, the method further comprises: etching the ferroelectric material in the first trench; and depositing channel material adjacent to the ferroelectric material within the first trench. In one embodiment, the method further comprises: etching the channel material; and depositing a dielectric material into the first trench to isolate the first portion of the channel material from the second portion of the channel material. In one embodiment, the depositing the first conductive material includes depositing a first seed layer. In one embodiment, the depositing the second conductive material includes depositing a second seed layer in physical contact with the first seed layer, wherein a total thickness of the first seed layer and the second seed layer is greater than a thickness of the first seed layer adjacent to a portion of the first dielectric material. In one embodiment, the first groove has a width less than the second groove.

According to still further embodiments, a semiconductor device includes: a ferroelectric material extending away from the substrate; a channel material on a first side of the ferroelectric material; a first dielectric material extending away from a second side of the ferroelectric material opposite the first side; a second dielectric material extending away from the second side of the ferroelectric material; a first conductive material extending away from the second side of the ferroelectric material between the first and second dielectric materials, the first conductive material comprising a first bulk material and a first seed layer; and a second conductive material extending away from the first conductive material between the first and second dielectric materials, the second conductive material including a second bulk material and a second seed layer, the second conductive material in physical contact with the first seed layer, the second conductive material having a width wider than the first conductive material. In one embodiment, the first seed layer and the second seed have an "H" shape. In one embodiment, the method further comprises a second ferroelectric material in physical contact with the second conductive material. In one embodiment, the first conductive material and the second conductive material collectively have a width of about 80 nm. In one embodiment, the first conductive material and the second conductive material are part of a word line of a memory cell. In one embodiment, the memory cell is part of a three-dimensional memory array.

In some embodiments, a method of manufacturing a semiconductor device, the method comprising: etching a first trench in a multilayer stack, the multilayer stack comprising alternating dielectric layers and sacrificial layers; depositing a first conductive material to fill the first trench; etching a second trench in the multilayer stack after the depositing of the first conductive material; depositing a second conductive material to fill the second trench; and etching the first conductive material and the second conductive material. In some embodiments, depositing the first conductive material deposits a first seed layer and a first bulk conductive material. In some embodiments, depositing a second conductive material deposits a second seed layer in physical contact with the first seed layer. In some embodiments, after said etching the first and second conductive materials, the first and second seed layers have a shape between the two dielectric layers, the shape being an "H" shape. In some embodiments, further comprising planarizing the first conductive material prior to the etching the second trench, wherein the first conductive material completely crosses the top of the first trench after the planarizing the first conductive material. In some embodiments, after the etching the first and second conductive materials, the first conductive material has a greater width than the second conductive material. In some embodiments, further comprising: depositing a ferroelectric material into the first trench and the second trench after the etching of the first conductive material and the second conductive material; depositing a channel material into the first trench; and depositing a dielectric material into the first trench after the depositing a channel material.

In some embodiments, a method for manufacturing a semiconductor device, the method comprising: forming an alternating stack of a first dielectric material and a sacrificial material; forming a first portion of a first wordline within the alternating stack of first dielectric material and sacrificial material, the forming the first portion of the first wordline comprising: etching a first trench in the alternating stack of first dielectric material and sacrificial material; forming a first recess by recessing a portion of the sacrificial material exposed within the first trench; and depositing a first conductive material into the first recess to fill the first trench; and forming a second portion of the first word line within the alternating stack of the first dielectric material and the sacrificial material after the forming the first portion of the first word line, the forming the second portion of the first word line comprising: etching a second trench in the alternating stack of first dielectric material and sacrificial material; forming a second recess by removing a remaining portion of the sacrificial material; and depositing a second conductive material into the second recess to fill the second trench. In some embodiments, further comprising etching the first conductive material and the second conductive material. In some embodiments, etching the ferroelectric material within the first trench; and depositing channel material adjacent to the ferroelectric material within the first trench. In some embodiments, the channel material is etched; and depositing a dielectric material into the first trench to isolate the first portion of the channel material from the second portion of the channel material. In some embodiments, depositing the first conductive material includes depositing a first seed layer. In some embodiments, depositing a second conductive material includes depositing a second seed layer in physical contact with the first seed layer, wherein a total thickness of the first seed layer and the second seed layer is greater than a thickness of the first seed layer adjacent to the portion of the first dielectric material. In some embodiments, the first groove has a width less than the second groove.

In some embodiments, a semiconductor device includes: a ferroelectric material extending away from the substrate; a channel material on a first side of the ferroelectric material; a first dielectric material extending away from a second side of the ferroelectric material opposite the first side; a second dielectric material extending away from the second side of the ferroelectric material; a first conductive material extending away from the second side of the ferroelectric material between the first and second dielectric materials, the first conductive material comprising a first bulk material and a first seed layer; and a second conductive material extending away from the first conductive material between the first and second dielectric materials, the second conductive material comprising a second bulk material and a second seed layer, the second seed layer in physical contact with the first seed layer, the second conductive material having a greater width than the first conductive material. In some embodiments, the first seed layer and the second seed have an "H" shape. In some embodiments, a second ferroelectric material in physical contact with the second conductive material is also included. In some embodiments, the first conductive material and the second conductive material collectively have a width of about 80 nm. In some embodiments, the first conductive material and the second conductive material are portions of a word line of a memory cell. In some embodiments, the memory cells are part of a three-dimensional memory array.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.