阅读说明：本技术 存储器系统以及存储器控制器 (Memory system and memory controller ) 是由 樱田健次 武田奈穗美 白川政信 高田万里江 于 2021-01-25 设计创作，主要内容包括：实施方式提供即使在不充分具有存储管理信息的RAM区域的存储器控制器中也能够以较小的等待时间读出管理信息的存储器系统以及存储器控制器。实施方式的存储器系统具有：非易失性的存储单元阵列(110)；控制器(200),控制数据的读出及写入；数据锁存器群(XDL),被使用于在控制器(200)与存储单元阵列(110)之间输入输出数据；以及数据锁存器群(ADL),在由控制器(200)从存储单元阵列(110)读出数据时维持被保存的数据,控制器(200)在从存储单元阵列(110)的数据的读出处理的执行时或执行之前,将在数据的读出中使用的管理信息(MI)存储于数据锁存器群(ADL)。(Embodiments provide a memory system and a memory controller capable of reading out management information with a small latency even in a memory controller that does not have a RAM area sufficiently storing the management information. The memory system of the embodiment has: a non-volatile memory cell array (110); a controller (200) that controls reading and writing of data; a data latch group (XDL) used for inputting and outputting data between the controller (200) and the memory cell array (110); and a data latch group (ADL) for maintaining the stored data when the controller (200) reads data from the memory cell array (110), wherein the controller (200) stores Management Information (MI) used for reading data in the data latch group (ADL) during or before execution of a process of reading data from the memory cell array (110).)

1. A memory system having:

a nonvolatile memory having a storage area;

a controller which controls reading and writing of the data;

a first data latch group used for inputting and outputting the data between the controller and the memory; and the number of the first and second groups,

a second group of data latches for maintaining stored data when the data is read out from the memory by the controller,

the controller stores management information for reading the data in the second data latch group at or before execution of a reading process for reading the data from the memory.

2. The memory system of claim 1,

the controller copies the management information from the second data latch group to the first data latch group in advance before the execution of the read processing.

3. The memory system of claim 1,

the second group of data latches is used when writing the data to the memory through the controller.

4. The memory system of claim 1,

the management information is stored in a prescribed storage area of the memory,

the controller reads the management information from the predetermined storage area and stores the management information in the second data latch group before the read processing corresponding to an external request is executed.

5. The memory system of claim 1,

the controller stores the updated management information in the memory when the management information is updated.

6. The memory system of claim 1,

there is a plurality of said second group of data latches.

7. The memory system of claim 6,

the memory has a plurality of physical blocks,

each of the plurality of second groups of data latches stores the management information of the corresponding physical block.

8. The memory system of claim 7,

each of the plurality of physical blocks has a storage area that can be accessed in units of pages.

9. The memory system of claim 6,

the memory has a plurality of physical blocks,

each of the plurality of second groups of data latches stores the management information of the corresponding physical block.

10. The memory system of claim 1,

the management information is shift information for shifting a readout level of the data when the controller executes the readout process.

11. The memory system of claim 10,

the controller stores the shift information updated as a result of the patrol processing in the memory when the patrol processing for verifying the storage state of the data is executed with respect to the memory.

12. A memory system having:

a non-volatile first memory having a storage area;

a nonvolatile second memory having a storage area;

a controller that controls reading and writing of the data to the first memory and the second memory;

a first data latch group used for inputting and outputting the data between the controller and the first memory;

a second data latch group used for inputting and outputting the data between the controller and the second memory;

a third data latch group that maintains stored data when the data is read out from the first memory by the controller; and

a fourth data latch group that maintains stored data when the data is read out from the second memory by the controller,

the controller stores management information for reading the data in the third data latch group and the fourth data latch group at or before execution of a reading process for reading the data from the first memory and the second memory.

13. The memory system of claim 12,

the controller reads the management information from the fourth data latch group and executes the data reading process using the management information when the data reading process is executed from the first memory while the writing process is executed on the first memory.

14. A memory system having:

a first semiconductor chip having a nonvolatile memory having a storage area; and

and a second semiconductor chip bonded to the first semiconductor chip, the second semiconductor chip including a controller that controls reading and writing of data, and a RAM area that can store management information for reading the data during or before execution of a reading process for reading the data from the memory.

15. A memory controller controls reading and writing of data to a nonvolatile memory having a storage area, a first data latch group used for input/output of data, and a second data latch group for holding data to be stored when the data is read,

the memory controller stores management information for reading the data in the second data latch group at or before execution of a reading process for reading the data from the memory.

16. The memory controller of claim 15,

the controller copies the management information from the second data latch group to the first data latch group in advance before the execution of the read processing.

17. The memory controller of claim 16,

the management information is copied from the second group of data latches to the first group of data latches in advance before the execution of the read process.

18. The memory controller of claim 16,

the management information is stored in a prescribed storage area of the memory,

before the read processing corresponding to an external request is executed, the management information is read from the predetermined storage area and stored in the second data latch group.

19. The memory controller of claim 15,

and if the management information is updated, storing the updated management information in the memory.

20. A memory controller having:

a nonvolatile first memory having a first storage area;

a nonvolatile second memory having a second storage area;

a first data latch group for inputting and outputting the data to and from the first memory;

a second data latch group used for inputting and outputting the data between the second data latch group and the second memory;

a third data latch group that holds first stored data when the data is read from the first memory; and

a fourth data latch group for holding second stored data when the data is read from the second memory,

the memory controller is configured to control the memory controller,

controlling reading and writing of the data to the first memory and the second memory,

management information for reading the data is stored in the third data latch group and the fourth data latch group at or before execution of a reading process for reading the data from the first memory and the second memory.

21. The memory controller of claim 20,

when a read process for reading the data from the first memory is performed in the middle of a write process performed on the first memory, the management information is read from the fourth data latch group, and the read process for the data is performed using the management information.

Technical Field

Embodiments of the present invention relate to a memory system and a memory controller.

Background

In the nonvolatile memory, management information used when reading data and the like is stored in a part of a storage area of the nonvolatile memory, and is copied to a RAM area managed by a memory controller and used. Since the management information is stored in the RAM area, the memory controller can read out and use the management information at high speed.

If the data size of the management information becomes large, a RAM area of a large data size is necessary, but a RAM area of a sufficient size may not be provided in the memory controller.

Disclosure of Invention

Embodiments provide a memory system and a memory controller capable of reading out management information with a small latency even in a memory controller that does not have a RAM area sufficiently storing the management information.

The memory system of the embodiment has: a nonvolatile memory having a storage area; a controller that controls reading and writing of the data in units of the pages; a first data latch group used for inputting and outputting the data between the controller and the memory; and a second data latch group that holds the stored data when the data is read from the memory by the controller, wherein the controller stores management information used for reading the data in the second data latch group when or before execution of a reading process for reading the data from the memory.

Drawings

Fig. 1 is a block diagram for explaining the structure of a memory system of the first embodiment.

Fig. 2 is a circuit diagram for explaining the structure of the memory cell array of the first embodiment.

Fig. 3 is a sectional view of a partial area of the 1 block of the first embodiment.

Fig. 4 is a circuit diagram of a column decoder and string units of the first embodiment.

Fig. 5 is a graph showing data that can be obtained for each memory cell transistor, threshold voltage distribution, and voltage used for reading in the first embodiment.

Fig. 6 is a diagram showing a command sequence at the time of writing data according to the first embodiment.

Fig. 7 is a diagram for explaining a change in the data storage status in the 5 data latches accompanying execution of the command sequence at the time of data writing according to the first embodiment.

Fig. 8 is a diagram for explaining a change in the data storage status in the 5 data latches accompanying execution of the command sequence at the time of data writing according to the first embodiment.

Fig. 9 is a diagram showing a basic command sequence in reading data according to the first embodiment.

Fig. 10 is a diagram for explaining a change in the storage status of data in 5 data latches with execution of an instruction sequence according to the first embodiment.

Fig. 11 is a diagram showing an example of a shift table for the lower page of 1 table as shift table information according to the first embodiment.

Fig. 12 is a diagram showing an example of a shift table of a middle-order page of the shift table information according to the first embodiment.

Fig. 13 is a diagram showing an example of a shift table of an upper page of shift table information according to the first embodiment.

Fig. 14 is a flowchart showing an example of a flow of a process of reading data from the controller and the NAND flash memory when there is a read request from the host according to the first embodiment.

Fig. 15 is a diagram showing a command sequence at the time of suspending reading according to the first embodiment.

Fig. 16 is a diagram for explaining a change in the storage state of data in the 5 data latches at the time of suspending reading according to the first embodiment.

Fig. 17 is a diagram for explaining a change in the storage state of the management information until the management information is stored in the data latch group according to the first embodiment.

Fig. 18 is a diagram for explaining a change in the storage state of the management information until the management information is stored in the data latch group according to the first embodiment.

Fig. 19 is a diagram for explaining a change in the storage state of the management information until the management information is stored in the data latch group according to the first embodiment.

Fig. 20 is a diagram showing an instruction sequence of the first storing procedure of the first embodiment.

Fig. 21 is a diagram showing the instruction sequences of the second and third storage procedures in the first embodiment.

Fig. 22 is a diagram showing an instruction sequence of the fourth storage procedure of the first embodiment.

Fig. 23 is a diagram for explaining a case where shift information as management information is read from a group of data latches according to the first embodiment.

Fig. 24 is a diagram showing a command sequence of a data reading process according to the first embodiment.

Fig. 25 is a diagram for explaining a case of reading data from the memory cell array according to the first embodiment.

Fig. 26 is a flowchart showing an example of the flow of the process of reading data between the controller and the NAND flash memory according to the first embodiment.

Fig. 27 is a flowchart showing an example of the flow of the process of writing updated shift information into the management information storage area according to the first embodiment.

Fig. 28 is a diagram for explaining changes in the storage status of data in the memory cell array and the 5 data latch groups in the read processing of data in fig. 26 and the write processing of updated management information in fig. 27 to the nonvolatile memory in the first embodiment.

Fig. 29 is a diagram for explaining changes in the storage status of data in the memory cell array and the 5 data latch groups in the data reading processing of fig. 26 and the writing processing of the updated management information in fig. 27 to the nonvolatile memory in the first embodiment.

Fig. 30 is a diagram showing an instruction sequence for the update process of data at a designated column address in the data latch group in SS42 of fig. 28 according to the first embodiment.

Fig. 31 is a diagram showing a command sequence for writing management information into a memory cell array in SS44 of fig. 29 according to the first embodiment.

Fig. 32 is a diagram showing a command sequence showing a change in the input/output signal of the controller when the reading is suspended according to the first embodiment.

Fig. 33 is a diagram for explaining a change in the storage status of data in a plurality of data latch groups with execution of an instruction sequence according to the first embodiment.

Fig. 34 is a diagram showing the data storage states of the management information storage area MIA and the plurality of data latch groups at the time of power-off or the like in the second embodiment.

Fig. 35 shows the storage state of the management information in the memory cell array and the plurality of data latch groups in the steady state according to the second embodiment.

Fig. 36 is a diagram for explaining data transfer in the case where management information is read and stored in a data latch group according to the second embodiment.

Fig. 37 is a diagram showing a method of copying the management information read out in SLC mode from the data latch group XDL to any of the data latch groups ADL to CDL to make a plurality of data latch groups stably state in the second embodiment.

Fig. 38 is a diagram showing another method of transferring management information stored in the data latch groups ADL, BDL, and CDL to the data latch group XDL to stably state a plurality of data latch groups according to the second embodiment.

Fig. 39 is a diagram showing a case where the management information according to the second embodiment is transferred to any one of the data latch groups ADL, BDL, and CDL via the data latch group SDL.

Fig. 40 is a diagram showing an instruction sequence for stably bringing a plurality of data latch groups into a state according to the second embodiment.

Fig. 41 is a diagram for explaining a change in the storage state of the management information until the management information is stored in the plurality of data latch groups according to the second embodiment.

Fig. 42 is a diagram showing another instruction sequence for stably state-changing a plurality of data latch groups according to the second embodiment.

Fig. 43 is a diagram for explaining a change in the storage state of the management information until the management information is stored in the plurality of data latch groups according to the second embodiment.

Fig. 44 is a diagram showing a command sequence for reading out management information from a steady state according to the second embodiment.

Fig. 45 is a diagram for explaining a change in the storage status of data in the memory cell array and the 5 data latch groups in the read-out process of the management information according to the second embodiment.

Fig. 46 is a diagram showing a command sequence of the update process of the management information MI in the steady state according to the second embodiment.

Fig. 47 is a diagram for explaining a change in the storage status of data in the memory cell array and the 5 data latch groups in the update processing of the management information according to the second embodiment.

Fig. 48 is a diagram for explaining a change in the storage status of data in writing of update data to the memory cell array according to the second embodiment.

Fig. 49 is a diagram for explaining selection of shift information, which is management information MI used when data is read in the second embodiment.

Fig. 50 is a diagram showing states of 6 data latch groups at the time of reading data according to the second embodiment.

Fig. 51 is a flowchart showing an example of the flow of the process of reading data between the controller and the NAND flash memory according to the second embodiment.

Fig. 52 is a flowchart showing an example of the flow of the patrol (control) process according to the second embodiment.

Fig. 53 is a flowchart showing an example of a flow of a predetermined process in reading out a target address in the patrol processing according to the second embodiment.

Fig. 54 is a diagram showing a storage state of data in the management information storage area and the plurality of data latch groups in an idle (idle) state according to the second embodiment.

Fig. 55 is a diagram for explaining a change in the storage status of data in the 5 data latch groups when the patrol processing is executed according to the second embodiment.

Fig. 56 is a diagram for explaining a change in the storage status of data in the 5 data latch groups when the patrol processing is executed according to the second embodiment.

Fig. 57 is a diagram showing the storage states of data in the management information storage areas and the plurality of data latch groups relating to the data of blocks BLK0 to BLK999 according to the second embodiment.

Fig. 58 is a block diagram for explaining the configuration of the memory system according to the second embodiment, which shows a state in which update data is stored in the middle of the RAM.

Fig. 59 is a block diagram for explaining the configuration of the memory system according to the second embodiment, in which the state in which the update data is transferred to the data latch group after the end of storing the update data in the RAM is shown.

Fig. 60 is a diagram showing the storage state of 2 pieces of management information of 2 NAND-type flash memories according to the third embodiment.

Fig. 61 is a diagram showing a storage state of 2 pieces of management information of 2 NAND-type flash memories according to the third embodiment.

Fig. 62 is a diagram showing the storage state of 2 pieces of management information of 2 NAND-type flash memories according to the third embodiment.

Fig. 63 is a diagram showing a command sequence of a data reading process according to the third embodiment.

Fig. 64 is an assembly diagram for explaining the structure of the memory system according to the fourth embodiment.

Fig. 65 is a flowchart showing an example of the flow of the process of reading data of the second chip by the first chip in the fourth embodiment.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings.

(first embodiment)

The memory system of the first embodiment will be explained. Hereinafter, a memory system including a NAND-type flash memory as a semiconductor memory device will be described as an example.

1. Structure of the product

[ overall Structure of memory System ]

First, a general overall configuration of the memory system according to the present embodiment will be described with reference to fig. 1.

Fig. 1 is a block diagram for explaining the structure of the memory system of the present embodiment. As shown in the figure, the memory system 1 includes a NAND-type flash memory 100 and a memory controller (hereinafter, also simply referred to as a controller) 200. The NAND-type flash memory 100 and the controller 200 are semiconductor devices formed on, for example, 1 substrate, and the semiconductor devices are used for memory cards such as SD cards, SSDs (solid state drives), and the like as examples.

The NAND flash memory 100, which is a nonvolatile memory, includes a plurality of memory cells and stores data in a nonvolatile manner. The controller 200 is connected to the NAND-type flash memory 100 via a NAND bus and to the host device 300 via a host bus. Also, the controller 200 is a memory controller that controls the NAND-type flash memory 100 and accesses the NAND-type flash memory 100 in response to a request received from the host device 300. The host device 300 is, for example, a digital camera, a personal computer, or the like, and the host bus is, for example, a bus conforming to an SD interface. The NAND bus is a bus that transmits and receives signals conforming to the NAND interface.

Various signals are transceived between the NAND-type flash memory 100 and the controller 200 via a NAND interface (I/F) circuit 250. The chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the read enable signal REn are supplied from the controller 200 to the NAND-type flash memory 100. The ready/busy signal RBn is supplied from the NAND-type flash memory 100 to the controller 200. The input/output signal I/O is transmitted and received between the controller 200 and the NAND-type flash memory 100.

The chip enable signal CEn is a signal for enabling the NAND-type flash memory 100, and is active (assert) at a low (low) level. The command latch enable signal CLE and the address latch enable signal ALE are signals for notifying the NAND-type flash memory 100 that the input/output signal I/O is a command and an address, respectively. The write enable signal WEn is a signal that is active at the low level and notifies the NAND-type flash memory 100 that the input/output signal I/O is written to the NAND-type flash memory 100. The read enable signal REn is also a signal which is active low for outputting the read data from the NAND-type flash memory 100 to the input/output signal I/O. The ready/busy signal RBn is a signal indicating whether the NAND-type flash memory 100 is in a ready state (a state capable of receiving a command from the controller 200) or in a busy state (a state incapable of receiving a command from the controller 200), and a low level indicates the busy state. The input/output signal I/O is, for example, an 8-bit signal. The input/output signal I/O is data transmitted and received between the NAND-type flash memory 100 and the controller 200, and is an instruction, an address, write data, read data, and the like.

[ Structure of controller ]

Next, the configuration of the controller 200 will be described in detail. As shown in fig. 1, the controller 200 is a circuit including a host interface (I/F) circuit 210, a random access memory (hereinafter, referred to as a RAM)220 as a built-in memory, a processor 230 having a Central Processing Unit (CPU), a buffer memory 240, a NAND interface circuit 250, and an ecc (error Checking and correcting) circuit 260.

The host interface circuit 210 is connected to the host device 300 via a host bus, and transfers a request and data received from the host device 300 to the processor 230 and the buffer memory 240, respectively. Further, in response to an instruction from the processor 230, the data in the buffer memory 240 is transferred to the host device 300.

The RAM220 is a semiconductor memory such as a DRAM or an SRAM, and is used as a work area of the processor 230. The RAM220 stores firmware and management information MI for managing the NAND-type flash memory 100. The management information MI is a lookup table (LUT), shift table information (TBL), and the like, which will be described later. The shift table information TBL contains shift information. The shift information is information for shifting the readout level of data when the controller 200 performs readout processing of data.

The processor 230 controls the overall operation of the controller 200. For example, the processor 230, upon receiving a data request from the host device 300, issues a read instruction to the NAND interface circuit 250 in response thereto. When receiving a data write request and a data erase request from the host device 300, the processor 230 similarly issues an instruction corresponding to the received request to the NAND interface circuit 250. In addition, the processor 230 executes various processes for managing the NAND-type flash memory 100, such as wear leveling (ware leveling).

The buffer memory 240 temporarily stores write data and read data.

The NAND interface circuit 250 is connected to the NAND-type flash memory 100 via a NAND bus, and is responsible for communication with the NAND-type flash memory 100. Further, the NAND interface circuit 250 transmits various signals including instructions, data, and the like to the NAND-type flash memory 100 based on the instructions received from the processor 230, and receives various signals and data from the NAND-type flash memory 100.

The NAND interface circuit 250 outputs a chip enable signal CEn, an instruction latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn to the NAND-type flash memory 100 based on an instruction received from the processor 230. In addition, at the time of data writing, the NAND interface circuit 250 transfers a write command issued by the processor 230 and write data in the buffer memory 240 to the NAND-type flash memory 100 as an input/output signal I/O. Further, at the time of reading data, the NAND interface circuit 250 transfers a read command issued from the processor 230 to the NAND-type flash memory 100 as an input/output signal I/O, and further receives data read from the NAND-type flash memory 100 as an input/output signal I/O, and transfers the data to the buffer memory 240.

The ECC circuit 260 performs error detection and error correction processing on data stored in the NAND flash memory 100. That is, the ECC circuit 260 generates an error correction code at the time of writing data, applies the error correction code to the written data, and decodes the data while performing error correction at the time of reading the data.

[ configuration of NAND type flash memory ]

Next, the structure of the NAND flash memory 100 will be described. As shown in fig. 1, the NAND-type flash memory 100 includes a memory cell array 110, a row decoder 120, a driver circuit 130, a column decoder 140, an address register 150, an instruction register 160, and a sequencer 170.

The memory cell array 110 includes a plurality of blocks BLK including a plurality of nonvolatile memory cells corresponding to rows and columns. Fig. 1 shows 4 blocks BLK0 to BLK3 as an example. Also, the memory cell array 110 nonvolatilely stores data supplied from the controller 200.

The row decoder 120 selects any one of the blocks BLK0 to BLK3 based on the block address BA in the address register 150, thereby selecting the word line WL in the selected block BLK.

The driver circuit 130 supplies a voltage to the selected block BLK via the row decoder 120 based on the page address PA within the address register 150.

The column decoder 140 includes a plurality of data latch circuits and a plurality of sense amplifiers. Each sense amplifier reads data read from the memory cell array 110 at the time of reading the data, and performs necessary operations. Then, the column decoder 140 outputs the data DAT to the controller 200 via a data latch circuit XDL described later. In writing data, the column decoder 140 receives the write data DAT received from the controller 200 in the data latch circuit XDL, and then performs a write operation to the memory cell array 110.

The address register 150 holds an address ADD received from the controller 200. The address ADD includes the aforementioned block address BA and page address PA. The command register 160 holds a command CMD received from the controller 200.

The sequencer 170 controls the operation of the entire NAND-type flash memory 100 based on the command CMD stored in the command register 160.

Next, the structure of the block BLK will be described with reference to fig. 2. Fig. 2 is a circuit diagram for explaining the structure of the memory cell array of the present embodiment. As shown, 1 block BLK contains, for example, 4 string units SU (SU 0-SU 3). In addition, each string unit SU includes a plurality of NAND strings 6.

The NAND strings 6 each include, for example, 8 memory cell transistors MT (MT 0-MT 7) and 2 select transistors ST1, ST 2. Each memory cell transistor MT includes a control gate and a charge storage layer, and stores data in a nonvolatile manner. Also, a plurality of (for example, 8) memory cell transistors MT are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST 2.

The gates of the select transistors ST1 in the string units SU0 to SU3 are connected to the select gate lines SGD0 to SGD3, respectively. In contrast, the gates of the selection transistors ST2 in the string units SU0 to SU3 are commonly connected to the selection gate line SGS, for example. Of course, the gates of the select transistors ST2 in the string units SU0 to SU3 may be connected to different select gate lines SGS0 to SGS3 for each string unit. The control gates of the memory cell transistors MT0 to MT7 in the same block BLK are commonly connected to word lines WL0 to WL7, respectively.

In the memory cell array 110, the drains of the select transistors ST1 of the plurality of NAND strings 6 in the same column are commonly connected to a bit line BL (BL0 to BL (K-1), where K is a natural number of 2 or more). That is, the bit line BL connects the plurality of NAND strings 6 in common among the plurality of blocks BLK. The sources of the plurality of selection transistors ST2 are commonly connected to the source line SL.

That is, each string unit SU includes a plurality of NAND strings 6 connected to a plurality of bit lines BL different from each other and connected to the same select gate line SGD. Each block BLK includes a plurality of string units SU sharing the word lines WL. The memory cell array 110 is an aggregate of a plurality of blocks BLK in which the bit lines BL are commonly connected.

Fig. 3 is a sectional view of a partial area of 1 block BLK. As shown, a plurality of NAND strings 6 are formed on the p-type well region 10. That is, on the p-type well region 10, for example, a 4-layer wiring layer 11 functioning as the select gate line SGS, an 8-layer wiring layer 12 functioning as the word lines WL0 to WL7, and for example, a 4-layer wiring layer 13 functioning as the select gate line SGD are stacked in this order. An insulating film, not shown, is formed between the stacked wiring layers.

A plurality of columnar conductors 14 penetrating these wiring layers 13, 12, and 11 and reaching the p-type well region 10 are formed. On the side surface of each conductor 14, a gate insulating film 15, a charge storage layer (insulating film or conductive film) 16, and a block insulating film 17 are formed in this order, and a plurality of memory cell transistors MT and selection transistors ST1 and ST2 are formed by these. Each conductor 14 functions as a current path of the NAND string 6 and serves as a region for forming a channel of each transistor. The upper end of each conductor 14 is connected to a metal wiring layer 18 functioning as a bit line BL.

N is formed in the surface region of the p-type well region 10⁺And a type impurity diffusion layer 19. At n⁺A contact plug 20 is formed on the type impurity diffusion layer 19, and the contact plug 20 is connected to a metal wiring layer 21 functioning as a source line SL. Further, p is formed in the surface region of the p-type well region 10⁺And a type impurity diffusion layer 22. At p⁺Contact plug 23 is formed on type impurity diffusion layer 22, and contact plug 23 is connected to metal wiring layer 24 functioning as well wiring CPWELL. The well wiring CPWELL is a wiring for applying a potential to the conductor 14 via the p-type well region 10.

In the above configuration, a plurality of NAND strings 6 are arranged in the depth direction of the paper surface shown in fig. 3, and a string unit SU is formed by a set of the NAND strings.

In this example, 1 memory cell transistor MT can hold 3 bits of data, for example. That is, the NAND-type flash memory 100 is a semiconductor memory device of a so-called tlc (triple level cell) system. The 3-bit data is called a Lower (Lower) bit, a Middle (Middle) bit, and an Upper (Upper) bit from the Lower bits. A set of lower bits stored in the plurality of memory cell transistors MT connected to the same word line WL in one string cell is referred to as a lower page, a set of middle bits is referred to as a middle page, and a set of upper bits is referred to as an upper page. A plurality of memory cell transistors MT connected to one word line in one string constitute one page unit that holds a lower bit, a middle bit, and an upper bit. That is, 3 pages are allocated to each page unit. Therefore, in the case of a block BLK having 4 string units SU each including 8 word lines WL, each block BLK has a capacity of an amount of 96 pages. Or in other words, "page" can also be defined as a part of a memory space formed by a plurality of memory cell transistors MT connected on the same word line WL in one string cell. Data is written in units of page units, and data is read for each page (this reading method is referred to as page-by-page reading).

In addition, the erasure of data can be performed in units of blocks BLK or in units smaller than blocks BLK. The erasing method is described in, for example, "non-volatile SEMICONDUCTOR DEVICE," us patent application 13/235, 389, filed on 2011, 9/18. Further, the invention is described in U.S. patent application No. 12/694, 690, entitled "NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE", filed on 27.1.2010. Further, the patent is described in U.S. patent application No. 13/483, 610, filed on 30/5/2012, of "NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DATA ERASE METHOD for thermal process. The entire contents of these patent applications are incorporated by reference into the present specification.

Further, the structure of the memory cell array 110 may be other structures. That is, the structure of the MEMORY cell array 110 is described in, for example, U.S. patent application No. 12/407, 403, entitled "method for manufacturing SEMICONDUCTOR device MEMORY", which was filed 3/19/2009. Further, THE invention is described in "THE present inventors filed on 3/18/2009 OF U.S. patent application 12/406, 524," NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME ", which was filed on 3/25/2009 OF 2009, AND in" THE present inventors filed on 3/23/2009 OF U.S. patent application 12/679, 991 OF "SEMICONDUCTOR STORAGE MEMORY AND metal OF MANUFACTURING THE SAME", which was filed on 3/23/2009 OF 2009, U.S. patent application 12/532, 030 OF "THE present inventors filed on 3/23/2009. The entire contents of these patent applications are incorporated by reference into the present specification.

As will be described later, the management information MI described later is stored in a storage area (management information storage area MIA described later) of a part of the memory cell array 110.

(Structure of column decoder)

Next, the structure of the column decoder 140 will be described with reference to fig. 4. Fig. 4 is a circuit diagram of the column decoder 140 and the string unit SU0 of the first embodiment.

As shown, the column decoder 140 includes a plurality of sense cells SAU (SAU0 to SAU (K-1)) provided for each bit line BL.

Each of the plurality of sense cells SAU includes a sense amplifier SA, an operation unit OP, and 4 data latch circuits (hereinafter, also simply referred to as data latches) ADL, BDL, CDL, and XDL. Each sense amplifier SA also includes a data latch SDL.

Each sense amplifier SA senses data that has been read out to the corresponding bit line BL, and applies a voltage to the bit line BL in accordance with the write data. That is, the sense amplifier SA is a block that directly controls the bit line BL. Also, in the sense amplifier SA, a strobe signal STB is supplied at the time of readout, for example, by the sequencer 170. The sense amplifier SA includes a node SEN and a data latch SDL (not shown in fig. 4) therein. The potential of the node SEN varies depending on whether the memory cell transistor MT connected to the selected word line WL is turned on or off. Then, the potential of the node SEN at the timing when the strobe signal STB is active determines whether the memory cell transistor MT is on or off, and as a result, the data is stored in the internal data latch (data latch SDL) as "0" or "1" data. The data held in the internal data latch SDL is further copied to any one of the data latches ADL, BDL, CDL, and XDL.

The data latches ADL, BDL, and CDL temporarily hold write data. That is, the data latches ADL, BDL, CDL are used for the controller 200 to write data to the NAND-type flash memory 100. The operation unit OP performs various logical operations such as a NOT operation, a logical sum (OR) operation, a logical product (AND) operation, an exclusive OR (XOR) operation, AND an exclusive nor (XNOR) operation on the data stored in the sense amplifier SA AND the data latches ADL, BDL, CDL, AND XDL. For example, the operation unit OP generates page data by operating data copied from the plurality of data latches SDL inside the sense amplifier SA.

These sense amplifiers SA, data latches ADL, BDL, CDL, and operation unit OP are connected by a bus so as to be able to transmit and receive data to and from each other. Also, the bus is also connected to the data latch XDL.

Data input/output to/from the column decoder 140 is performed via a plurality of data latches XDL. That is, the data received from the controller 200 is transferred to the plurality of data latches ADL, BDL, and CDL or the plurality of sense amplifiers SA via the plurality of data latches XDL. In addition, data of the plurality of data latches ADL, BDL, and CDL or the plurality of sense amplifiers SA is transmitted to the controller 200 via the plurality of data latches XDL. The plurality of data latches XDL function as a cache memory of the NAND-type flash memory 100. Therefore, even if the plurality of data latches ADL, BDL, and CDL are in use, the NAND-type flash memory 100 can become a ready state if the plurality of data latches XDL are idle.

Reading and writing of data are performed in units of pages. The column decoder 140 has a plurality of data latches ADL, BDL, CDL, XDL, SDL that store data of 1 page amount, respectively.

Hereinafter, as shown in fig. 4, a plurality of data latches XDL storing 1 page worth of data is referred to as a data latch group XDL, a plurality of data latches ADL storing 1 page worth of data is referred to as a data latch group ADL, a plurality of data latches BDL storing 1 page worth of data is referred to as a data latch group BDL, a plurality of data latches CDL storing 1 page worth of data is referred to as a data latch group CDL, and a plurality of data latches SDL storing 1 page worth of data is referred to as a data latch group SDL. That is, the column decoder 140 includes a data latch group XDL, a data latch group ADL, a data latch group BDL, a data latch group CDL, and a data latch group SDL, which store data of 1 page amount.

Therefore, the data latch group XDL constitutes a plurality of data latch circuits used for inputting and outputting data between the controller 200 and the NAND-type flash memory 100. The data latch groups ADL, BDL, and CDL are used when the controller 200 writes data into the NAND-type flash memory 100, and are not used when reading data. In each of the data latch groups ADL, BDL, and CDL, when the controller 200 reads data from the NAND-type flash memory 100, the stored data is maintained.

[ held data and threshold voltage of memory cell transistor ]

The stored data, the threshold voltage, and the read level (i.e., the read voltage) of each data of the memory cell transistor MT will be described with reference to fig. 5. Fig. 5 is a graph showing data that can be stored in each memory cell transistor MT, a threshold voltage distribution, and a voltage used for reading.

As described above, the memory cell transistor MT can take 8 states according to the threshold voltage. These 8 states are referred to as an "Er" state, an "a" state, a "B" state, a "C" state, and an … "G" state in order from the state in which the threshold voltage is low.

The threshold voltage of the memory cell transistor MT in the "Er" state is lower than the voltage VA, and corresponds to an erased state of data. The threshold voltage of the memory cell transistor MT in the "a" state is equal to or higher than the voltage VA and lower than the voltage VB (> VA). The threshold voltage of the memory cell transistor MT in the "B" state is equal to or higher than the voltage VB and lower than the voltage VC (> VB). The threshold voltage of the memory cell transistor MT in the "C" state is equal to or higher than the voltage VC and lower than the voltage VD (> VC). The threshold voltage of the memory cell transistor MT in the "D" state is equal to or higher than the voltage VD and lower than the voltage VE (> VD). The threshold voltage of the memory cell transistor MT in the "E" state is equal to or higher than the voltage VE and lower than the voltage VF (> VE). The threshold voltage of the memory cell transistor MT in the "F" state is equal to or higher than the voltage VF and lower than the voltage VG (> VF). The threshold voltage of the memory cell transistor MT in the "G" state is equal to or higher than the voltage VG and is smaller than the voltage VREAD. Among the 8 states thus distributed, the "G" state is the state in which the threshold voltage is the highest. The voltage VREAD is a voltage applied to the unselected word line WL during the read operation, and is a voltage for turning on the memory cell transistor MT regardless of the stored data. Voltages VA to VG are also collectively referred to as voltage VCGRV.

The threshold voltage distribution is realized by 3-bit (3-page) data including the lower bit, the middle bit, and the upper bit. That is, the relationships between the "Er" state to the "G" state and the lower bit, the middle bit, and the upper bit are as follows.

"Er" state: "111" (labeled in the order of "upper part/middle part/lower part")

The "A" state: "110"

The "B" state: "100"

The "C" state: "000"

The "D" state: "010"

The "E" state: "011"

The "F" state: "001"

The "G" state: "101"

In this way, only 1 bit of 3 bits changes between data corresponding to 2 states adjacent to each other in the threshold voltage distribution.

Therefore, when reading the lower bits, a voltage corresponding to a boundary at which the value ("0" or "1") of the lower bits changes may be used, and the same applies to the middle bits and the upper bits.

That is, as shown in fig. 5, the lower page readout uses, as readout levels, a voltage VA that distinguishes the "Er" state from the "a" state, and a voltage VE that distinguishes the "D" state from the "E" state. The read operations using the voltages VA and VE are referred to as read operations AR and ER, respectively.

The read operation AR determines whether or not the threshold voltage of the memory cell transistor MT is smaller than the voltage VA. That is, the memory cell transistor MT in the erase state is determined by the read operation AR. Read operation ER determines whether or not the threshold voltage of memory cell transistor MT is lower than voltage VE.

The middle bit page read uses, as read levels, a voltage VB that distinguishes "a" and "B" states, a voltage VD that distinguishes "C" and "D" states, and a voltage VF between "E" and "F" states. The read operations using the voltages VB, VD, and VF are referred to as read operations BR, DR, and FR, respectively.

Read operation BR determines whether or not the threshold voltage of memory cell transistor MT is lower than voltage VB. The read operation DR determines whether or not the threshold voltage of the memory cell transistor MT is lower than the voltage VD. Read operation FR determines whether or not the threshold voltage of memory cell transistor MT is lower than voltage VF.

Also, the upper page reading uses, as the read levels, a voltage VC that distinguishes the "B" state and the "C" state, and a voltage VG that distinguishes the "F" state and the "G" state. The read operations using the voltages VC and VG are referred to as read operations CR and GR, respectively.

The read operation CR determines whether or not the threshold voltage of the memory cell transistor MT is lower than the voltage VC. Read operation GR determines whether or not the threshold voltage of memory cell transistor MT is lower than voltage VG. That is, the memory cell transistor MT in the "G" state is determined by the read operation GR.

[ management information ]

In the memory system 1, the management information MI is used. The management information MI is shift table information TBL, history data HD, a lookup table LUT, and the like, which will be described later. The management information MI is stored in the NAND-type flash memory 100. The management information MI is copied from the NAND-type flash memory 100 to the RAM220 of the controller 200 and used when the power is turned on. As will be described later, a part of the management information MI (shift information in the present embodiment) is stored in at least 1 data latch group in the NAND-type flash memory 100.

The management information MI is written in a predetermined memory area (hereinafter, referred to as a management information memory area) MIA of the memory cell array 110 in a write mode (hereinafter, referred to as an SLC mode) in which 1-bit data is written for each memory cell transistor MT. As described above, in the present embodiment, the user data written from the host is data of 3 bits per memory cell transistor MT, but the management information MI is data of 1 bit per memory cell transistor MT, and is written in the management information storage area MIA of the memory cell array 110 in SLC mode.

As described above, the NAND-type flash memory 100 has the memory cell array 110 as a nonvolatile memory. The memory cell array 110 has a plurality of physical blocks each having a memory area accessible in units of pages.

The controller 200 performs read control of data in units of pages and write control of data in units of pages for a plurality of physical blocks of the memory cell array 110.

2. Movement of

Next, a write operation and a read operation of the memory system will be described.

As described above, the controller 200 reads data from the NAND-type flash memory 100 and writes data to the NAND-type flash memory 100 by outputting various signals and data to the NAND-type flash memory 100 in a predetermined sequence in response to a request from the host device 300.

[ action during data write ]

Fig. 6 is a diagram showing a command sequence at the time of writing data. Fig. 7 and 8 are diagrams for explaining a change in the storage status of data in the 5 data latch groups accompanying execution of the command sequence at the time of data writing. Fig. 7 and 8 show the storage state of data corresponding to the number K of data to be written for each data latch group. Therefore, the horizontal width of each band-shaped frame in fig. 7 and 8 indicates the length corresponding to the number of data K. K corresponds to the amount of data in one read operation and one write operation of data to the NAND-type flash memory 100. In fig. 10 and the like described later, the width of each band-shaped frame also indicates the length corresponding to the number K of data.

Here, the data writing is a program operation for writing data into the memory cell array 110 by the sequencer 170 after 3 pages of data of the lower bit, the middle bit, and the upper bit are written into the data latch groups ADL, BDL, and CDL.

Each command is supplied from the controller 200 to the NAND-type flash memory 100 by an 8-bit input/output signal I/O. The programming action is performed per page unit. Here, a command of a command sequence for writing, etc. is output from the controller 200 to the NAND-type flash memory 100 in the order of the lower bit, the middle bit, and the upper bit. In each instruction sequence, the controller 200 outputs 2 instructions in the first 2 instruction cycles, 5 addresses in the 5 address cycles, a plurality of data in the following cycles, and 1 instruction in the following 1 cycle. The controller 200 outputs commands, addresses, and data to the NAND-type flash memory 100 in the order of the command sequences SQ1, SQ2, and SQ3 of fig. 6.

As shown in the command sequence SQ1, the controller 200 first outputs a command "c 11" for making a reservation for writing to the lower bit to the input/output signal I/O. When the command "c 11" is output to the input/output signal I/O, as shown in LS1 of fig. 7, no data is stored in each data latch group. In fig. 7, the hatched lines indicate a state where no data is stored or a state where data is indefinite.

Following the command "c 11", the controller 200 outputs a command "c 21" to the input-output signal I/O. All of the data latches XDL of the data latch group XDL are reset by instruction "c 21". Here, the reset means that the value of each data latch XDL of the data latch group XDL becomes "1". By the instruction "c 21", as shown in LS2 of FIG. 7, the data of the group of data latches XDL is reset. As shown in fig. 7 with blank, the data of all the data latches XDL is in a state of "1".

Following the command "c 21", the controller 200 outputs 5 addresses to the input-output signal I/O. The first 2 addresses "CAL 1" and "CAL 2" are column addresses, and the remaining 3 addresses "RAL 1", "RAL 2", and "RAL 3" are row addresses.

Next, 5 addresses, the controller 200 outputs a plurality of data "DL 0", "DL 1", … "," DL (K-1) "to the input/output signal I/O. As described above, K represents the number of data. Each data of the input/output signal I/O is stored in the data latch XDL of the sense unit SAU of the column decoder 140 corresponding to the designated address.

LS3 in fig. 7 shows, with fine oblique lines, the storage states of data of a plurality of data "DL 0" to "DL (K-1)" halfway in the data latch group XDL. LS4 of FIG. 7 represents a state in which all data of a plurality of data "DL 0" through "DL (K-1)" are stored in the data latch group XDL.

Following the plurality of data, the controller 200 outputs a command "c 22" to the input-output signal I/O. Instruction "c 22" is an instruction to copy data of the data latch group XDL to other data latch groups.

The data of the data latch group XDL is copied to the data latch group ADL by a combination of instruction "c 11" and instruction "c 22". The sequencer 170 performs a process of copying data of the data latch group XDL to the data latch group ADL based on the instructions "c 11" and "c 22".

In instruction sequence SQ1 of fig. 6, the timing of the long white arrow indicates the start timing of data copying from the data latch group XDL to the data latch group ADL, and the timing of the short arrow indicates the completion timing of data copying from the data latch group XDL to the data latch group ADL. During data copying from the group of data latches XDL to the group of data latches ADL, the ready/busy signal RBn becomes low. LS5 of fig. 7 represents a state in which all data of the data latch group XDL is copied to the data latch group ADL.

Thus, the write reservation command sequence SQ1 for the lower bit in fig. 6 is completed, and subsequently, the write reservation command sequence SQ2 for the middle bit is executed.

In the command sequence SQ2, 5 addresses are output to the input/output signal I/O following the 2 commands "c 12" and "c 21" in the same manner as in the command sequence SQ 1. Next to the 5 addresses, instruction "c 22" is output to the input-output signal I/O.

The data of the data latch group XDL is copied to the data latch group BDL by the combination of instruction "c 12" and instruction "c 22". Based on the instructions "c 12" and "c 22", the sequencer 170 performs a process of copying and transferring data of the data latch group XDL to the data latch group BDL.

In instruction sequence SQ2 in fig. 6, the timing of the long white arrow indicates the start timing of data copy transfer from data latch group XDL to data latch group BDL, and the timing of the short arrow indicates the completion timing of data copy transfer from data latch group XDL to data latch group BDL. During data copying from the group of data latches XDL to the group of data latches BDL, the ready/busy signal RBn becomes low.

After the instruction sequence SQ2, an instruction sequence SQ3 for executing the upper bit write reservation and the lower/middle/upper bit write is executed.

In the command sequence SQ3, 5 addresses are output to the input/output signal I/O following the 2 commands "c 13" and "c 21" in the same manner as in the command sequence SQ 1. Next to the 5 addresses, instruction "c 23" is output to the input-output signal I/O. The instruction "c 23" is an instruction to copy data of the data latch group XDL to another data latch group and then to execute a write operation.

The data of the data latch group XDL is copied to the data latch group CDL by a combination of instruction "c 13" and instruction "c 23". Based on the instructions "c 13" and "c 23", the sequencer 170 performs a process of copying and transferring data of the data latch group XDL to the data latch group CDL.

In instruction sequence SQ3 in fig. 6, the timing of the long white arrow indicates the start timing of data copy transfer from the data latch group XDL to the data latch group CDL, and the timing of the short arrow ts indicates the completion timing of data copy transfer from the data latch group XDL to the data latch group CDL. During data copying from the group of data latches XDL to the group of data latches CDL, the ready/busy signal RBn becomes low.

In fig. 6, the commands "c 12" and "c 13" are commands for making reservations for writing to the middle bit and the upper bit, respectively. Addresses "CAM 1" and "CAM 2" are column addresses of medium bits, and addresses "CAU 1" and "CAU 2" are column addresses of high bits. The addresses "RAM 1", "RAM 2", and "RAM 3" are row addresses of middle bits, and the addresses "RAU 1", "RAU 2", and "RAU 3" are row addresses of upper bits. The data "DM 0", "DM 1", … "DM (K-1)" are data of medium-bit, and the data "DU 0", "DU 1", … "DU (K-1)" are data of medium-bit.

LS6 of fig. 7 represents a state in which all the data latches XDL are reset by the instruction c21 in the instruction sequence SQ 2. LS7 of fig. 8 indicates, by thin vertical lines, storage states of data of a plurality of data "DM 0" to "DM (K-1)" halfway in the data latch group XDL. LS8 of FIG. 8 represents a state in which all data of a plurality of data "DM 0" through "DM (K-1)" are stored in the corresponding group of data latches XDL.

When instruction "c 22" in instruction sequence SQ2 is output, the data of the data latch group XDL is copied to the data latch group BDL. Sequencer 170 performs a process of copying data of data latch group XDL to data latch group BDL based on instructions "c 12" and "c 22".

In the command sequence SQ3, following the command "c 13" for reserving writing of data and the command "c 21" for resetting the data latch group XDL, when the output of the data "DU 0", "DU 1", … "DU (K-1)" is completed, the command "c 23" is output to the NAND-type flash memory 100.

When instruction "c 23" in instruction sequence SQ3 is output, the data of the data latch group XDL is copied and forwarded to the data latch group CDL. The sequencer 170 performs a process of copying and transferring data of the data latch group XDL to the data latch group CDL based on the instructions "c 13" and "c 23", and then starts a program operation, which is writing data in units of page cells. The sequencer 170 starts a programming operation after resetting all the data latches XDL. That is, after that, the write process of 3 pages of data using 3 data latches ADL/BDL/CDL to the memory cell array 110 is performed.

LS9 in fig. 8 indicates a state in which write data is stored in the data latch groups ADL, BDL, and CDL immediately before the start of the programming operation. In LS9 of fig. 8, the state in which all of the plurality of data "DU 0" to "DU (K-1)" are stored in the corresponding data latch group CDL is indicated by thin horizontal lines.

LS10 in fig. 8 shows a state in which each data latch group becomes "1" after the programming operation. In fig. 6, the programming action starts at a timing ts and ends at a timing te.

The ready/busy signal RBn is low from the start of data copying from the data latch group XDL to the data latch group CDL to the end of the program operation.

[ operation at data read-out ]

First, a basic operation in data reading (hereinafter, also referred to as normal reading) based on a preset threshold voltage will be described.

1) Basic action of normal reading

Fig. 9 is a diagram showing a basic command sequence in reading data. Fig. 10 is a diagram for explaining a change in the storage status of data in the 5 data latches accompanying execution of the instruction sequence.

As shown in the command sequence SQ4, the controller 200 outputs a command "c 11", "c 12", or "c 13" for making a read reservation of any one of the lower bit, the middle bit, and the upper bit to the input/output signal I/O.

Shown in fig. 9, following the command "c 13", the controller 200 outputs a command "c 31" to the input-output signal I/O. The controller 200 then instructs "c 31" to output 5 addresses to the input/output signal I/O.

Following the 5 addresses, the controller 200 outputs a command "c 32" to the input-output signal I/O. The instruction "c 32" is an instruction that instructs execution of reading of data. Accordingly, the sequencer 170 performs reading of data to the designated address. The read result of each data is first stored in each sense amplifier SA.

When the command "c 32" is output to the input/output signal I/O, as shown in LS11 of fig. 10, no data is stored in each data latch group. After that, the sequencer 170 reads out the data, and stores the data in the data latch group SDL as indicated by fine oblique lines in LS12 of fig. 10.

The NAND-type flash memory 100 performs a read operation after receiving the command "c 32", and thus the ready/busy signal RBn becomes low (indicated by a long white arrow).

After all of the data is stored in the group of data latches SDL, all of the data is copied to the group of data latches XDL. When all data is copied to the group of data latches XDL, the ready/busy signal RBn is high (high) (indicated by the white short arrow). LS13 of fig. 10 represents a state in which data of the data latch group SDL is copied to the data latch group XDL.

After that, the controller 200 reads out data from the data latch group XDL of the NAND-type flash memory 100.

As described above, the controller 200 can read out data from the NAND-type flash memory 100.

2) Basic action of shift reading

In data reading, the threshold voltage of the memory cell transistor MT varies for various reasons, and there is a case where data cannot be correctly read if the data reading, that is, normal reading, is performed based on the read level corresponding to the preset threshold voltage. In this case, the controller 200 changes the read level to perform the data read operation. That is, the controller 200 performs a data reading operation by setting a voltage (for example, the voltage VBs) shifted by a certain value (hereinafter, also referred to as a shift amount) from a read level corresponding to a threshold voltage (for example, the voltage VB) in normal reading as the read level. Hereinafter, such a read operation is referred to as shift reading.

Therefore, in the RAM220 of the controller 200, a plurality of (here, 3) shift tables for determining the shift amount are stored as the shift table information TBL. Each shift table is a part of the management information MI. The management information MI is stored in the management information storage area MIA of the memory cell array 110 of the NAND-type flash memory 100, and when the power supply of the memory system 1 is turned on, it is generally transferred to the RAM220 and referred to and used by the processor 230.

Fig. 11 is a diagram showing an example of the shift table TBL1 for the lower page, which is 1 table of the shift table information TBL. Fig. 12 is a diagram showing an example of the shift table TBL2 of the middle-order page in the shift table information TBL. Fig. 13 is a diagram showing an example of the shift table TBL3 of the upper page in the shift table information TBL. Each shift table is set with a plurality of shift amounts corresponding to a plurality of index numbers.

Further, the controller 200 determines the shift amount based on data (hereinafter, referred to as history data) specifying the shift amount for each block BLK, for example. The history data HD is, for example, table data, and includes an index number of each block BLK. When reading data of a certain block BLK, the controller 200 reads an index number set for the target block BLK from the history data HD, refers to the shift table information TBL, and performs shift reading for the block BLK using shift amount data corresponding to the read index number.

The history data HD may be in units of blocks BLK, in units of lower bits, middle bits, and upper bits in each block BLK, or in units of word lines WL in each block BLK. The processor 230 can specify the read target block BLK or the like from the read target address.

For example, the processor 230 reads out the index number set to the determined block BLK from the history data HD. The processor 230 refers to the corresponding shift table TBL, obtains shift amount data corresponding to the read index number, and calculates a read level (read voltage) by adding the shift amount data to a preset read level. As a result, the processor 230 can read out the data from the block BLK using the calculated read level.

Here, as shown in fig. 11 to 13, the shift table information TBL includes 3 shift tables set for each page. In the shift table TBL1 for the lower page in fig. 11, shift amounts of a plurality of levels (5 levels in this case) are set in the read operations AR and ER. In the shift table TBL2 for the middle page in fig. 12, shift amounts of a plurality of levels (5 in this case) are set in the read operations BR, DR, and FR. In the shift table TBL3 for the upper page in fig. 13, shift amounts of a plurality of levels (5 levels in this case) are set in the reading operations CR and GR.

Each shift table has a plurality of index numbers and has a shift amount for each index number. Here, as the index number increases, the shift amount in each read operation also increases.

As described above, the shift amount is set to, for example, the shift table information TBL provided in block units, and each shift table of the shift table information TBL is transferred from the management information storage area MIA to the RAM 220.

When data cannot be read by reading (normal reading) data using a read level corresponding to a threshold voltage corresponding to each state set in advance, shift reading is performed. Therefore, when the data cannot be read out by the normal reading, the shift reading is performed during the re-reading, and when the data can be read out, the index number of the history data HD is updated. As a result, the index number for specifying the shift amount data at the time of the last (latest) data readout is stored in the history data HD, and when the data readout is enabled by the normal reading, the index number in the history data HD is set to "0", for example.

Fig. 14 is a flowchart showing an example of a flow of a process of reading data between the controller 200 and the NAND-type flash memory 100 when there is a read request from the host. Fig. 14 shows a reading process of data for each page. The controller 200 determines a read target address (i.e., a physical address) using the lookup table LUT (fig. 1) in the RAM220 in accordance with a read request of data from the host device 300 (step (hereinafter, abbreviated as S) 1).

The read request from the host apparatus 300 specifies an address of read data by a logical address. The controller 200 stores correspondence information between logical addresses and physical addresses of the NAND-type flash memory 100 in the look-up table LUT as table information. In S1, when receiving the read request, the controller 200 refers to the look-up table LUT to specify a physical address corresponding to the logical address included in the read request.

When the physical address is determined, the controller 200 calculates the readout level with reference to the above-described history data HD (S2). The history data HD is conventionally stored in the RAM220, but in the present embodiment, is stored in a group of data latches that are not used when reading data. As described above, the history data HD stores the index number of the shift amount at the time of the last reading. In shift reading, a voltage of a shift amount of an index number of the record is added to a read voltage corresponding to each state set in advance used in normal reading, and the added voltage value is calculated as a read level.

Further, when the power is turned off, the lookup table LUT, the shift table information TBL, and the history data HD are stored, i.e., updated, to the management information storage area MIA of the memory cell array 110 of the NAND-type flash memory 100, and then, when the power is turned on, read out from the NAND-type flash memory 100 and stored in the RAM220 or the data latch group.

The controller 200 issues a read instruction to the NAND-type flash memory 100 based on the determined physical address and the read level calculated in S2 (S3).

When receiving the read command from the controller 200, the NAND-type flash memory 100 reads data based on the read command (S4). When the index number at the time of the last readout is not stored in the history data HD (i.e., when the index number is 0), normal reading is performed. When the index number at the time of the last readout is stored in the history data HD, shift reading using the shift amount corresponding to the index number is performed.

The read result is obtained by the controller 200. The controller 200 determines whether or not data can be read, that is, whether or not error correction can be performed by the ECC circuit 260 even if there is an error (S5).

When the data can be read (yes in S5), the controller 200 returns the read data (i.e., the data after the correction process) to the host device 300 (S6).

When the data cannot be read (i.e., when the error-binding cannot be performed) (S5: no), the controller 200 executes the re-read processing (S7). In the rereading process, rereading is performed while changing the shift amount by incrementing the index number of each shift table. Instead of re-reading with the shift amount changed, the read voltage may be determined by Vth tracking and re-read may be performed. Vth tracking is a process of determining a read voltage (so-called bottom position voltage) at which data can be read accurately, based on a change in the number of memory cells that become conductive (the number of conductive cells) when the read voltage is changed.

Shift reading is performed in the re-readout process (S7), and it is determined whether error correction is successful (S8) after the re-readout process (S7). If the error correction is unsuccessful, that is, data cannot be read (no in S8), the controller 200 returns a read status error indicating that data cannot be read to the host device 300 (S10).

When the shift reading is performed and the error correction is successful, that is, the reading of the data can be performed in the re-reading process (S7), the controller 200 updates the history data HD (S9) and returns the read data (i.e., the data after the correction process) to the host device 300 (S6).

As described above, data is read out from the NAND-type flash memory 100 while using the history data HD and the shift table information TBL.

3) Basic operation when suspending reading

When a read request is received from the host device 300 in the middle of a programming operation, the controller 200 temporarily interrupts (hereinafter also referred to as "pause") the programming operation of the NAND-type flash memory 100, executes the reading operation, and after the reading operation is executed, the controller 200 has a function of restarting (hereinafter also referred to as "resume") the programming operation.

When receiving a read command during a programming operation, the NAND-type flash memory 100 temporarily suspends the programming operation, performs data reading, and then resumes the programming operation. Such an action is an action for speeding up a response to a read request, and is called suspending reading.

The controller 200 includes a predetermined register (not shown) for storing pause information when the programming operation is paused. The controller 200 resumes the programming action based on the pause information held by the register.

Fig. 15 is a diagram showing a command sequence when the reading is suspended.

In the programming operation of the NAND-type flash memory 100, when a read request is received from the host device 300, the processor 230 of the controller 200 outputs a command "c 41" to interrupt the programming operation to the NAND-type flash memory 100, and stores pause information in a predetermined register (not shown), as shown in a command sequence SQ 5. After interrupting the programming action, the controller 200 causes the sequencer 170 to perform a read action.

Specifically, after the command "c 41" is output, the command and the address shown in fig. 9 are supplied from the controller 200 to the NAND-type flash memory 100, and the read data are supplied from the NAND-type flash memory 100 to the controller 200. When the reading of the data is finished, the controller 200 outputs a command "c 42" to resume the programming action, and the sequencer 170 restarts the programming action according to the command "c 42".

Fig. 16 is a diagram for explaining a change in the storage state of data in the 5 data latches at the time of suspending reading. LS21 in fig. 16 indicates the state of each data latch in the programming operation, and write data is stored in the data latch groups ADL, BDL, and CDL, and data for verification is stored in the data latch group SDL. LS22 in fig. 16 indicates the state of each data latch immediately before the program operation is interrupted and the read operation is started.

In the read operation, as shown in fig. 9 and 10, the data latch groups SDL and XDL are used. LS23 of fig. 16 shows: after all the data is read, the sequencer 170 stores the data in the state of the data latch group SDL as shown by a fine dot pattern. LS24 represents the state where data for data latch group SDL is copied to data latch group XDL. Thus, the controller 200 can read out data from the data latch group XDL.

Since the data of the 3 data latch groups ADL, BDL, and CDL are not changed when the reading is suspended, the sequencer 170 can resume the programming operation by directly using the data of the data latch groups ADL, BDL, and CDL when the programming operation is resumed. When the program operation is restarted, the states of the data latch groups SDL, ADL, BDL, CDL, and XDL become the same state as LS 21.

4) Storage area and steady state of management information

The controller 200 uses the management information MI to perform data writing operation and data reading operation to the NAND-type flash memory 100. The management information MI is information used by the controller 200, for example, when the NAND flash memory 100 is read out, and is data such as the lookup table LUT, the shift table information TBL, and the history data HD.

In general, when the power supply of the memory system 1 is changed from off to on, the management information MI is read out from the management information storage area MIA in the memory cell array 110 of the NAND-type flash memory 100, copied to the RAM220 of the controller 200, and used by the processor 230. However, in the case where the RAM220 having a large data size cannot be provided in the controller 200, if the data size of the management information MI becomes large such as the number of blocks increases, the RAM220 may not store all the management information MI.

In addition, since the RAM220 storing the management information MI is used to temporarily store a large amount of data in the tracking process, the patrol process, and the like, a sufficient free area is also required in the RAM 220. The shift information updated by the tracking process, the patrol process, or the like is also stored in the management information storage area MIA in the memory cell array 110.

Further, even if the number of bits of data stored in the memory cell transistor MT increases, the data size of the management information MI increases.

However, the NAND-type flash memory 100 may mostly read data after data is written once, depending on the application. For example, when the NAND-type flash memory 100 is used in a data center or the like, the frequency of data read out after data is written once is higher than the frequency of data write.

Therefore, in the present embodiment, by storing a part of the management information MI in a group of data latches that are not used in reading data, the controller 200 can read the management information MI with a small latency even if the large-sized RAM220 cannot be provided in the controller 200. That is, the controller 200 stores the management information MI used for reading data in 1 of the data latch group including the plurality of data latch circuits, in the NAND-type flash memory 100 during or before the execution of the data reading process.

In the present embodiment, the data amount of a part of the management information MI stored in the data latch group that is not used for reading data is the data amount that converges to 1 page and is stored in the data latch group ADL.

Hereinafter, a state in which a part of the management information MI is stored in the data latch group ADL is referred to as a stable state of the data latch group.

In the following example, a case will be described in which the history data HD used in shift reading is stored in the data latch group ADL as a part of the management information MI. That is, the history data HD is stored in the data latch group ADL indicated by the two-dot chain line in fig. 4.

When the history data HD is stored in the data latch group ADL, the index number indicating the shift amount data used for each block BLK is stored in the data latch group ADL as shift information.

Therefore, the controller 200 generates a correspondence table CT in which the column addresses of the data latch group ADL corresponding to the block BLK of the read target address are stored, and stores the table CT in the RAM 220. The processor 230 can acquire the shift information (here, the index number) corresponding to the block BLK from the data latch group ADL by referring to the correspondence table CT, and perform shift reading.

In the present embodiment, the look-up table LUT and the shift table information TBL, both of which are management information, are stored in the RAM220 as indicated by broken lines in fig. 1, but when data is read, the controller 200 reads the index number of the target address in the history data HD from the data latch group ADL. The controller 200 can perform shift reading using the shift amount data determined according to the read index number with reference to the shift table information TBL.

When the history data HD as the management information MI is stored in the data latch group ADL, it may be stored in the data latch group XDL together.

A procedure of storing the management information MI from the management information storage area MIA in the memory cell array 110 into the data latch group ADL will be described.

First, a stable state set by transferring the management information MI to the data latch group ADL and a procedure of processing for stabilizing the state will be described. The process of stabilization of the state is performed before the read-out process of data is performed by the controller 200 in accordance with a request from the host apparatus 300. Fig. 17 to 19 are diagrams for explaining a change in the storage state of the management information MI until the management information MI is stored in the data latch group ADL. Fig. 17 to 19 show the storage states of the management information MI in the memory cell array 110 and the 5 data latches.

A first storing procedure of the management information MI will be explained. SS1 of fig. 17 indicates that in the initial state (or after data writing or after data erasing), management information MI is stored in the management information storage area MIA of the memory cell array 110. The processor 230 performs, in response to a read request of data from the host apparatus 300, reading out the management information MI in SLC mode from the management information storage area MIA, storing the management information MI (here, history data HD) in the data latch group SDL as indicated by a dotted line in SS2, and further copying to the data latch group XDL. Processor 230 then copies the management information MI from data latch group XDL to data latch group ADL, as indicated by the dashed line in SS 3. SS3 represents a steady state, but management information MI is also stored in the data latch group XDL.

As described above, before executing the read processing corresponding to the request from the external host device 300, the controller 200 reads the management information MI from the management information storage area MIA, which is a predetermined storage area, and stores the management information MI in the data latch group ADL.

Next, a second storing process of the management information MI will be explained. From the state of SS11 of fig. 18, which is the same as SS1 of fig. 17, as indicated by the broken line in fig. 18, the processor 230 performs reading out of the management information MI in SLC mode from the management information storage area MIA in response to a read-out request of data from the host apparatus 300, thereby storing the management information MI in the data latch group SDL as indicated by the broken line in SS 12. Processor 230 then copies management information MI from data latch population SDL to data latch population ADL as indicated by the dashed line in SS 12. SS12 represents the second stable state of the management information MI.

A third storing procedure of the management information MI will be explained. From the state of SS12 of fig. 18, processor 230 copies management information MI from the group of data latches ADL to the group of data latches XDL, as indicated by SS 13. SS13 represents the third stable state of the management information MI.

A fourth storing procedure of the management information MI will be explained. From the state of SS21 of fig. 19, which is the same as SS1 of fig. 17, processor 230 executes, as indicated by the broken line in fig. 19, reading out management information MI in SLC mode from management information storage area MIA in response to a read-out request of data from host apparatus 300, thereby storing the management information MI in data latch group SDL as indicated by the broken line in SS 22. Thereafter, processor 230 copies management information MI from data latch group SDL to both of the 2 data latch groups ADL and XDL, as indicated by the dashed lines in SS 22. SS22 represents the fourth stable state of management information MI, but management information MI is also stored in the data latch group XDL.

Fig. 20 is a diagram showing an instruction sequence SQ11 of the first storage procedure. When the processor 230 is in the initial state (or after data is written or after data is erased), the processor outputs a command "c 51" for executing reading of the management information MI from the management information storage area MIA in the SLC mode. Following the instruction "c 51", the processor 230 outputs the instruction "c 31" to the input-output signal I/O. Following the command "c 31", the controller 200 outputs 5 addresses to the input-output signal I/O. Following the 5 addresses, the controller 200 outputs a command "c 32" to the input-output signal I/O.

Instruction "c 32" is an instruction that instructs reading of data to be performed, and thus sequencer 170 performs reading of data to the specified address. The read result of the data is first stored in the plurality of sense amplifiers SA and then copied to the data latch group XDL.

The processor 230 outputs an instruction "c 52" to the input-output signal I/O that causes data of the data latch group XDL to be copied to the data latch group ADL. As a result, the management information MI is stored in the plurality of readout units SAU in a stable state shown by SS3 in fig. 17.

Fig. 21 is a diagram showing an instruction sequence SQ12 of the second and third storage procedures. When the processor 230 is in the initial state (or after data is written or after data is erased), the processor outputs a command "c 51" for executing reading of the management information MI from the management information storage area MIA in the SLC mode. Following the command "c 51", the processor 230 outputs commands "c 53" and "c 31" to the input/output signal I/O. The instruction "c 53" is an instruction indicating that the management information MI to be read out and stored in the data latch group SDL is copied to the data latch group ADL instead of being copied to the data latch group XDL. Following the command "c 31", the controller 200 outputs 5 addresses to the input-output signal I/O. Following the 5 addresses, the controller 200 outputs a command "c 32" to the input-output signal I/O.

Since the command "c 32" is a command for reading data from the designated address, the sequencer 170 reads data from the designated address and stores the read data in the data latch group ADL.

As described above, the management information MI is stored in the plurality of readout units SAU in the steady state shown by SS12 in fig. 18.

Further, as indicated by the broken line in fig. 21, the processor 230 outputs an instruction "c 54" for copying the data of the data latch group ADL of the plurality of sense amplifiers SA to the data latch group XDL to the input/output signal I/O, thereby storing the management information MI in the plurality of sense cells SAU in a stable state indicated by SS13 in fig. 18.

Fig. 22 is a diagram showing an instruction sequence SQ13 of the fourth storage procedure. When the processor 230 is in the initial state (or after data is written or after data is erased), the processor outputs a command "c 51" for executing reading of the management information MI from the management information storage area MIA in the SLC mode. Following the command "c 51", the processor 230 outputs commands "c 55" and "c 31" to the input/output signal I/O. The instruction "c 55" is an instruction to copy the management information MI read out and stored in the data latch group SDL to the data latch group XDL and the data latch group ADL. Following the command "c 31", the controller 200 outputs 5 addresses to the input-output signal I/O. Following the 5 addresses, the controller 200 outputs a command "c 32" to the input-output signal I/O.

Since the instruction "c 32" executes the instruction to read data from the designated address, the sequencer 170 reads data from the designated address and stores the read data in the data latch groups ADL and XDL.

As described above, the management information MI is stored in the plurality of readout units SAU in the steady state shown by SS22 of fig. 19.

Next, the operation of reading data in the above-described steady state will be described. In the data reading operation, first, the shift amount data included in the management information MI is read.

5) Shift amount data reading and setting

Fig. 23 is a diagram for explaining a case where shift information (here, an index number) as management information MI is read out from the data latch group XDL. Fig. 24 is a diagram showing a command sequence SQ14 in the process of reading data. The index number is read from the data latch group ADL in accordance with the command sequence, and data is read using the shift amount corresponding to the read index number. Here, a case will be described where, in a steady state, as shown in SS31, shift information as management information MI is also stored in advance in the data latch group XDL.

Processor 230 outputs instruction "c 56" as a register read instruction. Following the command "c 56", the controller 200 outputs 5 addresses to the input-output signal I/O. Here, only the column address is specified, and thus 3 row addresses are ignored. Then, the controller 200 outputs a command "c 57" to the input/output signal I/O.

The sequencer 170 reads data of the data latch group XDL at the designated column address, and outputs the read data "info 0". Data "info 0" is an index number corresponding to the shift amount data on the read data. Therefore, as shown in SS32 of fig. 23, the controller 200 can retrieve the index number from the group of data latches XDL.

The processor 230 reads data using the acquired data "info 0". The processor 230 can refer to the shift table information TBL and acquire the shift amount data based on the acquired data "info 0". As described above, the controller 200 copies the management information MI from the data latch group ADL to the data latch group XDL in advance before performing the readout process. Then, the shift amount data is acquired from the data latch group XDL.

As shown in fig. 24, the processor 230 outputs a shift amount setting command "c 41" for setting a shift amount used in readout to be executed later on for the NAND-type flash memory 100 to the input/output signal I/O, and outputs shift amount data to the input/output signal I/O following the shift amount setting command "c 41". In fig. 24, the Shift amount data "Shift a" and "Shift E" and "00" for the lower page are output. The third data is ignored. If the shift amount data is for the middle page, 3 pieces of shift amount data are output, and if the shift amount data is for the upper page, 2 pieces of shift amount data and "00" are output. As a result, the shift amount data is set in the NAND-type flash memory 100.

Fig. 25 is a diagram for explaining a case of reading data from the memory cell array 110.

As shown in fig. 24, the controller 200 outputs a command "c 11", "c 12", or "c 13" for making a read reservation of any one of the lower bit, the middle bit, and the upper bit corresponding to the read data to the input/output signal I/O. In fig. 24, following the command "c 11", the controller 200 outputs the command "c 31" to the input/output signal I/O, followed by the command "c 31", outputting 5 addresses to the input/output signal I/O.

When the controller 200 outputs the instruction "c 32" to the input-output signal I/O, the sequencer 170 performs shift reading using the set shift amount. The data read result is first stored in data latch group SDL, and then stored in data latch group XDL as shown in SS33 of fig. 25. As a result, the controller 200 can acquire user data from the data latch group XDL. In fig. 24, the timing of the long white arrow indicates that the ready/busy signal RBn is low, and the timing of the short arrow indicates that the ready/busy signal RBn is high.

Thereafter, the controller 200 outputs a command "c 54" to the input/output signal I/O as indicated by the one-dot chain line, and all data of the data latch group ADL is copied to the data latch group XDL as indicated by SS34 in fig. 25.

6) Overall flow of read processing

Next, a flow of data reading processing in the memory system 1 of the present embodiment will be described.

Fig. 26 is a flowchart showing an example of the flow of the process of reading data between the controller 200 and the NAND-type flash memory 100. In fig. 26, the same processes as those in fig. 14 are denoted by the same step numbers, and the description thereof is simplified. Fig. 26 shows a reading process of data for each page. The controller 200, upon receiving a read request from the host device 300, determines a read target address (i.e., a physical address) using the lookup table LUT in the RAM220 (S1).

When the physical address is specified, the controller 200 refers to the above-described correspondence table CT, and outputs an instruction to output data of the data latch group XDL in which a column address of a history value (here, an index number) which is shift information of a target address in the history data HD is registered (S11). In accordance with this instruction, the NAND-type flash memory 100 executes a process of returning data (i.e., an index number) of the data latch group XDL of the designated column address to the controller 200 (S12). The processing of S11 and S12 is shown in fig. 24.

The controller 200 outputs a read command to the NAND-type flash memory 100 based on the specified physical address and the shift amount data corresponding to the acquired index number (S3).

When receiving the read command from the controller 200, the NAND-type flash memory 100 executes reading of data based on the read command (S4). When the index number at the time of the last readout is not stored in the history data HD, that is, the index number is 0, normal reading is performed. When the index number at the time of the last readout is stored in the history data HD, shift reading using the shift amount corresponding to the index number is performed.

Since data is read in units of pages, the result of data reading, as shown in SS33 in fig. 25, is stored in the data latch group XDL for 1 page.

The read result is obtained by the controller 200. The controller 200 determines whether or not data can be read, that is, whether or not error correction can be performed by the ECC circuit 260 even if there is an error (S5).

When the readout of the data is enabled (S5: YES), the controller 200 returns the read data to the host device 300 (S6).

Since the management information MI of the data latch group XDL is erased by reading the data, when the data can be read (S5: yes), the controller 200 outputs a command for copying the data of the data latch group ADL to the data latch group XDL to the input/output signal I/O as shown by a dotted line in fig. 26 in order to set the data to a stable state (S13). As a result, sequencer 170 copies the data of data latch group ADL to data latch group XDL, as shown in SS34 of fig. 25 (S14).

When the data cannot be read (no in S5), the controller 200 executes the above-described re-reading process (S7).

In S7, the above-described re-read processing is performed while shift reading or the like is performed, and the controller 200 determines whether error correction has succeeded, that is, whether data can be read (S8). When the error correction is successful, that is, the data can be read (S8: YES), the controller 200 returns the error-corrected data to the host device 300 (S6).

Further, when the error correction is successful, that is, when data can be read (S8: YES), the controller 200 outputs a command "c 54" for copying the data of the data latch group ADL to the data latch group XDL to the input/output signal I/O as shown by a dotted line in FIG. 26 so that the data latch groups ADL and XDL are in a stable state (S15). As a result, the sequencer 170 copies the data of the data latch group ADL to the data latch group XDL (S16).

Further, after S15, the controller 200 outputs an instruction to rewrite and update the index number corresponding to the shift amount data when re-read is possible to the column address corresponding to the target address (S17). As a result, the sequencer 170 updates the data of the designated column address in the data latch group XDL with the index number of the shift amount data at the time of re-reading (S18).

Further, after S17, the controller 200 outputs an instruction to copy data of the data latch group XDL to the data latch group ADL (S19). As a result, the sequencer 170 copies the data of the data latch group XDL to the data latch group ADL (S20).

As described above, in the case where the error correction is successful in S5 and S8 (S5, S8: YES), the controller 200 can return the error-corrected user data to the host device 300 (S6).

When the error correction is successful in S8 (yes in S8), the controller 200 updates the data latch group ADL, and performs a process of writing updated shift information (here, the index number of the shift amount data) into the management information storage area MIA of the memory cell array 110 in addition to setting the data latch groups ADL and XDL to a stable state.

That is, when the management information MI is updated by the re-reading process, the controller 200 stores the updated management information MI in the NAND-type flash memory 100. Fig. 27 is a flowchart showing an example of the flow of processing for writing updated shift information into the management information storage area MIA.

The controller 200 determines whether or not it is necessary to write the updated shift information to the management information storage area MIA of the memory cell array 110, in other words, whether or not the error correction is successful in S8 (S21). The controller 200 does not perform any processing when it is not necessary to write the updated shift information to the management information storage area MIA of the memory cell array 110 (S21: no).

When it is necessary to write the updated shift information to the management information storage area MIA of the memory cell array 110 (S21: yes), the controller 200 writes the updated shift information (here, the index number corresponding to the shift amount data) to the management information storage area MIA of the memory cell array 110 in the SLC mode (S22). That is, the updated shift information is stored in the memory cell array 110 as the nonvolatile memory.

Therefore, the controller 200 does not write the updated shift information to the memory cell array 110 as the nonvolatile memory when the error subscription is completed in S5, but writes the updated shift information to the memory cell array 110 as the nonvolatile memory when the error subscription is completed in S8.

Returning to fig. 26, if the error correction is unsuccessful, i.e., the readout of the data cannot be performed (S8: no), the controller 200 returns a read status error indicating that the readout cannot be performed to the host apparatus 300 (S10).

Fig. 28 and 29 are diagrams for explaining changes in the storage status of data in the memory cell array and the 5 data latch groups in the data reading processing of fig. 26 and the writing processing of the updated management information in the nonvolatile memory of fig. 27.

SS41 in fig. 28 shows a state where data of the data latch group ADL is copied to the data latch group XDL by S14 and S16 in fig. 26.

SS42 in fig. 28 shows a state where the data of the designated column address in the data latch group XDL is updated with the index number of the shift amount data at which the data can be read again in S18 in fig. 26.

SS43 of fig. 29 represents a state in which data of the data latch group XDL is copied to the data latch group ADL by S20 of fig. 26.

SS44 in fig. 29 shows a state where the index number of the updated shift amount data is stored in another address in memory cell array 110 as the nonvolatile memory in S21 in fig. 27.

Fig. 30 is a diagram showing an instruction sequence for update processing of data of a specified column address in the data latch group XDL in SS42 of fig. 28.

The instruction "c 61" is an instruction for specifying a column address to be updated in the data latch group XDL and performing data update. Following the instruction "c 61," the column address is specified by 2 column addresses. The row address is ignored because only the data is written to the plurality of data latches XDL for the specified column address. The following data "info" is update data. Data "info" is output, and the processing is ended at the timing indicated by the white arrow. By the instruction "c 52", as shown in S43 of fig. 29, the data of the data latch group XDL is copied to the data latch group ADL.

Fig. 31 is a diagram showing a command sequence for writing management information MI to memory cell array 110 in SS44 of fig. 29.

The instruction "c 51" specifying SLC mode is an instruction specifying that the write mode is SLC. Next at instruction "c 61," a column address and a row address are specified. Instruction "c 61" is an instruction for data that will correspond to the specified column address in the data latch group XDL. When the instruction "c 23" is output, the sequencer 170 writes the data of the data latch group XDL into the management information storage area MIA specified by the address. As a result, as shown in S44 of fig. 29, the updated shift information is stored in the memory cell array 110.

As described above, the shift amount data is updated.

Next, an operation at the time of suspending reading in the present embodiment will be described.

Fig. 32 is a diagram showing a command sequence showing a change in the input/output signal I/O of the controller 200 when the reading is suspended. Fig. 33 is a diagram for explaining a change in the storage status of data in a plurality of data latch groups with execution of an instruction sequence.

As shown in the command sequence SQ17, when the read is suspended, the controller 200 outputs a predetermined command "c 41" to suspend the programming, i.e., the writing of data. In fig. 33, LS31 indicates that data for writing is stored in the data latch groups ADL, BDL, and CDL and that verification voltage data is stored in the data latch group SDL among the plurality of data latch groups during programming. LS32 represents the state of multiple groups of data latches in programming while suspended. In LS32, no valid data is stored in the groups of data latches SDL and XDL. That is, since the programming, that is, the data writing, has been performed so far, the management information MI is not stored in any data latch group. Therefore, when the suspended reading is performed, it is necessary to acquire the management information MI for reading out the data. In fig. 32, the timing of the long white arrow indicates that the ready/busy signal RBn is low (low), and the timing of the short arrow indicates that the ready/busy signal RBn is high (high).

Therefore, the controller 200 then outputs the instructions "c 51" and "c 31" for performing readout of the management information MI in the SLC mode. Following the instruction, the controller 200 outputs 5 addresses and an instruction "c 32" following the address to the input-output signal I/O. By the instruction "c 32", the management information MI is stored in the data latch group XDL after being stored in the data latch group SDL.

LS33 in fig. 33 indicates a state in which the management information MI read out in SLC mode is stored in the data latch group SDL, and LS34 indicates a state in which the management information MI is stored in the data latch group XDL.

Further, by an instruction "c 32", reading of data of a designated column address in the data latch group XDL is performed. The sequencer 170 reads data at the designated column address, and outputs the read data "info 0".

The processor 230 reads data using the acquired data "info 0". LS35 in fig. 33 indicates a state in which the index number of the shift amount data of the column address specified in the management information MI is read from the corresponding data latch group XDL.

The processor 230 outputs a shift amount setting command "c 41" for setting a shift amount to the input/output signal I/O, and then outputs shift amount data selected based on the index number to the input/output signal I/O following the shift amount setting command "c 41".

Then, the processor 230 outputs the command "c 11", "c 12", or "c 13" and "c 31" for making a read reservation of any one of the lower bit, the middle bit and the upper bit to the input/output signal I/O, and then outputs the address and the command "c 32". As a result, the processor 230 can read data. LS36 of fig. 33 represents a state when the processor 230 performs readout of data.

At the end of the suspended reading, the processor 230 outputs a program resume instruction "c 42".

Therefore, even when the reading is suspended, the shift information as the management information MI can be read out from the management information storage area MIA of the memory cell array 110, and the shift reading can be performed.

When there is a change based on the newly read shift information while the reading is suspended, the changed shift information (here, the index number) is written into the management information storage area MIA.

As described above, since a part of the management information MI is stored in the data latch group ADL which is not used at the time of reading, even if the management information MI increases when the capacity of the RAM of the controller 200 is limited, the management information MI can be used at high speed.

As described above, if the storage capacity of the memory cell transistor MT increases, for example, if the number of bits that can be stored in 1 memory cell transistor MT increases from 3 bits to 4 bits, the shift amount data also increases, and the shift amount data may not be stored in the RAM220 of the controller 200.

According to the NAND-type flash memory 100, data may be mostly read after data is temporarily written. The data latch groups ADL and BDL used for writing data are not used at the time of or before reading data.

In such a case, according to the above-described embodiment, even if the data amount of the history data HD, which is the shift information of the management information MI, increases, by storing the history data HD in the data latch group ADL, the RAM220 of the controller 200 may not be used.

In the above-described embodiment, the history data HD as the shift amount data of the management information is stored in the data latch group ADL, but may be stored in another data latch, for example, the data latch group BDL or CDL.

In the above-described embodiment, the shift information used in the shift reading is given as an example of the management information MI stored in the data latch group ADL or the like, but management information MI other than the shift information may be stored in the data latch group ADL or the like.

As described above, according to the above-described embodiments, it is possible to provide a memory system and a memory controller that can read out management information with a small latency even in a memory controller that does not have a RAM area sufficiently storing the management information.

Further, since a part of the management information is stored in the data latch group that is not used at the time of reading data, the memory controller 200 can read the management information MI with a small latency as long as the read request from the host device 300 continues.

(second embodiment)

In the first embodiment, the management information MI such as the shift information can be stored in 1 data latch group ADL of the NAND flash memory 100, that is, 1 page, but in the second embodiment, even when the necessary management information MI exceeds 1 page, the management information MI is stored in 2 or more data latch groups using the data latch group BDL other than the data latch group ADL.

Since the configuration of the memory system according to the second embodiment is the same as that of the memory system according to the first embodiment, the same reference numerals are used for the same components as those of the memory system according to the first embodiment in the memory system according to the second embodiment, and the description thereof is omitted, and only the configuration different from that of the memory system according to the first embodiment will be described.

Fig. 34 is a diagram showing the data storage states of the management information storage area MIA and the plurality of data latch groups at the time of power-off or the like in the present embodiment.

Fig. 34 shows the data storage states of the management information storage area MIA and the plurality of data latch groups when the power is off, after data writing (programming), or after data erasing. Management information of the corresponding physical block is stored in each of the data latch groups ADL, BDL, and CDL.

Specifically, here, the memory cell array 110 has 3000 blocks BLK. Shift information as data of the management information MI of the blocks 0 to 999 is stored in a first storage area MIA0 of the management information storage area MIA. Shift information of the data of blocks 1000 to 1999 is stored in the second storage area MIA1 of the management information storage area MIA. The shift information of the data of the blocks 2000 to 2999 is stored in the third storage area MIA2 of the management information storage area MIA.

In the present embodiment, each sense unit SAU includes data latches ADL, BDL, CDL, and XDL.

Fig. 35 shows the storage state of the management information MI in the memory cell array 110 and the plurality of data latch groups in the steady state according to the present embodiment.

When the power is turned on, after data is written (programmed), or after data is erased, the controller 200 outputs the various commands described in the first embodiment to the NAND-type flash memory 100, thereby bringing the plurality of data latch groups into a stable state in which a part of the management information MI is stored.

In a steady state, the management information MI stored in the first storage area MIA0 is copied to the data latch group ADL, the management information MI stored in the second storage area MIA1 is copied to the data latch group BDL, and the management information MI stored in the third storage area MIA2 is copied to the data latch group CDL.

By setting the plurality of data latches to a stable state, data reading can be handled.

When the target address of the read data is known, the management information MI is copied to the data latch group XDL from the data latch group storing the copy of the management information MI of the block BLK associated with the target address.

For example, when a request for reading data in blocks BLK0 to 999 is received, the controller 200 can store data in the storage area of the data latch group ADL in the data latch group XDL, and read the data using the shift information on the block BLK specified by the object address in the data latch group XDL.

The process of making the plurality of data latches stable will be briefly described.

Fig. 36 is a diagram for explaining data transfer in the case where the management information MI is read and stored in the data latch group XDL. As shown in SS41, the management information MI of the management information storage area MIA is read out in SLC mode and stored in the data latch group XDL via the data latch group SDL.

Fig. 37 is a diagram showing a method of copying the management information MI read out in SLC mode from the data latch group XDL to any of the data latch groups ADL to CDL, and stably state-changing a plurality of data latch groups. SS42 indicates a case where the management information MI read out in SLC mode is copied from the data latch group XDL to the data latch group ADL. That is, the management information MI is changed from the state of the SS41 to the state of the SS 42. S43 represents a case where the management information MI read out in SLC mode is copied from the data latch group XDL to the data latch group BDL. That is, the management information MI is changed from the state of the SS41 to the state of the SS 43. S44 shows a case where the management information MI read out in SLC mode is copied from the data latch group XDL to the data latch group CDL. That is, the management information MI is changed from the state of the SS41 to the state of the SS 44.

Fig. 38 is a diagram showing another method of copying the management information MI stored in the data latch groups ADL, BDL, and CDL to the data latch group XDL and stably state-changing the plurality of data latch groups. SS45 represents a case where the management information MI is copied from the data latch group ADL to the data latch group XDL. SS46 represents a case where management information MI is copied from the data latch group BDL to the data latch group XDL. SS47 represents a case where management information MI is copied from the data latch group CDL to the data latch group XDL.

In fig. 37, the management information MI is stored in the data latch group XDL and then copied to any of the data latch groups ADL, BDL, and CDL, but the management information MI may be directly copied to any of the data latch groups ADL, BDL, and CDL via the data latch group SDL.

Fig. 39 is a diagram showing a case where the management information MI is transferred to any one of the data latch groups ADL, BDL, and CDL via the data latch group SDL. SS48 represents a case where the management information MI is directly copied from the data latch group SDL to the data latch group ADL. SS49 represents a case where management information MI is copied directly from the data latch group SDL to the data latch group BDL. SS50 represents a case where the management information MI is directly copied from the data latch group SDL to the data latch group CDL.

Further, the management information MI may be copied from any one of the data latch groups ADL, BDL, and CDL shown in fig. 39 to the data latch group XDL, and stored in the data latch group XDL as shown in fig. 38.

Fig. 40 is a diagram showing an instruction sequence SQ18 for stably state-converting a plurality of data latch groups according to the present embodiment. Fig. 41 is a diagram for explaining a change in the storage state of the management information MI until the management information MI is stored in the plurality of data latch groups.

As shown in fig. 40, the processor 230 outputs an instruction "c 51" for executing readout of the management information MI from the management information storage area MIA in SLC mode. Following the command "c 51", the processor 230 outputs a command "c 53" and a command "c 31" to the input/output signal I/O. Following the command "c 31", the controller 200 outputs 5 addresses to the input-output signal I/O. 3 row addresses out of the 5 addresses represent addresses of data "info 0". Following the 5 addresses, the controller 200 outputs a command "c 32" to the input-output signal I/O. Through the above, as shown in SS51 of fig. 41, the management information MI of the first storage area MIA0 is transferred to the data latch group ADL.

Thereafter, in order to transfer the management information MI of the second storage area MIA1 to the data latch group BDL, the processor 230 outputs an instruction "c 51" for executing readout of the management information MI from the management information storage area MIA in the SLC mode and an instruction "c 71" and an instruction "c 31" following the instruction "c 51" to the input-output signal I/O. The instruction "c 71" is an instruction that designates the transfer destination of the management information MI as the data latch group BDL instead of the data latch group XDL. By outputting the instruction "c 51" before the instruction "c 71", the transfer destination of the management information MI becomes the data latch group BDL. Following the command "c 31", the controller 200 outputs 5 addresses to the input-output signal I/O. 3 row addresses out of the 5 addresses represent addresses of data "info 1". Following the 5 addresses, the controller 200 outputs a command "c 32" to the input-output signal I/O. Through the above, as shown in SS52 of fig. 41, the management information MI of the second storage region MIA1 is transferred to the data latch group BDL.

Thereafter, the command and data for transferring the management information MI of the third memory area MIA2 to the data latch group CDL are output to the input/output signal I/O. The processor 230 outputs to the input-output signal I/O an instruction "c 51" for executing reading out the management information MI from the management information storage area MIA in SLC mode and an instruction "c 72" and an instruction "c 31" following the instruction "c 51". The instruction "c 72" is an instruction to set the transfer destination of the management information MI to the data latch group CDL instead of the data latch group XDL. By outputting the instruction "c 51" before the instruction "c 72", the transfer destination of the management information MI becomes the data latch group CDL. Following the command "c 31", the controller 200 outputs 5 addresses to the input-output signal I/O. 3 row addresses out of the 5 addresses represent addresses of data "info 1". Following the 5 addresses, the controller 200 outputs a command "c 32" to the input-output signal I/O. By the above, as shown in SS53 of fig. 41, the management information MI of the third storage area MIA2 is transferred to the data latch group CDL.

Fig. 42 is a diagram showing another instruction sequence SQ19 for stably state-converting a plurality of data latch groups according to the present embodiment. Fig. 43 is a diagram for explaining a change in the storage state of the management information MI until the management information MI is stored in the plurality of data latch groups.

As shown in fig. 42, the processor 230 outputs an instruction "c 51" for executing readout of the management information MI from the management information storage area MIA in SLC mode. Following the command "c 51", the processor 230 outputs a command "c 53" and a command "c 31" to the input/output signal I/O. Following the command "c 31", the controller 200 outputs 5 addresses to the input-output signal I/O. 3 row addresses out of the 5 addresses represent addresses of data "info 0". Following the 5 addresses, the controller 200 outputs a command "c 32" to the input-output signal I/O. By the above, as shown in SS54 of fig. 43, the management information MI of the first storage area MIA0 is transferred to the data latch group ADL via the data latch group SDL.

In addition, in fig. 43, data of the data latch group ADL is copied to the data latch group XDL. Therefore, after the information MI is transferred to the data latch group ADL, an instruction "c 54" to copy the data of the data latch group ADL to the data latch group XDL is output to the input/output signal I/O.

Thereafter, in order to transfer the management information MI of the second storage area MIA1 to the data latch group BDL, the processor 230 outputs an instruction "c 51" for executing readout of the management information MI from the management information storage area MIA in the SLC mode and an instruction "c 71" and an instruction "c 31" following the instruction "c 51" to the input-output signal I/O. Following the command "c 31", the controller 200 outputs 5 addresses to the input-output signal I/O. 3 row addresses out of the 5 addresses represent addresses of data "info 1". Following the 5 addresses, the controller 200 outputs a command "c 32" to the input-output signal I/O. Through the above, as shown in SS55 of fig. 43, the management information MI of the second storage region MIA1 is transferred to the data latch group BDL.

Thereafter, the command and data for transferring the management information MI of the third memory area MIA2 to the data latch group CDL are output to the input/output signal I/O. The processor 230 outputs to the input-output signal I/O an instruction "c 51" for executing reading out the management information MI from the management information storage area MIA in SLC mode and an instruction "c 72" and an instruction "c 31" following the instruction "c 51". 0 then instructs "c 31" that controller 20 outputs 5 addresses to the input-output signal I/O. 3 row addresses out of the 5 addresses represent addresses of data "info 2". Following the 5 addresses, the controller 200 outputs a command "c 32" to the input-output signal I/O. As described above, as shown in SS56 of fig. 43, the management information MI of the third storage area MIA2 is transferred to the data latch group CDL.

Next, a sequence of management information for reading data is acquired from the stable state of the plurality of data latch groups. Here, a case will be described, as an example, where the selected block BLK belongs to the blocks 1000 to BLK1999, and the management information MI is read out for the selected block BLK.

Fig. 44 is a diagram showing a command sequence for reading out the management information MI from the steady state. Fig. 45 is a diagram for explaining a change in the storage status of data in the memory cell array and the 5 data latch groups in the read-out process of the management information MI.

As shown in fig. 44, in the instruction sequence SQ20, first, an instruction "c 73" for copying data of the data latch group BDL to the data latch group XDL is output, and as shown in SS57 to SS58 of fig. 45, data is copied from the data latch group BDL to the data latch group XDL.

Thereafter, the controller 200 outputs the command "c 56" and 5 addresses, outputting the command "c 57" to the input/output signal I/O. The sequencer 170 reads data of the data latch group XDL at the designated column address, and can output the read data "info" as shown by SS59 in fig. 45.

Then, the controller 200 performs a readout sequence of data using the readout data (shift information), thereby enabling readout of data.

Next, the update of the management information MI and the write processing of the management information MI to the memory cell array 110 will be described.

Fig. 46 is a diagram showing a command sequence of the update process of the management information MI in the steady state. Fig. 47 is a diagram for explaining a change in the storage status of data in the memory cell array and the 5 data latch groups in the update process of the management information MI. Here, updating of the management information MI of the data latch group BDL will be described.

In the update-processed instruction sequence SQ21, an instruction "c 73" is initially output, and data is copied from the data latch group BDL to the data latch group XDL as shown in SS61 to SS62 in fig. 47.

Thereafter, when the controller 200 outputs the instruction "c 61" for updating the data of the designated column address in the data latch group XDL and 5 addresses to the input/output signal I/O, a part of the data latch group XDL is updated as shown in SS63 of fig. 47.

The controller 200 executes the instruction shown in fig. 31 after the instruction sequence SQ21 shown in fig. 46, thereby storing the update data in the memory cell array 110.

Fig. 48 is a diagram for explaining a change in the storage status of data in writing of update data to the memory cell array 110. As shown in FIG. 48, the data in the memory cell array and the group of 5 data latches changes from SS64 to the state of SS 65.

Next, when the management information MI for 3 pages is stored in the data latch groups ADL, BDL, and CDL, a data reading operation will be described.

When it is determined which block BLK the read request from the host device 300 corresponds to, the controller 200 transfers the management information MI of the block BLK related to the read request to the data latch group XDL, acquires the management information MI from the data latch group XDL, and outputs the read command using the acquired management information MI.

Fig. 49 is a diagram for explaining selection of shift information as management information MI used when reading data. Fig. 50 is a diagram showing states of 5 data latch groups when data is read.

In a steady state, since the shift amount data of the read data does not exist in the data latch group XDL, the management information MI is copied from the data latch group in which the management information MI (e.g., shift information) related to the read data is stored to the storage area of the data latch group XDL after receiving the read request from the host apparatus 300.

For example, after determining that the data of the m-th word line WLm of the block BLKn in the blocks BLK0 to 999 is read, the controller 200 copies the data of the data latch group ADL storing the management information MI corresponding to the block BLKn in the blocks BLK0 to 999 to the data latch group XDL, and reads the shift information corresponding to the word line WLm of the block BLKn in the data area of the data latch group XDL. Using the read shift information, the controller 200 can perform reading of data.

As shown in fig. 50, when data is read, the data latch group XDL is used for storing read data. The user data of word line WLm of block BLKn is copied to the data area of data latch group XDL after being forwarded to data latch group SDL, and controller 200 can read data from the data area of data latch group XDL.

In addition, the management information MI may be transferred to the data latch group XDL not after receiving a read request from the host device 300, but the management information MI may be placed in the data latch group XDL from any one of the data latch groups ADL, BDL, and CDL.

In this case, 1 out of 3 of the data latch groups ADL, BDL, CDL is copied to the data latch group XDL, and therefore, the shift information of the read data exists in the data latch group XDL with a probability of 1 divided by 3.

Fig. 51 is a flowchart showing an example of the flow of the process of reading data between the controller 200 and the NAND-type flash memory 100. In fig. 51, the same processes as those in fig. 14 and 26 are denoted by the same step numbers for simplification of description.

After determining the target address related to the read request from the host device 300 (S1), the controller 200 determines the data latch group in which the shift information that is the history value of the target address is registered, and outputs an instruction to copy the data of the determined data latch group to the data latch group XDL (S21).

If a history value related to the object address with respect to the read instruction has already been stored in the data latch group XDL, the process is skipped. However, when the history value related to the target address of the read instruction is not stored in the data latch group XDL, the process of S21 is executed. As a result of execution of S21, in the NAND-type flash memory 100, data is copied to the data latch group XDL from the plurality of data latch groups in which the shift information that is the history value of the object address is registered (S22).

After execution of S21 or after skipping S21, the controller 200 outputs an instruction to output data of the data latch group XDL in which the column address of the history value (here, the index number) which is the shift information of the object address in the history data HD is registered (S11). In accordance with this instruction, the NAND-type flash memory 100 executes a process of returning data (i.e., an index number) of the data latch group XDL of the designated column address to the controller 200 (S12).

The controller 200 outputs a read command to the NAND-type flash memory 100 based on the specified physical address and the shift amount data corresponding to the acquired index number (S3). When receiving the read command from the controller 200, the NAND-type flash memory 100 executes reading of data based on the read command (S4).

The read result is obtained by the controller 200. The controller 200 determines whether or not data can be read, that is, whether or not error correction can be performed by the ECC circuit 260 even if there is an error (S5).

When the readout of the data is enabled (S5: YES), the controller 200 returns the read data to the host device 300 (S6).

When the data cannot be read (S5: no), the controller 200 executes the above-described re-reading process (S7).

In S7, the above-described re-read processing is performed while shift reading or the like is performed, and the controller 200 determines whether error correction has succeeded, that is, whether data can be read (S8). When the error correction is successful, that is, the data can be read (S8: YES), the controller 200 returns the error-corrected data to the host device 300 (S6).

Further, after the re-reading process (S7), when the error correction is successful, that is, when the data can be read (S8: YES), the controller 200 outputs to the input/output signal I/O a command for copying the data of the data latch group in which the shift information, which is the history value of the object address, is registered to the data latch group XDL (S25). As a result, sequencer 170 copies the data of the data latch group in which the shift information, which is the history value of the target address, is registered to the data latch group XDL (S26).

Further, after S25, the controller 200 outputs an instruction to rewrite and update the index number corresponding to the shift amount data at the time of being readably readable to the column address corresponding to the target address (S17). As a result, the sequencer 170 updates the data of the designated column address in the data latch group XDL with the index number of the shift amount data when the data can be read again (S18).

Further, after S17, the controller 200 outputs an instruction to copy the updated data of the data latch group XDL to the data latch group in which the shift information that is the history value of the target address is registered (S27). As a result, the sequencer 170 copies the data of the data latch group in which the shift amount, which is the history value of the object address, is registered, from the data latch group XDL (S28).

[ patrol treatment ]

In the NAND-type flash memory 100, in order to cope with the deterioration of the stored data with the passage of time, a polling process of reading the stored data and checking, that is, verifying, the storage state of the read data is executed. As a result of the polling process, the read level, that is, the shift information is updated. That is, when the patrol processing for verifying the storage state of the data is performed on the memory cell array 110, the controller 200 stores the management information, here, the shift information, which is updated as a result of the patrol processing, in the memory cell array 110.

Fig. 52 is a flowchart showing an example of the flow of the patrol processing. The patrol processing is executed under a predetermined condition at a predetermined cycle. Here, the patrol processing is performed for each predetermined target area (hereinafter, patrol target area) of the block BLK. The controller 200 selects a block BLK to be subjected to the patrol processing, selects a patrol target area within the block BLK, and performs the patrol processing.

The controller 200 first sets an index j of the patrol target area of the patrol target block BLKi for the patrol process (S31).

The controller 200 sets the target address addr of the inspection target area of the index j (S32), and executes predetermined processing when reading the target address addr (S33). S32 and S33 are repeated to execute the prescribed processing on all the object blocks within the object block BLK in S33.

When the reading process to the patrol target area set in S31 ends, the index j of the patrol target area of block i is incremented by 1.

The controller 200 executes each polling process for a plurality of polling target areas in each block BLK at a predetermined timing.

Fig. 53 is a flowchart showing an example of a flow of predetermined processing in the case of reading out the target address in the patrol processing.

The controller 200 reads the data of the target address with the shift amount of the index number of the table corresponding to the number of times of erasing of the block i, that is, performs shift reading (S35).

The controller 200 determines whether the ECC-based error correction is successful (S36). When the error correction is successful (S36: YES), the process does not perform any processing. If the error correction is unsuccessful (NO in S36), it is determined whether the index number of the table is smaller than the last number (S37).

When the index number of the above table is smaller than the last number (S37: yes), the controller 200 increments the index number of the page (S38), the process returns to S35, and the processes of S35 and S36 are repeated.

When the index number of the table is not less than the last number (S37: NO), the controller 200 performs other processing such as tracking processing (S39).

Fig. 54 to 57 are diagrams for explaining changes in the states of the memory cell array 110 and the plurality of data latch groups when the patrol processing is performed.

Fig. 54 is a diagram showing a storage state of data in the management information storage area MIA and the plurality of data latch groups in an idle state. In the idle state, neither writing nor reading is performed.

Fig. 55 and 56 are diagrams for explaining changes in the storage status of data in the 5 data latch groups when the patrol processing is executed.

To perform the patrol process on the data of blocks BLK 0-BLK 999, controller 200 copies the data of the storage area of data latch group ADL to the storage area of data latch group XDL. Then, as shown in SS61 of fig. 55, the verification of the storage state of data is performed using the shift information of the data latch group XDL. As shown in SS62 in fig. 55, since data is read, data in the memory region of the data latch group XDL is used for reading.

When the controller 200 determines that the update of the shift information is necessary based on the check result at the end of the check, the data of the data latch group ADL is copied to the data latch group XDL as shown in SS63 of fig. 55.

The controller 200 changes the shift information (e.g., index number) in the group of data latches XDL. SS64 in fig. 56 indicates a state in which data of a part of the data latch group XDL is rewritten. As shown in SS65 of fig. 56, controller 200 copies data in data latch group XDL to data latch group ADL.

By repeating the above-described processing, when the patrol processing is performed on the data of the blocks BLK0 to BLK999, the data in the data latch group XDL is copied to the data latch group ADL as shown in SS 66.

Fig. 57 is a diagram showing the storage states of data in the management information storage area MIA and the plurality of data latch groups concerning the data of blocks BLK0 to BLK 999. From the state of SS66, controller 200 writes management information MI into management information storage area MIA of memory cell array 110. Fig. 57 shows a state in which shift information is updated for 1/4 of the data of blocks BLK0 to BLK999, for example.

In the above example, the update data is stored in the data latch group XDL and then copied to the data latch group ADL, but the update data may be temporarily stored in the RAM220 and transferred from the RAM220 to the data latch group ADL.

Fig. 58 is a block diagram for explaining the configuration of a memory system showing a state in which update data is stored in the middle of the RAM 220. Fig. 59 is a block diagram illustrating a configuration of a memory system showing a state in which the update data is completely stored in the RAM220 and transferred to the data latch group ADL.

As shown in fig. 58, the update data is stored in a part of the area in the RAM 220. As shown in fig. 59, the update data stored in the RAM220 is transferred from the controller 200 to the data latch group ADL of the NAND-type flash memory 100.

As described above, according to the present embodiment, it is possible to provide a memory system and a memory controller capable of reading out more management information MI with a smaller latency while obtaining the same effects as those of the first embodiment.

In particular, when the update data is temporarily stored in the RAM220 and then transferred to the data latch group ADL, even if the programming operation occurs in the middle, the transfer of the update data to the data latch group ADL can be resumed after the end of the programming operation without causing the data in the RAM220 to be saved to the memory cell array 110.

(third embodiment)

In the first and second embodiments, the memory system has 1 NAND-type flash memory 100, but in the third embodiment, the memory system has 2 NAND-type flash memories 100, and 2 pieces of management information MI in 2 memory cell arrays 110 are stored in a plurality of data latch groups in each NAND-type flash memory 100.

Since the configuration of the memory system according to the third embodiment is the same as that of the memory system according to the first embodiment, the same reference numerals are used for the same components as those of the memory system according to the first embodiment in the memory system according to the third embodiment, and the description thereof is omitted, and only the configuration different from that of the memory system according to the first embodiment will be described.

Fig. 60 to 62 are diagrams for explaining a change in the storage state of 2 pieces of management information MI of 2 NAND-type flash memories 100. One of the 2 NAND-type flash memories 100 is chip C0, and the other is chip C1. That is, each of the chips C0 and C1 has a plurality of physical blocks, each of which has a memory cell array 110 as a nonvolatile memory having a memory area accessible in units of pages. The memory system 1A of the present embodiment includes 1 controller 200 and 2 chips C0 and C1. The controller 200 controls reading and writing of data in units of pages to the memories of the chips C0 and C1. The controller 200 may be formed on any one of the 2 chips C0 and C1, or may be formed on another chip.

Fig. 60 shows the storage state of 2 pieces of management information MI of 2 NAND-type flash memories 100. Fig. 61 shows the storage state of 2 pieces of management information MI of 2 NAND-type flash memories 100 when the chip C0 is under programming. Each of the chips C0 and C1 includes a plurality of data latch groups SDL, ADL, BDL, CDL, and XDL.

In the management information storage area MIAC0 of the memory cell array 110 of the chip C0, management information MI of both the chip C0 and the chip C1 is stored. Similarly, the management information MI of both the chip C0 and the chip C1 is stored in the management information storage area MIAC1 of the memory cell array 110 of the chip C1.

As shown in SS71 of fig. 60, in the chip C0, the management information MI of the chip C0 is stored in the half of the data latch group ADL and the data latch group BDL, and the management information MI of the chip C1 is stored in the half of the data latch group BDL and the data latch group CDL.

Similarly, as shown in SS72 of fig. 60, in the chip C1, the management information MI of the chip C0 is stored in the data latch group ADL and the half of the data latch group BDL, and the management information MI of the chip C1 is stored in the data latch group CDL and the half of the data latch group BDL.

That is, the controller 200 executes the stabilization processing of the data latch groups ADL, BDL, and CDL for storing the management information MI (for example, the history data HD) used for reading data in both the chips C0 and C1 during or before the execution of the data reading processing from the memory cell arrays 110 of the chips C0 and C1.

In such a configuration, when data is written to one chip C0, that is, when programming is performed, the controller 200 may receive a data read request for the chip C0.

In this case, as shown in SS73 of fig. 61, the data latch groups ADL, BDL, and CDL of the chip C0 are used for writing data, but as shown in SS74, the data latch groups ADL, BDL, and CDL of the chip C1 are not used for writing data, and the management information MI of the chip C0 and the chip C1 is stored.

Therefore, when data is written into the chip C0 and data is read from the chip C0, as shown in SS76 of fig. 62, the management information MI stored in part of the data latch groups ADL and BDL of the chip C1, here, the shift information, can be copied to the data latch group XDL and read from the data latch group XDL based on the column address corresponding to the read address. In SS76 of fig. 62, since the shift information corresponding to the read address is stored in the data latch group ADL, the data of the data latch group ADL is copied to the data latch group XDL.

That is, when the controller 200 executes the read processing of data from the memory cell array 110 of the chip C0 in the middle of the write processing of data to the memory cell array 110 of the chip C0, the management information MI is read from the data latch groups ADL and BDL of the chip C1, and the read processing of data from the chip C0 is executed using the read management information MI.

Therefore, by storing the management information MI of each other in the plurality of data latch groups by 2 chips, the controller 200 can acquire the management information MI, which is here shift information, from the plurality of data latch groups of another chip and read data using the shift information without executing a command sequence for reading the management information MI from the management information storage area MIA in the memory cell array 110 when the reading process is suspended as shown in fig. 32. That is, since the management information is stored in a distributed manner between chips, it is not necessary to read the management information MI in the SLC mode during the suspension of writing.

Fig. 63 is a diagram showing a command sequence SQ31 in the process of reading data. When the chip C0 is programmed and the management information MI is not stored in the data latch group of the chip C0, the controller 200 outputs a command "C74" for selecting the chip C1 to the input/output signal I/O and selects the chip C1. When the shift information for reading data is located in the data latch group ADL of the chip C1, the following processing is performed: the instruction "c 54" is output to the input-output signal I/O, and all data of the data latch group ADL is copied to the data latch group XDL.

Thereafter, a command "C56" as a register read command is output to the input/output signal I/O, and the head of the designated column address in the data latch group XDL of the chip C1 is designated, and the shift information is read.

After the read shift information is output to the NAND flash memory 100, a data read command is output to read data.

As described above, according to the present embodiment, the same effects as those of the first embodiment can be obtained. Further, in the case of the present embodiment, when there is a read request for a certain chip in a programming operation for the chip, it is not necessary to read the management information MI from the management information storage area MIA in the memory cell array 110 of the chip, and therefore the waiting time can be reduced by the amount of time for reading the management information MI from the management information storage area MIA.

(fourth embodiment)

In the present embodiment, the controller chip and the memory chip are bonded to each other, and the present invention relates to a memory system in which chips are stacked.

Since the configuration of the memory system according to the fourth embodiment includes the same components as those of the memory system according to the first embodiment, the same reference numerals are used for the same components as those of the memory system according to the first embodiment in the memory system according to the fourth embodiment, and the description thereof is omitted, and only the configuration different from that of the memory system according to the first embodiment will be described.

When the circuits of the NAND-type flash memory 100 and the circuits of the controller 200 are formed on 1 substrate, the circuits of the controller 200 are manufactured based on the manufacturing process of the memory cell array 110, and thus the size of the area of the RAM220 may not be increased.

Therefore, in the present embodiment, the chip on which the controller 200 is mounted and the chip on which the memory cell array 110 is mounted are different chips from each other.

Fig. 64 is an assembly diagram for explaining the structure of the memory system 1B of the present embodiment. Here, the chip on which the memory cell array 110 is mounted is stacked on the chip on which the controller 200 is mounted by 1 chip, but a plurality of chips on which the memory cell array 110 is mounted may be stacked on the chip on which the controller 200 is mounted.

The memory system 1B includes a first chip 400 on which a controller and the like are mounted and a second chip 401 on which the memory cell array 110 and the like are mounted, and the first chip 400 and the second chip 401 are bonded to each other.

The first chip 400 is a chip on which the controller 200 including the processor 230, the RAM420, various interface circuits, and the like, and the plurality of readout units SAU are mounted, and these circuits are formed on the first chip 400 as a semiconductor integrated circuit manufactured by a CMOS forming process. That is, the first chip 400 and the second chip 401 are bonded to each other, and include: a controller 200 that controls reading and writing of data in units of pages for a plurality of physical blocks; and a RAM 420. As described later, the RAM420 has a RAM area capable of storing management information MI (e.g., history data HD) used in readout of data at the time of execution or before execution of readout processing of data from the memory cell array 110 of the second chip 401.

On the other hand, the second chip 401 is a chip on which the memory cell array 110, which is a core portion of the NAND-type flash memory, is mounted, and is manufactured by a process for manufacturing the memory cell array 110. That is, the second chip 401 has a plurality of physical blocks, each of which is a semiconductor chip having a nonvolatile memory cell array 110 having a memory region accessible in units of pages. The second chip 401 having the memory cell array 110 is mounted on and bonded to the first chip 400.

As shown in fig. 64, the first chip 400 includes a peripheral circuit region (PERI) in which various circuits such as the controller 200 are formed, an SA/YLOG region in which a plurality of read units SAU and an arithmetic circuit YLOG are formed, and a RAM region in which the RAM220 is formed. Further, a plurality of pads for electrical connection to the second chip 401 are formed in the first chip 400. The plurality of pads include a plurality of pads PD1 for bit lines BL, a plurality of pads PD2 for word lines WL, and a pad PD3 for control signals and the like.

The second chip 401 has a Cell array region (Cell) in which the memory Cell array 110 is formed. In addition, a plurality of pads for electrical connection to the first chip 400 are also formed in the second chip 401. The plurality of pads include a plurality of pads PD1a for bit lines BL, a plurality of pads PD2a for word lines WL, and a pad PD3a for control signals and the like. The plurality of pads of the first chip 400 and the plurality of pads of the second chip 401 are electrically connected, for example, by ball bumps.

The memory system 1A is manufactured by bonding 2 chips such that the plurality of pads of the first chip 400 and the plurality of pads of the second chip 401 are connected to each other via ball bumps. The bonded 2-chip was mounted on another substrate, wire-bonded, and encapsulated with resin.

Conventionally, the controller 200 is also formed on the same substrate as the NAND-type flash memory 100, and therefore the RAM area for the RAM220 cannot be made wide, but according to the configuration of the present embodiment, the RAM area for the RAM220 can be enlarged in the first chip 400 different from the second chip 401, and therefore even if the data amount of the management information MI is increased, the management information MI can be stored in the RAM 220.

Since the management information MI stored in the RAM220 is updated by the patrol process or the like, the management information MI performs the process of storing into the management information storage area MIA of the memory cell array 110 at a predetermined cycle or at a predetermined timing.

Fig. 65 is a flowchart showing an example of the flow of the process of reading data of the second chip 401 by the first chip 400. In fig. 65, the same processes as those in fig. 14, 26, and 36 are denoted by the same step numbers for simplification of description.

After determining the object address relating to the read request from the host device 300 (S1), the controller 200 of the first chip 400 outputs an instruction to output management information MI (e.g., shift information) of the object address from the first chip 400 of the CMOS chip in which the shift information of the object address is registered (S41). That is, a command for reading the shift information data of the target address is output from the RAM220 in which the shift information as the history value of the target address is registered. The RAM220 outputs management information (shift information) of the designated address to the controller 200 (S32).

Thereafter, the data is read out, and after the data is read out again (S7), if the error correction is successful (S8: yes), an update command of the management information MI on the first chip 400 is output (S43). In the RAM220 within the first chip 400, the management information (shift information) of the address specified by the instruction is updated (S44).

As described above, according to the fourth embodiment, since the chip on which the controller 200 is mounted is separated from the chip on which the memory cell array 110 is mounted, a large RAM area can be obtained, and thus a storage area in which a sufficient amount of management information MI is stored can be ensured.

While several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

Description of the reference numerals

1. 1a … memory system, 6 … string, 10 … p type well region, 11, 12, 13 … wiring layer, 14 … conductor, 15 … gate insulating film, 17 … block insulating film, 18 … metal wiring layer, 19 … n⁺Type impurity diffusion layer, 20 … contact plug, 21 … metal wiring layer, 22 … p⁺A type impurity diffusion layer, a 23 … contact plug, a 24 … metal wiring layer, a 100 … NAND type flash memory, a 110 … memory cell array, a 120 … row decoder, a 130 … driver circuit, a 140 … column decoder, a 150 … address register, a 160 … command register, a 170 … sequencer, a 200 … memory controller, a 210 … host interface circuit, a 230 … processor, a 240 … buffer memory, a 250 … NAND interface circuit, a 260 … ECC circuit, a 300 … host device, a 400, a 401 … chip.