Method of manufacturing transistor

文档序号：1940217 发布日期：2021-12-07 浏览：25次中文

阅读说明：本技术 制造晶体管的方法 (Method of manufacturing transistor ) 是由陈玟儒柯忠廷谢宛蓁龙俊名黄泰钧徐志安于 2021-01-26 设计创作，主要内容包括：一种制造晶体管的方法包括在基板上方形成半导体层；蚀刻半导体层的部分以形成第一凹槽及第二凹槽；在半导体层上方形成第一掩膜层；对第一掩膜层执行第一热处理,第一热处理使第一掩膜层致密化；蚀刻第一掩膜层以便暴露第一凹槽；在第一凹槽中形成第一半导体材料；及移除第一掩膜层。(A method of manufacturing a transistor includes forming a semiconductor layer over a substrate; etching part of the semiconductor layer to form a first groove and a second groove; forming a first mask layer over the semiconductor layer; performing first heat treatment on the first mask layer, wherein the first heat treatment enables the first mask layer to be densified; etching the first mask layer to expose the first recess; forming a first semiconductor material in the first groove; and removing the first mask layer.)

1. A method of fabricating a transistor, comprising the steps of:

forming a semiconductor layer over a substrate;

etching a portion of the semiconductor layer to form a first recess and a second recess;

forming a first mask layer over the semiconductor layer;

performing a first heat treatment on the first mask layer, wherein the first heat treatment enables the first mask layer to be densified;

etching the first mask layer to expose the first recess;

forming a first semiconductor material in the first recess;

and removing the first mask layer.

2. The method of claim 1, wherein performing the first thermal process comprises a radiation process.

3. The method of claim 1, wherein performing the first thermal process comprises a plasma process.

4. The method of claim 1, wherein the first thermal treatment crystallizes at least a portion of the first mask layer.

5. The method of claim 1, wherein after the first thermal process, the first mask layer has a rougher upper surface than before the first thermal process.

6. The method of claim 1, further comprising the steps of:

forming a second mask layer above the semiconductor layer;

performing a second heat treatment on the second mask layer, wherein the second heat treatment enables the second mask layer to be densified;

etching the second mask layer to expose the second recess;

and forming a second semiconductor material in the second recess.

7. A method of fabricating a transistor, comprising the steps of:

forming a semiconductor layer over a first substrate;

etching the semiconductor layer to form a first groove in a first region and a second groove in a second region;

depositing a first mask layer over the first region and the second region;

roughening the first mask layer;

removing the first mask layer from the second region;

forming a first epitaxial source/drain region in the second recess;

removing the remaining part of the first mask layer;

depositing a second mask layer over the first region and the second region;

roughening the second mask layer;

removing the second mask layer from the first region;

forming a second epitaxial source/drain region in the first recess;

removing the remaining part of the second mask layer;

and forming a gate structure over the semiconductor layer.

8. The method of claim 7, wherein one of roughening the first mask layer and roughening the second mask layer comprises a heat treatment, and wherein the other comprises a plasma treatment.

9. The method of claim 7, wherein the first mask layer is amorphous prior to roughening the first mask layer, and wherein at least an upper portion of the first mask layer is crystalline after roughening the first mask layer.

10. A method of fabricating a transistor, comprising the steps of:

depositing a mask layer above a substrate, wherein the substrate comprises a first groove and a second groove;

performing post-deposition treatment on the mask layer;

anisotropically etching the mask layer to expose the second recess;

epitaxially growing a first portion of a semiconductor material over the mask layer and a second portion of the semiconductor material in the second recess, the first portion including discontinuous nodules;

and isotropically etching to remove the mask layer.

Technical Field

The present disclosure relates to a method of manufacturing a transistor.

Background

Semiconductor devices are used in various electronic applications such as, for example, personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by: layers of insulating or dielectric, conductive, and semiconductor materials are sequentially deposited on a semiconductor substrate, and the layers of materials are patterned using photolithography to form circuit features and elements thereon.

The semiconductor industry continues to improve the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size in order to allow more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that should be addressed.

Disclosure of Invention

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates an example of a nano-structured field-effect transistor (nano-FET) in a three-dimensional view in accordance with some embodiments;

fig. 2, 3, 4, 5, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 13C, 14A, 14B, 15A, 15B, 15C, 16A, 16B, 16C, 17A, 17B, 17C, 17D, 18A, 18B, 18C, 19A, 19B, 19C, 20A, 20B, 20C, 20D, 21A, 21B, 21C, 22A, 22B, 23A, 23B, 24A, 24B, 25A, 25B, 26A, 26B, 26C, 27A, 27B, 27C, 28A, 28B, and 28C are cross-sectional views of an intermediate stage in fabricating a nano-FET according to some embodiments.

[ notation ] to show

20: partition

50 base plate

50N: N type region

50P: P-type region

51 first semiconductor layer

51A-C first semiconductor layer

52 first nanostructure

52A-C first nanostructure

53 second semiconductor layer

53A-C second semiconductor layer

54 second nanostructure

54A-C second nanostructure

55 nano structure

60 dummy dielectric layer

64 multilayer Stack

66: fin

68 shallow trench isolation region

70 dummy dielectric layer

71 dummy gate dielectric

72 dummy gate layer

74 mask layer

76 dummy gate

78 mask

80 the first separating layer

81 first partition

82 second separator layer

83 second partition

86 first groove

88 lateral wall groove

90 first inner partition

92 epitaxial source/drain regions

92A first semiconductor material layer

92B a second semiconductor material layer

92C third semiconductor material layer

92N node

93: p-mask layer

93A amorphous layer

93B rough exposed surface

93C crystalline layer

93S smooth exposed surface

93R rough surface

94 n-mask layer

94A amorphous layer

94B rough surface

94C crystalline layer

94S smooth exposed surface

94R rough surface

95 contact etch stop layer

96 first interlayer dielectric

98 second groove

100 gate dielectric layer

102 gate electrode

104 gate mask

108 third groove

110 silicide region

112 contact point

114 gate contact

118 of electrically conductive material

200 post deposition treatment

201 area

300 post deposition treatment

301 area

Cross section A-A

B-B': cross section

Cross section of C-C

T_93CThickness of

T_93AThickness of

T_94CThickness of

T_94AThickness of

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of an embodiment of the disclosure. Specific examples of components and arrangements are described below in order to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, spatially relative terms, such as "below …," "below …," "below," "above …," "above," and the like, may be used herein to describe one element or feature's relationship to another element or feature or features as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

Various embodiments provide methods of forming a die comprising a nano-FET. The method includes forming a stack of semiconductor layers and etching the stack to form epitaxial source/drain regions. The die area dedicated to p-type transistors may be masked while features within the die area dedicated to n-type transistors are formed or processed. Similarly, the die regions dedicated to n-type transistors may be masked while features within the die regions dedicated to p-type transistors are formed or processed. The respective mask layers may be formed and processed in a manner that improves the efficiency of other processes while also making the respective mask layers easier to remove later. A gate structure may then be formed over the stack of semiconductor layers to form a transistor structure. Additionally, a front interconnect structure may be formed on a first side of the transistor structure and a back interconnect structure may be formed on an opposite side of the transistor structure. However, the various embodiments may be applied to dies that include other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, or the like) instead of or in combination with nano-FETs.

Fig. 1 illustrates an example of a nano-FET (e.g., nanowire FET, nanosheet FET, or the like) in a three-dimensional view in accordance with some embodiments. The nano-FET includes a nanostructure 55 (e.g., nanosheet, nanowire, or the like) over a fin 66 on a substrate 50 (e.g., a semiconductor substrate), where the nanostructure 55 serves as a channel region of the nano-FET. The nanostructures 55 may include p-type nanostructures, n-type nanostructures, or a combination thereof. Shallow Trench Isolation (STI) regions 68 are disposed between adjacent fins 66, which may protrude above and between adjacent STI regions 68. Although STI regions 68 are described/illustrated as being separate from substrate 50, as used herein, the term "substrate" may refer to a semiconductor substrate alone or in combination with isolation regions. Additionally, although the bottom portion of fin 66 is shown as a single continuous material with substrate 50, the bottom portion of fin 66 and/or substrate 50 may comprise a single material or multiple materials. In this case, fin 66 refers to the portion extending between adjacent STI regions 68.

Gate dielectric layer 100 is over the top surface of fin 66 and along the top surface, sidewalls, and bottom surface of nanostructures 55. A gate electrode 102 is over the gate dielectric layer 100. Epitaxial source/drain regions 92 are disposed on fin 66 on opposite sides of gate dielectric layer 100 and gate electrode 102.

Fig. 1 further shows a reference cross section for use in later figures. The cross-section a-a' is along the longitudinal axis of the gate electrode 102 and in a direction perpendicular to the direction of current flow between, for example, the epitaxial source/drain regions 92 of the nano-FET. Cross-section B-B 'is perpendicular to cross-section a-a' and parallel to the longitudinal axis of fin 66 of the nano-FET and in the direction of current flow between, for example, epitaxial source/drain regions 92 of the nano-FET. Cross section C-C 'is parallel to cross section a-a' and extends through the epitaxial source/drain regions of the nano-FET. For clarity, the subsequent figures refer to these reference cross sections.

Some embodiments discussed herein are discussed in the context of a nano-FET formed using a gate-last process. In other embodiments, a front gate process may be used. Also, some embodiments encompass aspects for use in planar devices such as planar FETs or fin-field-effect transistors (FinFETs).

Fig. 2-28C are cross-sectional views of intermediate stages in fabricating a nano-FET according to some embodiments. Fig. 2 to 5, 6A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, and 28A show the reference cross section a-a' shown in fig. 1. Fig. 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13C, 14B, 15B, 16B, 17D, 18B, 19B, 20D, 21B, 22B, 23B, 24B, 25B, 26B, 27B, and 28B illustrate a reference cross-section B-B' shown in fig. 1. Fig. 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15C, 16A, 16C, 17A, 17C, 18A, 18C, 19A, 19C, 20A, 20C, 21C, 26C, 27C, and 28C show a reference cross section C-C' shown in fig. 1.

In fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor (bulk semiconductor), a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, the SOI substrate layer is a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material substrate 50 may comprise silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof.

The substrate 50 has an N-type region 50N and a P-type region 50P. The N-type region 50N may be used to form an N-type device, such as an NMOS transistor, e.g., an N-type nano-FET, and the P-type region 50P may be used to form a P-type device, such as a PMOS transistor, e.g., a P-type nano-FET. The N-type region 50N may be physically separated from the P-type region 50P (as shown by the spacer 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the N-type region 50N and the P-type region 50P. Although one N-type region 50N and one P-type region 50P are shown, any number of N-type regions 50N and P-type regions 50P may be provided.

Also in fig. 2, a multi-layer stack 64 is formed on the substrate 50. The multi-layer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustration purposes and as discussed in more detail below, the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form a channel region of the nano-FET in the P-type region 50P. Also, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form a channel region of the nano-FET in the N-type region 50N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nano-FET in the N-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nano-FET in the P-type region 50P. In other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to simultaneously form channel regions of the nano-FETs in the N-type region 50N and the P-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to simultaneously form a channel region of the nano-FET in the N-type region 50N and the P-type region 50P.

For exemplary purposes, the multi-layer stack 64 is shown as including three layers of each of the first and second semiconductor layers 51, 53. In some embodiments, the multi-layer stack 64 may include any number of first and second semiconductor layers 51, 53. The layers of the multilayer stack 64 may be epitaxially grown using processes such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Vapor Phase Epitaxy (VPE), Molecular Beam Epitaxy (MBE), or the like. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nano-FET, such as silicon germanium or the like, and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nano-FET, such as silicon, silicon carbon, or the like. For exemplary purposes, the multi-layer stack 64 is shown with the lowest semiconductor layer suitable for a p-type nano-FET. In some embodiments, the multi-layer stack 64 may be formed such that the lowest layer is a semiconductor layer suitable for an n-type nano-FET.

The first semiconductor material and the second semiconductor material may be materials having high etch selectivity to each other. Accordingly, the first semiconductor layer 51 of the first semiconductor material may be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material in the N-type region 50N, thereby patterning the second semiconductor layer 53 to form a channel region of the N-type NSFETS. Similarly, the second semiconductor layer 53 of second semiconductor material may be removed without significantly removing the first semiconductor layer 51 of first semiconductor material in the P-type region 50P, thereby patterning the first semiconductor layer 51 to form a channel region of the P-type NSFETS.

Referring now to fig. 3, according to some embodiments, fins 66 are formed in substrate 50 and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 may be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. The etch can be any acceptable etch process, such as Reactive Ion Etch (RIE), Neutral Beam Etch (NBE), the like, or combinations thereof. The etching may be anisotropic. Forming the nanostructures 55 by etching the multi-layer stack 64 may further define first nanostructures 52A-C (collectively first nanostructures 52) from the first semiconductor layer 51 and second nanostructures 54A-C (collectively second nanostructures 54) from the second semiconductor layer 53. The first nanostructures 52 and the second nanostructures 54 may be further collectively referred to as nanostructures 55.

Fin 66 and nanostructures 55 may be patterned by any suitable method. For example, fin 66 and nanostructure 55 may be patterned using one or more lithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine lithography with self-alignment processes, allowing for the generation of patterns, for example, with pitches smaller than those otherwise obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the fins 66.

For exemplary purposes, fig. 3 illustrates fins 66 in N-type region 50N and P-type region 50P as having substantially equal widths. In some embodiments, the width of fin 66 in N-type region 50N may be greater or thinner than fin 66 in P-type region 50P. Further, although each of fin 66 and nanostructure 55 are shown as having a uniform width throughout, in other embodiments, fin 66 and/or nanostructure 55 may have tapered sidewalls such that the width of each of fin 66 and/or nanostructure 55 continuously increases in a direction toward substrate 50. In these embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

In fig. 4, a Shallow Trench Isolation (STI) region 68 is formed adjacent to the fin 66. STI regions 68 may be formed by depositing an insulating material on substrate 50, fins 66, and nanostructures 55, as well as between adjacent fins 66. The insulating material may be an oxide, such as silicon oxide, nitride, the like, or combinations thereof, and may be formed by high-density plasma CVD (HDP-CVD), Flowable CVD (FCVD), the like, or combinations thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructures 55. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, spacers (not separately shown) may first be formed along the surfaces of substrate 50, fin 66, and nanostructures 55. Thereafter, a fill material, such as those discussed above, may be formed on the liner.

A removal process is then applied to the insulating material to remove excess insulating material on the nanostructures 55. In some embodiments, a planarization process such as Chemical Mechanical Polishing (CMP), an etch back process, a combination thereof, or the like may be utilized. The planarization process exposes the nanostructures 55 such that the top surfaces of the nanostructures 55 and the insulating material are level after the planarization process is complete.

The insulating material is then recessed to form STI regions 68. The insulating material is recessed so that upper portions of fins 66 in regions 50N and 50P protrude between adjacent STI regions 68. Further, the top surface of STI region 68 may have a flat surface as shown, a convex surface, a concave surface (such as in a disk shape), or a combination thereof. The top surface of STI region 68 may be formed flat, convex, and/or concave by suitable etching. STI regions 68 may be recessed using an acceptable etch process, such as a process that is selective to the material of the insulating material (e.g., the material of the insulating material is etched at a faster rate than the material of fins 66 and nanostructures 55). For example, oxide removal using, for example, dilute hydrofluoric acid (dHF) may be used.

The process described above with respect to fig. 2-4 is but one example of how fin 66 and nanostructures 55 may be formed. In some embodiments, fin 66 and/or nanostructure 55 may be formed using a masked and epitaxial growth process. For example, a dielectric layer may be formed on the top surface of the substrate 50, and a trench may be etched through the dielectric layer so as to expose the underlying substrate 50. An epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fin 66 and/or the nanostructure 55. The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments in which the epitaxial structure is grown epitaxially, the epitaxial growth material may be doped in situ during growth, eliminating previous and/or subsequent implants, although in situ and implant doping may be used together.

Additionally, for exemplary purposes only, the first semiconductor layer 51 (and resulting first nanostructure 52) and the second semiconductor layer 53 (and resulting second nanostructure 54) are shown and discussed herein as including the same materials in the P-type region 50P and the N-type region 50N. Thus, in some embodiments, one or both of the first and second semiconductor layers 51, 53 may be different materials or formed in different orders in the P-type region 50P and the N-type region 50N.

Also in fig. 4, suitable holes (not separately shown) may be formed in fin 66, nanostructure 55, and/or STI region 68. In embodiments with different hole types, different implantation steps of N-type region 50N and P-type region 50P may be achieved using photoresist or other masks (not separately shown). For example, photoresist may be formed on fin 66 and STI regions 68 in N-type region 50N and P-type region 50P. The photoresist is patterned so as to expose P-type region 50P. The photoresist may be formed by using one or more spin-on coatings or spin-on coatingsDeposition techniques are used and may be patterned using acceptable lithography techniques. Once photoresist patterned, an N-type impurity implant is performed in P-type region 50P, and the photoresist may act as a mask so as to substantially prevent the N-type impurity from being implanted into N-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, or the like, which is present at about 10 deg.f¹³Atom/cm³To about 10¹⁴Atom/cm³A concentration within the range is implanted in the region. After implantation, the photoresist is removed, such as by an acceptable ashing process.

After or before implanting P-type region 50P, photoresist or other masks (not separately shown) are formed over fin 66, nanostructures 55, and STI regions 68 in P-type region 50P and N-type region 50N. The photoresist is patterned so as to expose the N-type region 50N. The photoresist may be formed using one or more spin-on or deposition techniques and may be patterned using acceptable lithography techniques. Once the photoresist is patterned, a P-type impurity implant may be performed in the N-type region 50N, and the photoresist may act as a mask so as to substantially prevent the P-type impurity from being implanted into the P-type region 50P. The p-type impurity may be boron, boron fluoride, indium, or the like, at about 10¹³Atom/cm³To about 10¹⁴Atom/cm³A concentration within the range is implanted in the region. After implantation, the photoresist may be removed, such as by an acceptable ashing process.

After implantation of the N-type region 50N and the P-type region 50P, an anneal may be performed in order to repair the implantation damage and activate the implanted P-type and/or N-type impurities. In some embodiments, the growth material of the epitaxial fin may be doped in situ during growth, which may eliminate implantation, although in situ and implant doping may be used together.

In fig. 5, a dummy dielectric layer 70 is formed on fin 66 and/or nanostructure 55. Dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 may be deposited on the dummy dielectric layer 70 and then planarized, such as by CMP. A masking layer 74 may be deposited on the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material and may be selected from the group consisting of amorphous silicon, poly-crystalline silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 72 may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other techniques for depositing selected materials. The dummy gate layer 72 may be made of other materials having a higher etch selectivity than the etch isolation regions. Masking layer 74 may comprise, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the N-type region 50N and the P-type region 50P. It should be noted that dummy dielectric layer 70 is shown covering only fins 66 and nanostructures 55 for exemplary purposes only. In some embodiments, dummy dielectric layer 70 may be deposited such that dummy dielectric layer 70 covers STI regions 68 such that dummy dielectric layer 70 extends between dummy gate layer 72 and STI regions 68.

Fig. 6A-20D illustrate various additional steps in fabricating an embodiment device. Fig. 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13C, 14A, 15C, 16A, 16C, 17A, 17C, 17D, 18A, 18C, 19A, 19C, 20A, and 20C illustrate features in the N-type region 50N or the P-type region 50P. In fig. 6A and 6B, masking layer 74 (see fig. 5) may be patterned using acceptable lithography and etching techniques to form mask 78. The pattern of mask 78 may then be transferred to dummy gate layer 72 and dummy dielectric layer 70 to form dummy gate 76 and dummy gate dielectric 71, respectively. Dummy gate 76 covers the corresponding channel area of fin 66. The pattern of mask 78 may be used to physically separate each of the dummy gates 76 from adjacent dummy gates 76. Dummy gates 76 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of respective fins 66.

In fig. 7A and 7B, a first separation layer 80 and a second separation layer 82 are formed on the structure shown in fig. 6A and 6B, respectively. The first and second separation layers 80, 82 are subsequently patterned so as to act as spacers for forming self-aligned source/drain regions. In fig. 7A and 7B, first spacer 80 is at the top surface of STI region 68; the top surface and sidewalls of fin 66, nanostructure 55, and mask 78; and dummy gate 76 and dummy gate dielectric 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first separation layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like using techniques such as thermal oxidation, or deposited by CVD, ALD, or the like. The second spacer layer 82 may be formed of a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like.

An implant (not separately shown) of lightly doped source/drain (LDD) regions may be performed after the first spacer 80 is formed and before the second spacer 82 is formed. In embodiments with different device types, similar to the implantation discussed above in fig. 4, a mask such as photoresist may be formed in the N-type region 50N while exposing the P-type region 50P, and appropriate type (e.g., P-type) impurities may be implanted into the exposed fins 66 and nanostructures 55 in the P-type region 50P. The mask can then be removed. Subsequently, while exposing N-type region 50N, a mask such as photoresist may be formed in P-type region 50P, and an appropriate type impurity (e.g., N-type) may be implanted into exposed fin 66 and nanostructures 55 in N-type region 50N. The mask can then be removed. The n-type impurity may be any of the n-type impurities previously discussed, and the p-type impurity may be any of the p-type impurities previously discussed. The lightly doped source/drain regions may have about 1x10¹⁵Atom/cm³To about 1x10¹⁹Atom/cm³Impurity concentration within the range. Annealing can be used to repair implant damage and activate implanted impurities.

In fig. 8A and 8B, the first and second spacer layers 80 and 82 are etched to form first and second spacers 81 and 83. As discussed in more detail below, first spacers 81 and second spacers 83 are used to self-align subsequently formed source drain regions and to protect the sidewalls of fin 66 and/or nanostructure 55 during subsequent processing. The first and second spacer layers 80, 82 may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. In some embodiments, the material of the second separation layer 82 has a different etch rate than the material of the first separation layer 80, such that the first separation layer 80 may act as an etch stop layer when patterning the second separation layer 82, and such that the second separation layer 82 may act as a mask when patterning the first separation layer 80. For example, the second spacer layer 82 may be etched using an anisotropic etch process, wherein the first spacer layer 80 acts as an etch stop, wherein the remaining portion of the second spacer layer 82 forms the second spacer 83, as shown in fig. 8A. Thereafter, the second spacers 83 serve as a mask when etching the exposed portions of the first spacer layers 80, thereby forming the first spacers 81, as shown in fig. 8A. Although not specifically shown in fig. 8B, an etching process (e.g., an anisotropic etching process) may additionally remove the first and second spacer layers 80, 82 from on top of the mask 78, and the second spacer layer 82 from the dummy gate 76 and the sides of the mask 78, according to some embodiments.

As shown in fig. 8A, first spacers 81 and second spacers 83 are disposed on sidewalls of fin 66 and/or nanostructures 55. As shown in fig. 8B, portions of the first and second spacers 81, 83 may remain adjacent to and above the mask 78, the dummy gate 76, and the dummy gate dielectric 71. In other embodiments not specifically shown, adjacent to and above the top mask 78, the dummy gate 76, and the dummy gate dielectric 71, the second spacer layer 82 may be removed from above the first spacer layer 80, and the first spacer layer 80 may be removed from the top of the mask 78.

It should be noted that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, a different sequence of steps may be utilized (e.g., the first spacers 81 may be patterned prior to depositing the second spacer layer 82), additional spacers may be formed and removed, and/or the like. In addition, n-type and p-type devices may be formed using different structures and steps.

In fig. 9A and 9B, a first recess 86 is formed in fin 66, nanostructure 55, and substrate 50, according to some embodiments. Epitaxial source/drain regions are then formed in the first recess 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. As shown in fig. 9A, the top surface of STI region 68 may be level with the bottom surface of first recess 86. In various embodiments, fin 66 may be etched such that a bottom surface of first recess 86 is disposed below a top surface of STI region 68; or the like. First recess 86 may be formed by etching fin 66, nanostructures 55, and substrate 50 using an anisotropic etching process, such as RIE, NBE, or the like. The first spacers 81, the second spacers 83, and the mask 78 shield portions of the fin 66, the nanostructures 55, and the substrate 50 during an etching process for forming the first recess 86. A single etch process or multiple etch processes may be used to etch the layers of nanostructures 55 and/or fins 66. A timed etch process may be used to terminate the etching of first recess 86 after first recess 86 reaches a desired depth.

In fig. 10A and 10B, portions of the sidewalls of the layers of the multi-layer stack 64 formed of the first semiconductor material (e.g., the first nanostructures 52) exposed by the first recess 86 are etched to form sidewall recesses 88 in the N-type region 50N, and portions of the sidewalls of the layers of the multi-layer stack 64 formed of the second semiconductor material (e.g., the second nanostructures 54) exposed by the first recess 86 are etched to form sidewall recesses 88 in the P-type region 50P. Although the sidewalls of the first nanostructures 52 and the second nanostructures 54 in the sidewall recesses 88 are shown as being straight in fig. 10B, the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process, such as a wet etch or similar process. While etching the first nanostructures 52 using an etchant selective to the first semiconductor material, the P-type region 50P may be protected using a mask (not shown) such that the second nanostructures 54 and the substrate 50 remain relatively unetched as compared to the first nanostructures 52 in the N-type region 50N. Similarly, the second nano-meter is etched using an etchant selective to the second semiconductor materialWhile the structure 54, the N-type region 50N may be protected using a mask (not shown) such that the first nanostructures 52 and the substrate 50 remain relatively unetched as compared to the second nanostructures 54 in the P-type region 50P. In one embodiment where the first nanostructures 52 comprise, for example, SiGe and the second nanostructures 54 comprise, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH), are used₄OH), or the like, may be used to etch the sidewalls of the first nanostructures 52 in the N-type region 50N, and a dry etch process using hydrogen fluoride, another fluorine-based etchant, or the like, may be used to etch the sidewalls of the second nanostructures 54 in the P-type region 50P.

In fig. 11A-11B, a first internal partition 90 is formed in the sidewall recess 88. The first inner spacer 90 may be formed by depositing an inner spacer layer (not separately shown) over the structure shown in fig. 10A and 10B. The first inner spacers 90 serve as isolation features between subsequently formed source/drain regions and the gate structure. As discussed in more detail below, source/drain regions are formed in the first recess 86 while the first nanostructures 52 in the N-type region 50N and the second nanostructures 54 in the P-type region 50P are replaced with corresponding gate structures.

The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The internal spacers may comprise a material such as silicon nitride or silicon oxynitride, but any suitable material may be utilized, such as a low-dielectric constant (low-k) material having a k-value of less than about 3.5. The inner spacer layer may then be anisotropically etched to form a first inner spacer 90. The first inner spacer 90 may be used to prevent a subsequent etch process, such as an etch process used to form a gate structure, from damaging subsequently formed source/drain regions (such as epitaxial source/drain regions 92, discussed below). Although the outer sidewall first inner spacers 90 are shown to be flush with the sidewalls of the second nanostructures 54 in the N-type region 50N and flush with the sidewalls of the first nanostructures 52 in the P-type region 50P, the outer sidewalls of the first inner spacers 90 may extend beyond or be recessed from the sidewalls of the second nanostructures 54 and/or the first nanostructures 52, respectively.

In fig. 12A-19C, epitaxial source/drain regions 92 are formed in the first recess 86. Specifically, fig. 12A-15C illustrate the formation of an epitaxial source/drain region 92 in an N-type region 50N, and fig. 16A-19C illustrate the formation of an epitaxial source/drain region 92 in a P-type region 50P. In some embodiments, the epitaxial source/drain regions 92 may stress the second nanostructures 54 in the N-type region 50N and the first nanostructures 52 in the P-type region 50P, thereby improving performance. As shown, epitaxial source/drain regions 92 are formed in the first recess 86 such that each dummy gate 76 is disposed between a respective adjacent pair of epitaxial source/drain regions 92. In some embodiments, the first spacers 81 are used to separate the epitaxial source/drain regions 92 from the dummy gate 76 and the first inner spacers 90 are used to separate the epitaxial source/drain regions 92 from the nanostructures 55 by a suitable lateral distance so that the epitaxial source/drain regions 92 are not shorted to subsequently formed gates of the resulting nano-FET.

Referring to fig. 12A-12B, a P-mask layer 93 is formed over the structure (e.g., N-type region 50N and P-type region 50P). The P-mask layer 93 protects the P-type region 50P during formation of the N-type epitaxial source/drain regions 92 in the first recess 86 of the N-type region 50N (e.g., NMOS region). The p-mask layer 93 may be deposited by a conformal deposition process, such as ALD, CVD, or the like. The p-mask layer 93 may comprise a material such as a metal oxide including aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, zinc oxide, or the like. The use of a metal oxide as the p-mask layer 93 allows for a thin p-mask layer 93, advantageously protecting the substrate by providing complete coverage even when features such as the first recess 86 have small critical dimensions. After deposition, the p-mask layer 93 may have a substantially smooth exposed surface 93S and be substantially or completely amorphous. For example, in some embodiments, the p-mask layer 93 may be deposited to a thickness of between about 1nm and about 10nm, about 2.6g/cm³And about 4.0g/cm³A density of between about 0.1nm and about 0.8nm, and a roughness of between about 0.1nm and about 0.8 nm.

Referring to fig. 13A-13C, after deposition, a post-deposition treatment 200 (or roughening treatment 200) may be performed on the p-mask layer 93. Post-deposition treatment 200 stabilizes the p-mask layer 93 to form a denser layer. Thus, the p-mask layer 93 may have a more contoured, or rougher, exposed surface 93R rather than the previously smooth exposed surface 93S. The more wavy (or rougher) shape of the exposed surface 93R improves selectivity during epitaxial growth in subsequent steps (see fig. 15A-15C) because on the rougher surface 93R of the p-mask layer 93, epitaxy grows less easily and with smaller nodules. The less growth of epitaxy over the p-mask layer 93 also allows for more efficient removal of the p-mask layer 93 after formation of the epitaxial source/drain regions 92 in the N-type region 50N (see fig. 16A-16C).

The post-deposition treatment 200 may include a thermal treatment, a plasma treatment, a UV treatment, a microwave treatment, a plasma bombardment, an implant, a reticle absorption treatment, an electron anneal, a radiation anneal, the like, or any combination thereof. According to some embodiments, the post-deposition treatment 200 may include a thermal treatment comprising annealing at a temperature greater than about 650 ℃, including a temperature between about 650 ℃ and about 900 ℃, for a duration between about 30 minutes and about 8 hours. The heat treatment may be performed in an atmosphere of nitrogen, argon, helium, hydrogen, or the like. The p-mask layer 93 may become thinner as some or all of the p-mask layer 93 crystallizes and/or densifies during the post-deposition process 200. After the post-deposition treatment 200, the p-mask layer 93 may have a thickness between about 0.5nm and about 6nm, about 2.8g/cm³And about 4.2g/cm³A density of between about 2nm and about 5nm, and a roughness of between about 2nm and about 5 nm.

Referring to fig. 13C, which shows an enlarged view of the region 201 of fig. 13B, the post-deposition process 200 may partially or completely convert the amorphous p-mask layer 93 to a crystalline form. Note that region 201 is shown depicting portions of p-mask layer 93, which represents any or all other portions of p-mask layer 93 disposed over the structure. For example, an upper portion of the p-mask layer 93 may comprise the crystalline layer 93C while a lower portion of the p-mask layer 93 may remain as a substantially amorphous layer 93A. The crystallized layer 93C may have a thickness T between about 2nm and about 5nm_93CAnd the amorphous layer 93A may have a thickness T between about 2nm and about 5nm_93A。

Additionally or alternatively, the post-deposition treatment 200 may include a plasma treatment. During plasma processing, the surface 93S of the p-mask layer 93 is exposed to a plasma of nitrogen, argon, ammonia, oxygen, helium, the like, or combinations thereof, in order to change the material properties of the p-mask layer 93 and/or etch portions. The plasma treatment may be performed at a temperature between about 50 ℃ and about 500 ℃ and at a pressure between about 0.5 torr and about 10 torr for a duration between about 10 seconds and about 10 minutes.

The post-deposition treatment 200 may further comprise a UV radiation treatment. During the UV radiation treatment, the surface 93S of the p-mask layer 93 is exposed to UV radiation in an environment of nitrogen, argon, ammonia, oxygen, helium, the like, or any combination thereof, in order to change the material properties of the p-mask layer 93 and/or etch portions. The UV radiation treatment may be performed at an energy between about 50 watts and about 1000 watts for a duration between about 30 seconds and about 10 minutes.

Additionally or alternatively, the post-deposition treatment 200 may include a microwave radiation treatment. During the microwave radiation treatment, the surface 93S of the p-mask layer 93 is exposed to microwave radiation in an environment of nitrogen, argon, ammonia, oxygen, helium, the like, or any combination thereof, in order to change the material properties of the p-mask layer 93 and/or etch portions. The microwave radiation treatment may be performed at an energy between about 500 watts and about 3000 watts for a duration between about 30 seconds and about 10 minutes.

According to some embodiments, the post-deposition process 200 may include a combination of one or more of the above processes. For example, the post-deposition treatment 200 may include a thermal treatment as well as a plasma treatment, whether performed simultaneously or consecutively. In other embodiments, the post-deposition treatment 200 may include a thermal treatment, a plasma treatment, and a UV radiation treatment, whether two or all performed simultaneously or all three performed in succession.

Referring to fig. 14A-14B, the p-mask layer 93 is removed from the N-type region 50N after the post-deposition process 200. A photoresist (not specifically shown), such as a hard mask, may be formed over the p-mask layer 93 and patterned to expose the p-mask layer 93 in the N-type region 50N. The p-mask layer 93 may then be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. The photoresist may then be removed by a suitable process, such as an isotropic etch process or an anisotropic etch process. In other embodiments, the p-mask layer 93 is removed in the N-type region 50N by one of the processes described above without first forming a photoresist over the p-mask layer 93.

Referring to fig. 15A-15C, epitaxial source/drain regions 92 are epitaxially grown in the first recess 86 in the N-type region 50N, and nodules 92N of epitaxial material may be formed over the p-mask layer 93. The epitaxial source/drain regions 92 may comprise any acceptable material suitable for an n-type nano-FET. For example, if the second nanostructure 54 is silicon, the epitaxial source/drain regions 92 may comprise a material that imparts a tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions 92 may have surfaces that rise from respective upper surfaces of the nanostructures 55 and may have end faces.

As described above, the nodules 92N (e.g., a small amount of epitaxy) may be grown over the p-mask layer 93. However, the rough surface 93R of the p-mask layer 93 reduces the number and size of the nodules 92N that may otherwise be formed, allowing greater control over the formation of the epitaxial source/drain regions 92 and improved removal of the p-mask layer 93 (and nodules 92N) in subsequent steps discussed in more detail below. As shown, each of the epitaxial source/drain regions 92 is formed as a unitary continuous material, while the nodules 92N are formed as discontinuous clusters or nodules.

Similar to the process previously discussed for forming lightly doped source/drain regions, the epitaxial source/drain regions 92, the first nanostructures 52, the second nanostructures 54, and/or the substrate 50 may be implanted with dopants to form source/drain regions, followed by annealing. The source/drain region may have about 1x10¹⁹Atom/cm³And about 1x10²¹Atom/cm³Impurity concentration in between. The n-type impurity of the source/drain regions may be any of the impurities previously discussed. The p-type region is still protected in the p-mask layer 93At the same time as the region 50P, n-type impurities may be implanted. In some embodiments, the epitaxial source/drain regions 92 may be doped in-situ during growth.

Due to the epitaxial process used to form the epitaxial source/drain regions 92, the upper surface of the epitaxial source/drain regions 92 has end surfaces that extend laterally outward beyond the sidewalls of the nanostructures 55. In some embodiments, these facets result in merging of adjacent epitaxial source/drain regions 92 of the same NSFET, as shown in fig. 15A. In other embodiments, adjacent epitaxial source/drain regions 92 remain separated after the epitaxial process is completed, as shown in fig. 15C. In the embodiment illustrated in fig. 15A and 15C, a first spacer 81 may be formed at the top surface of the STI region 68, thereby blocking epitaxial growth. In some other embodiments, the first spacer 81 may cover portions of the sidewalls of the nanostructures 55, further blocking epitaxial growth. In some other embodiments, the spacer etch used to form the first spacers 81 may be adjusted to remove the spacer material, allowing the epitaxially grown region to extend to the surface of the STI region 68.

The epitaxial source/drain regions 92 may include one or more layers of semiconductor material. For example, the epitaxial source/drain regions 92 may include a first layer of semiconductor material 92A, a second layer of semiconductor material 92B, and a third layer of semiconductor material 92C. Any number of semiconductor material layers may be used to epitaxially grow source/drain regions 92. Each of the first, second, and third layers of semiconductor material 92A, 92B, 92C may be formed of a different semiconductor material and may be doped to a different dopant concentration. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In an embodiment where the epitaxial source/drain region 92 includes three layers of semiconductor material, a first layer of semiconductor material 92A may be deposited, a second layer of semiconductor material 92B may be deposited over the first layer of semiconductor material 92A, and a third layer of semiconductor material 92C may be deposited over the second layer of semiconductor material 92B.

In fig. 16A-19C, the P-mask layer 93 and the nodules 92N may be removed from the P-type region 50P, and the epitaxial source/drain regions 92 in the P-type region 50P (e.g., PMOS region) may be formed in a similar manner as described above with respect to the epitaxial source/drain regions 92 in the N-type region 50N.

Referring to fig. 16A-16C, the P-mask layer 93 and the node 92N may be removed from the P-type region 50P. For example, the p-mask layer 93 and the nodules 92N may be etched using a wet or dry etch such as sulfuric acid (H)₂SO₄) Hydrogen fluoride (hydrogen fluoride; HF), hydrogen chloride (hydrogen chloride; HCl), ammonia (ammonia; NH (NH)₃+H₂O), the like, an etchant of any combination thereof, or any suitable etchant. The reduced size and number of the nodules 92N (due to the rough surface 93R of the p-mask layer 93) improves the efficiency of removing the p-mask layer 93 and the nodules 92N by the process described above. An N-mask layer 94 may then be formed over the structure (e.g., N-type region 50N and P-type region 50P). The N-mask layer 94 protects the N-type region 50N during the formation of the P-type epitaxial source/drain regions 92 in the first recess 86 of the P-type region 50P (e.g., PMOS region). n-mask layer 94 may be deposited by a conformal deposition process, such as ALD, CVD, or the like. n-mask layer 94 may comprise a material such as a metal oxide, including aluminum oxide, hafnium oxide (HfO)₂) Zirconium oxide (zirconia oxide; ZrO (ZrO)₂) Or the like. n-mask layer 94 may be the same as or different from p-mask layer 93 and may be formed by similar or different processes. The use of metal oxide as the n-mask layer 93 allows for a thin n-mask layer 94, advantageously protecting the substrate by providing complete coverage even when features such as the first recess 86 have small critical dimensions. After deposition, n-mask layer 94 may have a substantially smooth exposed surface 94S and be substantially or completely amorphous. n-mask layer 94 may become thinner and have a thickness between about 1nm and about 10nm, about 2.6g/cm³And about 4.0g/cm³A density of between about 0.1nm and about 0.8nm, and a roughness of between about 0.1nm and about 0.8 nm.

Referring to fig. 17A-17D, after deposition, a post-deposition treatment 300 (or roughening treatment 300) may be performed on n-mask layer 94. As with p-mask layer 93, post-deposition process 300 stabilizes n-mask layer 94 to form a denser layer. Thus, n-mask layer 94 may have a more contoured, or rougher, exposed surface 94B rather than a previously smooth exposed surface 94S. As with the rougher exposed surface 93R of the p-mask layer 93, the rougher exposed surface 94R of the n-mask layer 94 improves selectivity during epitaxial growth in subsequent steps (see fig. 19A-19C) because epitaxy is less easy and grows with smaller nodules on the rougher surface 94R of the n-mask layer 94. The less epitaxial growth above n-mask layer 94 also allows for more efficient removal of n-mask layer 94 after formation of epitaxial source/drain regions 92 in P-type region 50P (see fig. 20A-20D).

Any of the post-deposition treatments 200 described with respect to p-mask layer 93 may be used for post-deposition treatment 300 of n-mask layer 94 (e.g., thermal treatment, plasma treatment, UV treatment, microwave treatment, plasma bombardment, implantation, reticle absorption treatment, electron annealing, radiation annealing, the like, or any combination thereof). Post-deposition treatment 300 of n-mask layer 94 may be the same or similar process as post-deposition treatment 200 for p-mask layer 93, or these processes may be different. According to some embodiments, the post deposition treatment 300 may comprise a thermal treatment comprising annealing at a temperature greater than about 650 ℃, including a temperature between about 650 ℃ and about 900 ℃, for a duration between about 30 minutes and about 8 hours. The heat treatment may be performed in an atmosphere of nitrogen, argon, helium, hydrogen, or the like. N-mask layer 94 may become thinner as some or all of n-mask layer 94 crystallizes and/or densifies during post-deposition process 300. After post-deposition treatment 300, n-mask layer 94 may have a thickness between about 0.5nm and about 6nm, about 2.8g/cm³And about 4.2g/cm³A density of between about 2nm and about 5nm, and a roughness of between about 2nm and about 5 nm.

For example, in some embodiments, the two post-deposition treatments 200 and 300 may include thermal and/or plasma treatments. In other embodiments, one of the post-deposition processes 200 or 300 may include one type of process (e.g., a thermal process) while the other post-deposition process 200 or 300 includes a different type of process (e.g., a plasma process). In other embodiments, one of the post-deposition treatments 200 or 300 may comprise one combination of treatments (e.g., thermal treatment and plasma treatment), while the other post-deposition treatment 200 or 300 comprises a single treatment or a different combination of treatments (e.g., thermal treatment and UV radiation treatment).

Referring to fig. 17D, which shows an enlarged view of region 301 of fig. 17B, post-deposition process 300 may partially or completely convert amorphous n-mask layer 94 to a crystalline form. Note that region 301 is shown depicting a portion of n-mask layer 94 that represents any or all other portions of n-mask layer 94 disposed over the structure. For example, an upper portion of n-mask layer 94 may comprise crystallized layer 94C while a lower portion of n-mask layer 94 may remain substantially amorphous layer 94A. The crystallized layer 94C may have a thickness T between about 2nm and about 5nm_94CAnd the amorphous layer 94A may have a thickness T between about 2nm and about 5nm_94A. The n-mask layer 93 may become thinner as some or all of the p-mask layer 93 crystallizes and/or densifies during the post-deposition process 300.

Referring to fig. 18A-18C, after post-deposition treatment 300, n-mask layer 94 is removed from P-type region 50P. A photoresist (not specifically shown), such as a hard mask, may be formed over n-mask layer 94 and patterned to expose n-mask layer 94 in P-type region 50P. N-mask layer 94 may then be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. The photoresist may then be removed by a suitable process, such as an isotropic etch process or an anisotropic etch process. In other embodiments, n-mask layer 94 is removed in P-type region 50P by one of the processes described above without first forming a photoresist over n-mask layer 94.

Referring to fig. 19A-19C, epitaxial source/drain regions 92 are epitaxially grown in the first recess 86 in the P-type region 50P, and nodules 92N of epitaxial material may be formed over the N-mask layer 94. The epitaxial source/drain regions 92 may comprise any acceptable material suitable for a p-type nano-FET. For example, if the first nanostructure 52 is silicon germanium, the epitaxial source/drain regions 92 may comprise a material that imparts a compressive strain on the first nanostructure 52, such as silicon-germanium, germanium tin, or the like. The epitaxial source/drain regions 92 may have surfaces raised from respective surfaces of the multilayer stack 64 and may have end faces.

As described above, nodules 92N (e.g., a small amount of epitaxy) may be grown over N-mask layer 94. However, rough surface 94B of N-mask layer 94 reduces the number and size of nodules 92N that may otherwise be formed, allowing greater control over the formation of epitaxial source/drain regions 92 and improved removal of N-mask layer 94 (and nodules 92N) in subsequent steps discussed in more detail below. As shown, each of the epitaxial source/drain regions 92 is formed as a unitary continuous material, while the nodules 92N are formed as discontinuous clusters or nodules.

Similar to the process previously discussed for forming lightly doped source/drain regions, the epitaxial source/drain regions 92, the first nanostructures 52, the second nanostructures 54, and/or the substrate 50 may be implanted with dopants to form source/drain regions, followed by annealing. The source/drain region may have about 1x10¹⁹Atom/cm³And about 1x10²¹Atom/cm³Impurity concentration in between. The p-type impurity of the source/drain regions may be any of the impurities previously discussed. P-type impurities may be implanted while N-mask layer 94 still protects N-type region 50N. In some embodiments, the epitaxial source/drain regions 92 may be doped in-situ during growth.

As discussed above with respect to the epitaxial source/drain regions 92 in the N-type region 50N, the epitaxial source/drain regions 92 in the P-type region 50P may include similar or different shapes for similar reasons as set forth above with respect to the epitaxial source/drain regions 92 in the N-type region 50N. Due to the epitaxial process used to form the epitaxial source/drain regions 92 in the P-type region 50P, the upper surface of the epitaxial source/drain regions 92 has end surfaces that extend laterally outward beyond the sidewalls of the nanostructures 55. In some embodiments, these facets result in merging of adjacent epitaxial source/drain regions 92 of the same NSFET, similarly as shown above in fig. 15A. In other embodiments, after the epitaxy process is completed, adjacent epitaxial source/drain regions 92 remain separated, similarly as shown in fig. 15C above. In an embodiment similar to that shown in fig. 15A and 15C, a first spacer 81 may be formed at the top surface of STI region 68, thereby blocking epitaxial growth. In some other embodiments, the first spacer 81 may cover portions of the sidewalls of the nanostructures 55, further blocking epitaxial growth. In some other embodiments, the spacer etch used to form the first spacers 81 may be adjusted to remove the spacer material, allowing the epitaxially grown region to extend to the surface of the STI region 68.

As discussed above in connection with fig. 15A-15C with respect to the epitaxial source/drain regions 92 in the N-type region 50N, the epitaxial source/drain regions 92 in the P-type region 50P may include one or more layers of semiconductor material having one or more different dopant concentrations, similar or different than that discussed above.

Referring to fig. 20A-20D, N-mask layer 94 and node 92N may be removed from N-type region 50N. For example, N-mask layer 94 and nodules 92N may be etched using a wet or dry etch such as sulfuric acid (H)₂SO₄) Hydrogen fluoride (hydrogen fluoride; HF), hydrogen chloride (hydrogen chloride; HCl), ammonia (ammonia; NH (NH)₃+H₂O), the like, an etchant of any combination thereof, or any suitable etchant. The reduced size and number of nodules 92N (due to rough surface 94R of N-mask layer 94) improves the efficiency of removing N-mask layer 94 and nodules 92N by the process described above.

Referring to fig. 20D, although the outer sidewalls of the first inner partition 90 are illustrated as straight in fig. 10B to 20B, the outer sidewalls of the first inner partition 90 may be concave or convex. For example, fig. 20D shows an embodiment in which the sidewalls of the first nanostructures 52 are concave, the outer sidewalls of the first interior spacers 90 are concave, and the first interior spacers are recessed from the sidewalls of the second nanostructures 54 in the N-type region 50N. As shown with respect to the N-type region 50N, an epitaxial source/drain region 92 may be formed in contact with the first interior spacer 90 and may extend beyond the sidewalls of the second nanostructure 54. Also shown is an embodiment in which the sidewalls of the second nanostructures 54 are concave, the outer sidewalls of the first interior spacers 90 are concave, and the first interior spacers are recessed from the sidewalls of the first nanostructures 52 in the P-type region 50P. As shown with respect to the P-type region 50P, epitaxial source/drain regions 92 may be formed in contact with the first interior spacer 90 and may extend beyond sidewalls of the second nanostructure 54.

In fig. 21A-21C, a first interlayer dielectric (ILD) 96 is deposited over the structure shown in fig. 6A and 20A-20D (the process of fig. 7A-20D does not change the cross-section shown in fig. 6A). The first ILD96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a Contact Etch Stop Layer (CESL) 95 is disposed between the first ILD96 and the epitaxial source/drain regions 92, the mask 78, and the first spacers 81. The CESL 95 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material overlying the first ILD 96.

In fig. 22A-22B, a planarization process, such as CMP, may be performed to level the top surface of the first ILD96 with the top surface of the dummy gate 76 or mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and the portions of the first spacers 81 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD96 are level within process variations. Accordingly, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process aligns the top surface of the first ILD96 with the top surfaces of the mask 78 and the first spacers 81.

In fig. 23A and 23B, dummy gate 76, and mask 78 if present, are removed in one or more etching steps such that second recess 98 is formed. The portion of the dummy dielectric layer 60 in the second recess 98 is also removed. In some embodiments, dummy gate 76 and dummy dielectric layer 60 are removed by an anisotropic dry etch process. For example, the etch process may include a dry etch process using one or more reactive gases that selectively etch the dummy gate 76 at a faster rate than the first ILD96 or the first spacer 81. Each second recess 98 exposes and/or covers portions of the nanostructures 55, which serve as channel regions for subsequently completed nano-FETs. The portion of the nanostructure 55 that serves as a channel region is disposed between adjacent pairs of epitaxial source/drain regions 92. During removal, the dummy dielectric layer 60 may serve as an etch stop when the dummy gate 76 is etched. Then, after removing the dummy gate 76, the dummy dielectric layer 60 may be removed.

In fig. 24A and 24B, the first nanostructures 52 in the N-type region 50N and the second nanostructures 54 in the P-type region 50P are removed, extending the second groove 98. The first nanostructures 52 may be removed by forming a mask (not shown) over the P-type region 50P and performing an isotropic etching process, such as a wet etch or similar process, using an etchant that is selective to the material of the first nanostructures 52, while the second nanostructures 54, the substrate 50, the STI regions 68 remain relatively unetched as compared to the first nanostructures 52. In embodiments where the first nanostructures 52 comprise, for example, SiGe, and the second nanostructures 54A-54C comprise, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH)₄OH), or the like may be used to remove the first nanostructures 52 in the N-type region 50N.

The second nanostructures 54 in the P-type region 50P may be removed by forming a mask (not shown) over the N-type region 50N and performing an isotropic etching process, such as a wet etch or similar process, using an etchant that is selective to the material of the second nanostructures 54, while the first nanostructures 52, the substrate 50, the STI regions 68 remain relatively unetched as compared to the second nanostructures 54. In embodiments where the second nanostructures 54 comprise, for example, SiGe, and the first nanostructures 52 comprise, for example, Si or SiC, hydrogen fluoride, another fluorine-based etchant, or the like may be used to remove the second nanostructures 54 in the P-type region 50P.

In fig. 25A and 25B, the gate dielectric layer 100 and the gate electrode 102 form a replacement gate. A gate dielectric layer 100 is conformally deposited in the second recess 98. In the N-type region 50N, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and on the top surface, sidewalls, and bottom surface of the second nanostructures 54, and in the P-type region 50P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and on the top surface, sidewalls, and bottom surface of the first nanostructures 52. A gate dielectric layer 100 may also be deposited on the top surfaces of the first ILD96, CESL 95, first spacer 81, and STI regions 68.

According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as an oxide, a metal oxide, the like, or combinations thereof. For example, in some embodiments, the gate dielectric may comprise a silicon oxide layer and a metal oxide layer on the silicon oxide layer. In some embodiments, the gate dielectric layer 100 comprises a high-k dielectric material, and in such embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0 and may comprise a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the N-type region 50N and the P-type region 50P. The gate dielectric layer 100 may be formed by a molecular-beam deposition (MBD), ALD, PECVD, or the like.

Gate electrodes 102 are deposited over the gate dielectric layers 100, respectively, and fill the remaining portions of the second recesses 98. The gate electrode 102 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, a combination thereof, or multilayers thereof. For example, although a single layer of the gate electrode 102 is shown in fig. 25A and 25B, the gate electrode 102 may include any number of liner layers, any number of work function adjusting layers, and a filling material. Any combination of layers making up the gate electrode 102 may be deposited in the N-type region 50N between adjacent second nanostructures 54 and between the second nanostructures 54A and the substrate 50, and may be deposited in the P-type region 50P between adjacent first nanostructures 52.

Forming the gate dielectric layers 100 in the N-type region 50N and the P-type region 50P may occur simultaneously such that the gate dielectric layers 100 in each region are formed of the same material, and forming the gate electrodes 102 may occur simultaneously such that the gate electrodes 102 in each region are formed of the same material. In some embodiments, the gate dielectric layers 100 in each region may be formed by different processes such that the gate dielectric layers 100 may be different materials and/or have different numbers of layers, and/or the gate electrodes 102 in each region may be formed by different processes such that the gate electrodes 102 may be different materials and/or have different numbers of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate areas.

After filling the second recesses 98, a planarization process, such as CMP, may be performed to remove excess portions of the material of the gate dielectric layer 100 and the gate electrode 102, which are above the top surface of the first ILD 96. Thus, the remaining portions of the material of the gate electrode 102 and the gate dielectric layer 100 form the replacement gate structure of the resulting nano-FET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate structure".

In fig. 26A-26C, the gate structure (including the gate dielectric layer 100 and the respective overlying gate electrode 102) is recessed such that a recess is formed directly above the gate structure and between opposing portions of the first spacer 81. A gate mask 104 comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess followed by a planarization process in order to remove excess portions of the dielectric material extending over the first ILD 96. Subsequently formed gate contacts, such as gate contact 114 discussed below with respect to fig. 27A-28C, penetrate through gate mask 104 so as to contact the top surface of recessed gate electrode 102.

As further illustrated by fig. 26A-26C, a second ILD 106 is deposited over the first ILD96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed by a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like.

In fig. 27A-27C, the second ILD 106, the first ILD96, CESL 95, and the gate mask 104 are etched to form a third recess 108 that exposes the surface of the epitaxial source/drain regions 92 and/or the gate structure. The third recess 108 may be formed by etching using an anisotropic etching process, such as RIE, NBE, or the like. In some embodiments, the third recess 108 may be etched through the second ILD 106 and the first ILD96 using a first etch process; a second etch process may be used to etch through gate mask 104; and then a third etch process may be used to etch through CESL 95. A mask, such as photoresist, may be formed and patterned over the second ILD 106 in order to shield portions of the second ILD 106 from the first and second etch processes. In some embodiments, the etching process may overetch, and thus, the third recess 108 extends into the epitaxial source/drain region 92 and/or the gate structure, and the bottom of the third recess 108 may be level with (e.g., at the same level, or at the same distance from) the epitaxial source/drain region 92 and/or the gate structure, or lower (e.g., closer to the substrate). Although fig. 27B shows the third recess 108 as exposing the epitaxial source/drain regions 92 and the gate structure in the same cross-section, in various embodiments, the epitaxial source/drain regions 92 and the gate structure may be exposed in different cross-sections, thereby reducing the risk of shorting subsequently formed contacts. After the third recess 108 is formed, a silicide region 110 is formed over the epitaxial source/drain regions 92. In some embodiments, the silicide regions 110 are formed by: a metal (not shown), such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, capable of reacting with the semiconductor material (e.g., silicon germanium, germanium) of the underlying epitaxial source/drain regions 92 to form silicide or germanide regions is first deposited over the exposed portions of the epitaxial source/drain regions 92, and then a thermal annealing process is performed to form the silicide regions 110. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicide regions 110 are referred to as silicide regions, the silicide regions 110 may also be germanide regions, or silicide-germanide regions (e.g., regions comprising silicide and germanide). In one embodiment, the silicide region 110 comprises TiSi and has a thickness in a range between about 2nm and about 10 nm.

Subsequently, in fig. 28A-28C, contacts 112 and 114 (which may also be referred to as contact plugs) are formed in the third recess 108. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a fill material. For example, in some embodiments, contacts 112 and 114 each comprise a barrier layer and a conductive material (not separately shown) and are electrically coupled to underlying conductive features (e.g., gate electrode 102 and/or silicide region 110 in the illustrated embodiment). The contact 114 is electrically coupled to the gate structure (e.g., the gate electrode 102) and may be referred to as a gate contact, and the contact 112 is electrically coupled to the silicide region 110 and may be referred to as a source/drain contact. The barrier layer may include titanium, titanium nitride, tantalum nitride, or the like. The conductive material 118 may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second ILD 106.

Although fig. 28A-28C illustrate contacts 112 extending to each of the epitaxial source/drain regions 92, the contacts 112 may be omitted from some of the epitaxial source/drain regions 92. For example, although not specifically shown, conductive features (e.g., power rails) may then be attached via the backside of one or more epitaxial source/drain regions 92. For these particular epitaxial source/drain regions 92, the source/drain contacts 112 may be omitted or may be dummy contacts that are not electrically connected to any overlying conductive lines (also not specifically shown).

Embodiments may achieve advantages. For example, embodiments disclosed herein improve yield and effectiveness in forming epitaxial source/drain regions 92. In particular, forming a metal oxide-containing mask layer (e.g., p-mask layer 93 and n-mask layer 94) allows for a thinner mask layer, thereby forming a complete protection layer on critical dimensions that become smaller as technology progresses. Additionally, performing post-deposition processing 200 or 300 on the masking layer achieves additional benefits. First, the post-deposition treatment 200 or 300 converts the smooth exposed surfaces (e.g., smooth exposed surfaces 93S and 94S) of the mask layer to rough exposed surfaces (e.g., rough exposed surfaces 93R and 94R). The rougher exposed surfaces 93B/94B have a lower selectivity for epitaxial growth during formation of the epitaxial source/drain regions 92 than the smoother exposed surfaces 93A/94A. Second, the lower selectivity of epitaxial growth improves critical dimension control by minimizing the number and/or duration of epitaxial etch steps that may be performed for epitaxial growth. Third, reducing epitaxial growth over the mask layer produces a mask layer that can be subsequently removed (e.g., by an isotropic wet etch) without being hindered by larger nodules of epitaxial material or a larger number of nodules of epitaxial material disposed over the mask layer.

In one embodiment, a method includes forming a semiconductor layer over a substrate; etching part of the semiconductor layer to form a first groove and a second groove; forming a first mask layer over the semiconductor layer; performing first heat treatment on the first mask layer, wherein the first heat treatment enables the first mask layer to be densified; etching the first mask layer to expose the first recess; forming a first semiconductor material in the first groove; and removing the first mask layer. In another embodiment, the first semiconductor material comprises at least one of silicon germanium, silicon carbide, phosphorus doped silicon carbide, and silicon phosphide. In another embodiment, performing the first thermal treatment comprises radiation treatment. In another embodiment, performing the first thermal process comprises a plasma process. In another embodiment, the first thermal treatment crystallizes at least a portion of the first mask layer. In another embodiment, after the first thermal treatment, the first mask layer has a rougher upper surface than before the first thermal treatment. In another embodiment, a method includes forming a second mask layer over a semiconductor layer; performing second heat treatment on the second mask layer, wherein the second heat treatment enables the second mask layer to be densified; etching the second mask layer to expose the second recess; and forming a second semiconductor material in the second recess. In another embodiment, one of the first thermal process and the second thermal process further comprises a plasma process.

In one embodiment, a method includes forming a semiconductor layer over a first substrate; etching the semiconductor layer to form a first groove in the first region and a second groove in the second region; depositing a first mask layer above the first area and the second area; roughening the first mask layer; removing the first mask layer from the second region; forming a first epitaxial source/drain region in the second recess; removing the remaining part of the first mask layer; depositing a second mask layer above the first area and the second area; roughening the second mask layer; removing the second mask layer from the first region; forming a second epitaxial source/drain region in the first recess; removing the remaining part of the second mask layer; and forming a gate structure over the semiconductor layer. In another embodiment, roughening the first mask layer includes performing a heat treatment on the first mask layer. In another embodiment, the performing the heat treatment on the first mask layer is performed at a temperature greater than 650 ℃. In another embodiment, the first mask layer comprises a metal oxide. In another embodiment, one of roughening the first mask layer and roughening the second mask layer comprises a heat treatment, and the other comprises a plasma treatment. In another embodiment, one of roughening the first mask layer and roughening the second mask layer further comprises UV radiation treatment. In another embodiment, the first mask layer is amorphous prior to roughening the first mask layer, and wherein at least an upper portion of the first mask layer is crystalline after roughening the first mask layer. In another embodiment, removing the remaining portions of the first mask layer comprises a wet etch using hydrofluoric acid.

In one embodiment, a method includes depositing a mask layer over a substrate, the substrate including a first recess and a second recess; performing post-deposition treatment on the mask layer; anisotropically etching the mask layer to expose the second groove; epitaxially growing a first portion of the semiconductor material over the mask layer and a second portion of the semiconductor material in the second recess, the first portion including a discontinuous nodule; and isotropically etching to remove the mask layer. In another embodiment, performing a post-deposition treatment includes performing a thermal treatment. In another embodiment, performing the post-deposition treatment further comprises performing a plasma treatment. In another embodiment, the post-deposition treatment further comprises a UV treatment.

The foregoing outlines features of various embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

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