阅读说明：本技术 半导体器件及其形成方法 (Semiconductor device and method of forming the same ) 是由 沙哈吉·B·摩尔 于 2021-07-01 设计创作，主要内容包括：本发明提供了一种半导体器件及其形成方法。方法包括：形成延伸到半导体衬底中的隔离区；以及在隔离区上方形成第一多个突出鳍和第二突出鳍。第一多个突出鳍包括远离第二突出鳍的外部鳍和最靠近第二突出鳍的内部鳍。该方法还包括蚀刻第一多个突出鳍以形成第一凹进,从第一凹进生长第一外延区,其中,将第一外延区合并以形成合并的外延区,蚀刻第二突出鳍以形成第二凹进,从第二凹进生长第二外延区。合并的外延区的顶表面在面向第二外延区的一侧比在背离第二外延区的一侧低。(The invention provides a semiconductor device and a forming method thereof. The method comprises the following steps: forming isolation regions extending into the semiconductor substrate; and forming a first plurality of protruding fins and a second plurality of protruding fins over the isolation region. The first plurality of protruding fins includes an outer fin distal from the second protruding fin and an inner fin closest to the second protruding fin. The method also includes etching the first plurality of protruding fins to form a first recess, growing a first epitaxial region from the first recess, wherein the first epitaxial region merges to form a merged epitaxial region, etching the second protruding fins to form a second recess, and growing a second epitaxial region from the second recess. The top surface of the merged epitaxial region is lower on the side facing the second epitaxial region than on the side facing away from the second epitaxial region.)

1. A method of forming a semiconductor device, comprising:

forming isolation regions extending into the semiconductor substrate;

forming a first plurality of protruding fins and a second protruding fin over the isolation region, wherein the first plurality of protruding fins includes an outer fin distal from the second protruding fin and an inner fin closest to the second protruding fin;

etching the first plurality of protruding fins to form a first recess;

growing a first epitaxial region from the first recess, wherein the first epitaxial region is merged to form a merged epitaxial region;

etching the second protruding fin to form a second recess; and

growing a second epitaxial region from the second recess, wherein a top surface of the merged epitaxial region is lower on a side facing the second epitaxial region than on a side facing away from the second epitaxial region.

2. The method of claim 1, further comprising forming a plurality of fin spacers on sidewalls of the first plurality of protruding fins, wherein the plurality of fin spacers includes a first outer fin spacer facing the second epitaxial region and a second outer fin spacer facing away from the second epitaxial region, wherein the second outer fin spacer is taller than the first outer fin spacer.

3. The method of claim 2, wherein the first and second outer fin spacers have bottoms that contact a top surface of the isolation region.

4. The method of claim 2, wherein the plurality of fin spacers further comprises an interior fin spacer between adjacent fins of the first plurality of protruding fins, wherein the interior fin spacer is shorter than the first exterior fin spacer and higher than the second exterior fin spacer.

5. The method of claim 1, wherein the inner and outer fins overlap inner and outer semiconductor strips, respectively, and wherein the first epitaxial region comprises:

an outer portion directly over an outer semiconductor strip and an inner portion directly over the inner semiconductor strip, wherein a first elevation of the outer portion is higher than a second elevation of the inner portion.

6. The method of claim 1, wherein a bottom of the first recess is higher than a top surface of the isolation region.

7. The method of claim 1, further comprising: forming a first silicide region on the merged epitaxial region, wherein the first silicide region is sloped such that a first portion of the first silicide region closer to the second epitaxial region is lower than a second portion of the first silicide region further from the second epitaxial region.

8. The method of claim 7 wherein a tangent formed on the additional top surface of the first silicide region has a tilt angle greater than about 6 degrees.

9. A semiconductor device, comprising:

a semiconductor substrate;

a first plurality of isolation regions and a second plurality of isolation regions extending into the semiconductor substrate;

a first strip group comprising a first plurality of semiconductor strips between the first plurality of isolation regions;

a second strip group comprising at least one second semiconductor strip between the second plurality of isolation regions;

a first fin group including a first plurality of semiconductor fins overlapping corresponding first plurality of semiconductor strips;

a second fin group including at least one second semiconductor fin overlapping with the at least one second semiconductor strip;

a plurality of epitaxial regions each including a portion filling a first recess extending to one of the first plurality of semiconductor fins, wherein the plurality of epitaxial regions are merged to form a merged epitaxial region; and

a second epitaxial region comprising a second portion filling a second recess extending into the at least one second semiconductor fin, wherein a top surface of the merged epitaxial region slopes toward the second epitaxial region, a first portion of the top surface closer to the second epitaxial region being lower than a second portion away from the second epitaxial region.

10. A semiconductor device, comprising:

a plurality of semiconductor fins;

a plurality of gate stacks on top surfaces and sidewalls of the plurality of semiconductor fins;

a plurality of epitaxial regions between and joining sidewalls of two of the plurality of semiconductor fins, respectively, wherein the plurality of epitaxial regions are merged into a merged epitaxial region and an outermost epitaxial region of the plurality of epitaxial regions is the shortest of the plurality of epitaxial regions;

a silicide region in contact with a top surface of the merged epitaxial region; and

a contact plug over and in contact with the silicide region.

Technical Field

Embodiments of the invention relate to semiconductor devices and methods of forming the same.

Background

In the formation of a finfet, source/drain regions are typically formed by forming a semiconductor fin, recessing the semiconductor fin to form a recess, and growing an epitaxial region from the recess. The epitaxial regions grown from the recesses of adjacent semiconductor fins may merge with one another, and the resulting epitaxial regions may have a planar top surface. Source/drain contact plugs are formed to be electrically connected to the source/drain regions.

Disclosure of Invention

According to an aspect of an embodiment of the present invention, there is provided a method of forming a semiconductor device, including: forming isolation regions extending into the semiconductor substrate; forming a first plurality of protruding fins and a second protruding fin over the isolation region, wherein the first plurality of protruding fins comprises: an outer fin distal to the second protruding fin and an inner fin closest to the second protruding fin; etching the first plurality of protruding fins to form a first recess; growing a first epitaxial region from the first recess, wherein the first epitaxial region is merged to form a merged epitaxial region; etching the second protruding fin to form a second recess; and growing a second epitaxial region from the second recess, wherein a top surface of the merged epitaxial region is lower on a side facing the second epitaxial region than on a side facing away from the second epitaxial region.

According to another aspect of an embodiment of the present invention, there is provided a semiconductor device including: a semiconductor substrate; a first plurality of isolation regions and a second plurality of isolation regions extending into the semiconductor substrate; a first strip group comprising a first plurality of semiconductor strips between a first plurality of isolation regions; a second strip group comprising at least one second semiconductor strip between a second plurality of isolation regions; a first fin group including a first plurality of semiconductor fins overlapping corresponding first plurality of semiconductor strips; a second fin group including at least one second semiconductor fin overlapping with the at least one second semiconductor strip; a plurality of epitaxial regions, each epitaxial region including a portion filling a first recess extending to one of the first plurality of semiconductor fins, wherein the plurality of epitaxial regions are merged to form a merged epitaxial region; and a second epitaxial region including a second portion filling a second recess extending into the at least one second semiconductor fin, wherein a top surface of the merged epitaxial region slopes toward the second epitaxial region, a first portion near the top surface of the second epitaxial region being lower than a second portion away from the second epitaxial region.

According to still another aspect of an embodiment of the present invention, there is provided a semiconductor device including: a plurality of semiconductor fins; a plurality of gate stacks on top surfaces and sidewalls of the plurality of semiconductor fins; a plurality of epitaxial regions, each epitaxial region between two of the plurality of semiconductor fins and joining the sidewalls, wherein the plurality of epitaxial regions are merged into a merged epitaxial region, and an outermost epitaxial region of the plurality of epitaxial regions is the shortest of the plurality of epitaxial regions; a silicide region in contact with a top surface of the merged epitaxial region; and a contact plug over and in contact with the silicide region.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1, 2, 3A, 3B, 3C, 4A, 4B, 5-8, 9A, 9B, 10, 11A, and 11B illustrate perspective and cross-sectional views of intermediate stages in forming a fin field effect transistor (FinFET), according to some embodiments.

Fig. 12 illustrates a perspective view of a recess in a semiconductor fin according to some embodiments.

Fig. 13 illustrates a perspective view of a structure having Shallow Trench Isolation (STI) regions and semiconductor fins, in accordance with some embodiments.

Fig. 14 illustrates a process flow for forming n-type and p-type finfets in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. The term spaced relationship is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such.

Fin field effect transistors (finfets) and methods of forming the same are provided. According to some embodiments of the present disclosure, the merged epitaxial region, which is a source/drain region of a FinFET, has an asymmetric profile, where epitaxial regions grown from different fins have different heights, and a top surface of the merged epitaxial region is sloped. Accordingly, when the source/drain silicide regions and the source/drain contact plugs are formed to be connected to the epitaxial region, both the top surface and the sidewalls of the epitaxial region are in contact with the source/drain silicide regions, and thus the contact resistance is reduced. The embodiments discussed herein will provide examples to enable or use the subject matter of the present disclosure, and one of ordinary skill in the art will readily appreciate modifications that may be made while remaining within the intended scope of the various embodiments. Like reference numerals are used to indicate like elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

Fig. 1, 2, 3A, 3B, 3C, 4A, 4B, 5-8, 9A, 9B, 10, 11A, and 11B illustrate cross-sectional views of an intermediate stage in a FinFET and corresponding source/drain region formation process, according to some embodiments of the present disclosure. The corresponding flow is also reflected schematically in the flow shown in fig. 14.

Fig. 1 shows a perspective view of the initial structure. The initial structure includes a wafer 10, the wafer 10 further including a substrate 20. The substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The top surface of the substrate 20 may have a (100) surface plane. The substrate 20 may be doped with p-type or n-type impurities. Isolation regions 22, such as Shallow Trench Isolation (STI) regions, may be formed to extend from the top surface of the substrate 20 into the substrate 20. In the process flow shown in fig. 14, the corresponding process is shown as process 202. The portions of the substrate 20 between adjacent STI regions 22 are also referred to as semiconductor strips 24. According to some embodiments, the top surfaces of the semiconductor strips 24N and 24P and the top surface of the STI region 22 may be substantially flush with each other.

STI regions 22 may include a pad oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The liner oxide may also be a deposited silicon oxide layer using, for example, Atomic Layer Deposition (ALD), High Density Plasma Chemical Vapor Deposition (HDPCVD), or Chemical Vapor Deposition (CVD). The STI region 22 may also include a dielectric material over the pad oxide, where the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin coating, or the like.

The wafer 10 includes a first device region and a second device region adjacent to each other. Each device region is used to form a FinFET therein. The FinFET formed in each of the first and second device regions may be an n-type FinFET or a p-type FinFET. In an example embodiment, the first device region is used to form an n-type FinFET and the second device region is used to form a p-type FinFET. Accordingly, the first device region and the second device region are referred to as device regions 100N and 100P, respectively. To distinguish the components in the N-type device region 100N and the P-type device region 100P from each other, the components formed in the N-type device region 100N may be denoted by a reference numeral followed by the letter "N" and the components formed in the P-type device region 100P may be denoted by a reference numeral followed by the letter "P". For example, the semiconductor strips 24 in the N-type device regions 100N are referred to as 24N and the semiconductor strips 24 in the P-type device regions 100P are referred to as 24P. According to some embodiments, semiconductor strips 24N are formed of (or include) silicon (without germanium), while semiconductor strips 24P are replaced with silicon germanium. According to alternative embodiments, semiconductor strips 24N and 24P are each formed of or include silicon that does not include germanium.

Referring to fig. 2, the STI region 22 is recessed such that the tops of the semiconductor strips 24N and 24P protrude higher than the top surface 22A of the STI region 22 to form protruding fins 24N 'and 24P', respectively. In the process flow shown in fig. 14, the corresponding process is shown as process 204. The portions of semiconductor strips 24N and 24P in STI regions 22 are still referred to as semiconductor strips. The etching may be performed using a dry etching process in which HF and NH may be mixed₃The mixture of (a) is used as an etching gas. NF may also be used₃And NH₃The mixture of (a) is used as an etching gas to perform etching. During the etching process, plasma may be generated. Argon may also be included. In accordance with an alternative embodiment of the present disclosure, the recessing of the STI regions 22 is performed using a wet etch process. The etching chemistry may include, for example, an HF solution.

According to some embodiments, the fins used to form the finfets may be formed/patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine lithographic and self-aligned processes, allowing for the generation of patterns with, for example, pitches smaller than those obtainable using single pass direct lithography. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the fin may then be patterned using the remaining spacers or mandrels.

Referring to fig. 3A, 3B, and 3C, a dummy gate stack 30 is formed on the top surface and sidewalls of the protruding fins 24N 'and 24P'. The corresponding process is shown as process 206 in the process flow shown in fig. 14. The section shown in FIG. 3B is taken from reference sections B1-B1 and B2-B2 in FIG. 3A. In fig. 3B and subsequent fig. 11B, the level of the top surface 22A (also refer to fig. 3A) of the STI region 22 may be shown, and the semiconductor fin 24' is higher than the top surface 22A. A bottom surface 22B (also refer to fig. 3A) of the STI region 22 is also shown in the cross-sectional view. The STI regions 22 are located at a level between 22A and 22B, and are not shown in fig. 3B and 11B because they are in a different plane from that shown in the figure.

The cross-section shown in fig. 3C is taken from reference cross-section C-C in fig. 3A, except that fig. 3A shows a portion of device region 100P. According to some embodiments, the protruding fins 24N' may be positioned closely to each other to form a fin group. The protruding fins 24P' may also be adjacent to each other to form a fin group. The inner group spacing S1 (fig. 3C) between fins in the same fin group is less than the inner group spacing S2 between adjacent fin groups. According to some embodiments, both fin sets are multi-fin sets, as shown in fig. 3C. According to an alternative embodiment, one of the sets of fins is a single set of fins. For example, the rightmost fin in fig. 3C may not be formed, and thus there is one 2-fin set on the left and one single-fin set on the right. According to some embodiments, each fin group may also include more than two fins.

Dummy gate stack 30 may include a dummy gate dielectric 32 (fig. 3B) and a dummy gate electrode 34 over dummy gate dielectric 32. The dummy gate electrode 34 may be formed using, for example, amorphous silicon or polysilicon, and other materials may also be used. Each dummy gate stack 30 may also include one (or more) hard mask layer(s) 36 on dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon carbonitride, or the like. The length direction of the dummy gate stack 30 is also perpendicular to the length direction of the protruding fin 24'.

Next, gate spacers 38 are formed on sidewalls of the dummy gate stack 30 (fig. 3A and 3C). In the process flow shown in fig. 14, a corresponding process is also shown as process 206. According to some embodiments of the present disclosure, the gate spacer 38 is formed of a dielectric material such as silicon oxynitride (SiCN), silicon nitride, silicon oxynitride (SiOCN), or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. The formation process includes depositing a conformal spacer layer and then performing an anisotropic etch process to form the gate spacers 38 (and fin spacers 39). According to some embodiments of the present disclosure, the gate spacer 38 is a multi-layer gate spacer. For example, each gate spacer 38 may include a SiN layer and a SiOCN layer over the SiN layer. Fig. 3A and 3C also show fin spacers 39 formed on the sidewalls of the protruding fins 24'. In the process flow shown in fig. 14, the various processes are also shown as process 206.

Fin spacers 39 (including 39A, 39B, and 39C) are formed by the same process used to form gate spacers 38, according to some embodiments of the present disclosure. For example, in the process for forming the gate spacers 38, a blanket dielectric layer is deposited to form the gate spacers 38, and when etched, portions may remain on the sidewalls of the protruding fins 24'N and 24P', forming the fin spacers 39.

Referring to fig. 4A and 4B, a first epitaxial mask 40N is formed. FIG. 4B shows reference section B2-B2 of FIG. 4A. As shown in fig. 14, the corresponding process is shown as process 208 in process flow 200. According to some embodiments, the epitaxial mask 40N is formed of a dielectric material, which may be made of SiON, SiOCN, AlO, SiN, SiOC, SiO₂And the like. The material of the epitaxial mask 40N is also different from the material of the fin spacers 39 and the STI regions 22. According to some embodiments of the present disclosure, the epitaxial mask 40N is deposited using a conformal deposition process such as Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), and the like. According to some embodiments, an etch mask 42N is formed, which may be formed of or include photoresist. Other layers such as a bottom anti-reflective coating (BARC) may or may not be formed as part of the etch mask 42N. The etch mask 42N is patterned to cover the N-type FinFET region 100N and expose the P-type FinFET region 100P. An etching process is then performed to remove portions of the epitaxial mask 40N in the P-type FinFET region 100P, while portions of the epitaxial mask 40N in the N-type FinFET region 100N are not removed. The etching process is an isotropic process, which may be dryAn etching process or a wet etching process.

Next, the protruding fin 24P' is recessed by etching, thereby forming a recess 44P. The corresponding process is shown as process 210 in the process flow 200 shown in fig. 14. The etch mask 42N is also removed and may be removed before or after etching the protruding fin 24P'. According to some embodiments, the etching of the protruding fins 24P' is performed until the recess 44P extends to a level below the top of the fin spacers 39 (fig. 4A) and above the top surface of the STI region 22. In fig. 4A, a dashed line is shown to represent an etched portion of the protruding fin 24P'. The dashed lines also show the top surface and sidewalls of the portion of protruding fin 24P' directly below dummy gate stack 30 (see fig. 3B).

According to some embodiments of the present disclosure, the recessing of the protruding fins 24' is performed by a dry etching step. May use a signal such as C₂F₆、CF₄、SO₂、HBr、Cl₂And O₂HBr, Cl₂、O₂And CF₂The mixture of (a) and (b) to perform dry etching. The etching may be anisotropic. According to some embodiments of the present disclosure, as shown in fig. 4B, the sidewalls of the protruding fin 24' facing the recess 40 are substantially vertical and substantially flush with the outer sidewalls of the gate spacer 38. The surface of the sidewall of the protruding fin 24 'facing the recess 40 may be on the (110) surface of the protruding fin 24P'.

According to some embodiments, during the etching of the protruding fins 24', the fin spacers 39 are also etched and their height is reduced. The etching of the fin spacers 39 may be performed while recessing the fins 24', wherein one or more etching gases for etching the fin spacers 39 are added to the etching gas for recessing the protruding fins 24'. According to some embodiments, fin spacers 39 include external fin spacers, such as fin spacers 39A and 39C (fig. 4A), located on the outer sides of the outermost fins in the set of fins. Fin spacers 39 also include internal fin spacers, such as fin spacers 39B1 and 39B2, located between fins in the same fin group. Throughout the description, the outer fin spacers 39 include fin spacers 39C facing the adjacent fin group and fin spacers 39A facing away from the adjacent fin group.

According to some embodiments, the process conditions for etching fin spacers 39 are adjusted such that the height H1 of the outer spacers 39A is higher than the heights H2 and H3 of the inner spacers 39B1 and 39B2, and the inner spacers 39B1 and 39B2 are connected to each other due to the small inner fin pitch. Further, the process for etching the fin spacers is adjusted so that the heights H2 and H3 of the internal spacers 39B1 and 39B2 are greater than the height H4 of the external spacer 39C, thereby obtaining the relationship (H1 > H2& H3 > H4). Height H2 may be greater than, equal to, or less than height H3. The ratio of heights H1, H2, H3, and H4 may also be within a desired range. According to some embodiments, the ratios H1/H2 and H1/H3 may be greater than about 1.05, and may range between about 10nm and about 30 nm. The ratio of H2/H4 and H3/H4 may be greater than about 1.2, and may range between about 5nm to about 20 nm.

Such as CF may be used₄、O₂And N₂NF of₃And O₂Mixture of (1), SF₆、SF₆And O₂The mixture of (a) and (b) to perform the etching of the fin spacers. The gas is used to bombard the outer spacer 39A, such as argon. The adjusted process conditions include, but are not limited to, partial pressures of the etching gas and the bombardment gas, bias voltage, and the like. Furthermore, the loading effect may be used to help achieve a desired height of the fin spacers. For example, the ratio S2/S1, i.e., the ratio of the inner group spacing S2 to the inner group spacing S1, may be adjusted to adjust the loading effect so that the heights H1, H2, H3, and H4 may be adjusted.

According to some embodiments, after etching the protruding fin 24P', an additional etching process is performed to further etch the fin spacer 39 and adjust the height of the protruding fin 39. According to an alternative embodiment, the etching is skipped. The etch process, if performed, may also be performed using an anisotropic etch process using, for example, a process gas similar to that used in the formation of the fin spacers. According to some embodiments, the formation of fin spacers 39 may not achieve this relationship (H1 > H2& H3 > H4). For example, in previous formation of fin spacers 39, heights H2 and H3 may be disadvantageously less than height H4. An etch process is performed to adjust the height of the fin spacers. Alternatively, the relationship (H1 > H2 and H3 > H4) may have been achieved by previously formed fin spacers 39, but the ratio between fin spacer heights H1, H2, H3, and H4 is not satisfactory. Therefore, an additional etching process may be performed to adjust the ratio to a desired value.

Fig. 5 illustrates the formation of epitaxial region 48P, which may include epitaxial layers 48PA, 48PB, and 48PC, in accordance with some embodiments. As shown in fig. 14, the corresponding process is shown in process stream 212 as process 212. The epitaxial layers 48PA, 48PB, and 48PC are formed by a selective epitaxial process. The deposition of epitaxial layers 48PA, 48PB, and 48PC may be performed using RPCVD, PECVD, or the like. According to some embodiments, the deposition of epitaxial layer 48PA is performed by a non-conformal deposition process such that the bottom portion of epitaxial layer 48PA is thicker than the sidewall portions. According to some embodiments, epitaxial layers 48PA, 48PB, and 48PC are formed of or include SiGeB. The process gas may include a silicon-containing gas, such as silane, disilane (Si)₂H₆) Dichlorosilane (DCS), etc., germanium-containing gases such as germane (GeH)₄) Digermane (Ge)₂H₆) Etc., and a process gas containing a dopant, such as B₂H₆And the like. The boron concentration of epitaxial layer 48PA may be about 1 x 10²⁰/cm³To about 6X 10²⁰/cm³Within the range of (1). The atomic percent of germanium may range between about 15% to about 40%, and may be graded with an upper portion having a higher atomic percent of germanium than a corresponding lower portion.

Epitaxial layer 48PB may have a higher boron concentration than the boron concentration in epitaxial layer 48 PA. For example, according to some embodiments, the boron concentration in epitaxial layer 48PB may be about 6 x 10²⁰/cm³To about 3X 10²¹/cm³Within the range of (1). In addition, the atomic percent of germanium in epitaxial layer 48PB is higher than the atomic percent of germanium in epitaxial layer 48 PA. For example, according to some embodiments, the atomic percent of germanium in epitaxial layer 48PB may range between about 40% to about 60%.

The top end of the epitaxial layer 48PB is near the top end of the protruding fin 24P'. Fig. 11B illustrates a cross-sectional view of reference section B2-B2 in fig. 5, which shows that the opposite ends of epitaxial layer 48PB are flush with the top surface of protruding fin 24P ', while the surface of the top, middle portion epitaxial layer 48PB may be lower, flush with, or slightly higher than the top surface of protruding fin 24P'. As shown in fig. 5, epitaxial layers 48PB grown from adjacent recesses are merged and air gaps 46P are sealed beneath epitaxial layers 48 PB. The top surface of the merged epitaxial layer 48PB may have a non-planar profile (also referred to as having an undulating (concave) shape) with the intermediate portions between adjacent fins 24P' (and corresponding recesses 44P) being lower than the portions on opposite sides thereof. Further, the left portion of the epitaxial layer 48PB closer to the protruding fin 24N' is shorter than the right portion of the epitaxial layer 48 PB.

The top surface of the epitaxial layer 48PC may have a non-waved (convex) shape. Further, the top surface is highest on the right side and lower on the left side. According to some embodiments, epitaxial layer 48PC comprises silicon SiGeB. According to some embodiments, the boron concentration in epitaxial layer 48PC may be about 8 x 10²⁰/cm³To about 1X 10²¹/cm³Within the range of (1). Further, the atomic percent of germanium in epitaxial layer 48PC is lower than the atomic percent of germanium in epitaxial layer 48 PB. For example, according to some embodiments, the atomic percent of germanium in epitaxial layer 48PC may range between about 45% to about 55%. Throughout the specification, the epitaxial layers 48PA, 48PB, and 48PC are collectively referred to as an epitaxial layer (region) 48P, and hereinafter also collectively referred to as a source/drain region 48P.

The deposition process for forming each of the epitaxial layers 48PA, 48PB, and 48PC may include an etch-back process after deposition. The etch back may be performed using an etching gas (e.g., HCl) and may or may not include, for example, SiH₄The silicon-containing gas of (1). The etch back results in and improves the formation of (111) facets.

Throughout the specification, the protruding fins 24P 'and 24N' (the second and third protruding fins from the left) of the fin group closest to its adjacent fin group 24N 'are referred to as inner fins, and the protruding fins 24P' and 24N '(the first and fourth protruding fins from the left) of the fin group farthest from the adjacent fin group 24N' are referred to as outer fins. Similarly, the portion of the epitaxial region grown based on the inner fin is referred to as the inner portion, and the portion of the epitaxial region grown based on the outer fin is referred to as the outer portion. Since the fin spacers have heights that conform to the relationship (H1 > H2 and H3 > H4), epitaxial layers 48PB and 48PC have asymmetric profiles with inner portions of epitaxial layers 48PB and 48PC being shorter than outer portions of epitaxial layers 48PB and 48 PC. For example, the elevated height RH1 of the top of the inner portion of epitaxial layer 48PB is lower than the elevated height RH2 of the top of the outer portion of epitaxial layer 48 PB. The raised height is the height of epitaxial region 48P above the corresponding protruding fin 24P'. The height difference (RH2-RH1) may be greater than about 2nm, and may range between about 2nm to about 15 nm. Further, height H5 may be less than height H6 and height H7 may be less than H8, meaning that the height of the epitaxial region generally tends to decrease from the outer portion to the inner portion. In general, if referenced to a centerline 50P between the inner and outer fins 24P 'and 24P', the inner portions of the epitaxial region 48P are shorter than the corresponding outer portions. Furthermore, the top surface of epitaxial region 48P slopes toward its neighboring set of fins due to the adjusted heights H1, H2, H3, and H4 of fin spacers 39.

After the epitaxial region 48P is formed, the epitaxial mask 40N is removed. The corresponding process is shown as process 214 in the process flow 200 shown in fig. 14. Next, as shown in fig. 6, an epitaxial mask 40P is formed to protect the epitaxial region 48P while leaving the N-type device region 100N open. As shown in fig. 14, the corresponding process is shown as process 216 in process flow 200. The etch mask 42P may be formed for patterning the epitaxial mask 40P and removed after patterning the epitaxial mask 40P. The protruding fin 24N' is recessed to form a recess 44N. As shown in fig. 14, the corresponding process is shown in process flow 200 as process 218. According to some embodiments, the top surface of the remaining protruding fins 24N' is lower than the top end of the fin spacer 39. During the process of etching the protruding fins 24N ', the fin spacers 39 are also recessed to reach the relationship (H1' > H2' and H3' > H4 '). According to some embodiments, after recessing protruding fin 24N ', an additional etching process is used to further etch fin spacers 39 and adjust the height of protruding fins 39 such that the relationships (H1' > H2' and H3' > H4') are reached and the ratios between fin spacer heights H1', H2', H3' and H4' are adjusted to obtain the desired ratios. In the additional etching process, the protruding fin 24N' is not recessed. According to an alternative embodiment, the additional etching process is skipped.

Fig. 7 illustrates a selective epitaxy process for forming epitaxial layers 48NA, 48NB, and 48NC in N-type FinFET region 100N. The corresponding process is shown as process 220 in the process flow shown in fig. 14. The cross-sectional pattern of epitaxial layers 48NA, 48NB, and 48NC in reference section B1-B1 can also be found in fig. 11B. According to some embodiments, the deposition of epitaxial layers 48NA, 48NB, and 48NC may be performed using RPCVD, PECVD, or the like. In the discussion of epitaxial layers 48NA, 48NB, and 48NC (fig. 11A and 11B), phosphorous is used as an exemplary n-type dopant, other n-type dopants (e.g., arsenic, antimony, etc.) or combinations thereof may also be used. Also, in the epitaxial layers 48PA, 48PB, and 48PC (fig. 11A and 11B) discussed above, boron is discussed as an example of a p-type dopant, but other p-type dopants, such as indium, may be used.

According to some embodiments, the epitaxial layer 48NA is formed of or includes silicon phosphorous (SiP). The epitaxial layer 48NA may have a thickness of about 1 × 10²⁰/cm³And about 8X 10²⁰/cm³With a dopant concentration (e.g., P or As). In a deposition process, an etching gas, such as HCl, is added to the process gas to achieve selective deposition on the semiconductor rather than the dielectric. A carrier gas such as H₂And/or N₂May also be included in the process gas, for example, at a flow rate in a range between about 500sccm to about 5000 sccm.

According to some embodiments, epitaxial layer 48NB includes SiP with a second phosphorus concentration higher than the phosphorus concentration in epitaxial layer 48 NA. For example, according to some embodiments, the phosphorus concentration in epitaxial layer 48NB may be about 8 x 10²⁰/cm³To about 5X 10²¹/cm³Within the range of (1). The process gases used to form epitaxial layer 48NB may be similar to the process gases used in forming epitaxial layer 48 NA.

As shown in fig. 7, the top end of the epitaxial layer 48NB is close to the top end of the protruding fin 24N 'and may be higher or lower than the top end of the protruding fin 24N'. Epitaxial layers 48NB grown from adjacent recesses are merged and air gaps 46N are sealed beneath epitaxial layers 48 NB. The top surface of the merged epitaxial layer 48NB may have a non-planar profile (also referred to as having a wavy shape), with intermediate portions between adjacent semiconductor fins 24N' being lower than portions on opposite sides thereof.

According to some embodiments, epitaxial layer 48NC comprises phosphorus silicon. In addition, germanium may be incorporated, for example, in an atomic percent of germanium between about 1% and about 5%. According to some embodiments, the phosphorus concentration in the epitaxial layer 48NC may be about 1 × 10²¹/cm³To about 3X 10²¹/cm³Within the range of (1). The process gases used to form epitaxial layer 48NC may be similar to the process gases in forming epitaxial layer 48NB, except that a germanium-containing gas such as germane, digermane, or the like may be added. Throughout the description, epitaxial layers 48NA, 48NB, and 48NC are collectively referred to as epitaxial layers or epitaxial regions 48N, and hereinafter also collectively referred to as source/drain regions 48N.

The deposition process for forming each of the epitaxial layers 48NA, 48NB, and 48NC may include an etch-back process after deposition. The etch back may be performed using an etching gas (e.g., HCl) and may or may not include, for example, SiH₄The silicon-containing gas of (1). The etch back results in and improves the formation of (111) facets. Further, epitaxial layers 48NA, 48NB, and 48NC may have (110) facets formed.

Since fin spacer 39 has heights (H1'> H2' and H3'> H4') with the following relationships, epitaxial layers 48NB and 48NC have asymmetric profiles with the inner portions of epitaxial layers 48NB and 48NC grown from the recess of the inner fin being shorter than the outer portions of epitaxial layers 48NB and 48NC grown from the recess of the outer fin. For example, the raised height RH3 of the top of the inner portion of epitaxial layer 48NC is lower than the raised height RH4 of the top of the outer portion of epitaxial layer 48 NC. The height difference (RH4-RH3) may be greater than about 2nm, and may range between about 2nm and about 10 nm. Furthermore, height H5 'may be less than height H6', and height H7 'may be less than H8', meaning that the height decreases with conventional trenches from the outer portion to the inner portion of source/drain region 48N. In general, if referenced to the centerline 50N, the inner portions of the epitaxial region 48N are lower than the corresponding outer portions.

After formation of epitaxial region 48N, epitaxial mask 40P is removed and the resulting structure is shown in fig. 8. In the process flow 200 shown in fig. 14, the corresponding process is shown as process 222. Next, referring to fig. 9A, a Contact Etch Stop Layer (CESL)52 and an interlayer dielectric (ILD)54 are formed over the epitaxial regions 48P and 48N and over the dummy gate stack 30 (fig. 3A and 4B). The corresponding process is shown as process 224 in process flow 200 shown in fig. 14. A planarization, such as a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process, is performed to remove excess portions of the CESL 52 and ILD 54 until the dummy gate stack 30 (fig. 8) is exposed.

As shown in fig. 9B, the dummy gate stack 30 is replaced with a replacement gate stack 56 (fig. 3A and 4B). In the process flow shown in fig. 14, the corresponding process is shown as process 226. It should be understood that the illustrated epitaxial region 48P is shown as being based on a single fin-set, but it may also be formed based on two fin-sets, as shown in fig. 9A. The replacement gate stack 56 includes a gate dielectric 58, the gate dielectric 58 further including an interfacial layer 58A (fig. 11B) on the top surface and sidewalls of the protruding fin 24', and a high-k dielectric 58B (fig. 11B) on the interfacial layer 58A. The replacement gate stack 56 also includes a gate electrode 60 over the high-k dielectric 58B. Referring again to fig. 9B, after forming the replacement gate stack 56, the replacement gate stack 56 is recessed to form trenches between the gate spacers 38. A dielectric material such as silicon nitride, silicon oxynitride, or the like is filled into the resulting trench. A hard mask 62 is formed (fig. 9B).

Next, referring to fig. 10, the ILD 54 and CESL 52 are etched to form source/drain contact openings 64. In the process flow shown in fig. 14, the corresponding process is shown as process 228. Epitaxial layers 48NC and 48PC are also etched through. And the top surfaces of epitaxial layers 48NB and 48PB are exposed. The etch can be controlled to stop on epitaxial layers 48NB and 48PB with little over-etching of epitaxial layers 48NB and 48 PB. For example, opening 64 may extend into epitaxial regions 48NB and 48PB to a depth in a range between about 1nm and about 3 nm. The exposed top surfaces of the epitaxial layers 48NB and 48PB are waved with recessed portions lower than the opposite portions on the opposite sides of the middle portion, so that the exposed top surfaces of the epitaxial layers 48NB and 48PB have a V-shaped cross-sectional view. The etch of ILD 54 is controlled so that openings 64 extend downward and also etch some of the side corners of epitaxial regions 48NC and 48PC and the sidewalls of epitaxial layers 48NB and 48PB are exposed and some of the side corner portions may be removed. Because the top surfaces of the inner portions of epitaxial regions 48N and 48P are lower than the top surfaces of the corresponding outer portions, it is easier to clean the bottom of opening 64.

Next, as shown in fig. 11A and 11B, source/drain silicide regions 66N and 66P are formed. In the process flow shown in fig. 14, the corresponding process is shown as process 230. FIG. 11B shows a cross-sectional view in reference sections B1-B1 and B2-B2 in FIG. 11A, and FIG. 11A shows a cross-sectional view in reference section C-C in FIG. 11B. The reference sections B1-B1, B2-B2, C-C are also the same as in FIG. 3A. In accordance with some embodiments of the present disclosure, the formation of source/drain silicide regions 66N and 66P includes depositing a metal layer, such as a titanium layer, a cobalt layer, etc., that extends into opening 64 (fig. 10), and then performing an annealing process to react the bottom of the metal layer with epitaxial layers 48NB and 48PB to form silicide regions 66N and 66P, respectively. The remaining unreacted metal layer may be removed. Source/drain contact plugs 68 are then formed in the trenches 64 and electrically connected to the source/drain silicide regions 66N and 66P. In the process flow shown in fig. 14, the corresponding process is shown as process 232. N-type FinFET 70N and P-type FinFET 70P are thereby formed, and source/drain regions 48N and 48P are electrically interconnected by contact plug 68.

As shown in fig. 11A, the top surface of each of the epitaxial regions 48P and 48N is asymmetric and sloped, with the top surface of the inner portion being lower than the respective outer portion. The silicide regions 66N and 66P are correspondingly sloped. According to some embodiments, the top surface of the inner portion of each silicide region 66N and 66P is lower than the corresponding outer portion by a height difference Δ H1 and Δ H2, which may be greater than about 2nm, and may range between about 2nm to about 10 nm. Also, if the tangent line 67 is formed on the top surface of the silicide regions 66N and 66P, the inclination angles θ 1 and θ 2 may be greater than about 6 degrees, and may range between about 6 degrees and about 45 degrees, or between about 20 degrees and about 45 degrees.

It is observed that by forming an asymmetric profile for epitaxial regions 48N and 48P, and by making the inner portions of the epitaxial regions lower than the corresponding outer portions, silicide sides 66N 'and 66P' are formed (and are enlarged) in addition to the portions of silicide regions 66N and 66P directly above epitaxial regions 48N and 48P. This results in an increase in contact area and a decrease in contact resistance. In comparison, if the epitaxial regions 48N and 48P are formed to have a symmetrical profile, the portions 66N 'and 66P' of the silicide regions may not be formed or may be smaller, and the contact area and contact resistance will be higher.

In the above examples, n-type source/drain regions and p-type source/drain regions are discussed and illustrated as examples. According to other embodiments, both finfets may be n-type finfets or p-type finfets. These figures are similar to those shown in fig. 11A, except that the flip symmetry of the two n-type finfets or p-type finfets is higher. Also, one of the fin groups may be a single fin group, and the other may be a multi-fin group. Although two fin sets are exemplified, the fin set may include three fins or more. In addition, although in the above examples, the p-type epitaxial region is formed before the n-type epitaxial region is formed, according to an alternative embodiment, the n-type epitaxial region may also be formed before the p-type epitaxial region is formed.

Fig. 12 shows a perspective view of the structure, showing recesses 44N and 44P and protruding fins 24N 'and 24P'. It should be understood that the recesses 44N and 44P may be formed in the same etching process, and thus may coexist at the same time. Alternatively, the recesses 44N and 44P may be formed by different processes, and thus may not exist at the same point in time, as shown in fig. 4A and 6.

Fig. 13 shows a schematic diagram of N-type FinFET 68N and P-type FinFET 68P. The silicide regions and contact plugs are not shown. Epitaxial region 48N of N-type FinFET 70N and epitaxial region 48P of P-type FinFET 70P also have asymmetric profiles. According to some embodiments, height H48N of epitaxial region 48N is greater than height H48P of epitaxial region 48P. Also, the height H22N of the STI region 22N in the inner group spacing of the corresponding group of fins in the N-type FinFET 70N is shallower than the STI region 22P in the inner group spacing of the corresponding group of fins in the P-type FinFET 70P.

In the example shown in fig. 13, the portion of epitaxial region 48P on the inner fin that faces epitaxial region 48N is shorter than the portion of epitaxial region 48P on the outer fin that faces away from epitaxial region 48N. The portion of epitaxial region 48N on the inner fin facing epitaxial region 48P is shorter than the portion of epitaxial region 48N on the outer fin facing away from epitaxial region 48P. According to other embodiments, the portion of epitaxial region 48P on the inner fin facing epitaxial region 48N may be higher than the portion of epitaxial region 48P on the outer fin facing away from epitaxial region 48N. The portion of epitaxial region 48N on the inner fin facing epitaxial region 48P may also be higher than the portion of epitaxial region 48N on the outer fin facing away from epitaxial region 48P. These embodiments may be implemented by forming the illustrated epitaxial region 48N while an additional N-type epitaxial region (not shown) on its right side in a first formation process, and forming the illustrated epitaxial region 48P while an additional P-type epitaxial region (not shown) on its left side in a second formation process.

Embodiments of the present disclosure have some advantageous features. By forming the epitaxial regions with asymmetric profiles, the source/drain silicide regions can extend to the sidewalls of the corresponding epitaxial source/drain regions, thereby reducing contact resistance. Further, since the inner portion of the epitaxial region is short, cleaning of the opening bottom is easy.

According to some embodiments of the disclosure, a method comprises: forming isolation regions extending into the semiconductor substrate; forming a first plurality of protruding fins and a second protruding fin over the isolation region, wherein the first plurality of protruding fins comprises: an outer fin distal to the second protruding fin and an inner fin closest to the second protruding fin; etching the first plurality of protruding fins to form a first recess; growing a first epitaxial region from the first recess, wherein the first epitaxial region is merged to form a merged epitaxial region; etching the second protruding fin to form a second recess; and growing a second epitaxial region from the second recess, wherein a top surface of the merged epitaxial region is lower on a side facing the second epitaxial region than on a side facing away from the second epitaxial region. In one embodiment, the method further includes forming a plurality of fin spacers on sidewalls of the first plurality of protruding fins, wherein the plurality of fin spacers includes a first outer fin spacer facing the second epitaxial region and a second outer fin spacer facing away from the second epitaxial region, wherein the second outer fin spacer is taller than the first outer fin spacer. In one embodiment, the first and second outer fin spacers have a bottom portion contacting a top surface of the isolation region. In one embodiment, the plurality of fin spacers further includes an inner fin spacer between adjacent fins in the first plurality of protruding fins, wherein the inner fin spacer is shorter than the first outer fin spacer and taller than the second outer fin spacer. In one embodiment, the inner and outer fins overlap the inner and outer semiconductor strips, respectively, and wherein the first epitaxial region comprises: an outer portion directly over the outer semiconductor strips and an inner portion directly over the inner semiconductor strips, wherein a first elevation of the outer portion is higher than a second elevation of the inner portion. In one embodiment, the bottom of the first recess is higher than the top surface of the isolation region. In one embodiment, the method further comprises: a first silicide region is formed on the merged epitaxial region, wherein the first silicide region is sloped such that a first portion of the first silicide region closer to the second epitaxial region is lower than a second portion of the first silicide region further from the second epitaxial region. In one embodiment, a tangent line formed on the additional top surface of the first silicide region has a tilt angle greater than about 6 degrees. In one embodiment, the method further comprises: forming a second silicide region on the second epitaxial region; and forming a contact plug connected to the first silicide region and the second silicide region.

According to some embodiments of the disclosure, a device comprises: a semiconductor substrate; a first plurality of isolation regions and a second plurality of isolation regions extending into the semiconductor substrate; a first strip group comprising a first plurality of semiconductor strips between a first plurality of isolation regions; a second strip group comprising at least one second semiconductor strip between a second plurality of isolation regions; a first fin group including a first plurality of semiconductor fins overlapping corresponding first plurality of semiconductor strips; a second fin group including at least one second semiconductor fin overlapping with the at least one second semiconductor strip; a plurality of epitaxial regions, each epitaxial region including a portion filling a first recess extending to one of the first plurality of semiconductor fins, wherein the plurality of epitaxial regions are merged to form a merged epitaxial region; and a second epitaxial region including a second portion filling a second recess extending into the at least one second semiconductor fin, wherein a top surface of the merged epitaxial region slopes toward the second epitaxial region, a first portion near the top surface of the second epitaxial region being lower than a second portion away from the second epitaxial region. In one embodiment, the first plurality of semiconductor strips includes an outer strip furthest from the second set of fins and an inner strip closest to the second set of fins, wherein an outer portion of the merged epitaxial region that overlaps the outer strip is higher than an inner portion of the merged epitaxial region that overlaps the inner strip. In one embodiment, the merged epitaxial region is of a first conductivity type and the second epitaxial region is of a second conductivity type opposite the first conductivity type. In one embodiment, the merged epitaxial region and the second epitaxial region have the same conductivity type. In one embodiment, the device further comprises a first silicide region on the merged epitaxial region, wherein the first silicide region is sloped, wherein a first portion of the first silicide region closer to the second epitaxial region is lower than a second portion of the first silicide region further from the second epitaxial region. In one embodiment, the device further comprises: a second silicide region on the second epitaxial region, wherein the second silicide region is inclined toward the first silicide region; and a contact plug connected to the first silicide region and the second silicide region. In one embodiment, the device further comprises: a plurality of fin spacers located on sidewalls of the first plurality of semiconductor fins, wherein the plurality of fin spacers includes a first outer fin spacer facing the second epitaxial region and a second outer fin spacer facing away from the second epitaxial region, wherein the second outer fin spacer is taller than the first outer fin spacer. In one embodiment, the plurality of fin spacers further includes an inner fin spacer between adjacent fins in the first plurality of semiconductor fins, wherein a height of the inner fin spacer is less than the second outer fin spacer and greater than a height of the first outer fin spacer.

According to some embodiments of the disclosure, a device comprises: a plurality of semiconductor fins; a plurality of gate stacks on top surfaces and sidewalls of the plurality of semiconductor fins; a plurality of epitaxial regions, each epitaxial region between two of the plurality of semiconductor fins and joining the sidewalls, wherein the plurality of epitaxial regions are merged into a merged epitaxial region, and an outermost epitaxial region of the plurality of epitaxial regions is the shortest of the plurality of epitaxial regions; a silicide region in contact with a top surface of the merged epitaxial region; and a contact plug over and in contact with the silicide region. In one embodiment, the device further comprises: an additional epitaxial region adjacent to the merged epitaxial region, wherein an outermost epitaxial region is closest to the additional epitaxial region in the plurality of semiconductor fins; and a second silicide region in contact with the other top surface of the additional epitaxial region, wherein the contact plug also contacts the second silicide region. In one embodiment, the device further comprises: a plurality of fin spacers located on sidewalls of the plurality of epitaxial regions, wherein the plurality of fin spacers includes a first outer fin spacer on a sidewall of an outermost fin of the plurality of semiconductor fins and a second outer fin spacer on an opposite side of the plurality of semiconductor fins from the first outer fin spacer, wherein the first outer fin spacer is taller than the second outer fin spacer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.