阅读说明：本技术 一种改善栅极特性的mosfet芯片制造工艺 (MOSFET chip manufacturing process for improving grid characteristics ) 是由 潘光燃 胡瞳腾 于 2021-08-12 设计创作，主要内容包括：本发明公开了一种改善栅极特性的MOSFET芯片制造工艺,包括将沟槽区域的隔离氧化层去除,在沟槽外周侧获得第一轻掺杂多晶硅及第二轻掺杂多晶硅,并对沟槽内的轻掺杂多晶硅进行重掺杂,获得第一重掺杂多晶硅,去除剩余的隔离氧化层,在外延层靠近沟槽的区域成型体区和源区,并对第一轻掺杂多晶硅的部分区域进行重掺杂,获得第二重掺杂多晶硅,向上成型介质层,第二重掺杂多晶硅与第一轻掺杂多晶硅的类型相反,以第一轻掺杂多晶硅和第二重掺杂多晶硅组成二极管,以第二轻掺杂多晶硅两端组成电阻,二极管与电阻并联,并串接于栅极上。在芯片内部集成了多晶硅电阻和多晶硅二极管,有效限制流经栅极的电流,实现对栅极的保护。(The invention discloses a MOSFET chip manufacturing process for improving grid characteristics, which comprises the steps of removing an isolation oxide layer in a groove region, obtaining first lightly doped polycrystalline silicon and second lightly doped polycrystalline silicon on the outer peripheral side of the groove, carrying out heavy doping on the lightly doped polycrystalline silicon in the groove to obtain first heavily doped polycrystalline silicon, removing the rest isolation oxide layer, forming a body region and a source region in a region of an epitaxial layer close to the groove, carrying out heavy doping on a partial region of the first lightly doped polycrystalline silicon to obtain second heavily doped polycrystalline silicon, forming a dielectric layer upwards, forming a dielectric layer, wherein the type of the second heavily doped polycrystalline silicon is opposite to that of the first lightly doped polycrystalline silicon, forming a diode by using the first lightly doped polycrystalline silicon and the second heavily doped polycrystalline silicon, forming resistors by using two ends of the second lightly doped polycrystalline silicon, and connecting the diode in parallel to a grid electrode in series. The polycrystalline silicon resistor and the polycrystalline silicon diode are integrated in the chip, so that current flowing through the grid electrode is effectively limited, and the grid electrode is protected.)

1. A MOSFET chip manufacturing process for improving gate characteristics, the MOSFET chip comprises a gate and a polysilicon gate connected with the inside, and is characterized in that: the method comprises the following steps:

step S1: growing an epitaxial layer on the surface of a substrate, forming a groove in the epitaxial layer, and forming a gate oxide layer on the surface of the groove;

step S2: forming lightly doped polysilicon in the trench, and forming an isolation oxide layer upwards;

step S3: removing the isolation oxide layer in the groove region, obtaining first lightly doped polycrystalline silicon and second lightly doped polycrystalline silicon on the outer peripheral side of the groove, and heavily doping the lightly doped polycrystalline silicon in the groove to obtain first heavily doped polycrystalline silicon;

step S4: removing the rest isolation oxide layer, forming a body region and a source region in a region of the epitaxial layer close to the trench, heavily doping a partial region of the first lightly doped polysilicon to obtain second heavily doped polysilicon, and upwardly forming a dielectric layer, wherein the type of the second heavily doped polysilicon is opposite to that of the first lightly doped polysilicon;

step S5: and the diode is connected with the resistor in parallel and connected in series on the grid electrode.

2. The process of manufacturing a MOSFET chip with improved gate characteristics as claimed in claim 1, wherein: step S5 mainly includes the following steps:

step S51: punching holes at two ends of the second lightly doped polysilicon to obtain two resistance contact holes, wherein the resistance contact holes sequentially penetrate through the dielectric layer and the lightly doped polysilicon, the holes are punched in the groove area to obtain source area contact holes, and the source area contact holes sequentially penetrate through the dielectric layer, the gate oxide layer, the source area and the body area;

step S52: punching the first lightly doped polysilicon to obtain a first diode hole, and punching the second heavily doped polysilicon to obtain a second diode hole;

step S53: forming a first metal connecting wire and a second metal connecting wire in the resistor contact hole, forming a third metal connecting wire in the source region contact hole, connecting the first metal connecting wire with the polysilicon gate, and connecting the second metal connecting wire with the gate;

step S54: and forming a fourth metal connecting line and a fifth metal connecting line in the first diode hole and the second diode hole, wherein the fourth metal connecting line is connected with the polysilicon gate, and the fifth metal connecting line is connected with the gate.

3. The process of manufacturing a MOSFET chip with improved gate characteristics according to claim 2, wherein: between the step S52 and the step S53, the method further comprises:

step S100: forming heavily doped silicon regions at the bottoms of the two resistor contact holes, the source region contact hole and the first diode hole respectively;

the heavily doped silicon region is of the opposite type to the MOSFET chip.

4. The process of manufacturing a MOSFET chip with improved gate characteristics as claimed in claim 1, wherein: step S2 mainly includes the following steps:

step S21: depositing initial polysilicon on the surface of the gate oxide layer in the trench region;

step S22: lightly doping the polycrystalline silicon by adopting an ion implantation process method to obtain lightly doped polycrystalline silicon;

step S23: an isolation oxide layer is formed upward.

5. The process of manufacturing a MOSFET chip with improved gate characteristics according to claim 4, wherein: in step S22, lightly doped polysilicon is formed by implanting boron atoms, or implanting phosphorus atoms and/or arsenic atoms;

the type of the lightly doped polysilicon is opposite to that of the MOSFET chip;

the dose of the ion implantation is 2E13-6E14 atoms/square centimeter.

6. The process of manufacturing a MOSFET chip with improved gate characteristics as claimed in claim 1, wherein: in step S3, implanting boron atoms, or implanting phosphorus atoms and/or arsenic atoms into the lightly doped polysilicon to form a first heavily doped polysilicon;

the type of the first heavily doped polysilicon is the same as that of the MOSFET chip;

the dose of the atom implantation is 1E15-2E16 atoms/square centimeter.

7. The process of manufacturing a MOSFET chip with improved gate characteristics as claimed in claim 1, wherein: in step S4, implanting boron atoms or implanting phosphorus atoms and/or arsenic atoms into the first lightly doped polysilicon to form second heavily doped polysilicon by using an ion implantation process;

the dose of the ion implantation is 2E15-2E16 atoms/cm.

8. The process of manufacturing a MOSFET chip with improved gate characteristics as claimed in claim 1, wherein: the type of the body region is opposite to that of the MOSFET chip, and the type of the source region is the same as that of the MOSFET chip.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a MOSFET chip manufacturing process for improving grid characteristics.

Background

The MOSFET chip is a discrete device, belongs to the field of semiconductor power devices, and belongs to the field of semiconductor chips with integrated circuits, wherein the integrated circuits integrate thousands of transistors in one chip through a process method, and the MOSFET is a single transistor formed by juxtaposing thousands of cells with the same structure.

The key index parameters of the MOSFET include breakdown voltage (specifically, drain-source breakdown voltage), on-resistance, threshold voltage, and avalanche current, and generally, the larger the breakdown voltage and avalanche current, the better the on-resistance. In order to realize the nominal breakdown voltage, an epitaxial layer with specific resistivity and specific thickness is adopted in the internal structure of the MOSFET chip to bear pressure, and the higher the breakdown voltage to be realized is, the larger the resistivity or (and) thickness of the epitaxial layer is, the larger the on-resistance of the chip per unit area is, so that the breakdown voltage and the on-resistance per unit area are a pair of contradictory parameters; on the premise of ensuring the set breakdown voltage, the on-resistance of the unit area is reduced to the maximum extent, which is the responsibility of a chip engineer.

The MOSFET chip comprises three ports of a grid electrode, a source electrode and a drain electrode, and the three ports are respectively connected with a polysilicon gate, a drain region and a source region in the chip by adopting metal connecting wires and contact holes. The MOSFET is a voltage control device, that is, a driving circuit controls a potential difference between a gate and a source, thereby controlling on (on) and off (off) of the MOSFET. As shown in fig. 1, which is an equivalent circuit diagram of a MOSFET, parasitic capacitances Cgs, Cgd, and Cds exist between three ports of a gate, a source, and a drain.

In practical applications, the gate of the MOSFET is easily damaged by the impact of a pulse current, so that a current limiting circuit is usually designed in the driving circuit to limit the current flowing through the gate of the MOSFET, thereby protecting the gate of the MOSFET.

Disclosure of Invention

The invention provides a manufacturing process of an MOSFET chip with improved grid characteristics, and aims to solve the problem that the current flowing through a grid cannot be effectively limited in the conventional MOSFET chip.

According to an embodiment of the present application, there is provided a MOSFET chip manufacturing process for improving gate characteristics, the MOSFET chip including a gate and a polysilicon gate connected to the inside, the MOSFET chip manufacturing process including the steps of: step S1: growing an epitaxial layer on the surface of a substrate, forming a groove in the epitaxial layer, and forming a gate oxide layer on the surface of the groove; step S2: forming lightly doped polysilicon in the trench, and forming an isolation oxide layer upwards; step S3: removing the isolation oxide layer in the groove area, obtaining first lightly doped polycrystalline silicon and second lightly doped polycrystalline silicon on the outer peripheral side of the groove, and heavily doping the lightly doped polycrystalline silicon in the groove to obtain first heavily doped polycrystalline silicon; step S4: removing the rest isolation oxide layer, heavily doping a partial region of the first lightly doped polysilicon in a region forming body region and a source region of the epitaxial layer close to the trench to obtain second heavily doped polysilicon, and upwards forming a dielectric layer, wherein the type of the second heavily doped polysilicon is opposite to that of the first lightly doped polysilicon; and step S5: and the diode is connected with the resistor in parallel and connected in series on the grid electrode.

Preferably, step S5 mainly includes the steps of: step S51: punching holes at two ends of the second lightly doped polysilicon to obtain two resistance contact holes, wherein the resistance contact holes sequentially penetrate through the dielectric layer and the lightly doped polysilicon, the holes are punched in the groove area to obtain source area contact holes, and the source area contact holes sequentially penetrate through the dielectric layer, the gate oxide layer, the source area and the body area; step S52: punching the first lightly doped polysilicon to obtain a first diode hole, and punching the second heavily doped polysilicon to obtain a second diode hole; step S53: forming a first metal connecting wire and a second metal connecting wire in the resistor contact hole, forming a third metal connecting wire in the source region contact hole, connecting the first metal connecting wire with the polysilicon gate, and connecting the second metal connecting wire with the gate; and step S54: and forming a fourth metal connecting line and a fifth metal connecting line in the first diode hole and the second diode hole, wherein the fourth metal connecting line is connected with the polysilicon gate, and the fifth metal connecting line is connected with the gate.

Preferably, between step S52 and step S53, further comprising: step S100: forming heavily doped silicon regions at the bottoms of the two resistor contact holes, the source region contact hole and the first diode hole respectively; the type of the heavily doped silicon region is opposite to the type of the MOSFET chip.

Preferably, step S2 mainly includes the steps of: step S21: depositing initial polysilicon on the surface of the gate oxide layer in the trench region; step S22: lightly doping the polycrystalline silicon by adopting an ion implantation process method to obtain lightly doped polycrystalline silicon; step S23: an isolation oxide layer is formed upward.

Preferably, in step S22, lightly doped polysilicon is formed by implanting boron atoms, or implanting phosphorus atoms and/or arsenic atoms; the type of the lightly doped polysilicon is opposite to that of the MOSFET chip; the dose of the ion implantation is 2E13-6E14 atoms/square centimeter.

Preferably, in step S3, implanting boron atoms, or implanting phosphorus atoms and/or arsenic atoms into the lightly doped polysilicon to form a first heavily doped polysilicon; the type of the first heavily doped polysilicon is the same as that of the MOSFET chip; the dose of the atom implantation is 1E15-2E16 atoms/square centimeter.

Preferably, in step S4, the second heavily doped polysilicon is formed by implanting boron atoms or implanting phosphorus atoms and/or arsenic atoms into the first lightly doped polysilicon by an ion implantation process; the dose of the ion implantation is 2E15-2E16 atoms/cm.

Preferably, the type of the body region is opposite to that of the MOSFET chip, and the type of the source region is the same as that of the MOSFET chip.

Compared with the prior art, the manufacturing process of the MOSFET chip with the improved grid characteristic has the following beneficial effects:

1. according to the manufacturing process of the MOSFET chip for improving the grid characteristic, the polycrystalline silicon resistor and the polycrystalline silicon diode are integrated in the MOSFET chip, the polycrystalline silicon resistor is positioned between the polycrystalline silicon gate and the grid port, and the current flowing through the MOSFET grid can be effectively limited, so that the MOSFET grid is protected. The polysilicon diode is positioned between the polysilicon gate and the gate port, when the MOSFET needs to discharge, the polysilicon diode is conducted in the forward direction, and charges in the polysilicon gate flow through the polysilicon diode to discharge quickly, so that the discharge efficiency of the MOSFET gate is improved, the turn-off speed of the MOSFET is accelerated, and the switching loss of the MOSFET is reduced. Further, the grown isolation oxide layer can be used as a barrier layer for heavily doping the polysilicon in the trench region (to block the resistor region from being doped in this step), and can also be used as a barrier layer for etching the heavily doped polysilicon from top to bottom (to block the resistor region from being etched away). Particularly, the process method only needs to grow the polysilicon once, thereby saving the productivity of the polysilicon deposition process and having lower corresponding process cost.

2. The polycrystalline silicon resistor integrated in the MOSFET chip can adjust the resistance value by adjusting the ion implantation dosage of the second lightly doped polycrystalline silicon, and the process is simple.

3. The polycrystalline silicon diode integrated in the MOSFET chip can realize reverse breakdown voltage adjustment of the diode by adjusting the ion implantation dosage of the first lightly doped polycrystalline silicon, and the process is simple.

4. The integrated resistor and the diode are positioned in the MOSFET chip, and the resistor and the diode connected with the MOSFET grid electrode do not need to be designed on the periphery of the MOSFET chip, so that the space of a PCB (printed circuit board) can be saved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a schematic diagram of an equivalent circuit of a MOSFET chip in the prior art.

Fig. 2 is a schematic diagram of an equivalent circuit of a MOSFET chip manufactured by a MOSFET chip manufacturing process for improving gate characteristics according to a first embodiment of the present invention.

Fig. 3 is a flowchart of a MOSFET chip manufacturing process for improving gate characteristics according to a first embodiment of the present invention.

Fig. 4 is a flowchart of step S2 in the MOSFET chip manufacturing process for improving the gate characteristics according to the first embodiment of the present invention.

Fig. 5 is a flowchart of step S5 in the MOSFET chip manufacturing process for improving the gate characteristics according to the first embodiment of the present invention.

Fig. 6 is a schematic view of the structure of an epitaxial layer grown on the surface of a substrate.

Fig. 7 is a schematic structural diagram of a gate oxide layer formed by an oxidation process after a groove is formed by etching.

Fig. 8 is a schematic diagram of a structure for depositing and forming lightly doped polysilicon.

Fig. 9 is a schematic structural diagram of a patterned isolation oxide layer.

Fig. 10 is a schematic structural view of removing the isolation oxide layer of the trench region and performing heavy doping.

Fig. 11 is a schematic structural diagram of adjusting the height of the first heavily doped polysilicon.

Fig. 12 is a schematic structural view of the body region being shaped and the remaining isolation oxide layer being removed.

Fig. 13 is a schematic structural view of the shaped source region and the second heavily doped polysilicon.

Fig. 14 is a schematic view of a structure in which a dielectric layer is formed and perforated upward.

Fig. 15 is a schematic diagram of a structure for forming heavily doped silicon regions at the bottom of contact holes.

Fig. 16 is a schematic diagram of a metal line formed in a contact hole.

Description of reference numerals:

1. a substrate; 2. an epitaxial layer; 3. a groove, 4 and a gate oxide layer; 5. lightly doping polycrystalline silicon; 5.1, first heavily doped polysilicon; 5.2, second heavily doped polysilicon; 5.3, first lightly doped polysilicon; 5.4, second lightly doped polysilicon; 6. isolating the oxide layer; 7. a body region; 8. a source region; 9. a dielectric layer; 10.1, a source region contact hole; 10.2/10.3 resistance contact hole; 11. a heavily doped silicon region; 12.1, a third metal connecting line; 12.2, a first metal connecting line; 12.3, a second metal connecting line; 12.4, a first diode aperture; 12.5, second diode aperture.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without any inventive step, are within the scope of the present invention.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

Referring to fig. 2 and fig. 3, a first embodiment of the present invention discloses a process for manufacturing a MOSFET chip with improved gate characteristics, wherein the MOSFET chip includes a gate (e.g., a gate (port) node in fig. 2) and a polysilicon gate (e.g., a gate node in fig. 2) connected inside, and the process specifically includes the following steps:

step S1: growing an epitaxial layer on the surface of the substrate, forming a groove in the epitaxial layer, and forming a gate oxide layer on the surface of the groove.

Step S2: and forming lightly doped polysilicon in the groove, and forming an isolation oxide layer upwards.

Step S3: and removing the isolation oxide layer in the groove area, obtaining first lightly doped polycrystalline silicon and second lightly doped polycrystalline silicon on the outer peripheral side of the groove, heavily doping the lightly doped polycrystalline silicon in the groove, and adjusting the height of the first heavily doped polycrystalline silicon after obtaining the first heavily doped polycrystalline silicon.

Step S4: and removing the residual isolation oxide layer, forming a body region and a source region in the region of the epitaxial layer close to the trench, heavily doping a partial region of the first lightly doped polysilicon to obtain second heavily doped polysilicon, and upwardly forming a dielectric layer, wherein the type of the second heavily doped polysilicon is opposite to that of the first lightly doped polysilicon. And

step S5: and the diode is connected with the resistor in parallel and connected in series on the grid electrode.

It is to be understood that in step S1, epitaxial layer 2 is grown on the surface of substrate 1, and trenches 3 and gate oxide layer 4 are formed in epitaxial layer 2 by photolithography, etching, and oxidation processes, as detailed in fig. 6 and 7.

It will be appreciated that in step S2, a profiled lightly doped polysilicon 5 is deposited in the region of the trench 3 and a barrier oxide layer 6 is profiled upwardly. This step is the first polysilicon deposition operation in the process. See fig. 8 and 9 for details.

It can be understood that, in step S3, the isolation oxide layer 6 in the region of the trench 3 is removed by photolithography and etching process to obtain the first lightly doped polysilicon 5.3 and the second lightly doped polysilicon 5.4 on the outer peripheral side of the trench 3, and both the first lightly doped polysilicon 5.3 and the second lightly doped polysilicon 5.4 are covered by the isolation oxide layer 6, while the lightly doped polysilicon 5 in the trench 3 is heavily doped to obtain the first heavily doped polysilicon 5.1, during the heavily doped process, both the first lightly doped polysilicon 5.3 and the second lightly doped polysilicon 5.4 are covered by the isolation oxide layer 6 without being affected, and after the first heavily doped polysilicon 5.1 is obtained, the height is adjusted by etching process to be not higher than the height of the trench 3. See figures 10 and 11 for details.

It is to be understood that in step S3, boron atoms, or phosphorus atoms and/or arsenic atoms are implanted into the lightly doped polysilicon 5 to form a first heavily doped polysilicon 5.1, the type of the first heavily doped polysilicon 5.1 is the same as that of the MOSFET chip, and the ion implantation dose is 1E15-2E16 atoms per square centimeter. For example, when the MOSFET is an N-type MOSFET, phosphorus atoms or (and) arsenic atoms are implanted to form N-type first heavily doped polysilicon 5.1, and when the MOSFET is a P-type MOSFET, boron atoms are implanted to form P-type first heavily doped polysilicon 5.1.

It is understood that in step S4, the isolation oxide layer 6 remaining on the surfaces of the first lightly doped polysilicon 5.3 and the second lightly doped polysilicon 5.4 is first removed by etching process. Then, a body region 7 and a source region 8 are formed in the region of the epitaxial layer 2 close to the trench 3, a partial region of the first lightly doped polysilicon 5.3 is heavily doped to obtain second heavily doped polysilicon 5.2, and then a dielectric layer 9 is formed upwards. See figures 12 and 13 for details.

It is understood that in step S4, the second heavily doped polysilicon 5.2 is formed by implanting boron atoms or phosphorus atoms and/or arsenic atoms into the first lightly doped polysilicon 5.3 by an ion implantation process, and the dose of the ion implantation is 2E15-2E16 atoms per square centimeter. For example, when the MOSFET is an N-type MOSFET, the ion-implanted element is phosphorus atoms or (and) arsenic atoms, forming N-type second heavily doped polysilicon 5.2. When the MOSFET is a P-type MOSFET, the ion implanted element is boron atom to form P-type second heavily doped polysilicon 5.2.

The type of ion implantation doping in step S4 is opposite to the light doping type in step S2, but because the ion implantation dosage in this step is much larger than that in step S2, the partial region of the first lightly doped polysilicon 5.3 is inverted into the second heavily doped polysilicon 5.2 after the heavy doping is implanted in this step, i.e., the first lightly doped polysilicon 5.3 and the second heavily doped polysilicon 5.2 are opposite, one of them is P-type, the other is N-type, both form a PN junction made of polysilicon material, contact holes are made at both ends of the PN junction and metal wires are used for leading out, i.e., the complete polysilicon diode.

Further, in step S4, the type of the body region 7 is opposite to that of the MOSFET chip, and the type of the source region 8 is the same as that of the MOSFET chip. For example, when the MOSFET is an N-type MOSFET, boron atoms are implanted to form P-type body region 7, and when the MOSFET is a P-type MOSFET, phosphorus atoms or (and) arsenic atoms are implanted to form N-type body region 7. When the MOSFET is an N-type MOSFET, the ion-implanted element is a phosphorus atom or (and) an arsenic atom to form the N-type source region 8, and when the MOSFET is a P-type MOSFET, the ion-implanted element is a boron atom to form the P-type source region 8.

It can be understood that in step S5, a diode is formed by punching and forming metal connecting lines in the first lightly doped polysilicon 5.3 and the second heavily doped polysilicon 5.2, and a polysilicon resistor is formed by punching holes in the second lightly doped polysilicon 5.4, and the formed diode D is connected in parallel with the polysilicon resistor R and then connected in series with the gate of the MOSFET chip, the specific equivalent circuit diagram is shown in fig. 2, and the process structure is shown in fig. 16.

Referring to fig. 4, step S2 mainly includes the following steps:

step S21: and depositing initial polysilicon on the surface of the gate oxide layer in the trench area.

Step S22: and lightly doping the polycrystalline silicon by adopting an ion implantation process method to obtain the lightly doped polycrystalline silicon.

Step S23: an isolation oxide layer is formed upward.

In step S21, the lightly doped polysilicon 5 is formed by first depositing (chemical vapor deposition process) undoped polysilicon and lightly doping the polysilicon using an ion implantation process based on step S22.

In step S22, lightly doped polysilicon 5 is formed by implanting boron atoms, or implanting phosphorus atoms and/or arsenic atoms, the type of the lightly doped polysilicon 5 being opposite to that of the MOSFET chip. The dose of the ion implantation is 2E13-6E14 atoms/square centimeter. For example, when the MOSFET is an N-type MOSFET, boron atoms are implanted to form P-type lightly doped polysilicon 5, and when the MOSFET is a P-type MOSFET, phosphorus atoms or (and) arsenic atoms are implanted to form N-type lightly doped polysilicon 5.

Referring to fig. 5, step S5 mainly includes the following steps:

step S51: and punching holes at two ends of the second lightly doped polysilicon to obtain two resistance contact holes, wherein the resistance contact holes sequentially penetrate through the dielectric layer and the lightly doped polysilicon, the holes are punched in the groove area to obtain source area contact holes, and the source area contact holes sequentially penetrate through the dielectric layer, the gate oxide layer, the source area and the body area.

Step S52: and punching the first lightly doped polysilicon to obtain a first diode hole, and punching the second heavily doped polysilicon to obtain a second diode hole.

Step S53: and forming a first metal connecting wire and a second metal connecting wire in the resistor contact hole, forming a third metal connecting wire in the source region contact hole, connecting the first metal connecting wire with the polysilicon gate, and connecting the second metal connecting wire with the gate. And

step S54: and forming a fourth metal connecting line and a fifth metal connecting line in the first diode hole and the second diode hole, wherein the fourth metal connecting line is connected with the polysilicon gate, and the fifth metal connecting line is connected with the gate.

It is to be understood that in step S51, two resistor contacts 10.2 and 10.3 are formed by punching holes in both ends of the second lightly doped polysilicon 5.4, and one source contact 10.1 is formed by punching holes in the trench region. See figure 14 for details.

It is to be understood that in step S52, a hole is made in the first lightly doped polysilicon 5.3 to obtain the first diode hole 10.4, and a hole is made in the second heavily doped polysilicon 5.2 to obtain the second diode hole 10.5. See figure 14 for details.

It is understood that in step S53, the first metal line 12.2 and the second metal line 12.3 are respectively formed in the resistor contact holes 10.2 and 10.3, the third metal line 12.1 is formed in the source region contact hole 10.1, the first metal line 12.2 is connected to the polysilicon gate, and the second metal line 12.3 is connected to the gate. The polycrystalline silicon gate and the grid are two different nodes of the grid in the equivalent circuit of the MOSFET chip, and the connection mode of the first metal connecting line 12.2 and the second metal connecting line 12.3 enables the polycrystalline silicon resistor R formed by the second lightly doped polycrystalline silicon 5.4 to be connected in series in the grid in the equivalent circuit of the MOSFET chip. See figure 16 for details.

It is to be understood that in step S54, a fourth metal wire 12.4 and a fifth metal wire 12.5 are formed in the first diode hole 10.4 and the second diode hole 10.5, the fourth metal wire 12.4 is connected to the polysilicon gate, and the fifth metal wire 12.5 is connected to the gate. That is, the polysilicon diode D formed between the first lightly doped polysilicon 5.3 and the second heavily doped polysilicon 5.2 is also connected in series in the gate of the equivalent circuit of the MOSFET chip and is arranged in parallel with the polysilicon resistor R. See figure 16 for details.

It can be understood that, in the embodiment, since the schematic diagram only shows a certain cross section of the MOSFET chip, the contact hole and the metal connection line of the polysilicon gate of the MOSFET, and the gate port of the MOSFET are not shown in the schematic diagram. The main structure of the MOSFET chip is already completed, and the subsequent processes related to the passivation layer and the backside processing of the MOSFET chip belong to the conventional practice and are not described herein again.

Optionally, as an embodiment, between the step S52 and the step S53, the method further includes:

step S100: and forming heavily doped silicon regions at the bottoms of the two resistor contact holes, the source region contact hole and the first diode hole respectively.

It is understood that in step S100, heavily doped silicon region 11 is also formed at the bottom of the two resistor contact holes 10.2 and 10.3, the source contact hole 10.1 and the first diode hole 10.4, respectively. See figure 15 for details.

Specifically, ion implantation is carried out on the bottom of the contact hole, annealing is carried out, a hole bottom heavily doped silicon region 11 is formed, when the MOSFET is an N-type MOSFET, boron atoms are implanted, then annealing is carried out, a P-type hole bottom heavily doped silicon region 11 is formed, when the MOSFET is a P-type MOSFET, phosphorus atoms or (and) arsenic atoms are implanted, then annealing is carried out, an N-type hole bottom heavily doped silicon region 11 is formed, and the dose of ion implantation is 1E 14-5E 14 atoms/square centimeter.

The type of ion implantation doping in step S100 is opposite to the ion implantation heavily doped type in step S4, but the dose of ion implantation in this step is much smaller than that in step S4, so that a (inverted) heavily doped silicon region is not formed at the bottom of the second diode contact hole 10.5. Meanwhile, the doping type of the ion implantation in this step is the same as the doping type of the body region 7 and the lightly doped polysilicon 5, so that the purpose of reducing the contact resistance of the body region and the contact resistance of the lightly doped polysilicon 8 can be achieved.

Compared with the prior art, the manufacturing process of the MOSFET chip with the improved grid characteristic has the following beneficial effects:

1. according to the manufacturing process of the MOSFET chip for improving the grid characteristic, the polycrystalline silicon resistor and the polycrystalline silicon diode are integrated in the MOSFET chip, the polycrystalline silicon resistor is positioned between the polycrystalline silicon gate and the grid port, and the current flowing through the MOSFET grid can be effectively limited, so that the MOSFET grid is protected. The polysilicon diode is positioned between the polysilicon gate and the gate port, when the MOSFET needs to discharge, the polysilicon diode is conducted in the forward direction, and charges in the polysilicon gate flow through the polysilicon diode to discharge quickly, so that the discharge efficiency of the MOSFET gate is improved, the turn-off speed of the MOSFET is accelerated, and the switching loss of the MOSFET is reduced. Further, the grown isolation oxide layer can be used as a barrier layer for heavily doping the polysilicon in the trench region (to block the resistor region from being doped in this step), and can also be used as a barrier layer for etching the heavily doped polysilicon from top to bottom (to block the resistor region from being etched away). Particularly, the process method only needs to grow the polysilicon once, thereby saving the productivity of the polysilicon deposition process and having lower corresponding process cost.

2. The polycrystalline silicon resistor integrated in the MOSFET chip can adjust the resistance value by adjusting the ion implantation dosage of the second lightly doped polycrystalline silicon, and the process is simple.

3. The polycrystalline silicon diode integrated in the MOSFET chip can realize reverse breakdown voltage adjustment of the diode by adjusting the ion implantation dosage of the first lightly doped polycrystalline silicon, and the process is simple.

4. The integrated resistor and the diode are positioned in the MOSFET chip, and the resistor and the diode connected with the MOSFET grid electrode do not need to be designed on the periphery of the MOSFET chip, so that the space of a PCB (printed circuit board) can be saved.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present invention, and these modifications or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.