阅读说明：本技术 耐功率型声表面波滤波器芯片及其搭桥套刻工艺和滤波器 (Power-resistant surface acoustic wave filter chip, bridging overlay process thereof and filter ) 是由 王君 魏家贵 孟腾飞 陈晓阳 徐浩 于海洋 倪烨 袁燕 张倩 崔洋 于 2021-09-07 设计创作，主要内容包括：本发明涉及耐功率型声表面波滤波器芯片及其搭桥套刻工艺和滤波器,滤波器芯片包括叉指图层和耐功率层,叉指图层包含叉指部分、汇流条及电极部分,耐功率层覆盖于叉指部分且露出电极部分；采用搭桥套刻工艺制作有跨设在汇流条上的绝缘凸块,绝缘凸块上制作有连接电极部分的金属条。在声表面波滤波器芯片叉指位置制作耐功率层,提高产品耐功率特性,应滤波器小型化趋势要求,利用搭桥套刻工艺减小芯片尺寸,同时制作加厚电极层,便于后续植金球或金丝键合工艺。本发明将耐功率工艺与搭桥套刻工艺结合,简化工艺步骤,耐功率层与绝缘凸块同步制作,金属条与加厚电极层同步制作,使声表面波滤波器产品既能满足耐功率需求,又便于后续小型化封装。(The invention relates to a power-resistant surface acoustic wave filter chip, a bridging alignment process thereof and a filter, wherein the filter chip comprises an interdigital layer and a power-resistant layer, the interdigital layer comprises an interdigital part, a bus bar and an electrode part, and the power-resistant layer covers the interdigital part and exposes the electrode part; and an insulating bump striding over the bus bar is manufactured by adopting a bridging and alignment process, and a metal bar connected with an electrode part is manufactured on the insulating bump. The power-resistant layer is manufactured at the interdigital position of the surface acoustic wave filter chip, the power-resistant characteristic of a product is improved, the size of the chip is reduced by utilizing a bridging overlay process according to the requirement of the miniaturization trend of the filter, and meanwhile, the thickened electrode layer is manufactured, so that the subsequent gold ball or gold wire bonding process is facilitated. The invention combines the power-resistant process and the bridging alignment process, simplifies the process steps, synchronously manufactures the power-resistant layer and the insulating bump, and synchronously manufactures the metal strip and the thickened electrode layer, so that the surface acoustic wave filter product can meet the power-resistant requirement and is convenient for subsequent miniaturized packaging.)

1. The power-resistant surface acoustic wave filter chip is characterized by comprising an interdigital layer and a power-resistant layer, wherein the interdigital layer comprises an interdigital part, a bus bar and an electrode part, and the power-resistant layer exposes and covers the electrode part of the interdigital layer; and an insulating bump striding over the bus bar is manufactured by adopting a bridging and alignment process, and a metal bar connected with an electrode part is manufactured on the insulating bump.

2. The power-tolerant surface acoustic wave filter chip as claimed in claim 1, wherein the electrode portion includes an inner electrode inside the structure and an outer electrode outside the structure, and the metal strips are connected to the inner electrode and the outer electrode, respectively.

3. The power-tolerant surface acoustic wave filter chip as claimed in claim 1, wherein a thickened electrode layer is formed on the electrode portion simultaneously with the metal strips.

4. A power-resistant type surface acoustic wave filter chip bridging alignment process is characterized by comprising the following steps:

s1, preparing a metal pattern on the surface of the piezoelectric wafer to form an interdigital pattern layer;

s2, synchronously manufacturing a power-resistant layer and an insulating bump on the surface of the interdigital layer, enabling the power-resistant layer to cover the interdigital parts of the interdigital layer, enabling the insulating bump to cover the bus bar between the interdigital parts, and enabling the electrode parts of the interdigital layer to be exposed;

and S3, stripping the electrode part and the surface of the insulation bump by photoetching coating, evaporating a thickened electrode layer and a metal strip at the same time, covering the thickened electrode layer on the surface of the electrode part, and enabling the metal strip to cross over the bus bar and be connected with the inner electrode and the outer electrode of the electrode part to obtain the power-resistant surface acoustic wave filter chip.

5. The process of claim 4, wherein in S1, a metal pattern is formed by a photolithographic film stripping process.

6. The process of claim 4, wherein in step S2, the power-tolerant layer and the insulation bump are fabricated simultaneously by photolithography, sputtering and stripping at corresponding positions on the surface of the interdigital layer, and the power-tolerant layer and the insulation bump are collectively referred to as an insulation layer.

7. A power-tolerant surface acoustic wave filter comprising the power-tolerant surface acoustic wave filter chip according to any one of claims 1 to 3.

Technical Field

The invention relates to the technical field of bridging and alignment of surface acoustic wave filters, in particular to a power-resistant surface acoustic wave filter chip, a bridging and alignment process thereof and a filter.

Background

Along with the gradual development of surface acoustic wave devices in the miniaturization direction, the requirements of chip design size are smaller and smaller, an internal electrode and an external electrode are connected by utilizing a bridging overlay process in a design mode commonly adopted at present to obtain a smaller chip size, an insulating bump needs to be manufactured to cross a bus bar, a metal bar needs to be manufactured to cross an insulating bump to connect the internal electrode and the external electrode, meanwhile, the electrode needs to be thickened so as to be convenient for subsequent ball planting or gold wire bonding, in addition, most of surface acoustic wave filters have power resistance requirements at present, an insulating layer needs to be manufactured to cover an interdigital part when the device meets the power resistance requirement, and the interdigital is protected from being damaged while the power resistance requirement is met, namely the power resistance layer.

However, in the conventional process, after the bridging alignment process is completed, the electrode part is thickened, and then the power-resistant layer is manufactured on the surface of the chip, the process is complicated, and the manufacturing period is long, so that a simple process scheme is required to combine three requirements into one process, and simultaneously meet the requirements of bridging alignment, electrode thickening and power resistance.

Disclosure of Invention

The invention aims to solve the technical problem of the prior art and provides a power-resistant surface acoustic wave filter chip, a bridging overlay process thereof and a filter.

The technical scheme for solving the technical problems is as follows: a power-resistant surface acoustic wave filter chip comprises an interdigital layer and a power-resistant layer, wherein the interdigital layer comprises an interdigital part, a bus bar and an electrode part, and the power-resistant layer exposes the electrode part of the interdigital layer and covers the interdigital part; and an insulating bump striding over the bus bar is manufactured by adopting a bridging and alignment process, and a metal bar connected with an electrode part is manufactured on the insulating bump.

The invention has the beneficial effects that: compared with the common product, the power-resistant layer is manufactured at the interdigital part of the surface acoustic wave filter chip, so that the power-resistant characteristic of the product can be improved, and the surface of the interdigital layer can be protected from being damaged. According to the requirement of miniaturization trend of the filter, the design size of the chip is reduced by utilizing a bridging alignment process, the surface of the interdigital pattern layer is protected from being damaged, and the subsequent gold ball implantation or gold wire bonding process is facilitated.

On the basis of the technical scheme, the invention can be further improved as follows.

Further, the electrode part comprises an inner electrode positioned on the inner side of the power-resistant layer and an outer electrode positioned on the outer side of the power-resistant layer, and the metal strips are respectively connected with the inner electrode and the outer electrode.

Further, a thickened electrode layer is formed on the electrode portion simultaneously with the metal strip. The beneficial effect of adopting the further scheme is that: the design size of the chip is reduced by using a bridging alignment process, the insulating bump and the power-resistant layer are synchronously manufactured, the metal strip for connecting the inner electrode and the outer electrode and the thickened electrode layer are synchronously manufactured, the power-resistant requirement of the small-size chip is met while the process steps are simplified, the surface of the interdigital image layer is protected from being damaged, and the subsequent gold ball implantation or gold wire bonding process is facilitated.

A power-resistant type surface acoustic wave filter chip bridging alignment process comprises the following steps:

s1, preparing a metal pattern on the surface of the piezoelectric wafer to form an interdigital pattern layer;

s2, synchronously manufacturing a power-resistant layer and an insulating bump on the surface of the interdigital layer, enabling the power-resistant layer to cover the interdigital part of the interdigital layer, enabling the insulating bump to be arranged on the bus bar in a spanning mode, and enabling the electrode part of the interdigital layer to be exposed;

and S3, stripping the electrode part and the surface of the insulation bump by photoetching coating, evaporating a thickened electrode layer and a metal strip at the same time, covering the thickened electrode layer on the surface of the electrode part, and enabling the metal strip to cross over the bus bar and be connected with the inner electrode and the outer electrode of the electrode part to obtain the power-resistant surface acoustic wave filter chip.

The invention has the beneficial effects that: the invention combines the insulated lug and the power-resistant layer which are subjected to bridging alignment into one layer, which is called as the manufacture of an insulating layer, and combines the metal strip and the thickened electrode layer into one layer, which is called as the manufacture of a metal thickening layer, so that the power-resistant layer is manufactured while the bridging alignment process is realized, and the electrode part is thickened, thereby simplifying the process steps, ensuring that the product can resist power. The invention combines the power-resisting process and the bridging alignment process, simplifies the process steps, manufactures the insulating bump while manufacturing the power-resisting layer, manufactures the thickened electrode layer while manufacturing the metal strip, ensures that the surface acoustic wave filter product can meet the power-resisting requirement and is convenient for subsequent miniaturized packaging.

Further, in S1, a metal pattern is prepared by a photolithography coating film stripping process.

Further, in S2, an insulating layer is simultaneously formed on the corresponding position on the surface of the interdigital layer by photolithography, sputtering and stripping.

The beneficial effect of adopting the further scheme is that: an insulating layer can be arranged at the position corresponding to the interdigital layer, so that the metal bar is insulated and isolated from the bus bar, and the interdigital part is protected.

A power-tolerant surface acoustic wave filter comprises the power-tolerant surface acoustic wave filter chip.

The invention has the beneficial effects that: according to the miniaturized power-tolerant surface acoustic wave filter, the bridging overlay process and the power-tolerant process are combined, compared with common products, the process steps are simplified, the miniaturization requirement of the surface acoustic wave filter is met, and meanwhile the power-tolerant requirement is met.

Drawings

FIG. 1 is a schematic diagram of a periodically arranged SAW filter chip in accordance with the present invention;

FIG. 2 is a schematic diagram of an interdigital layer for a single SAW filter in accordance with the present invention;

FIG. 3 is a schematic view of an interdigital layer surface covered with an insulating layer in accordance with the present invention;

FIG. 4 is a schematic view of the insulating layer covered with a metal thickening layer according to the present invention;

FIG. 5 is a schematic structural diagram of forming an interdigital layer by forming a metal pattern on a wafer surface according to the present invention;

FIG. 6 is a schematic structural diagram of an insulating layer formed on the surface of an interdigital layer according to the present invention;

FIG. 7 is a schematic structural diagram of the present invention illustrating the fabrication of metal strips on the surface of an insulating layer and the fabrication of a thickened electrode layer on the inner and outer electrodes;

FIG. 8 is a schematic structural diagram of spin-coating a photoresist on the surface of the interdigital layer and the insulating layer according to the present invention;

FIG. 9 is a schematic structural diagram of a photoresist pattern formed by exposure and development according to the present invention;

FIG. 10 is a schematic structural diagram of a method for evaporating a metal thickening layer on a photoresist surface by electron beam evaporation according to the present invention;

fig. 11 is a schematic structural diagram of the photoresist in fig. 10 after being stripped.

In the drawings, the components represented by the respective reference numerals are listed below:

1. an interdigital layer; 2. an outer electrode; 3. an inner electrode; 4. a bus bar; 5. an insulating layer; 6. a metal strip; 7. an interdigitated portion; 8. thickening the electrode layer; 9. a piezoelectric wafer; 10. and (5) photoresist pattern.

Detailed Description

The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.

Example 1

As shown in fig. 1 to fig. 11, the power-tolerant surface acoustic wave filter chip of this embodiment includes an interdigital layer 1 and a power-tolerant layer, where the interdigital layer 1 includes an interdigital portion 7, a bus bar 4, and an electrode portion, and the power-tolerant layer exposes the electrode portion of the interdigital layer 1 and covers the interdigital portion 7; an insulating bump striding over the bus bar 4 is manufactured by adopting a bridging and alignment process, and a metal bar 6 connected with an electrode part is manufactured on the insulating bump.

As shown in fig. 2, the electrode part of the present embodiment includes an inner electrode 3 located inside the structure and an outer electrode 2 located outside the structure, and the metal strips 6 are connected to the inner electrode 3 and the outer electrode 2, respectively.

As shown in fig. 3, the insulating bump of this embodiment covers the bus bar 4 in the interdigital layer 1, and the power-tolerant layer covers the interdigital portion 7 in the interdigital layer 1, that is, the insulating layer 5 covers the bus bar 4 and the interdigital portion 7 in the interdigital layer 1 at the same time.

As shown in fig. 4, a thickened electrode layer 8 is formed on the electrode portion at the same time as the metal strip 6. The design size of the chip is reduced by using a bridging alignment process, the insulating bump and the power-resistant layer are synchronously manufactured, the metal strip 6 for connecting the inner electrode and the outer electrode and the thickened electrode layer 8 are synchronously manufactured, the power-resistant requirement of the small-size chip is met while the process steps are simplified, the surface of the interdigital image layer is protected from being damaged, and the subsequent gold ball implantation or gold wire bonding process is facilitated.

The insulating bump and the power-resistant layer are synchronously manufactured, namely, a film layer made of the same insulating material is manufactured at the corresponding position on the surface of the interdigital layer 1, and the insulating bump and the power-resistant layer are collectively called as an insulating layer 5. The metal strip 6 and the thickened electrode layer 8 are synchronously manufactured, namely, the film layer made of the same metal material is manufactured at the corresponding position on the surface of the insulating layer 5, and the metal strip 6 and the thickened electrode layer 8 are collectively called as a metal thickening layer. The insulating lug and the power-resistant layer are combined into one layer, the metal strip 6 and the thickened electrode layer 8 are combined into one layer, the bridging and alignment process is carried out, and meanwhile, the four processes of the insulating lug, the power-resistant layer, the metal strip and the thickened electrode layer are manufactured.

As shown in fig. 4, the outer electrode 2 located on the outer periphery of the structure is formed with a thickened electrode layer 8, and the inner electrode 3 located on the inner side of the structure is also formed with a thickened electrode layer 8. And thickened electrode layers 8 are manufactured on the inner electrode 3 and the outer electrode 2, so that the subsequent miniaturized packaging processes such as gold ball implantation or gold wire bonding are facilitated.

The power-resistant surface acoustic wave filter chip of the embodiment is characterized in that the power-resistant layer is manufactured at the interdigital part of the surface acoustic wave filter chip, and compared with a common product, the power-resistant surface acoustic wave filter chip can improve the power-resistant characteristic of the product and protect the surface of the interdigital layer from being damaged. According to the requirement of miniaturization trend of the filter, the design size of the chip is reduced by utilizing a bridging alignment process, and meanwhile, a thickened electrode layer is manufactured, so that the subsequent gold ball implanting or gold wire bonding process is facilitated.

Example 2

As shown in fig. 1 to 11, the process for lapping and aligning a power-tolerant saw filter chip of this embodiment includes the following steps:

s1, preparing a metal pattern on the surface of the piezoelectric wafer 9, and forming an interdigital layer 1, as shown in fig. 5, where the interdigital layer includes an interdigital portion 7, a bus bar 4, an inner electrode 3, and an outer electrode 2;

s2, overlaying a photoresist pattern 10 on corresponding positions around the interdigital layer 1, and synchronously forming a power-tolerant layer and an insulating bump on the surface of the interdigital layer 1 by photolithography, sputtering and stripping, as shown in fig. 6, so that the power-tolerant layer covers the interdigital portion 7 of the interdigital layer 1, and the insulating bump covers the bus bar 4 in the interdigital layer 1, and the sputtering method can adopt a PECVD process; the power resisting layer and the insulating bump can be made of SiO₂Or Si₃N₄And the like insulating materials; stripping the photoresist pattern 10, the power-resistant layer on the photoresist pattern and the insulating bump by a lift-off process to expose the inner electrode 3 and the outer electrode 2 on the outer side; because the power-resisting layer and the insulating bump are made of the same material and have the same manufacturing process, the power-resisting layer and the insulating bump can be made of the same material and can be made of the same materialReferred to as insulating layer 5.

And S3, stripping the electrode part and the surface of the insulating bump by photoetching coating, and simultaneously evaporating a thickened electrode layer 8 and a metal strip 6, wherein as shown in FIG. 7, the thickened electrode layer 8 covers the surface of the electrode part, and the metal strip 6 crosses over the bus bar 4 and is connected with the inner electrode 3 and the outer electrode 2 of the electrode part, so that a power-resistant surface acoustic wave filter chip is obtained, and the manufacture of the bridging and overlaying process of the surface acoustic wave filter chip wafer is completed.

The embodiment combines the insulating lug and the power-resistant layer which are subjected to bridging alignment into one layer, combines the thickened electrode layer and the metal strip into one layer for manufacturing, realizes the bridging alignment process, manufactures the power-resistant layer on the surface of the interdigital part, thickens the electrode part, simplifies the process steps, can meet the requirement of product miniaturization, can improve the power resistance of the product, protects the surface of the interdigital layer from being damaged, and is convenient for the subsequent gold ball or gold wire bonding process.

In S1, a metal pattern is prepared by a photoetching coating stripping process.

In the step S2, a power-resistant layer is manufactured at the interdigital position by utilizing an overlay process and photoetching, sputtering and stripping at the corresponding position on the surface of the interdigital layer 1, so that the interdigital part is protected from being damaged; and an insulating bump is arranged at the position of the bus bar, so that the bus bar is ensured to be insulated and isolated from the metal bar.

In S3, when the metal bars 6 are simultaneously deposited on the surfaces of the insulating bumps, the thick electrode layers 8 are also simultaneously deposited on the outer electrodes 2 and the inner electrodes 3. The electrode part is thickened while the bridging overlay process is realized, compared with a common product, the process steps are simplified, and the subsequent gold ball implanting or gold wire bonding process is convenient to perform.

In S3, spin-coating a photoresist on the surfaces of the interdigital layer 1 and the insulating layer 5, as shown in fig. 8; then, a photoresist pattern is formed through an exposure and development process, as shown in fig. 9; then, utilizing an electron beam evaporation process to manufacture a metal thickening layer, as shown in FIG. 10; finally, the photoresist is stripped to form the metal strips 6 connecting the inner and outer electrodes and the inner and outer electrodes 3 and 2 covered with the thickened electrode layers 8, as shown in fig. 11.

Example 3

The power-tolerant surface acoustic wave filter of the embodiment comprises the power-tolerant surface acoustic wave filter chip.

The power-resistant surface acoustic wave filter combines the bridging alignment process with the power-resistant process, combines the insulating bump and the power-resistant layer into one layer, combines the metal strip 6 and the thickened electrode layer 8 into one layer, and compared with a common product, the power-resistant surface acoustic wave filter simplifies the process steps, meets the power-resistant requirement while realizing the miniaturization requirement of the surface acoustic wave filter product.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.

In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.