阅读说明：本技术 存储装置及其制造方法 (Memory device and method of manufacturing the same ) 是由 江昱维 胡志玮 邱家荣 于 2019-11-18 设计创作，主要内容包括：本发明公开了一种存储装置及其制造方法。存储装置包含漏极柱状结构、源极柱状结构、电荷捕捉结构、垂直通道结构和栅极结构。漏极柱状结构形成于第一开口中。源极柱状结构形成于第二开口中。垂直通道结构与电荷捕捉结构形成于孔洞中,孔洞部分重叠于第一开口和第二开口。垂直通道结构被漏极柱状结构和源极柱状结构分开为两弧形通道部件。栅极结构围绕漏极柱状结构、源极柱状结构和垂直通道结构。(The invention discloses a memory device and a manufacturing method thereof. The memory device comprises a drain electrode columnar structure, a source electrode columnar structure, a charge trapping structure, a vertical channel structure and a grid electrode structure. The drain electrode columnar structure is formed in the first opening. The source electrode columnar structure is formed in the second opening. The vertical channel structure and the charge trapping structure are formed in the hole, and the hole partially overlaps the first opening and the second opening. The vertical channel structure is divided into two arc-shaped channel parts by the drain electrode columnar structure and the source electrode columnar structure. The gate structure surrounds the drain columnar structure, the source columnar structure and the vertical channel structure.)

1. A method of manufacturing a memory device, comprising:

forming a hole in an oxide-nitride stack;

forming a vertical channel structure and a charge trapping structure on an inner wall of the hole;

forming a first opening and a second opening, wherein the first opening and the second opening are partially overlapped with the hole, and the first opening and the second opening penetrate through the vertical channel structure, wherein the vertical channel structure is divided into two arc-shaped channel parts by the first opening and the second opening;

forming a drain electrode columnar structure and a source electrode columnar structure in the first opening and the second opening respectively; and

and forming a gate structure which surrounds the drain electrode columnar structure, the source electrode columnar structure and the vertical channel structure.

2. The method of claim 1, wherein in the step of forming the drain pillar and the source pillar in the first opening and the second opening, respectively, the drain pillar or the source pillar is partially within the hole and partially outside the hole.

3. The method according to claim 1, wherein in the step of forming the drain pillar structure and the source pillar structure in the first opening and the second opening, respectively, two ends in each of the arc-shaped channel parts are connected to the drain pillar structure and the source pillar structure, respectively.

4. The method of claim 1, wherein in the step of forming the first opening and the second opening, the charge trapping structure is separated into two arc-shaped charge trapping elements by the first opening and the second opening.

5. A memory device, comprising:

a drain electrode columnar structure formed in a first opening;

a source electrode columnar structure formed in a second opening;

a charge trapping structure;

a vertical channel structure formed in a hole partially overlapping the first opening and the second opening with the charge trapping structure, wherein the vertical channel structure is separated into two arc-shaped channel parts by the drain pillar structure and the source pillar structure; and

and a gate structure surrounding the drain columnar structure, the source columnar structure and the vertical channel structure.

6. The memory device of claim 5, wherein the drain pillar or the source pillar is partially within the hole and the drain pillar or the source pillar is partially outside the hole.

7. The memory device of claim 5, wherein a maximum distance between an edge of the drain pillar and a center point of the hole is greater than a radius of the hole in one plane.

8. The memory device of claim 5, wherein two ends of each of the arc-shaped channel members are respectively connected to the drain pillar structure and the source pillar structure.

9. The memory device of claim 5, further comprising a dielectric portion formed between the drain pillar structure and the gate structure.

10. The memory device of claim 5, wherein the charge trapping structure is separated into two arc-shaped charge trapping members by the drain pillar structure and the source pillar structure.

Technical Field

The present invention relates to a memory device and a method for fabricating the same, and more particularly, to a memory device having a vertical channel and a method for fabricating the same.

Background

In modern computer systems, Dynamic Random Access Memory (DRAM) type memory devices and NAND flash (NAND flash) type memory devices have been widely used for storing data. Generally, the DRAM type memory device has advantages of low latency and high access speed, but has a limited memory capacity and a high cost per bit. In contrast, NAND flash type memory devices have advantages of high memory density and low cost per bit, while they have higher latency and lower access speed. Because a great difference exists between the access speed of the DRAM type storage device and the NAND flash type storage device, a bottleneck occurs in the data transfer process, and the data processing speed of the computer system is further reduced. Although a code flash (NOR flash) type memory device has been available in the market, the NOR flash type memory device has a higher access speed and a lower latency compared to the NAND flash type memory device, but the conventional NOR flash type memory device has a limited storage density and cannot meet the storage requirement of a large capacity.

In recent years, a new memory technology, storage-class memory (SCM), has been proposed, in which a storage class memory is considered as being interposed between a DRAM type memory device and a NAND flash type memory device, and the access speed drop between the DRAM type memory device and the NAND flash type memory device can be filled. Various types of memory rank memories have been developed, such as 3D XPoint memories, Magnetoresistive Random Access Memories (MRAMs), and Phase Change Memories (PCMs). However, these types of storage class memories still do not meet all the demands on the storage class memories in the market.

Therefore, there is a need to provide a three-dimensional memory technology with high storage density, high access speed and low latency.

Disclosure of Invention

The invention relates to a memory device and a method for manufacturing the same. According to embodiments, the method may provide a memory device including a drain pillar structure, a source pillar structure, and two arc-shaped channel members, thereby improving the memory density and operating speed of the memory device.

According to an embodiment of the present invention, a method for manufacturing a memory device is provided. The method for manufacturing a memory device includes the following steps. A hole is formed in the oxide-nitride stack. A vertical channel structure and a charge trapping structure are formed on the inner wall of the hole. A first opening and a second opening are formed, the first opening and the second opening partially overlap the hole, and the first opening and the second opening penetrate through the vertical channel structure. The vertical channel structure is divided into two arcuate channel members by a first opening and a second opening. And forming a drain electrode columnar structure and a source electrode columnar structure in the first opening and the second opening respectively. And forming a grid structure which surrounds the drain electrode columnar structure, the source electrode columnar structure and the vertical channel structure.

According to an embodiment of the present invention, a memory device is provided. The memory device comprises a drain electrode columnar structure, a source electrode columnar structure, a charge trapping structure, a vertical channel structure and a grid electrode structure. The drain electrode columnar structure is formed in the first opening. The source electrode columnar structure is formed in the second opening. The vertical channel structure and the charge trapping structure are formed in the hole, and the hole partially overlaps the first opening and the second opening. The vertical channel structure is divided into two arc-shaped channel parts by the drain electrode columnar structure and the source electrode columnar structure. The gate structure surrounds the drain columnar structure, the source columnar structure and the vertical channel structure.

In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the appended drawings.

Drawings

Fig. 1A-14B illustrate a method for fabricating a memory device according to an embodiment of the invention.

[ notation ] to show

101: substrate

102: bottom oxide layer

103: nitride layer

103 g: gate material

103 x: hollow spaces

104: oxide layer

105: charge trapping structure

106: vertical channel structure

107: dielectric material

108: high dielectric constant material layer

109: low temperature oxide layer

110: hole(s)

115: channel

116: conductive film

120: external circuit

510. 512, 514, 516: first opening

511. 513, 515, 517: second opening

601: drain electrode columnar structure

601 s: dielectric part

602: source pole structure

710. 712: slit

710r, 712 r: alcove

C1: center point

D1: a first direction

D2: second direction

D3: third direction

P5-P14: thread

R1, R2, R3: distance between two adjacent plates

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.

In an embodiment of the invention, a memory device and a method for manufacturing the memory device are provided. Embodiments of the fabrication method can provide a memory device, such as a memory device including a drain pillar structure, a source pillar structure, and two arc-shaped channel members separated by the drain pillar structure and the source pillar structure, thereby filling the access speed gap between a DRAM type memory device and a NAND flash type memory device, and simultaneously optimizing the memory density and operating speed of the memory device.

In practice, embodiments of the invention may be implemented as a number of different storage devices. For example, the embodiments may be applied to a three-dimensional vertical channel type memory device, but the present invention is not limited to this application. The following embodiments are provided to explain in detail the memory device and the manufacturing method thereof in accordance with the present invention by referring to the accompanying drawings. However, the invention is not limited thereto. The description of the embodiments, such as the partial structures, the steps of the manufacturing method, and the application of the materials, are for illustrative purposes only, and the scope of the present invention is not limited to the embodiments.

Also, it is to be noted that the invention does not show all possible embodiments. Those skilled in the art will appreciate that variations and modifications in the structure and method of manufacture of the embodiments described herein may be made without departing from the spirit and scope of the invention, as described in the appended claims. Thus, other embodiments not set forth herein may also be applicable. Moreover, the drawings are simplified to clearly illustrate the embodiments, and the dimensional proportions in the drawings are not drawn to scale as actual products. Accordingly, the specification and drawings are to be regarded in an illustrative manner and are not intended to limit the scope of the invention.

Furthermore, the use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims is intended to modify a claimed element by itself and not to imply any previous order to the claimed element, nor to the order in which a claimed element may be sequenced or a method of manufacture, but merely to distinguish one claimed element having a certain name from another claimed element having a similar name.

Fig. 1A-14B illustrate a method for manufacturing a memory device according to an embodiment of the invention. Fig. 1A shows a top view and fig. 1B shows a cross-sectional view of an exemplary structure at this stage of processing. As shown in fig. 1A-1B, a bottom oxide layer 102 is formed on a substrate 101, and an oxide-nitride stack is formed on the bottom oxide layer 102. The oxide-nitride stack comprises a plurality of nitride layers 103 and a plurality of oxide layers 104, wherein the plurality of nitride layers 103 and the plurality of oxide layers 104 are alternately stacked along a third direction D3 (e.g., Z direction) perpendicular to the substrate 101. In one example, the plurality of nitride layers 103 may comprise silicon nitride (SiN). In one example, the oxide-nitride stack may comprise only a nitride layer 103 and an oxide layer 104 formed on the nitride layer 103.

Next, as shown in fig. 2A-2B, fig. 2A illustrates a top view and fig. 2B illustrates a cross-sectional view of the exemplary structure at this stage of processing. In this processing stage, the oxide-nitride stack is patterned to form a plurality of holes 110, for example by a photolithographic process. The hole 110 may have a cylindrical shape or a conical shape, but the present invention is not limited thereto. The holes 110 expose the sidewalls of the oxide-nitride stack. In one example, the etching process for the hole 110 may stop at the bottom oxide layer 102, that is, the hole 110 extends downward in the third direction D3 to penetrate through the oxide-nitride stack and the bottom oxide layer 102 to expose the bottom oxide layer 102. Next, a charge trapping structure 105 is formed on the oxide-nitride stack and is formed in the hole 110 in a liner manner. In the hole 110, the charge trapping structure 105 is formed on the inner wall and the bottom of the hole 110. The charge trapping structure 105 may be formed by a deposition process, such as a Chemical Vapor Deposition (CVD) process. In one example, the charge trapping structure 105 is formed in a furnace (furnace). Next, a vertical channel structure 106 is formed over the charge trapping structure 105, exposing the charge trapping structure 105 at the bottom of the hole 110.

The charge trapping structure 105 described above may comprise a multilayer (multilayered) structure, such as ONO (oxide-nitride-oxide), ONO (oxide-nitride-oxide), onoono (oxide-nitride-oxide), SONOS (silicon-oxide-nitride-oxide-silicon), BE-SONOS (bandgap engineered silicon-oxide-nitride-oxide-silicon), TANOS (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon (tantalum nitride, aluminum oxide, silicon oxide)), (oxide-nitride, silicon oxide, silicon) as known in the memory art, And MA BE-SONOS (metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon), or other types of charge trapping layers, or combinations of these layers. In one example, the vertical channel structure 106 may comprise polysilicon (polysilicon).

Next, as shown in fig. 3A-3B, fig. 3A illustrates a top view and fig. 3B illustrates a cross-sectional view of an exemplary structure at this stage of processing. A dielectric material 107 is formed on the vertical via structure 106 and fills the hole 110. The dielectric material 107 may comprise an oxide.

Fig. 4A shows a top view and fig. 4B shows a cross-sectional view of an exemplary structure at this stage of processing. In this stage, the charge trapping structure 105, the vertical channel structure 106 and the dielectric material 107 above the oxide-nitride stack are removed to expose the top of the oxide-nitride stack and to form a planar top surface in the first direction D1 (e.g., the X direction). In one example, a planarization process may be applied to the structure, stopping on the vertical channel structure 106 above the oxide-nitride stack, which may be a chemical-mechanical planarization (CMP) process. Next, an etch process is applied to the structure, the etch process stopping on top of the oxide-nitride stack. In one example, as shown in fig. 4B, the charge trapping structure 105 has a hollow cylindrical shape and one end is closed, and the vertical channel structure 106 has a hollow cylindrical shape and two ends are open.

Fig. 5A is a top view of the exemplary structure after the processing stage shown in fig. 4A-4B, and fig. 5B is a cross-sectional view of the exemplary structure taken along line P5 of fig. 5A. The first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 are formed to partially overlap the hole 110. The first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517 may be formed by a dry etching (dry etching) process, but the present invention is not limited thereto. The first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 extend downward in the third direction D3 to penetrate through the ono stack, the charge trapping structure 105, the vertical channel structure 106, and the dielectric material 107. In an example, the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 stop at the bottom oxide layer 102 in the third direction D3. In an example, in the third direction D3, the depth of the first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517 is greater than the depth of the hole 110 in the third direction D3. In an example, the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 may have a cylindrical shape or a conical shape, but the present invention is not limited thereto.

First openings 510, 512, 514, and 516 and second openings 511, 513, 515, and 517 are formed on both sides of the hole 110. In an example, the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 are formed on opposite sides of the hole 110.

After the first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517 are formed, the vertical channel structure 106 in the hole 110 is divided into two arc-shaped channel parts by the first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517. In one example, the arc-shaped channel members are disposed on opposite inner walls of the hole 110, respectively. In addition, the charge trapping structure 105 is separated from the second openings 511, 513, 515, and 517 by the first openings 510, 512, 514, and 516 into two arc-shaped charge trapping elements.

Fig. 6A is a top view of the exemplary structure after the processing stage shown in fig. 5A-5B, and fig. 6B is a cross-sectional view of the exemplary structure taken along line P6 of fig. 6A. In this stage of processing, the drain pillar 601 and the source pillar 602 are formed in the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517, respectively. Specifically, a conductive material is deposited in the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517, and then a planarization process is applied to the top surface of the structure to form the drain pillar 601 and the source pillar 602. The drain pillar 601 and the source pillar 602 directly contact the charge trapping structure 105 and the vertical channel structure 106. The charge trapping structure 105 in the hole 110 is separated from the source pillar 602 by the drain pillar 601 into two arc-shaped charge trapping members. The vertical channel 106 in the hole 110 is divided into two arc-shaped channel portions by the drain pillar 601 and the source pillar 602. Two ends of the arc-shaped channel part are respectively connected with the drain electrode columnar structure 601 and the source electrode columnar structure 602.

In one example, the conductive material may comprise N + type polysilicon (N + polysilicon). In one example, the planarization process may be a chemical mechanical planarization process. In one example, when the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 partially overlap the hole 110, the drain pillar 601 and the source pillar 602 are partially located in the hole 110 and partially located outside the hole 110. In one example, the drain pillar 601 and the source pillar 602 are both partially located in the hole 110 and partially located outside the hole 110. In one example, one of the drain pillar 601 and the source pillar 602 is partially located in the hole 110 and partially located outside the hole 110, and the other of the drain pillar 601 and the source pillar 602 is completely disposed in the hole 110. In a plane including the first direction D1 and the second direction D2 (i.e., in the plane D1-D2), the cross-sectional areas of the drain pillar 601 and the source pillar 602 may be smaller than the cross-sectional area of the hole 110 in the plane D1-D2, but the invention is not limited thereto.

As shown in FIG. 6A, in the plane D1-D2, the hole 110 has a center point C1, and the distance between the edge of the hole 110 and the center point C1 is defined as the distance R1 (i.e., the radius of the hole 110). The maximum distance between the edge of the drain pillar 601 and the center point C1 is defined as a distance R2. The maximum distance between the edge of the source pillar 602 and the center point C1 is defined as a distance R3. The distance R2 and the distance R3 are greater than the distance R1. In one example, the distance R2 and the distance R3 are both greater than the distance R1.

In one example, at least one of the drain pillar 601 and the source pillar 602 may intersect the edge of the hole 110 to create more than two distinct intersections in the plane D1-D2. For example, in the plane D1-D2, the edges of the drain pillar 601 and the hole 110 are staggered to form two distinct intersections. For example, in the plane D1-D2, the edges of the source pillar 602 and the edge of the hole 110 are staggered to form two distinct intersections. For example, in the plane D1-D2, the edges of the drain pillar 601 and the source pillar 602 intersect the edge of the hole 110 at two different intersections, respectively, to generate four different intersections.

Fig. 7A is a top view of the exemplary structure after the processing stage shown in fig. 6A-6B, and fig. 7B is a cross-sectional view of the exemplary structure taken along line P7 of fig. 7A. In this stage of processing, the oxide-nitride stack is patterned to form slits 710 and 712 and stop at bottom oxide layer 102, for example by patterning the oxide-nitride stack by a photolithographic process. The slits 710 and 712 extend downward in the third direction D3 to penetrate through the oxide-nitride stack and the bottom oxide layer 102 to expose the bottom oxide layer 102.

Fig. 8A is a top view of the exemplary structure after the processing stage shown in fig. 7A-7B, and fig. 8B is a cross-sectional view of the exemplary structure taken along line P8 of fig. 8A. Next, as shown in fig. 8A-8B, the plurality of nitride layers 103 in the oxide-nitride stack are removed through the slits 710 and 712 to form a void 103x, where the plurality of nitride layers 103 were originally formed. The plurality of nitride layers 103 may be removed by an etching process. The void 103x exposes portions of the sidewalls of the drain pillar 601, the source pillar 602, and the charge trapping layer 105, where the exposed sidewalls originally contacted the plurality of nitride layers 103.

Fig. 9A is a top view of the exemplary structure after the processing stage shown in fig. 8A-8B, and fig. 9B is a cross-sectional view of the exemplary structure taken along line P9 of fig. 9A. Next, as shown in fig. 9A-9B, a plurality of dielectric portions 601s are disposed on the sidewalls of the drain pillar structure 601 and the source pillar structure 602 exposed by the void 103 x. In one example, the dielectric portion 601s may be formed by applying an oxidation process to sidewalls of the drain pillar structure 601 and the source pillar structure 602 exposed by the void 103 x. In one example, the dielectric portion 601s may include polycrystalline silicon oxide. The width of the dielectric portion 601s in the second direction D2 is about 200 angstroms (angstrom;) More preferably greater than 200 angstroms, although the present invention is not limited to this value. The dielectric portion 601s can prevent or improve short-circuit (short-circuit) problems caused by contact between the word line and the drain pillar 601 or contact between the word line and the source pillar 602.

Fig. 10A is a top view of the exemplary structure after the processing stage shown in fig. 9A-9B, and fig. 10B is a cross-sectional view of the exemplary structure taken along line P10 of fig. 10A. In this stage of processing, a layer of high dielectric constant (high-k) material 108 is formed on the sidewalls and bottom of the slots 710 and 712, on the walls of the oxide layers 104 exposed by the voids 103x, on the sidewalls of the charge trapping structure 105 exposed by the voids 103x, and on the exposed sidewalls of the dielectric portion 601 s. In other words, the high-k material layer 108 is formed lining the slits 710 and 712 and the void 103 x. The high-k material layer 108 may comprise a high-k material, such as aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Silicon nitride (Si)₃N₄) Zirconium dioxide (ZrO)₂) Titanium dioxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Lanthanum oxide (La)₂O) or other suitable material, etc. Can be processed by deposition or by co-formulation with phosphoric acid (H)₃PO₄) The solution is subjected to a wet etching (wet etching) process to form the high-k material layer 108.

Fig. 11A is a top view of the exemplary structure after the processing stage shown in fig. 10A-10B, and fig. 11B is a cross-sectional view of the exemplary structure taken along line P11 of fig. 11A. In this stage of processing, gate material 103g is formed in the remaining spaces of voids 103x and slits 710 and 712. In one example, gate material 103g is deposited in the remaining spaces of voids 103x and slits 710 and 712. The gate material 103g may comprise a metal such as titanium nitride (TiN), tantalum nitride (TaN), and the like.

Fig. 12A is a top view of the exemplary structure after the processing stage shown in fig. 11A-11B, and fig. 12B is a cross-sectional view of the exemplary structure taken along line P12 of fig. 12A. Next, an etching back (etchback) process is applied to the structure to remove a portion of the gate material 103g through the slits 710 and 712, thereby forming a plurality of recesses 710r and 712r, as shown in fig. 12B. In one example, each of the plurality of recesses 710r and 712r is a lateral recess extending (along the second direction D2) from the slits 710 and 712 into the gate material 103 g. Thus, each of the alcoves 710r connects the slits 710, and each of the alcoves 712r connects the slits 712. Each of the recesses 710r may be defined as a space formed by two adjacent oxide layers 104, the gate material 103g between the two adjacent oxide layers 104, and the slit 710. Each of the recesses 712r may be defined as a space formed by two adjacent oxide layers 104, the gate material 103g between the two adjacent oxide layers 104, and the slit 712. After the etch-back process, the remaining gate material 103g may be regarded as a gate structure, and the gate structure surrounds the drain pillar 601, the source pillar 602 and the vertical channel structure 106. The dielectric portion 601s is formed between the drain pillar structure 601 and the gate structure, or between the source pillar structure 602 and the gate structure.

Thus, a plurality of memory cells are formed in the structure. Each memory cell includes a drain pillar 601, a source pillar 602, two curved channel features formed in a hole 110 between the drain pillar 601 and the source pillar 602, and gate material 103g (i.e., the gate structure). Each memory cell is of the dual channel type.

In an embodiment of the invention, the processing stages depicted in fig. 13A-14B may also be applied to the exemplary structure after the processing stages depicted in fig. 12A-12B.

Fig. 13A is a top view of the exemplary structure after the processing stage shown in fig. 12A-12B, and fig. 13B is a cross-sectional view of the exemplary structure taken along line P13 of fig. 13A. In this stage of processing, a Low Temperature Oxide (LTO) layer 109 is formed in the slots 710 and 712, followed by the formation of the channel 115, the channel 115 extending downward in the third direction D3 to penetrate the low temperature oxide layer 109. The trench 115 exposes the low temperature oxide layer 109, but the gate material 103g (i.e., the gate structure) and the high-k material layer 108 are not exposed by the trench 115. In one example, low temperature oxide layer 109 is formed in slots 710 and 712 by a deposition process, and then low temperature oxide layer 109 is etched to form channel 115.

Next, as shown in fig. 14A to 14B, a conductive film 116 is formed in the channel 115. Fig. 14A is a top view of the exemplary structure after the stage of processing shown in fig. 13A-13B, and fig. 14B is a cross-sectional view of the exemplary structure taken along line P14 of fig. 14A. In one example, conductive film 116 is deposited in trenches 115 and fills trenches 115, followed by applying a chemical mechanical planarization process to the structure. In one example, the conductive film 116 may comprise the same material as the gate material 103 g. In the slits 710 and 712, the low-temperature oxide layer 109 separates the conductive film 116 and the gate material 103 g.

Then, an external circuit 120 is connected to the conductive film 116 to apply a current to the conductive film 116. The current passing through the conductive film 116 may generate heat, also known as Joule heating. The heat generated by this process helps repair the memory cells.

According to the present invention, the drain pillar structure and the source pillar structure of the memory device are partially overlapped with the hole having the vertical channel structure formed therein, so that the size of the hole is reduced. Therefore, the present invention is advantageous in that the size of each memory cell in the memory device is reduced, the storage density and storage capacity of the memory device are improved, and the size of the memory device is reduced. In addition, the architecture of the memory device can perform random access, that is, the memory address to be read or written can be completed in the same time, so that the memory device has higher access speed compared with a NAND flash type memory device which can only perform sequential access (block access). Furthermore, compared to the conventional planar (2D) memory device, the memory device of the present invention has a three-dimensional stacked structure, so that the memory density and the memory capacity of the memory device can be significantly increased.

It should be noted that the drawings, structures and steps described above are used to describe some embodiments or application examples of the present invention, and the present invention is not limited to the scope and application examples of the structures and steps. Other embodiments of different structures, such as known components of different internal components, may be used, and the illustrated structures and steps may be modified according to the requirements of the actual application. Accordingly, the drawings are only for purposes of illustration and are not to be construed as limiting the invention. It will be apparent to those skilled in the art that the structures and processes involved in implementing the present invention, such as the arrangement or configuration of the elements and layers involved in the memory device, or the details of the fabrication steps, may be modified and varied as desired for specific applications.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.