阅读说明：本技术 具有用于不同电容密度电容器的侧壁间隔件的局部硅氧化 (Localized silicon oxidation with sidewall spacers for capacitors of different capacitance densities ) 是由 亨利·利茨曼·爱德华兹 于 2019-10-08 设计创作，主要内容包括：一种集成电路IC(100)包含第一电容器(150a)、第二电容器(150b)及与所述电容器一起配置用于在衬底(102)上的半导体表面层(106)中实现至少一个电路功能的功能电路(180)。所述电容器包含在局部硅氧化LOCOS氧化物(110a、110b)上的顶板(112),其中用于所述第二电容器的所述LOCOS氧化物的厚度比用于所述第一电容器的所述LOCOS氧化物的厚度厚。针对所述第一及第二电容器存在用于所述顶板的接触件(122a)及用于底板的接触件(122b)。(An Integrated Circuit (IC) (100) includes a first capacitor (150a), a second capacitor (150b), and a functional circuit (180) configured with the capacitors for implementing at least one circuit function in a semiconductor surface layer (106) on a substrate (102). The capacitor includes a top plate (112) on a local oxidation of silicon, LOCOS oxide (110a, 110b), wherein a thickness of the LOCOS oxide for the second capacitor is thicker than a thickness of the LOCOS oxide for the first capacitor. There is a contact (122a) for the top plate and a contact (122b) for a bottom plate for the first and second capacitors.)

1. A method of fabricating an integrated circuit, IC, comprising:

depositing a first oxygen diffusion barrier, ODB, layer on a pad oxide layer on a semiconductor surface layer on a substrate;

patterning and then etching the first ODB layer to form a first ODB layer opening and at least a second first ODB layer opening, wherein the width of the second first ODB layer opening is greater than the width of the first ODB layer opening;

growing a first LOCOS layer of local oxidation of silicon (LOCOS) in the first ODB layer opening and in the second first ODB layer opening;

depositing a second ODB layer, and then depositing a sacrificial sidewall film over the second ODB layer;

etching the sacrificial sidewall film to form a spacer in the second first ODB layer opening but not in the first ODB layer opening remaining blocked by the sacrificial sidewall film, and removing the second ODB layer not protected by the sacrificial sidewall film;

stripping the sacrificial side wall film;

growing a second LOCOS layer in the second first ODB layer opening but not in the first ODB layer opening;

removing the first and the second ODB layers, and

a top plate is formed over the first opening to complete a first capacitor and a top plate is formed over the second opening to complete a second capacitor.

2. The method of claim 1, wherein both the first capacitor and the second capacitor comprise planar capacitors.

3. The method of claim 1, further comprising etching the semiconductor surface layer to a predetermined depth in the first opening and in the second opening after the patterning and then etching the first ODB layer and before the growing the first LOCOS layer, wherein both the first capacitor and the second capacitor comprise trench capacitors.

4. The method of claim 1 further comprising etching the semiconductor surface layer in the second opening to a predetermined depth after the stripping the sacrificial sidewall film and before the growing the second LOCOS layer, wherein the first capacitor is a planar capacitor and the second capacitor is a trench capacitor.

5. The method of claim 1, wherein the first LOCOS layer is 200 to 1000A thick.

6. The method of claim 1, wherein both the first and second ODB layers comprise silicon nitride.

7. The method of claim 1, wherein the width of the second first ODB layer opening is at least 0.05 μ ι η greater than the width of the first ODB layer opening.

8. The method of claim 1, wherein the first ODB layer comprises silicon nitride and is 300-2000A thick.

9. The method of claim 1, wherein the top plate comprises polysilicon.

10. An Integrated Circuit (IC), comprising:

a first capacitor, a second capacitor and a functional circuit configured with the capacitor for implementing at least one circuit function in a semiconductor surface layer on a substrate;

the capacitor includes:

a top plate on the local silicon oxide LOCOS oxide layer, wherein a thickness of the LOCOS oxide layer for the second capacitor is thicker than a thickness of the LOCOS oxide layer for the first capacitor, an

Contacts for the top plate and contacts for the bottom plate for the first and second capacitors.

11. The IC of claim 10, wherein the thickness of the LOCOS oxide layer for the second capacitor is at least 500A thicker than the thickness of the LOCOS oxide layer for the first capacitor.

12. The IC of claim 10, wherein both the first capacitor and the second capacitor comprise planar capacitors.

13. The IC of claim 10, wherein both the first capacitor and the second capacitor comprise trench capacitors.

14. The IC of claim 13, wherein the semiconductor surface layer is recessed for the second capacitor as compared to the first capacitor.

15. The IC of claim 10, wherein a width of an opening of the LOCOS oxide layer for the second capacitor is at least 0.05 μ ι η greater than a width of an opening of the LOCOS oxide layer for the first capacitor.

16. The IC of claim 10, wherein the top plate comprises polysilicon.

17. The IC of claim 10, wherein the semiconductor surface layer comprises an epitaxial layer.

18. The IC of claim 10, wherein the contacts for the top plate and the bottom plate for the first and the second capacitors are both top side contacts.

Technical Field

The present description relates to an integrated circuit with LOCOS capacitors.

Background

Local oxidation of silicon (LOCOS) is a semiconductor manufacturing process that uses a patterned oxygen diffusion barrier layer, typically a silicon nitride layer on regions not intended to be oxidized, wherein a thermally grown silicon dioxide layer is formed in etched pores in the oxygen diffusion barrier layer of a given thickness, with thinner tapered silicon oxide regions formed along the edges of the oxygen diffusion barrier layer. The Si-silicon oxide interface is formed at a point lower than the rest of the silicon surface. Some capacitors utilize LOCOS oxide as their dielectric. While the width of the active region surrounded by LOCOS oxide can vary, LOCOS, like other oxide growth processes, provides a single given oxide thickness throughout the die and throughout the wafer.

Disclosure of Invention

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description, including the figures provided. This summary is not intended to limit the scope of the claimed subject matter.

Disclosed aspects include an Integrated Circuit (IC) formed in a semiconductor surface layer on a substrate including a first capacitor and a second capacitor. The first and second capacitors include a top plate over a LOCOS oxide, and a thickness of the LOCOS oxide for the second capacitor is thicker than a thickness of the LOCOS oxide for the first capacitor. For the first and second capacitors, there is a contact for the top plate and a contact for the bottom plate.

Drawings

Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

fig. 1 is a cross-sectional depiction of an example IC including first and second LOCOS capacitors having different LOCOS oxide thicknesses to provide different capacitance densities, according to an example.

Fig. 2A-2F are cross-sectional views showing a process progression of an example method of forming an IC including first and second planar LOCOS capacitors having different capacitance densities, according to an example.

Fig. 3A-3G are cross-sectional views showing a process progression of an example method of forming an IC including first and second trench LOCOS capacitors having different capacitance densities, according to an example.

Fig. 4A-4F are cross-sectional views showing a process progression of another example method of forming an IC having a first planar LOCOS capacitor and a second trench LOCOS capacitor having different capacitance densities according to an example.

Detailed Description

Examples are described with reference to the accompanying drawings, wherein like reference numerals are used to refer to like or equivalent elements. The order of acts or events described should not be considered limiting, as some acts or events may occur in different orders and/or concurrently with other acts or events. Moreover, some illustrated acts or events may not be required to implement a methodology in accordance with this description.

Furthermore, the terms "coupled to" or "coupled with …" (and the like) as used herein are intended to describe an indirect or direct electrical connection without further limitation. Thus, if a first device is "coupled" to a second device, that connection may be through a direct electrical connection where only parasitics are present in the path, or through an indirect electrical connection via intervening items including other devices and connections. For indirect coupling, the intermediate items generally do not modify the information of the signal, but may adjust its current level, voltage level, and/or power level.

The disclosed aspects recognize that it is desirable to be able to form capacitors of different capacitance densities (capacitance/unit area) using a single mask level and a single patterning step. This presents a cost and/or complexity problem for some power transistors integrated into a bipolar complementary metal oxide semiconductor (BiCMOS) process, as multiple different capacitance density capacitors are required to coexist in the same technology, including on the same IC product in some cases. It is also recognized that some LOCOS processes, like other oxidation processes, have the disadvantage of providing only a single oxide thickness. This description describes a LOCOS oxidation process flow that utilizes sidewall spacers to create two or more different LOCOS oxide thicknesses.

Forming sidewall spacers in wider Oxygen Diffusion Barrier (ODB) layer openings on the semiconductor surface layer, rather than forming sidewall spacers in narrower width ODB layer openings on the semiconductor surface, enables at least two different LOCOS oxide thicknesses to be produced from a single mask level and patterning step. A thicker LOCOS oxide for a planar LOCOS capacitor will be thicker in the thickest central region of the LOCOS oxide and in the thinner bird's beak (bird's peak) regions at the edges of the LOCOS oxide than a thinner LOCOS oxide. Sidewall spacers (e.g., comprising silicon nitride) formed in the wider first ODB layer openings, rather than in the narrower first ODB layer openings, result in two (or more) different LOCOS layer thicknesses, which are thus dependent on the width of the first ODB layer openings. The width of the wider first ODB layer opening (referred to herein as the second first ODB layer opening) is typically at least 0.05 μm wider than the width of the narrower first ODB layer opening (referred to herein as the first ODB layer opening).

Fig. 1 is a cross-sectional depiction of an example IC 100, the example IC 100 including a first trench capacitor 150a and a second trench capacitor 150b having different LOCOS oxide thicknesses to provide different capacitance densities. Second trench capacitor 150b is seen to be significantly wider and have a significantly thicker LOCOS oxide 110b thickness than the width and thickness of LOCOS oxide 110a for first trench capacitor 150 a. The trench capacitors 150a, 150b each have a top plate 112. The IC 100 also includes a functional circuit 180 shown as a block comprising circuit elements (including transistors, and typically including diodes, resistors, capacitors, etc.) formed in the semiconductor surface layer 106 of the substrate 102 or on the substrate 102, the substrate 102 together with the trench capacitors 150a and 150b configured for at least one circuit function, such as an analog (e.g., amplifier, power converter, or power Field Effect Transistor (FET)), RF, digital, or memory function.

Although field oxide is not shown, the IC 100 typically includes field oxide, which may include Shallow Trench Isolation (STI) structures or the field oxide may also have LOCOS oxide structures. A pre-metal dielectric (PMD) layer is shown at 159 with a pad oxide layer 158 below it. Top side contacts are shown formed through the PMD layer 159 and the pad oxide layer 158, including contact 122a to the top plate 112 and contact 122b to the portion of the semiconductor surface layer 106 that provides a bottom plate with metal contacts 123a and 123b (shown as metal 1(M1) contacts) thereon. The top side contact shown also includes contact 122c to functional circuit 180 having contact 123c of M1 thereon. Although trench capacitor 150a is shown with two trenches and trench capacitor 150b with one trench, a trench capacitor may generally have any number of trenches.

Fig. 2A-2G are cross-sectional views showing process progress of an example method of forming an IC including a first planar capacitor 180a and a second planar capacitor 180b having different LOCOS oxide thicknesses to provide different capacitance densities. Referring to fig. 2A, an in-process IC is shown after forming a first relatively narrow first ODB layer opening 164a and a second relatively wide first ODB layer opening 164b in a first ODB layer 160 on a pad oxide layer 158 layer on a semiconductor surface layer 106 of a substrate 102. The ODB layer openings 164a, 164b are typically formed using a photoresist pattern as an etch mask, and then an aperture comprising a first width and at least a second width is etched in the first ODB layer 160.

The substrate 102 may be formed by: starting from a p-type silicon wafer, possibly with at least one epitaxial layer thereon, and passing through a silicon wafer at 1X 10¹⁵cm^-2To 1X 10¹⁶cm^-2An n-type dopant (e.g., antimony or arsenic) is implanted to form the n-type buried layer. The thermally driven process heats the wafer to activate and diffuse the implanted n-type dopants. A p-type layer for the semiconductor surface layer 106 may be formed on the wafer by an epitaxial process using in-situ p-type doping. The epitaxially formed material may be, for example, 4 microns to 6 microns thick. Although not shown, there may be an n-type buried layer overlapping the boundary between the raw silicon wafer and the epitaxially grown material for the semiconductor surface layer 106. The average bulk resistivity of the p-type layer may be, for example, 1 ohm-cm to 10 ohm-cm. In the case of the p-type semiconductor surface layer 106, an optional p-type buried layer may also be formed by implanting boron at an energy of, for example, 2 megaelectron volts (MeV) to 3 MeV.

The pad oxide layer 158 may be, for example, 20-250A thick, 100A thick, and may be formed by thermal oxidation or by any of several Chemical Vapor Deposition (CVD) processes. The first ODB layer 160 may comprise, for example, silicon nitride, for example, formed by a Low Pressure Chemical Vapor Deposition (LPCVD) process using dichlorosilane and ammonia. Alternatively, the silicon nitride for the first ODB layer 160 may be formed by decomposition of bis (t-butylamino) silane (BTBAS). Other processes for forming the first ODB layer 160 are possible.

The etch mask may comprise a photoresist formed by a photolithography process, and may also comprise a hard mask material, such as amorphous carbon, and may comprise an antireflective layer, such as an organic bottom antireflective coating (BARC). The exposed area of the top surface of the semiconductor surface layer 106, defined by the second first ODB layer opening 164b for the second planar capacitor 180b, has a dimension wider than the width of the first ODB layer opening 164a for the first planar capacitor 180 a. The second first ODB layer opening 164b is wide enough so that after etching the second ODB layer 181 as described below with respect to fig. 2C, the central portion of the etched region becomes clear resulting in the formation of sidewall spacers, while the first ODB layer opening 164a for the first planar capacitor 180a has a width narrow enough so that the entire first ODB layer opening 164a remains covered by the second ODB layer 181 after etching the second ODB layer 181. The first ODB layer 160 in the areas exposed by the etch mask may be removed by a wet etch (e.g., aqueous phosphoric acid) that undercuts the etch mask. A portion of the pad oxide 158 may also be removed in the areas exposed by the etch mask.

Referring now to fig. 2B, this figure shows the results after growing the first LOCOS oxide layer 210, with an example thickness between 200 to 1,000A. A characteristic LOCOS oxide bird beak is shown with a thinner LOCOS oxide at the edge under the first ODB layer 160.

An example furnace thermal oxidation process for growing first LOCOS oxide layer 210 may include using an environment of 2% to 10% oxygen, raising the furnace temperature to about 1000 ℃ over a period of 45 minutes to 90 minutes, maintaining the furnace temperature at about 1000 ℃ for a period of 10 minutes to 20 minutes while increasing the oxygen in the environment to 80% to 95% oxygen, maintaining the furnace temperature at about 1000 ℃ for a period of 60 minutes to 120 minutes while maintaining the oxygen in the environment at 80% to 95% oxygen, and adding hydrogen chloride gas to the environment, maintaining the furnace temperature at about 1000 ℃ for a period of 30 minutes to 90 minutes while maintaining the oxygen in the environment at 80% to 95% oxygen in the absence of hydrogen chloride, and reducing the furnace temperature in a nitrogen environment.

Fig. 2C shows the result after deposition of the second ODB layer 181 followed by deposition of the sacrificial sidewall film 182 that acts as a sacrificial sidewall layer over the second ODB layer 181, followed by a maskless etch of the sacrificial sidewall film 182 to form spacers 182a in the second first ODB layer opening 164b because it is wide enough. The second ODB layer 181 is removed in the second first ODB layer opening 164b because it is not protected by the sacrificial sidewall film 182. The sidewall spacer is not shown in the first ODB layer opening 164a because it is narrower than the second first ODB layer opening 164b, such that the first ODB layer opening 164a is again shown as a sacrificial sidewall film 182 over the second ODB layer 181 in the first ODB layer opening 164 a.

Fig. 2D shows the result after stripping the sacrificial sidewall film 182 and the spacers 182a, which reveals the spacers 181a in the second first ODB layer opening 164 b. Fig. 2E shows the result after growing the second LOCOS oxide layer, creating additional LOCOS portions, shown as LOCOS 2 with portions above and below the first LOCOS oxide layer 210, which is typically 500 to 1,500A of LOCOS 2 at the center of the wider second first ODB layer opening 164b of the second planar capacitor 180b, which is not shown growing LOCOS 2 in the first ODB layer opening 164a as a narrower opening due to the presence of the second ODB layer 181 over the entire opening.

Thus, for the narrower first ODB layer opening 164a, the sidewalls of the second ODB layer 181 remain merged so that only the first LOCOS oxidation process is able to oxidize the exposed silicon surface. This thinner LOCOS oxide is used to form all of the oxide of the first planar capacitor 180 a. The sidewalls are different for the wider second first ODB layer opening 164b (as shown as spacer 181a in fig. 2D) so that the second LOCOS oxidation can make the LOCOS layer thicker by adding LOCOS 2 in the second first ODB layer opening 164 b. As with the first LOCOS oxide layer 210, the LOCOS 2 oxide will taper under the spacers 181a, which correspond to the beak area.

This completes the oxide thickness, making the LOCOS oxide for the second planar capacitor 180b thicker, since it contains LOCOS oxide from both the first LOCOS oxide layer 210 and the LOCOS 2 oxide, as compared to the LOCOS oxide of the first planar capacitor 180a, which contains only the first LOCOS oxide layer 210. Fig. 2F shows the result after removing the first ODB layer 160 and the second ODB layer 181, and then depositing a top plate layer, and patterning this top plate layer to form the top plate 112 (e.g., a top plate comprising polysilicon over LOCOS oxide for the first and second planar capacitors 180a, 180 b). Spacers 191 are shown on the sidewalls of the top plate 112.

Fig. 3A-3G are cross-sectional views showing process progress of an example method of forming an IC including a first trench capacitor 350a and a second trench capacitor 350b having different LOCOS oxide thicknesses to provide different capacitance densities. Fig. 3A shows the result after forming a first ODB layer opening 164a (shown as relatively narrow) and a second first ODB layer opening 164b (shown as relatively wide) in the first ODB layer 160 on the pad oxide layer 158 layer on the semiconductor surface layer 106 on the substrate 102. The ODB layer opening is typically formed by patterning an etch mask using a photoresist, and then etching the first ODB layer 160 to form a first ODB layer opening 164a for the trench capacitor 350a and a second first ODB layer opening 164b for the trench capacitor 350 b. Fig. 3B shows the result after a silicon etch of the top surface of the semiconductor surface layer 106 after an oxide etch to remove the pad oxide 158 in the first and second first ODB layer openings 164a, 164B. Example silicon etch depths are 100A to 6000A.

Fig. 3C shows the results after growing the first LOCOS oxide layer 210, with example thicknesses between 200A and 1,000A. A characteristic LOCOS oxidized bird beak was shown. Fig. 3D shows the result after deposition of the second ODB layer 181, followed by deposition of a sacrificial sidewall film 182 that serves as a sacrificial sidewall layer over the second ODB layer 181, followed by maskless etching of the sacrificial sidewall film 182 to form spacers 182a in the relatively wider second first ODB layer openings 164b, but without forming sidewall spacers, shown as sacrificial sidewall film 182, over the relatively narrower entire first ODB layer openings 164a, and followed by removal of the second ODB layer 181 not protected by the sacrificial sidewall film 182. Fig. 3E shows the result after removing the sacrificial sidewall film 182 including the spacers 182 a.

Fig. 3F shows the result after growing a second LOCOS oxide layer in the second first ODB layer opening 164b for trench capacitor 350b, creating additional LOCOS portions, shown as LOCOS 2 above and below the first LOCOS oxide layer 210, which is typically 500 to 1,500A of LOCOS at the center of the wider second first ODB layer opening 164 b. Growth of LOCOS 2 in the narrower first ODB layer openings 164a is not shown due to the presence of the second ODB layer 181 over the entire opening.

Thus, for the narrower first ODB layer opening 164a, the sidewalls of the second ODB layer 181 remain merged and only the first LOCOS oxidation process is able to oxidize the exposed silicon. This thinner oxide is used to form the LOCOS oxide for trench capacitor 350 a. The sidewalls are different for the wider second first ODB layer opening 164b (as shown by spacer 182a in fig. 3D), so that the second LOCOS oxidation adds LOCOS 2, which makes the LOCOS layer in the middle of the second first ODB layer opening 164b for the trench capacitor 350b thicker. The LOCOS oxide will taper under the spacer 182a, which corresponds to a bird's beak area controlled by the spacer thickness. This thicker LOCOS oxide is used to form trench capacitor 350 b.

This completes the oxide thickness such that the LOCOS oxide for trench capacitor 350b is thicker than the LOCOS oxide for trench capacitor 350 a. Fig. 3G shows the result after the first ODB layer 160 and the second ODB layer 181 are removed, and then the patterned top plate 112 is formed, which patterned top plate 112 may comprise polysilicon over LOCOS oxide for the trench capacitors 350a and 350 b.

Fig. 4A-4F are cross-sectional views showing a process progression of another example method of forming an IC including a first planar capacitor shown as 450a and a second trench capacitor shown as 450b having different LOCOS thicknesses, according to one example. Fig. 4A shows the result after forming a first, relatively narrow first ODB layer opening 164A for a first trench capacitor and a second, relatively wide first ODB layer opening 164b for a second trench capacitor 164b in a first ODB layer 160 on a pad oxide layer 158 layer on a substrate 102 having a semiconductor surface layer 106. This process typically includes patterning an etch mask using a photoresist and then etching the first ODB layer 160 to form first and second first ODB layer openings 164a, 164 b.

Fig. 4B shows the results after growing the first LOCOS oxide layer 210, with example thicknesses between 200 and 1,000A. A characteristic LOCOS oxidized bird beak was shown. Fig. 4C shows the result after deposition of the second ODB layer 181, followed by deposition of the sacrificial sidewall film 182 used as a sacrificial sidewall layer over the second ODB layer 181, followed by maskless etching of the sacrificial sidewall film 182 and the second ODB layer 181. In the second first ODB layer opening 164b associated with the second trench capacitor 450b, because it is relatively wide, the etching of the sacrificial sidewall film 182 forms a spacer 182a as shown, which enables the maskless etch to etch away the second ODB layer 181 from the edges in the second first ODB layer opening 164b to form a spacer 181a, because the second ODB layer 181 is not protected there by the sacrificial sidewall film 182. Sidewall spacers are not shown in the first ODB layer opening 164a associated with the first trench capacitor 450a because they are narrower, so after the maskless etch, there is a sacrificial sidewall film 182 on the second ODB layer 181 over the entire area of the first ODB layer opening 164 a.

Fig. 4D shows the result after stripping the sacrificial sidewall film 182 in the first ODB layer opening 164a for the first trench capacitor 450a and the spacer 182a in the second first ODB layer opening 164b for the second trench capacitor 450b, and then performing a silicon etch in the exposed semiconductor surface layer 106 in the second first ODB layer opening 164b, wherein the second ODB layer 181 extends over the entire first ODB layer opening 164a for the first trench capacitor 450a preventing any etching of the semiconductor surface layer 106. The silicon etch depth for the second trench capacitor 450b may be 100A to 30 μm, with an example silicon etch depth between 500A to 2 μm.

Fig. 4E shows the results after growing the second LOCOS oxide layer, creating LOCOS portions, shown as LOCOS 2 above and below the first LOCOS oxide layer 210, which is typically 500 to 1,500A of LOCOS oxide at the center of the wider second first ODB layer opening 164b for the second trench capacitor 450b, where LOCOS 2 is not shown grown in the narrower first ODB layer opening 164a for the first trench capacitor 450A due to the presence of the second ODB layer 181 over the entire opening.

Thus, for the narrower first ODB layer opening 164a for the first trench capacitor 450a, the sidewalls of the second ODB layer 181 remain merged and only the first LOCOS oxidation process is able to oxidize the exposed silicon. This thinner oxide is used to form the oxide for the first trench capacitor 450 a. For the wider second first ODB layer opening 164b for the second trench capacitor 450b, the sidewalls are different, so a second LOCOS oxidation can be grown in the middle of the second first ODB layer opening 164 b. The oxide will taper under the spacers 182a, which corresponds to a bird's beak area controlled by the spacer thickness. This thicker oxide is used to form trench capacitor 450 b. Fig. 4E shows the result after removing the sacrificial sidewall film 182 including the spacers 182 a. Fig. 4F shows the result after the first and second ODB layers 160, 181 and spacers 181a are removed, and then the patterned top plate 112, which may comprise polysilicon over LOCOS oxide for the trench capacitors 450a, 450b, is formed.

A front-end-of-line (FEOL) MOS process to complete the formation of the capacitor, including the formation of the top plate and contacts, is described below. A patterned layer of top plate material, as shown as 112 in fig. 1, is formed over the LOCOS oxide 110a, 110b layer. The top plate 112 may comprise, for example, polysilicon (polysilicon), referred to herein as polysilicon (polysilicon), which may be doped with an n-type dopant. The polysilicon as a layer of the top plate 112 may be, for example, 300 nanometers to 800 nanometers thick.

The disclosed aspects may be used to form semiconductor dies that may be integrated into various assembly flows to form a variety of different devices and related products. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active and passive elements, including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, and the like. Further, the semiconductor die may be formed by a variety of processes, including bipolar, Insulated Gate Bipolar Transistor (IGBT), CMOS, BiCMOS, and MEMS.

Those skilled in the art to which this description relates will appreciate that many other aspects are possible within the scope of the claimed invention, and that further additions, deletions, substitutions and modifications may be made to the described aspects without departing from the scope of the present description.