阅读说明：本技术 具有电路的集成组合件 (Integrated assembly with circuit ) 是由 李继云 C·L·英戈尔斯 于 2020-07-30 设计创作，主要内容包括：本申请案涉及具有电路的集成组合件。一些实施例包含一种具有呈第一阵列的第一存储器单元及呈第二阵列的第二存储器单元的集成组合件。第一数字线及第二数字线分别沿着所述第一阵列及所述第二阵列的列延伸。所述第一数字线通过感测放大器电路与所述第二数字线比较性地耦合。所述感测放大器电路经分布在至少两个贴片位置当中。所述贴片位置中的第一者具有所述感测放大器电路的第一部分且具有第一局部列选择结构。所述贴片位置中的第二者具有所述感测放大器电路的第二部分且具有第二局部列选择结构。列选择总线从解码器电路延伸到所述第一局部列选择结构及所述第二局部列选择结构。(The present application relates to an integrated assembly having circuitry. Some embodiments include an integrated assembly having a first memory cell in a first array and a second memory cell in a second array. First and second digit lines extend along columns of the first and second arrays, respectively. The first digit line is comparatively coupled with the second digit line through a sense amplifier circuit. The sense amplifier circuitry is distributed among at least two patch locations. A first one of the patch locations has a first portion of the sense amplifier circuitry and has a first local column select structure. A second one of the patch locations has a second portion of the sense amplifier circuitry and has a second local column select structure. A column select bus extends from a decoder circuit to the first and second local column select structures.)

1. An integrated assembly, comprising:

a first array of first memory cells;

a second array of second memory cells;

a first digit line extending along a column of the first array;

a second digit line extending along a column of the second array;

a sense amplifier circuit configured to comparatively couple the first digit line and the second digit line; the sense amplifier circuitry is distributed among at least two patch locations; a first of the at least two patch locations has a first portion of the sense amplifier circuitry and has a first local column select structure; the first local column select structure is associated with the first digit line and the second digit line comparatively coupled through the first portion of the sense amplifier circuit; a second one of the at least two patch locations has a second portion of the sense amplifier circuitry and has a second local column select structure; the second local column select structure is associated with the first digit line and the second digit line comparatively coupled through the second portion of the sense amplifier circuitry; and

a column select bus extending from a decoder circuit to the first and second local column select structures; the column select bus is selectively coupled to the first local column select structure by a first switch and to the second local column select structure by a second switch.

2. The integration assembly of claim 1, comprising word lines extending along rows of the first and second arrays, and wherein first and second patch locations include word line driver circuitry coupled with the word lines.

3. The integrated assembly of claim 1, wherein the first switch and the second switch are transistors.

4. The integrated assembly of claim 1, wherein the first digit line and the second digit line are selectively coupled with an input/output circuit, and wherein the first local column selection structure and the second local column selection structure control the selective coupling of the first digit line and the second digit line with the input/output circuit.

5. The integrated assembly of claim 1, wherein the first digit line and the second digit line are selectively coupled with input/output circuitry through transistor devices, and wherein the first local column selection structure and the second local column selection structure are coupled with gates of the transistor devices.

6. The integrated assembly of claim 1, wherein the first array and the second array are above the sense amplifier circuitry.

7. The integrated assembly of claim 6, wherein the sense amplifier circuitry is supported by a substrate level; wherein two additional deck planes are above the base deck plane, wherein the two additional deck planes are a first deck plane and a second deck plane; wherein some of the first memory cells of the first array are along the first level and some of the first memory cells are along the second level; and wherein some of the second memory cells of the second array are along the first level and some of the second memory cells are along the second level.

8. The integration assembly of claim 7, wherein each of the first digit lines extends along both the first level and the second level, and wherein each of the second digit lines extends along both the first level and the second level.

9. The integration assembly of claim 8, comprising word lines extending along rows of the first and second arrays; wherein the first and second patch locations include word line driver circuitry coupled with the word lines; wherein the sense amplifier circuitry within each of the tile locations is subdivided into two separate modules corresponding to SA-O and SA-E, and wherein the word line driver circuitry within each of the tile locations is subdivided into at least two separate modules.

10. The integrated assembly of claim 1, wherein:

the first patch location has a first orientation when viewed from above; and is

The second patch position has a second orientation when viewed from above, wherein the second orientation is inverted relative to the first orientation.

11. The integrated assembly of claim 1, comprising more than two of the tile locations.

12. The integrated assembly of claim 1, wherein the first memory cell and the second memory cell are DRAM cells.

13. The integrated assembly of claim 12, wherein each of the DRAM cells comprises a vertically extending access transistor below a container capacitor.

14. An integrated assembly, comprising:

a first array of first memory cells;

a second array of second memory cells;

a first digit line extending along a column of the first array;

a second digit line extending along a column of the second array;

a sense amplifier circuit configured to comparatively couple the first digit line and the second digit line; the sense amplifier circuit is subdivided into at least four patch locations; a first of the at least four patch locations has a first portion of the sense amplifier circuitry and has a first local column select structure; a second one of the at least four patch locations has a second portion of the sense amplifier circuitry and has a second local column select structure; a third one of the at least four patch locations has a third portion of the sense amplifier circuitry and has a third local column select structure; a fourth one of the at least four patch locations has a fourth portion of the sense amplifier circuitry and has a fourth partial column select structure;

a first column select bus extending from a decoder circuit to the first and second local column select structures; the first column select bus is selectively coupled to the first local column select structure by a first switch and to the second local column select structure by a second switch; and

a second column select bus extending from the decoder circuit to the third and fourth local column select structures; the second column select bus is selectively coupled to the third local column select structures by a third switch and to the fourth local column select structures by a fourth switch.

15. The integration assembly of claim 14, wherein the first switch, the second switch, the third switch, and the fourth switch are transistors.

16. The integration assembly of claim 14, wherein the first switch, the second switch, the third switch, and the fourth switch are all coupled to a global switch control circuit.

17. The integrated assembly of claim 16, wherein the first switch and the third switch are both coupled to a first local switch control circuit that is in turn coupled to the global switch control circuit, and wherein the second switch and the fourth switch are both coupled to a second local switch control circuit that is in turn coupled to the global switch control circuit.

18. The integrated assembly of claim 14 in an operational mode with only one of the at least four switches in a closed position and all others of the at least four switches in an open position.

19. The integrated assembly of claim 14 in an operational mode with at least two of the at least four switches in a closed position and at least one other of the at least four switches in an open position.

20. The integrated assembly of claim 14, wherein the first and third patch locations share connections with inputs/outputs.

21. The integration assembly of claim 14, comprising more than four of the tile locations.

22. An integrated assembly, comprising:

a substrate comprising sense amplifier circuitry subdivided into at least two spaced apart patch locations; each of the tile locations includes a SA-O region and a SA-E region;

a first local column select structure associated with the first patch location and a second local column select structure associated with the second patch location;

a column select bus extending from a decoder circuit to the first and second local column select structures; the column select bus is selectively coupled to the first local column select structure by a first switch and to the second local column select structure by a second switch;

a first level over the substrate; the first level includes a first portion of a first array of first memory cells and includes a first portion of a second array of second memory cells;

a second deck above the first deck; the second deck includes a second portion of the first array of the first memory cells and includes a second portion of the second array of the second memory cells;

a first digit line associated with the first array;

a second digit line associated with the second array; and is

The first digit line and the second digit line are comparatively coupled to each other through the sense amplifier circuit.

23. The integrated assembly of claim 22, wherein:

the first digit line is used to address the first memory cell;

the first word line is also used to address the first memory cell;

each of the first memory cells is uniquely addressed by one of the first digit lines and one of the first word lines;

the second digit line is for addressing the second memory cell;

a second word line is also used to address the second memory cell; and is

Each of the second memory cells is uniquely addressed by one of the second digit lines and one of the second word lines.

24. The integrated assembly of claim 23, wherein the first and second word lines are coupled with word line driver circuitry along the substrate and within the patch location.

25. The integration assembly of claim 24, wherein at least one of the tile locations is directly below the first memory array and the second memory array.

26. The integrated assembly of claim 22, wherein the first switch and the second switch are transistors.

27. The integrated assembly of claim 22, wherein the first digit line and the second digit line are selectively coupled with an input/output circuit, and wherein the first local column selection structure and the second local column selection structure control the selective coupling of the first digit line and the second digit line with the input/output circuit.

28. The integrated assembly of claim 22, comprising more than two of the tile locations.

29. The integrated assembly of claim 22, wherein the first memory cell and the second memory cell are DRAM cells.

30. The integrated assembly of claim 29, wherein each of the DRAM cells comprises a vertically extending access transistor below a capacitor.

Technical Field

A memory array (e.g., a DRAM array). An integrated assembly comprising vertically stacked levels. An integrated assembly having sense amplifier circuits distributed among two or more locations and having circuitry configured to isolate local column select structures from global structures (column select buses).

Background

Memory is utilized in modern computing architectures to store data. One type of memory is Dynamic Random Access Memory (DRAM). DRAM may provide the advantages of simple structure, low cost, and high speed compared to alternative types of memory.

DRAM may utilize a memory cell having one capacitor in combination with one transistor (a so-called 1T-1C memory cell), where the capacitor is coupled with the source/drain region of the transistor. An example 1T-1C memory cell 2 is shown in FIG. 1, where the transistor is labeled T and the capacitor is labeled C. The capacitor has one node coupled with the source/drain region of the transistor and another node coupled with common plate CP. The common plate can be coupled with any suitable voltage, such as a voltage ranging from greater than or equal to ground to less than or equal to VCC (i.e., ground ≦ CP ≦ VCC). In some applications, the common plate is at a voltage of about one-half of VCC (i.e., about VCC/2). The transistor has a gate coupled to a word line WL (i.e., access line) and has source/drain regions coupled to a bit line BL (i.e., digit line or sense line). In operation, an electric field generated by a voltage along the word line can gate couple a bit line to the capacitor during read/write operations.

Another prior art 1T-1C memory cell configuration is shown in FIG. 2. The configuration of FIG. 2 shows two memory cells 2a and 2 b; wherein memory cell 2a includes transistor T1 and capacitor C1, and memory cell 2b includes transistor T2 and capacitor C2. Word lines WL0 and WL1 are electrically coupled to the gates of transistors T1 and T2, respectively. The connection to the bit line BL is shared by the memory cells 2a and 2 b.

The memory cells described above can be incorporated into a memory array, and in some applications the memory array can have an open bit line arrangement. An example integration assembly 9 having an open bit line architecture is shown in fig. 3. The assembly 9 includes two laterally adjacent memory arrays ("array 1" and "array 2"), with each of the arrays including memory cells of the type described in figure 2 (not labeled in figure 3 for simplicity of the drawing). Word lines WL 0-WL 7 extend across the array and are coupled with word line drivers. The digit lines D0 to D8 are associated with the first array (array 1) and the digit lines D0 to D8 are associated with the second array (array 2). Sense amplifiers SA 0-SA 8 are provided between the first and second arrays. The same height digitlines are paired with each other and compared by the sense amplifier (e.g., digitlines D0 and D0 are paired with each other and compared with sense amplifier SA 0). In a read operation, one of the paired digit lines can be used as a reference in determining an electrical property (e.g., voltage) of the other of the paired digit lines.

Individual digit lines are independently addressed using column DECODER circuitry (DECODER).

A continuing goal of integrated circuit fabrication is to increase packing density and thus integration. It is desirable to develop three-dimensional arrangements with tightly packed memory.

Disclosure of Invention

In one aspect, the present application provides an integrated assembly comprising: a first array of first memory cells; a second array of second memory cells; a first digit line extending along a column of the first array; a second digit line extending along a column of the second array; a sense amplifier circuit configured to comparatively couple the first digit line and the second digit line; the sense amplifier circuitry is distributed among at least two patch locations; a first of the at least two patch locations has a first portion of the sense amplifier circuitry and has a first local column select structure; the first local column select structure is associated with the first digit line and the second digit line comparatively coupled through the first portion of the sense amplifier circuit; a second one of the at least two patch locations has a second portion of the sense amplifier circuitry and has a second local column select structure; the second local column select structure is associated with the first digit line and the second digit line comparatively coupled through the second portion of the sense amplifier circuitry; and a column select bus extending from a decoder circuit to the first and second local column select structures; the column select bus is selectively coupled to the first local column select structure by a first switch and to the second local column select structure by a second switch.

In another aspect, the present application further provides an integrated assembly comprising: a first array of first memory cells; a second array of second memory cells; a first digit line extending along a column of the first array; a second digit line extending along a column of the second array; a sense amplifier circuit configured to comparatively couple the first digit line and the second digit line; the sense amplifier circuit is subdivided into at least four patch locations; a first of the at least four patch locations has a first portion of the sense amplifier circuitry and has a first local column select structure; a second one of the at least four patch locations has a second portion of the sense amplifier circuitry and has a second local column select structure; a third one of the at least four patch locations has a third portion of the sense amplifier circuitry and has a third local column select structure; a fourth one of the at least four patch locations has a fourth portion of the sense amplifier circuitry and has a fourth partial column select structure; a first column select bus extending from a decoder circuit to the first and second local column select structures; the first column select bus is selectively coupled to the first local column select structure by a first switch and to the second local column select structure by a second switch; and a second column select bus extending from the decoder circuit to the third and fourth local column select structures; the second column select bus is selectively coupled to the third local column select structures by a third switch and to the fourth local column select structures by a fourth switch.

In yet another aspect, the present application further provides an integrated assembly comprising: a substrate comprising sense amplifier circuitry subdivided into at least two spaced apart patch locations; each of the tile locations includes a SA-O region and a SA-E region; a first local column select structure associated with the first patch location and a second local column select structure associated with the second patch location; a column select bus extending from a decoder circuit to the first and second local column select structures; the column select bus is selectively coupled to the first local column select structure by a first switch and to the second local column select structure by a second switch; a first level over the substrate; the first level includes a first portion of a first array of first memory cells and includes a first portion of a second array of second memory cells; a second deck above the first deck; the second deck includes a second portion of the first array of the first memory cells and includes a second portion of the second array of the second memory cells; a first digit line associated with the first array; a second digit line associated with the second array; and the first and second digit lines are comparatively coupled to each other through the sense amplifier circuitry.

Drawings

FIG. 1 is a schematic diagram of a prior art memory cell having one transistor and one capacitor.

FIG. 2 is a schematic diagram of a pair of prior art memory cells each having one transistor and one capacitor and sharing a bitline connection.

FIG. 3 is a schematic diagram of a prior art integration assembly having an open bit line architecture.

FIG. 4 is a schematic diagram of an example integrated assembly having multiple levels vertically displaced relative to each other.

Figure 5 is a diagrammatic top view of a region of a deck having multiple patch locations.

Fig. 6 is a diagrammatic, schematic view of a region of an example patch location.

FIG. 7 is a diagrammatic, schematic view of a region of an example device having multiple patch locations with local column select structures controllably coupled with decoder circuitry.

FIG. 8 is a diagrammatic, schematic view of regions of the example device of FIG. 7 shown in a different mode of operation relative to FIG. 7.

Fig. 9 is a diagrammatic, schematic view of regions of the example device of fig. 7 shown in a different mode of operation relative to fig. 7 and 8.

FIG. 10 is a diagrammatic, schematic view of regions of the example device of FIG. 7, and additionally shows example connections with input/output (I/O).

FIG. 11 is a diagrammatic, schematic view of regions of the example device of FIG. 7, and additionally shows an example switch configured as a transistor.

Fig. 12 is a diagrammatic, cross-sectional side view and schematic view of a region of an example multi-level assembly showing an example arrangement of circuit components.

Fig. 13 is a diagrammatic side view and schematic view of a region of an example multi-level assembly showing an example arrangement of circuit components.

FIG. 14 is a diagrammatic schematic of a region of an example sense amplifier circuit.

Detailed Description

Some embodiments include integrated assemblies (e.g., DRAM components) having sense amplifier circuitry distributed among two or more separate regions. The separate areas may be referred to as patch locations and may be considered together to form a quilt pattern. Each of the patch locations may be coupled with an associated local column select structure (e.g., a wire, line, etc.) that selectively couples the digit line from the patch location with an input/output (I/O) to transfer data to and from the digit line. The local column select structures may be selectively coupled to one or more column select buses (CS buses) by switches (e.g., transistors). The CS bus may be coupled with control circuitry (e.g., column decoder circuitry). A problem with some conventional integrated assemblies may be; all digit lines of a memory arrangement (e.g., DRAM) are non-selectively coupled with a column decoder circuit through a CS bus, and routing through all such digit lines creates additional capacitance on the CS bus to slow down signals and/or cause other difficulties. Some embodiments include switches that selectively couple some digit lines of a memory arrangement to a CS bus while decoupling other digit lines from the CS bus, which can mitigate or prevent problems associated with conventional assemblies. Example embodiments are described with reference to fig. 4-14.

Referring to fig. 4, the integrated assembly 10 includes a base 12, a first level 14 above the base, and a second level 16 above the first level. Structures 12, 14 and 16 are stacked vertically above one another. Base 12, first level 14, and second level 16 may be considered as examples of levels stacked on top of each other. The levels may be within different semiconductor dies, or at least two of the levels may be within the same semiconductor die.

First and second levels 14 and 16 have memory regions 18 and 22, respectively. First and second memory arrays (array 1 and array 2) are supported by first and second levels 14 and 16, with each of the memory arrays having a first portion along first (lower) level 14 and a second portion along second (lower) level 16. The first memory array includes a second Memory Cell (MC)20a, and the second memory array includes a second Memory Cell (MC)20 b. The memory cells are illustrated diagrammatically as circles. Only portions of the first memory cell and the second memory cell are marked. The first and second memory arrays may include any suitable number of memory cells, and may include hundreds, thousands, millions, etc. of memory cells in some embodiments. Memory cells MC may be DRAM cells and may be configured in some embodiments with reference to arrangements of the type described in prior art fig. 1-3 (i.e., array 1 and array 2 may be DRAM arrays).

In some embodiments, first and second levels 14 and 16 may be referred to as first and second memory levels, respectively.

Substrate 12 may comprise a semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base 12 may be referred to as a semiconductor substrate. The term "semiconductor substrate" refers to any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrate described above. In some applications, base 12 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, and the like. Each of levels 14 and 16 may also comprise semiconductor material.

In the embodiment shown, substrate 12 includes sense amplifier circuitry (SA)26 and word line driver circuitry (WD) 28.

The sense amplifier circuit includes regions (modules) labeled "SA-E" to identify them as being associated with "even" portions of the circuit and regions (modules) labeled "SA-O" to identify them as being associated with "odd" portions of the circuit. The terms "even" and "odd" are arbitrary and are used to distinguish different sense amplifier circuits from each other. The illustrated configuration has sense amplifier modules SA-O and SA-E paired with each other and distributed among the patch locations (patch areas) 24. The SA-O and SA-E modules within each of the patch areas 24 are laterally displaced relative to each other.

Two of the patch locations 24 are shown in fig. 4 and are labeled as patch 1 and patch 2, respectively. The patch locations 24 are spread across the base 12 and spaced apart from one another. Although two patch locations 24 are illustrated, it should be understood that any suitable number of patch locations may be utilized. In some embodiments, there may be at least two of the tile locations, at least three of the tile locations, at least four of the tile locations, at least eight of the tile locations, and so on.

The modules SA-O and SA-E of patch 1 may be considered part of the overall configuration of sense amplifier circuitry, with this configuration of sense amplifier circuitry being associated with memories within array 1 and array 2 (i.e., memories along levels 14 and 16). Each of the tile locations may comprise its own portion of the overall configuration of sense amplifier circuitry associated with the memories within array 1 and array 2.

In the embodiment shown, two of the patch locations 24 are located directly below the memory cells MC of array 1 and array 2. In some embodiments, there may be a large number of patch locations, and one or more of the patch locations may be under the memory cells of array 1 and array 2.

The word line driver circuits (i.e., row driver circuits) include regions labeled SWD-UE, SWD-UO, SWD-LE, and SWD-LO. The acronym SWD stands for sub-wordline driver, and is used to emphasize that the components SWD-UE, SWD-UO, SWD-LE, and SWD-LO are part of a common wordline driver circuit. The word line driver circuits SWD-UE and SWD-LE are utilized together during operation of Memory Cells (MC) associated with "even" circuits coupled with: SA-E; SWD-LE along lower level 14 drives wordlines; and SWD-UE driving wordlines along upper level 16. The word line driver circuits SWD-LO and SWD-UO are utilized together during operation of Memory Cells (MC) associated with an "odd" circuit coupled with: SA-O; SWD-LO along lower level 14 drives the wordlines; and SWD-UO along upper level 16 drives the word lines. In some embodiments, the wordline driver circuits SWD-UE and SWD-LE may be considered as first wordline driver circuits (circuits for driving "even" circuits), and the wordline driver circuits SWD-UO and SWD-LO may be considered as second wordline driver circuits (circuits for driving "odd" circuits). In some embodiments, the word line driver circuits SWD-UE, SWD-UO, SWD-LO, and SWD-LE may be considered as separate modules with respect to each other.

The first digit lines D0, D1, and D8 are associated with a first memory array (array 1). First digit lines D0, D1, and D8 extend along columns of the first memory array (array 1) and are coupled with first memory cell 20a of the first memory array. Digit lines D0, D1, and D8 are laterally spaced apart from one another and may represent a large number of substantially identical digit lines extending across the first memory array; wherein the term "substantially the same" means the same within reasonable manufacturing and measurement tolerances.

The first digit lines alternate between even first digit lines and odd first digit lines, where digit lines D0 and D8 represent even first digit lines and digit line D1 represents odd first digit lines. Even first digit lines (e.g., D0) are coupled with SA-E modules (with D0 coupled with modules in patch 1 and D8 coupled with modules in patch 2). An odd first digit line (e.g., D1) is coupled with the SA-O module. Digit lines D0, D1, and D8 have a first portion along first level 14 and have a second portion along second level 16.

Second digit lines D0, D1, and D8 are associated with the second memory array (array 2). Second digit lines D0, D1, and D8 extend along columns of the second memory array and are coupled to second memory cell 20b of the second memory array (array 2). Digit lines D0, D1, and D8 are laterally spaced from one another and may represent a plurality of substantially identical digit lines extending across the second memory array.

The second digit lines alternate between even second digit lines and odd second digit lines, wherein digit lines D0 and D8 represent even second digit lines and digit line D1 represents odd second digit lines. Even second digit lines (e.g., D0) are coupled to the SA-E modules and odd second digit lines (e.g., D1) are coupled to the SA-O modules. Digit lines D0, D1, and D8 have a first portion along first level 14 and have a second portion along second level 16.

Even first digit lines D0 and D8 are comparatively coupled to even second digit lines D0 and D8 through SA-E modules within patches 1 and 2, respectively; and the odd first digit line D1 is comparatively coupled to the odd second digit line D1 by an SA-O module within the patch 1. For purposes of understanding the present disclosure and appended claims, a first digit line is "comparatively coupled" with a second digit line by a sense amplifier circuit (or sense amplifier module) if the sense amplifier circuit (or sense amplifier module) is configured to compare electrical properties (e.g., voltages) of the first digit line and the second digit line to one another. Fig. 14 (discussed below) shows example sense amplifier modules SA-E, and shows an example application in which digit lines D0 and D0 are comparatively coupled through the example sense amplifier modules.

In the illustrated embodiment of fig. 4, the digit lines D0, D0, D1, D1, D8, and D8 are all vertically displaced relative to the sense amplifier circuits 26 within the patch locations 24. Furthermore, the digit lines D0, D0, D1, D1, D8 and D8 are all laterally displaced relative to each other.

Still referring to fig. 4, a first set of word lines extends along the first memory array (array 1). Representative word lines of this first group are labeled WL0, WL2, WL16, and WL 18. The first set of word lines may be referred to as a first word line. A second set of word lines extends along a second memory array (array 2). Representative word lines of this second set are labeled WL8, WL14, WL24, and WL 30. The second group of word lines may be referred to as second word lines.

Each of the first memory cells 20a within the first memory array (array 1) is uniquely addressed by one of the digit lines extending along the first memory array (e.g., one of digit lines D0, Dl, and D8) and one of the word lines extending along the first memory array (e.g., one of word lines WL0, WL2, WL16, and WL 18). Similarly, each of memory cells 20b within the second memory array (array 2) is uniquely addressed by one of the digitlines extending along the second memory array (e.g., one of digitlines D0, D1, and D8) and one of the wordlines extending along the second memory array (e.g., one of wordlines WL8, WL14, WL24, and WL 30). In some embodiments, the digit lines along the first memory array (array 1) may be referred to as a first set of digit lines, while the digit lines along the second memory array (array 2) are referred to as a second set of digit lines; and similarly, word lines along the first memory array (array 1) may be referred to as a first set of word lines, while word lines along the second memory array (array 2) may be referred to as a second set of word lines. Thus, each of the memory cells 20a of array 1 can be considered to be uniquely addressed with a word line from the first set of word lines in combination with a digit line from the first set of digit lines; and each of the memory cells 20b of array 2 can be considered to be uniquely addressed by combining digit lines from the second set of digit lines with word lines from the second set of word lines.

An advantage of the configuration of FIG. 4 may be that all sense amplifier circuitry and all word line driver circuitry are provided directly beneath the memory arrays (array 1 and array 2) in the patch location 24, which may enable close packing of the memory arrays across a semiconductor substrate; or in other words, this may save valuable semiconductor real estate as compared to conventional configurations in which at least some sense amplifier circuitry and/or at least some word line driver circuitry is not directly underneath the memory array. Vertical stacking of regions of the memory arrays (array 1 and array 2) can further save valuable semiconductor real estate.

In some embodiments, the patch locations 24 may be incorporated into a quilt pattern 36, the quilt pattern 36 being directly beneath the memory cells MC of the first and second memory arrays (array 1 and array 2). The term "quilt pattern" is used to indicate that the patch locations 24 may be distributed as a substantially repeating pattern of subunits (where each subunit is a patch 24). This subunit can be viewed as a "block" (patch) of fabric similar to that incorporated into some types of bedding. The patch locations 24 may all have the same orientation as one another (as shown in fig. 4), or at least one of the patch locations may have a different orientation relative to at least one other of the patch locations. For example, fig. 5 shows a top view of a region of an example base 12 having a quilt pattern 36, the quilt pattern 36 having a plurality of patch locations 24 (patch 1, patch 2, patch 3, and patch 4). The relative orientation of the patch positions is illustrated with the symbol "F". In the illustrated embodiment, the third and fourth patch positions (patch 3 and patch 4) are inverted relative to the first and second patch positions (patch 1 and patch 2). The various regions are shown in phantom lines (virtual views) within the patch location 24 of fig. 5 to assist the reader in understanding the relative orientation of the patch locations. In some embodiments, the configuration of fig. 5 may enable the switch to control two patches at once by feeding a signal down into the socket between the two patches.

Referring again to FIG. 4, the sense amplifier circuits 26 within patch locations 24 are coupled with column select structures 32 (column select, also referred to as LOCAL column select structures or LOCAL-CS), which column select structures 32 are in turn coupled to a CS bus (also referred to as GLOBAL column select structures or GLOBAL-CS) through switches 30. Specifically, patch 1 is coupled to a first column select structure (LOCAL-CS)32a, which first column select structure (LOCAL-CS)32a is coupled to a CS bus line (GLOBAL-CS) by a first switch 30a, and patch 2 is coupled to a second column select structure (LOCAL-CS)32b, which second column select structure (LOCAL-CS)32b is coupled to the CS bus line (GLOBAL-CS) by a second switch 30 b. The CS bus (GLOBAL-CS) may in turn be coupled with column decoder circuitry (not shown in FIG. 4). Column select structures (LOCAL-CS)32 and at least portions of CS bus lines (GLOBAL-CS) may be along substrate 12, as shown.

Fig. 6 diagrammatically shows example circuitry associated with the patch location 24 in more detail. Fig. 6 specifically shows example circuitry associated with patch 1 of fig. 4, but it is understood that substantially the same circuitry may be associated with all patch locations of the integrated assembly.

The odd numbered lines DL-1, DL-3, DL-5, DL-7 and DL-7 extend to the SA-O module, and the even numbered lines DL-0, DL-2, DL-4, DL-6 and DL-6 extend to the SA-E module.

Each of the digit lines is selectively coupled with an input/output circuit (I/O) through a switch 34 (e.g., DL-1 is selectively coupled to I/O-1 through switch 34). In the embodiment shown, the switch 34 is a transistor. Each of the transistors 34 has a gate controlled by a column select structure 32a (CS; also referred to as LOCAL-CS). Thus, column select structures 32a may be used to controllably couple individual digit lines to input/output circuits associated with such digit lines. In some embodiments, column select structure 32a may be considered a local column select structure associated with patch location 24 designated as patch 1. Each of the tile locations may have its own local column select structure associated with it. The local column select structures may be considered to be associated with digit lines controlled by such local column select structures (i.e., local column select structure 32a of FIG. 6 may be considered to be associated with digit lines DL-0, DL-1, etc. of patch 1).

The local column select structure 32a is selectively coupled to a column select bus (CS bus; also known as GLOBAL-CS) by a switch 30a, and the CS bus is in turn coupled to a DECODER circuit (DECODER). The switch 30a may comprise any suitable configuration, and may be a transistor in some embodiments. Switch 30a enables the circuitry of patch 1 to be coupled with the CS bus during utilization of such circuitry, and to be electrically isolated from the CS bus when the circuitry of patch 1 is not utilized (i.e., is not subject to memory operations; such as, for example, reading, writing, erasing, etc.).

Although the illustrated diagram of patch 1 utilizes eight digitlines from each of array 1 and array 2 (DL-0 to DL-7 from array 1, and DL-0 to DL-7 from array 2), it should be understood that in other embodiments, a patch may utilize more than eight digitlines from each of the arrays, or less than eight digitlines from each of the arrays.

Referring again to fig. 4, this shows that each of the illustrated patch locations 24 (patch 1 and patch 2) has an associated local column select structure (i.e., a first local column select structure 32a for patch 1 and a second local column select structure 32b for patch 2), and each of the local column select structures is selectively coupled to the CS bus by a switch (i.e., a first switch 30a for patch 1 and a second switch 30b for patch 2). Switches 30a and 30b may be used to selectively couple/decouple the local column select structures 32a and 32b from the CS bus depending on whether the patch location 24 associated with that column select structure is operated. Decoupling of the column select structures from the CS bus during periods of non-operating associated patch positions may advantageously enable reducing undesired capacitive coupling by removing capacitive coupling associated with non-operating patch positions to be isolated from the CS bus. For example, during periods when patch 1 is not operated, switch 30a may be used to isolate column select structure 32a and associated patch 1 from the CS bus.

The patch locations 24 of fig. 4 represent numerous patch locations that may be utilized in conjunction with memory (e.g., memory within array 1 and array 2 of fig. 4). Fig. 7 diagrammatically illustrates the integration assembly 10 including six patch locations 24 (labeled as patch 1, patch 2, patch 3, patch 4, patch 5, and patch 6). Sense amplifier circuitry 26 (FIG. 4) may be considered to be subdivided among six patch locations, with each of patch locations 24 including portions of the sense amplifier circuitry. For example, patches 1-6 may be considered to include first, second, third, fourth, fifth, and sixth portions of sense amplifier circuitry, respectively (with such portions of sense amplifier circuitry being illustrated in the patches as SA-1, SA-2, SA-3, SA-4, SA-5, and SA-6 diagrammatically). Although fig. 7 shows six patch locations, there may be more than six patch locations illustrated, or six patch locations illustrated below, in some embodiments. In some example embodiments, there may be at least four of the tile locations.

The assembly 10 of fig. 7 includes a CS control (e.g., a decoder) that is in communication with two CS buses (labeled CS bus 1 and CS bus 2; and also referred to as GLOBAL-CS-1 and GLOBAL-CS-2). The CS bus may be referred to as a first CS bus (CS bus 1) and a second CS bus (CS bus 2); or a first GLOBAL CS structure (GLOBAL-CS-1) and a second GLOBAL CS structure (GLOBAL-CS-2).

Each of the CS busses is selectively coupled with three local column select structures 32 (also referred to as local column select structures) by switches 30. Specifically, CS bus 1 is coupled with column select structures 32a, 32b, and 32c (also labeled CS-1, CS-2, and CS-3) through switches 30a, 30b, and 30c (also labeled SW-1, SW-2, and SW-3); and CS bus 2 is coupled with column select structures 32d, 32e, and 32f (also labeled CS-4, CS-5, and CS-6) through switches 30d, 30e, and 30f (also labeled SW-4, SW-5, and SW-6). Local column select structures 32 are associated with individual patch locations 24; and specifically with the portion of the sense amplifier circuitry within the patch location. Specifically, CS-1 is associated with a first portion of the sense amplifier circuitry within patch 1, CS-2 is associated with a second portion of the sense amplifier circuitry within patch 2, CS-3 is associated with a third portion of the sense amplifier circuitry within patch 3, CS-4 is associated with a fourth portion of the sense amplifier circuitry within patch 4, CS-5 is associated with a fifth portion of the sense amplifier circuitry within patch 5, and CS-6 is associated with a sixth portion of the sense amplifier circuitry within patch 6. Each of patches 1-6 may be substantially the same as patch 1 described above with reference to fig. 6, except that patches 2-6 may utilize a different digit line than that specifically designated in fig. 6 as being associated with patch 1.

Switches 30 a-f are selectively operated using local switch control units 38a, 38b, and 38c (also labeled as switch control 1, switch control 2, and switch control 3). Each of the switch control units operates two of the switches (e.g., switch control unit 38a operates switches 30a and 30 d).

The local switch control units 38a, 38b, and 38c are coupled with global switch controls (i.e., global switch control circuitry) that selectively control the operation of the individual local switch control units during operation of the assembly 10.

Some of the claims provided below relate to an assembly similar to that of figure 7 but including "at least four patch positions". In interpreting such claims, it may be useful to understand the patch positions shown as patch 1, patch 2, patch 4 and patch 5 as first, second, third and fourth patch positions, respectively. Thus, in some embodiments, the first and third patch positions (patch 1 and patch 4) may be considered to share the first switch control unit 38a, and the second and fourth patch positions (patch 2 and patch 5) may be considered to share the second switch control unit 38 b.

Fig. 8 and 9 illustrate example modes of operation of the integrated assembly 10 of fig. 7. FIG. 8 shows an operating mode in which only one of the switches (SW-1) is in the closed position while all other switches are in the open position. Thus, only tile 1 is coupled with the CS control (decoder), and the other tiles 2-6 are isolated (decoupled) from the CS control (decoder). FIG. 9 shows a mode of operation in which one of the switches along the first column select bus (CS bus 1), specifically switch SW-1, is closed and in which one of the switches along the second column select bus (CS bus 2), specifically switch SW-6, is closed. The remaining switches remain open. Thus, tiles 1 and 6 are coupled with the CS control (decoder), and the other tiles 2-5 are isolated (decoupled) from the CS control (decoder). In other embodiments (not shown), more than two of the illustrated switches of fig. 9 may be in a closed position during an operational mode of the assembly 10.

In some embodiments, two or more of the patches may share input/output circuitry, as the patches may be selectively decoupled (electrically isolated) with respect to each other. For example, FIG. 10 shows a configuration in which patch 1 and patch 4 share input/output circuitry (I/O); in other words, example applications that share connections with input/outputs. Each of the patches is shown to include a Digit Line (DL) coupled to the I/O through a transistor 34 gated by an associated local column select structure (CS-1 for patch 1 and CS-4 for patch 4). The switches SW-1 and SW-4 can be operated so that either patch 1 or patch 4 can be operated while the other is decoupled, and thus, shared I/O will be utilized by only one of the patches during the operational mode of the assembly 10.

The switches SW-1, SW-2, SW-3, SW-4, SW-5 and SW-6 may be transistors. Fig. 11 diagrammatically illustrates the integrated assembly 10 in an example embodiment in which such switches correspond to example transistors. The gates of the transistors are coupled with switch control units (switch controls 1-3) to selectively couple/decouple the local column select structure (e.g., CS-1) with the CS bus.

Memory cells 20a and 20b of FIG. 4 may have any suitable configuration. In some embodiments, the memory cells may be DRAM cells that each include an access transistor and a capacitor. Fig. 12 shows an example configuration of the regions of the integrated assembly 10, and shows the digit lines D0 and D0 extending from the SA-E modules.

The access transistors (T) of memory cells 20a and 20b are shown as comprising vertically-extending pillars 50 of semiconductor material 52. Semiconductor material 52 may comprise, consist essentially of, or consist of any suitable composition(s), and in some embodiments may comprise, consist essentially of, or consist of silicon, germanium, a III/V semiconductor material (e.g., gallium phosphide), a semiconductor oxide, and the like; wherein the term III/V semiconductor material refers to a semiconductor material comprising an element selected from groups III and V of the periodic table of elements (wherein groups III and V are old terms and are now referred to as groups 13 and 15). Source/drain and channel regions (not shown) may be provided within the pillars 50. The pillar 50 may comprise a vertically extending channel region between source/drain regions, and thus the access transistor T may be considered to correspond to a vertically extending transistor in some embodiments.

Gate dielectric material 54 is along the sidewalls of the pillars 50 and conductive gate material 56 is along the gate dielectric material.

The gate dielectric material 54 may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

Conductive gate material 56 may comprise any suitable conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.).

The capacitor (C) of memory cells 20 and 20b includes a first conductive node 58, a second conductive node 60, and an insulating material (capacitor dielectric material) 62 between the first and second conductive nodes.

First conductive node 58 and second conductive node 60 may comprise any suitable conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). The first and second conductive nodes may comprise the same composition as one another, or may comprise different compositions relative to one another.

The insulating material 62 may comprise any suitable composition(s), and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

In the embodiment shown, the lower conductive node 58 is configured as an upwardly open container, and thus the capacitor C may be referred to as a container-type capacitor. In other embodiments, the lower conductive node may have other suitable shapes.

The lower conductive node 58 may be referred to as a storage node and the upper conductive node 60 may be referred to as a plate electrode. In some embodiments, the plate electrodes within array 1 may all be coupled to each other and the plate electrodes within array 2 may also all be coupled to each other.

Digit lines D0 and D0 are shown as including conductive materials 64 and 66, respectively. Such conductive materials may include any suitable conductive composition; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). Conductive materials 64 and 66 may be the same composition as one another, or may be different compositions relative to one another.

A number of word lines (WL 0-WL 15) are illustrated diagrammatically in FIG. 12. The word lines are coupled with sub-word line drivers designated SWD-E1 and SWD-E2. Such sub-wordline drivers may include the driver modules SWD-UE and SWD-LE described above with reference to fig. 4.

Digit lines D0 and D0 are shown selectively coupled to input/output circuits (I/O-1 and I/O-1) through transistors 34 controlled by local column select structures 32a (cs); with this local column select structure 32a coupled to the gate of transistor 34. The column select structure 32a is selectively coupled to the CS bus (GLOBAL-CS) by a switch 30 a.

The view of fig. 12 shows that each of the digit lines D0 and D0 has a first portion (lower portion) along lower level 14 and has a second portion (upper portion) along upper level 16. Each of the arrays of memory cells (array 1 and array 2) has a first portion (lower portion) along lower deck 14 and has a second portion (upper portion) along upper deck 16. In some embodiments, the digit lines associated with the first array (array 1) can be considered first digit lines, while the digit lines associated with the second array (array 2) can be considered second digit lines. Thus, digitline D0 may be considered an example of a first digitline, while digitline D0 may be considered an example of a second digitline. The first and second digit lines are comparatively coupled to each other through the sense amplifier circuitry, and in the embodiment of FIG. 12 through the modules SA-E of the sense amplifier circuitry.

The integrated assembly 10 may include any suitable vertical relationship between the various components. FIG. 13 graphically illustrates example relationships. The configuration of FIG. 13 diagrammatically illustrates lower level 12 in dashed lines, and diagrammatically illustrates memory cells on upper levels (levels 14 and 16) vertically above lower level 12. The CS bus (GLOBAL-CS) is coupled to a LOCAL column select structure 32a (CS or LOCAL-CS) by a switch 30 a. The local column select structure (CS) controls a second transistor 34, which second transistor 34 selectively couples an input/output circuit (I/O) with a Digit Line (DL) extending from the memory cell to a sense amplifier circuit (SA).

In the embodiment shown, the switch 30a corresponds to a transistor 100 supported by a semiconductor substrate 102. The semiconductor substrate 102 may comprise any suitable semiconductor material; including, for example, silicon.

Transistor 100 includes a pair of source/drain regions 104 and 106 separated from each other by an intermediate channel region 108. The transistor 100 also includes a conductive gate 110 separated from the channel region 108 by a gate dielectric material 112.

The conductive gate 110 may comprise any suitable conductive composition(s); including, for example, metal silicides, metal nitrides, metals, conductively-doped silicon, and the like.

The gate dielectric material 112 may comprise any suitable composition(s); such as, for example, silicon dioxide.

Insulating spacers 112 are along the conductive gate 110 and an insulating cap material 114 is over the conductive gate 110. The spacer 112 and cover material 114 may comprise any suitable insulating composition(s); including, for example, silicon dioxide, silicon nitride, and the like.

Gate 110 may be electrically coupled to a switch control circuit (e.g., switch control 1) of the type described above with reference to fig. 7.

In the illustrated embodiment, portions of the CS bus line extend vertically from the source/drain region 104, and portions of the local CS extend vertically from the source/drain region 106. Local CS then extends above lower level 12 and extends back down to lower level 12 to couple with the gate of transistor 34. I/O and SA are shown along lower level 12. In other embodiments, at least a portion of the I/O circuitry may be vertically (vertically) offset from the lower deck 12.

Sense amplifier modules SA-E and SA-O of embodiments described herein may comprise any suitable configuration. An example sense amplifier module SA-E for patch 1 is illustrated diagrammatically in fig. 14. Dashed lines 71 are provided to show the approximate boundaries of the sense amplifier circuitry. Although the illustrated circuit is described as a SA-E module, it should be understood that the SA-O module may include the same configuration.

The SA-E module of FIG. 14 includes a p sense amplifier 80 including a pair of cross-coupled pull-up transistors 82 and 84, and includes an n sense amplifier 86 including a pair of cross-coupled pull-down transistors 88 and 90. The p sense amplifier 80 is coupled with an active pull-up circuit (labeled ACT) and the n sense amplifier 86 is coupled with a common node (labeled RNL). The illustrated SA-E module is coupled to digit lines D0 and D0; or in other words, digit lines D0 and D0 are comparatively coupled to each other through the SA-E module. In operation, amplifiers 80 and 86 may be used together to detect the relative signal voltages of D0 and D0 and drive the higher signal voltage to VCC while driving the lower signal voltage to ground. Also, the inputs and outputs (labeled I/O) associated with the modules may be used to derive data regarding the relative signal voltages of D0 and D0, and/or to program memory cells along one or both of D0 and D0.

The illustrated module also has equalization circuitry (labeled EQ) provided therein to balance electrical properties within the module. Other circuitry (not shown) may also be provided within the module. The SA-E module of fig. 14 may comprise any suitable configuration.

The assemblies and structures discussed above may be used within an integrated circuit (where the term "integrated circuit" denotes an electronic circuit supported by a semiconductor substrate); and may be incorporated into an electronic system. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic system may be any of a wide range of systems such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, gaming consoles, lighting devices, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, airplanes, and the like.

Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method now known or yet to be developed, including, for example, Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), etc.

The terms "dielectric" and "insulating" may be used to describe a material having insulating electrical properties. The terms are considered synonyms in the present invention. The use of the term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may provide language changes within the invention to simplify the preceding basis within the appended claims and is not used to indicate any significant chemical or electrical difference.

Both the terms "electrically connected" and "electrically coupled" may be utilized in this disclosure. The terms are considered synonyms. Utilizing the next term in some instances and utilizing another term in other instances can provide language changes within the disclosure to simplify the antecedent basis within the claims that follow.

The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and in some applications the embodiments may be rotated relative to the orientation shown. The description provided herein and the appended claims refer to any structure having the described relationships between various features, regardless of whether the structure is in the particular orientation of the drawings or rotated relative to such orientation.

To simplify the drawings, the cross-sectional views of the drawings show only features within the cross-sectional plane, and do not show material behind the cross-sectional plane, unless otherwise indicated.

When a structure is referred to above as being "on," "adjacent to," or "against" another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on," "directly adjacent to," or "directly against" another structure, there are no intervening structures present. The terms "directly below", "directly above", and the like do not indicate direct physical contact (unless explicitly stated otherwise), but rather indicate vertical alignment.

Structures (e.g., layers, materials, etc.) may be referred to as extending "vertically" to indicate that the structures extend generally upward from an underlying base (e.g., substrate). The vertically extending structures may or may not extend substantially orthogonally relative to the upper surface of the substrate.

Some embodiments include an integrated assembly having a first array of first memory cells and a second array of second memory cells. First digit lines extend along columns of the first array. Second digit lines extend along columns of the second array. Sense amplifier circuitry is configured to comparatively couple the first digit line and the second digit line. The sense amplifier circuitry is distributed among at least two patch locations. A first of the at least two patch locations has a first portion of the sense amplifier circuitry and has a first local column select structure. The first local column select structure is associated with the first digit line and the second digit line comparatively coupled through the first portion of the sense amplifier circuit. A second one of the at least two patch locations has a second portion of the sense amplifier circuitry and has a second local column select structure. The second local column select structure is associated with the first digit line and the second digit line comparatively coupled through the second portion of the sense amplifier circuitry. A column select bus extends from the decoder circuit to the first and second local column select structures. The column select bus is selectively coupled to the first local column select structure by a first switch and to the second local column select structure by a second switch.

Some embodiments include an integrated assembly having a first array of first memory cells and a second array of second memory cells. First digit lines extend along columns of the first array. Second digit lines extend along columns of the second array. Sense amplifier circuitry is configured to comparatively couple the first digit line and the second digit line. The sense amplifier circuit is subdivided among at least four patch locations. A first of the at least four patch locations has a first portion of the sense amplifier circuitry and has a first local column select structure. A second one of the at least four patch locations has a second portion of the sense amplifier circuitry and has a second local column select structure. A third one of the at least four patch locations has a third portion of the sense amplifier circuitry and has a third partial column select structure. A fourth one of the at least four patch locations has a fourth portion of the sense amplifier circuitry and has a fourth partial column select structure. A first column select bus extends from a decoder circuit to the first and second local column select structures. The first column select bus is selectively coupled to the first local column select structure by a first switch and to the second local column select structure by a second switch. A second column select bus extends from the decoder circuit to the third and fourth local column select structures. The second column select bus is selectively coupled to the third local column select structures by a third switch and to the fourth local column select structures by a fourth switch.

Some embodiments include an integrated assembly comprising a substrate supporting sense amplifier circuitry. The sense amplifier circuit is subdivided among at least two spaced patch locations. Each of the tile locations includes a SA-O region and a SA-E region. A first partial column select structure is associated with the first patch location and a second partial column select structure is associated with the second patch location. A column select bus extends from a decoder circuit to the first and second local column select structures. The column select bus is selectively coupled to the first local column select structure by a first switch and to the second local column select structure by a second switch. The first level is above the substrate. The first level includes a first portion of a first array of first memory cells and includes a first portion of a second array of second memory cells. A second deck is above the first deck. The second deck includes a second portion of the first array of the first memory cells and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array. A second digit line is associated with the second array. The first digit line and the second digit line are comparatively coupled to each other through the sense amplifier circuit.

In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are, therefore, to be accorded the full scope literally and appropriately interpreted in accordance with the doctrine of equivalents.