阅读说明：本技术 存储器控制器、存储器系统和存储器系统的操作方法 (Memory controller, memory system, and method of operating memory system ) 是由 朴益均 申崇晩 崔奎锡 于 2020-11-09 设计创作，主要内容包括：提供存储器控制器、存储器系统和存储器系统的操作方法。所述操作方法包括：基于与多个存储器芯片之中的存储器芯片的多个操作状态中的每个操作状态的功耗有关的信息,针对所述多个操作状态中的每个操作状态,设置指示允许并行操作的存储器芯片的数量的参数；获得与所述多个存储器芯片中的每个存储器芯片的操作状态有关的信息；以及基于所述参数和与所述多个存储器芯片中的每个存储器芯片的操作状态有关的信息,对通过分别与所述多个存储器芯片对应的多个通道的数据存取进行调度。(A memory controller, a memory system, and a method of operating the memory system are provided. The operation method comprises the following steps: setting a parameter indicating the number of memory chips that are allowed to operate in parallel for each of a plurality of operating states of a memory chip among a plurality of memory chips based on information on power consumption of each of the plurality of operating states; obtaining information related to an operating state of each of the plurality of memory chips; and scheduling data access through a plurality of channels respectively corresponding to the plurality of memory chips based on the parameter and information about an operating state of each of the plurality of memory chips.)

1. A method of operation of a memory system including a memory device including a plurality of memory chips, the method of operation comprising:

setting a parameter indicating the number of memory chips that are allowed to operate in parallel for each of a plurality of operating states and/or each combination of the plurality of operating states based on information on power consumption of each of the plurality of operating states of a memory chip among the plurality of memory chips;

obtaining information related to an operating state of each of the plurality of memory chips; and

scheduling data access through a plurality of channels corresponding to the plurality of memory chips based on the parameter and information about an operating state of each of the plurality of memory chips.

2. The operating method of claim 1, wherein the step of setting parameters comprises: setting a maximum number of memory chips allowed to operate in parallel to each of the plurality of operating states and/or each combination of the plurality of operating states as the parameter so that a total power consumption does not exceed a preset power amount by using information on power consumption of each of the plurality of operating states of a memory chip among the plurality of memory chips.

3. The operating method according to claim 1 or 2, wherein the step of setting parameters comprises: setting a different parameter for each of the plurality of operating states or each combination of the plurality of operating states.

4. The method of operation of claim 3, wherein scheduling data access through the plurality of channels comprises:

checking values of parameters corresponding to operations of the plurality of memory chips based on information about an operation state of each of the plurality of memory chips; and

scheduling data access through the plurality of channels based on the checked values.

5. The operating method of claim 1 or 2, wherein the plurality of operating states include at least one of a program operation, a read operation, an erase operation, and an idle state.

6. The operating method according to claim 1 or 2, wherein the step of setting the parameter includes setting a parameter table including a parameter indicating the number of memory chips that are allowed to operate in parallel for each of the plurality of operating states and/or each combination of the plurality of operating states in each of a plurality of temperature ranges, the parameter table being set for each of the plurality of temperature ranges.

7. The method of operation of claim 6, wherein scheduling data access through the plurality of channels comprises:

sensing a temperature of the memory system;

checking a parameter table corresponding to the sensed temperature; and

scheduling data access through the plurality of channels based on the checked parameter table and information regarding respective operating states of the plurality of memory chips.

8. The operating method according to claim 1 or 2, wherein the step of setting parameters comprises:

receiving specification information from a host; and

setting the parameter based on the received specification information and information related to power consumption of each of the plurality of operating states.

9. A memory system, comprising:

a memory device including a plurality of memory chips;

a memory controller configured to control an operation of the memory device; and

a plurality of channels configured to connect each of the plurality of memory chips to a memory controller,

wherein the memory controller is configured to: the method includes checking an operating state of each of the plurality of memory chips, and scheduling data access through the plurality of channels by using a parameter and the checked operating state of each of the plurality of memory chips, the parameter being set based on information on power consumption of each of a plurality of operating states of a memory chip among the plurality of memory chips and indicating a number of memory chips that allow parallel operation for each of the plurality of operating states and/or each combination of the plurality of operating states.

10. The memory system of claim 9, wherein the memory controller is configured to: determining the number of channels to be approved to perform data transmission or reception by using the parameter and the checked operation state of each of the plurality of memory chips, and approving transmission or reception of the determined number of channels such that the total power consumption does not exceed a preset power amount.

11. The memory system of claim 10, wherein the memory controller is configured to: determining as many channels as parameters from among the plurality of channels according to an order of operations of the memory system.

12. The memory system of claim 11, wherein the memory controller is configured to: delaying a job corresponding to one of the channels that is not approved for transmission or reception.

13. The memory system of claim 9, wherein the memory controller is configured to: when a new request is received from the host or an operation of at least one of the plurality of memory chips has ended, re-determining a channel to be approved for transmission or reception.

14. The memory system according to any one of claims 9 to 13, further comprising: a temperature sensor configured to sense a temperature of the memory system,

wherein the parameter comprises a plurality of sub-parameters defining a number of memory chips that are allowed to operate in parallel for each of the plurality of operating states and/or each combination of the plurality of operating states within each of a plurality of temperature ranges, and

the memory controller is configured to: checking a sub-parameter corresponding to the sensed temperature, and scheduling data transmission or reception of the plurality of channels based on the checked sub-parameter and the checked operation state of each of the plurality of memory chips.

15. A memory controller for controlling operation of a memory device including a plurality of memory chips, the memory controller comprising:

a memory interface configured to: transmitting or receiving data via a plurality of channels connecting each of the plurality of memory chips to a memory controller; and

a channel arbitration module configured to: when an approval request for data transmission or reception via a first channel has been received from a memory interface, obtaining information on an operating state of each of the plurality of memory chips, determining whether to approve the first channel based on a parameter that is set based on power consumption of each of a plurality of operating states of the memory chips and that indicates the number of memory chips that allow parallel operation for each of the plurality of operating states and/or each combination of the plurality of operating states and information on the operating state of each of the plurality of memory chips, and providing a result of the determination to the memory interface.

16. The memory controller of claim 15, wherein the channel arbitration module is configured to:

comparing the parameter with information on an operation state of each of the plurality of memory chips, and determining whether the number of memory chips currently being operated has reached the number of memory chips corresponding to the parameter,

determining that the first channel is not approved when the number of memory chips currently being operated has reached the number of memory chips corresponding to the parameter, and

determining to approve the first channel when the number of memory chips currently being operated does not reach the number of memory chips corresponding to the parameter.

17. The memory controller of claim 15, wherein the channel arbitration module comprises: a state checker configured to check an operation state of each of the plurality of memory chips, and

the status checker is configured to: information on commands corresponding to the plurality of channels is received from a memory interface, and an operation state of each of the plurality of memory chips is checked.

18. The memory controller of claim 16, wherein the channel arbitration module comprises: a job scheduler configured to manage job scheduling of the plurality of memory chips, and

when the job scheduler receives a new approval request from the memory interface or receives information on the end of the operation of the memory chip corresponding to the second channel among the plurality of channels, the job scheduler updates the job schedule.

19. The memory controller of claim 18, wherein the channel arbitration module is further configured to: when the job schedule is updated, the number of channels corresponding to the parameter is checked according to an order in the updated job schedule, and it is determined whether to approve the first channel according to whether the first channel is included in the checked channels.

20. The memory controller of claim 15, wherein the memory interface is configured to:

transmitting or receiving data to or from a first memory chip corresponding to a first channel among the plurality of memory chips via the first channel when the first channel is approved,

when the first channel is not approved, delaying sending or receiving data to or from the first memory chip via the first channel.

Technical Field

The inventive concepts relate to memory controllers, memory systems, and methods of operating memory systems.

Background

A memory system may include a plurality of memory chips, a memory controller, and a plurality of channels connecting the memory chips to the memory controller. Power may be managed in a memory system by applying methods that prevent operation of some channels or by reducing the frequency of operation. However, from a quality of service (QoS) perspective, this approach can severely degrade performance and cannot dynamically adapt, thus leading to situations where the total power consumption exceeds the allowed amount of power.

Disclosure of Invention

At least one embodiment of the inventive concept provides a memory controller that schedules data transmission or reception of a plurality of channels based on information on operating states of a plurality of chips, thereby preventing total power consumption from exceeding an allowable power level and maximizing memory utilization, a memory system, and an operating method of the memory system.

According to an exemplary embodiment of the inventive concept, there is provided an operating method of a memory system including a memory device including a plurality of memory chips. The operation method comprises the following steps: setting a parameter indicating the number of memory chips that are allowed to operate in parallel for each of a plurality of operating states of a memory chip among the plurality of memory chips based on information on power consumption of each of the plurality of operating states; obtaining information related to an operating state of each of the plurality of memory chips; and scheduling data access on a plurality of channels corresponding to the plurality of memory chips based on the parameter and information about the operating state of each of the plurality of memory chips.

According to an exemplary embodiment of the inventive concept, there is provided a memory system including: a memory device including a plurality of memory chips; a memory controller configured to control an operation of the memory device; and a plurality of channels configured to connect each of the plurality of memory chips to a memory controller. The memory controller is configured to: the method includes checking an operating state of each of the plurality of memory chips, and scheduling data access on the plurality of channels based on information about power consumption of each of a plurality of operating states of a memory chip among the plurality of memory chips by using a parameter indicating a number of memory chips that are allowed to operate in parallel for each of the plurality of operating states and the checked operating state of each of the plurality of memory chips.

According to an exemplary embodiment of the inventive concept, there is provided a memory controller for controlling an operation of a memory device including a plurality of memory chips, the memory controller including: a memory interface (I/F) configured to: transmitting or receiving data via a plurality of channels connecting each of the plurality of memory chips to a memory controller; and a channel arbitration module configured to: when an approval request for data transmission or reception via a first channel has been received from a memory I/F, information on an operating state of each of the plurality of memory chips is obtained, and based on power consumption of each of a plurality of operating states of the memory chips, it is determined whether to approve the first channel based on a parameter indicating the number of memory chips that allow parallel operation for each of the plurality of operating states and the information on the operating state of each of the plurality of memory chips, and a result of the determination is provided to the memory I/F.

Drawings

Exemplary embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of a computing system according to an exemplary embodiment of the inventive concepts;

fig. 2A and 2B are parameter tables according to exemplary embodiments of the inventive concept;

fig. 3 is a table illustrating information related to respective operating states of a plurality of memory chips according to an exemplary embodiment of the inventive concepts;

fig. 4A to 4C illustrate a method of scheduling data transmission or reception of a channel for each operation of a memory chip according to an exemplary embodiment of the inventive concept;

fig. 5 is a block diagram of a memory system according to an exemplary embodiment of the inventive concepts;

fig. 6 is a block diagram of a memory controller according to an exemplary embodiment of the inventive concepts;

FIG. 7 is a block diagram of a channel arbitration (arbitration) module in accordance with an exemplary disclosed embodiment;

fig. 8A and 8B illustrate a method of generating a job schedule according to an exemplary embodiment of the inventive concept;

fig. 9 is a block diagram illustrating a method of scheduling data transmission or reception of a channel according to an exemplary embodiment of the inventive concept;

fig. 10 is a flowchart of a method of scheduling data transmission or reception of a plurality of channels according to an exemplary embodiment of the inventive concepts;

fig. 11 is a flowchart of a method of scheduling data transmission or reception of a plurality of channels according to an exemplary embodiment of the inventive concepts;

fig. 12 is a flowchart of a method of determining approval or disapproval of a target channel according to an exemplary embodiment of the inventive concept;

fig. 13 is a flowchart of a method of determining approval or disapproval of a target channel according to an exemplary embodiment of the inventive concept;

fig. 14 is a block diagram of a computing system according to an exemplary embodiment of the inventive concepts;

fig. 15 is a block diagram of a memory system according to an exemplary embodiment of the inventive concepts;

fig. 16 is a block diagram of a memory system according to an exemplary embodiment of the inventive concepts;

fig. 17 is a block diagram of a memory device according to an exemplary embodiment of the inventive concept;

fig. 18 is a view for explaining a three-dimensional (3D) V-NAND structure according to an exemplary embodiment of the inventive concept;

fig. 19 is a view for explaining a BVNAND structure according to an exemplary embodiment of the inventive concept;

fig. 20 is a block diagram of a system to which a storage device is applied according to an exemplary embodiment of the inventive concept; and

fig. 21 is a block diagram for explaining a Universal Flash Storage (UFS) system according to an exemplary embodiment of the inventive concepts.

Detailed Description

Fig. 1 is a block diagram of a computing system 10 according to an exemplary embodiment of the inventive concepts.

Referring to fig. 1, a computing system 10 includes a host 100 (e.g., a host device) and a memory system 200. Memory system 200 includes a memory controller 210 (e.g., control circuitry) and a memory device 220.

The host 100 provides the memory system 200 with a command CMD for a memory operation or DATA associated with the command CMD. For example, host 100 may provide write or read requests for data to memory system 200. According to a data erase request from the host 100, the memory system 200 may perform an erase operation for data of an area indicated by the host 100. According to one embodiment, host 100 may correspond to a Central Processing Unit (CPU), processor, microprocessor, or Application Processor (AP). According to an example embodiment, host 100 may be implemented as a system on a chip (SoC). Although transmission or reception of a command CMD or DATA between the host 100 and the memory system 200 is performed via different channels in fig. 1, embodiments of the inventive concept are not limited thereto. According to an exemplary embodiment, the transmission or reception of the command CMD or the DATA may be performed via a single channel.

The memory system 200 may include a storage medium for storing data according to a request from the host 100. For example, the memory system 200 may include one or more Solid State Drives (SSDs). However, the inventive concept is not limited thereto, and the memory system 200 may be implemented as any of various types of devices, such as an embedded multimedia card (eMMC), a universal flash memory (UFS) or compact flash memory (CF) card, a Secure Digital (SD) card, a Micro-secure digital (Micro-SD) card, a Mini-secure digital (Mini-SD) card, an extreme digital (xD) card, or a memory stick.

When the memory system 200 includes an SSD, the memory device 220 may include a plurality of flash memory chips (e.g., NAND memory chips) that store data in a nonvolatile manner. Alternatively, the memory device 220 may correspond to a flash memory device, or the memory device 220 may include a memory card including one or more flash memory chips.

When the memory system 200 includes flash memory, the flash memory may include a two-dimensional (2D) NAND memory array or a three-dimensional (3D) (or vertical) NAND (vnand) memory array. The 3D memory array is monolithically (monolithically) formed on one or more physical levels in an array of memory cells having an active region disposed on or above a silicon substrate, or as circuitry related to the operation of the memory cells formed on or above or within the silicon substrate. The term "monolithic" means that the layers making up each stage of the array are stacked directly above the layers of each underlying stage of the array.

According to an embodiment of the inventive concept, a 3D memory array includes vertical NAND strings arranged in a vertical direction such that at least one memory cell is located on or above another memory cell. The at least one memory cell may include a charge trapping layer.

The following patent documents, which are incorporated herein by reference in their entirety, describe suitable configurations of 3D memory arrays, wherein the 3D memory array is configured as a plurality of levels with word lines and/or bit lines shared between the levels: 7,679,133, 8,553,466, 8,654,587, 8,559,235 and 2011/0233648.

As another example, memory system 200 may include various other types of memory. For example, the memory system 200 may include non-volatile memory. Examples of non-volatile memory may include various types of memory, such as Magnetic Random Access Memory (MRAM), spin-transfer torque MRAM, conductive bridging RAM (cbram), ferroelectric RAM (feram), phase change RAM (pram), resistive RAM, nanotube RAM, polymer RAM (ponam), Nano Floating Gate Memory (NFGM), holographic memory, molecular electronic memory, and insulator resistance change memory.

Memory controller 210 may control memory operations (such as data writes and data reads) with respect to memory device 220. Memory controller 210 may control memory operations with respect to memory device 220 via one or more channels. For example, the memory controller 210 may be connected to the memory device 220 via n (where n is a positive integer) channels CH1 through CHn, and may write or read data. Memory controller 210 may control memory devices 220 connected to different channels in parallel.

According to one exemplary embodiment, memory device 220 includes a plurality of memory chips. The memory device 220 may include one or more memory chips to correspond to each of the n channels CH1 through CHn. The memory controller 210 may queue the command CMD for each of the n channels CH1 through CHn according to the command CMD (or request) received from the host 100, and may transmit the command CMD or DATA related to the command CMD to the memory device 220 via the n channels CH1 through CHn, or receive the command CMD or DATA related to the command CMD from the memory device 220. For example, memory controller 210 may include a buffer in which commands CMD are stored until they are executed.

According to an exemplary embodiment of the inventive concept, the memory controller 210 includes a channel arbitration module 211 that arbitrates (or manages) the n channels CH1 through CHn. The channel arbitration module 211 may be implemented in various ways and may be included in the memory controller 210. For example, the channel arbitration module 211 may be implemented as hardware (such as circuitry that arbitrates multiple channels). Alternatively, the channel arbitration module 211 may be implemented as software including a program, and the processing unit may perform various types of processing related to arbitration of a plurality of channels by executing the channel arbitration module 211 loaded in the operation memory. Alternatively, the channel arbitration module 211 may be implemented as a combination of hardware and software. Although the channel arbitration module 211 is included in the memory controller 210 in fig. 1, embodiments of the inventive concept are not limited thereto. For example, the channel arbitration module 211 can be disposed external to the memory controller 210, but within the memory system 200.

In one exemplary embodiment, the channel arbitration module 211 supports the function of arbitrating multiple channels connecting the memory controller 210 to the memory devices 220. For example, the channel arbitration module 211 may check the operation states of the plurality of memory chips of the memory device 220, and arbitrate the n channels CH1 to CHn based on the checked operation states and information on power consumption of each operation.

In one exemplary embodiment, the channel arbitration module 211 calculates the current total power consumption (for example, the power consumption of the memory system 200 or the memory device 220) based on the checked operation states of the plurality of memory chips and the information on the power consumption of each operation, and predicts whether the total power consumption will exceed the allowable power amount when the memory device 220 additionally performs the memory operation corresponding to the queued command CMD. When it is predicted that the total power consumption will exceed the allowable power amount, the channel arbitration module 211 defers transmission of the queued command CMD, and may restrict data transmission or reception through the channel corresponding to the corresponding queued command CMD. On the other hand, when it is predicted that the total power consumption will not exceed the allowable power amount, the channel arbitration module 211 transmits the queued command CMD, and may allow data transmission or reception through the channel corresponding to the queued command CMD.

Accordingly, while the memory device 220 performs a memory operation (or processing of a command) corresponding to the plurality of commands CMD as the memory controller 210 transmits the plurality of commands CMD to the memory device 220, power consumption may be prevented from exceeding the allowable amount of power.

The operation of the memory chip may include at least one of a program operation, a read operation, an erase operation, and an idle state. The programming operation may be divided into a plurality of detailed operations. For example, the program operation may be divided into a data input/output (I/O) operation (referred to as a first program operation for convenience of explanation) and a data write operation (referred to as a second program operation for convenience of explanation). The I/O operation corresponds to an operation in which a program command CMD and DATA are input to the memory chip through the channel and buffered in an I/O buffer (not shown) included in the memory chip. The DATA write operation corresponds to an operation in which DATA buffered in an I/O buffer included in the memory chip is programmed or written to the memory cell array. Each of the first and second program operations constitutes a part of the entire program operation, but the two operations can be distinguished from each other because a difference in power consumption between the two operations is large. For example, an I/O operation may consume a first amount of power, and a data write operation may consume a second amount of power different from the first amount.

The above-described operation types of the memory chip are merely examples, and embodiments of the inventive concept are not limited thereto. For example, the read operation may be divided into an operation of reading DATA from the memory cell array and an operation of inputting the read DATA to the memory controller 210 via a channel.

According to an exemplary embodiment of the inventive concept, the channel arbitration module 211 sets parameters based on information on power consumption of each operation, and arbitrates the n channels CH1 to CHn by using the set parameters and operation states of the plurality of memory chips. The parameter may be the number of memory chips that can perform each memory operation in parallel as long as the total power consumption does not exceed a preset amount of power (i.e., an allowable amount of power). For example, the parameter may be a maximum number of memory chips capable of performing the first programming operation in parallel as long as the total power consumption does not exceed the allowable amount of power. Since the operation of the memory chip may include a second program operation, a read operation, and an erase operation in addition to the first program operation, different parameters (e.g., sub-parameters) may be set for these different operations, respectively. The plurality of parameters may be included in a single parameter table. The parameter table may be stored in the memory controller 210 or the memory device 220. The method of setting the parameters is not limited to the above-described exemplary method.

As one example of arbitration using parameters, the channel arbitration module 211 may allow data transmission or reception through a number of channels corresponding to the parameters. For example, the channel arbitration module 211 may allow data transmission or reception through a number of channels corresponding to the parameter (including channels corresponding to memory chips currently performing an operation). For example, the channel arbitration module 211 may only allow data transmission or reception through channels connected to memory chips that are currently performing operations. In other words, when the number of memory chips currently performing an operation is smaller than a parameter, the channel arbitration module 211 may allow data transmission or reception through the channel corresponding to the queued command CMD. On the other hand, when the number of memory chips currently performing an operation is equal to the parameter, the channel arbitration module 211 does not allow data transmission or reception of the channel corresponding to the queued command CMD.

Accordingly, the channel arbitration module 211 may manage power consumption of the memory system 200 via comparison with preset parameters without calculating power consumption, and thus may reduce the number of calculations performed.

The computing system 10 according to the above-described embodiment may maximize memory utilization by scheduling data transmission or reception through a plurality of channels based on information about the operating states of a plurality of chips within the memory device 220 and information about power consumption of each operation (or parameters set based on the information about power consumption of each operation). Thus, the computing system 10 according to the above-described embodiments may ensure higher system performance and ensure high QoS by preventing the total power consumption from exceeding the allowable power level, as compared to conventional inefficient power management methods.

Fig. 2A and 2B are parameter tables according to exemplary embodiments of the inventive concept.

Referring to fig. 2A, the parameter TABLE a may include different parameters for each operation of the memory chip or each combination of operations of the memory chip. Each operation of the memory chip may include at least one of the first program operation PG, the second program operation tPROG, the read operation RD, and the erase operation ER described above with reference to fig. 1, and a combination of the operations of the memory chip may include at least one of: a combination of the first program operation PG and the erase operation ER (see, for example, parameter 5), a combination of the erase operation ER and the read operation RD (see, for example, parameter 6), a combination of the first program operation PG and the read operation RD (see, for example, parameter 7), and a combination of the first program operation PG, the erase operation ER, and the read operation RD (see, for example, parameter 8). Each operation of the memory chip or each combination of operations of the memory chip is not limited thereto.

The column of the parameter TABLE a indicates parameters (first to eighth parameters) corresponding to each operation of the memory chip or each combination of operations of the memory chip. For example, in the parameter TABLE a, a first parameter (e.g., parameter 1) may indicate a parameter corresponding to the first program operation PG, a seventh parameter (e.g., parameter 7) may indicate a parameter corresponding to a combination of the first program operation PG and the read operation RD, and an eighth parameter (e.g., parameter 8) may indicate a parameter corresponding to a combination of the first program operation PG, the erase operation ER, and the read operation RD.

The row of the parameter TABLE a may indicate the number of memory chips capable of performing an operation corresponding to the corresponding parameter. For example, in the parameter TABLE a, X1 of the first parameter corresponding to the first program operation PG may represent the maximum number of memory chips capable of performing the first program operation PG. X3 and Y2 of the fifth parameter corresponding to a combination of the first program operation PG and the erase operation ER may represent the maximum number of memory chips capable of performing the first program operation PG and the maximum number of memory chips capable of performing the erase operation ER, respectively.

The channel arbitration module 211 of fig. 1 may check a parameter corresponding to the operation of the current memory chip from the parameter TABLE a, and may approve data transmission or reception through the number of channels corresponding to the parameter. For example, when the current memory chip performs the first program operation PG, the channel arbitration module 211 may check X1 (e.g., 3) as a parameter corresponding to the first program operation PG, and may approve data transmission or reception through the number of channels (e.g., 3 channels) corresponding to X1.

A number of parameter tables may be provided as described above. According to an exemplary embodiment, different parameter tables are set according to different temperature ranges. Power consumption due to the operation of the memory chip may vary according to the temperature of the memory system. Therefore, in order to perform power management suitable for the temperature of the memory system, the channel arbitration module 211 may set different parameter tables according to different temperature ranges, and may schedule data transmission or reception of a plurality of channels by using the parameter tables corresponding to the temperature of the memory system.

Referring to fig. 2B, the parameter TABLE B may correspond to a temperature range B different from the temperature range a of the parameter TABLE a. In the parameter TABLE B, like the parameter TABLE a, the columns may indicate parameters (first to eighth parameters) corresponding to each operation of the memory chip or each combination of operations of the memory chip, and the rows may represent the number of memory chips capable of performing the operations corresponding to the respective parameters. Temperature range B may be higher or lower than temperature range a. In one exemplary embodiment, when the temperature range B is higher than the temperature range a, the parameters included in the parameter TABLE B have values smaller than the values of the parameters included in the parameter TABLE a.

The channel arbitration module 211 of fig. 1 may check a parameter Table B corresponding to a temperature of the current memory system from among a plurality of parameter TABLEs (e.g., Table a and Table B), may check a parameter corresponding to an operation of the current memory chip from among the parameter Table B, and may approve data transmission or reception through a number of channels corresponding to the parameter. In one exemplary embodiment, the memory system 200 includes a temperature sensor, and the channel arbitration module 211 selects an appropriate one of the plurality of parameter tables based on the temperature output by the temperature sensor, and checks parameters corresponding to the selected parameter table to determine through which channels it should authorize data transmission or reception.

Although it has been described with reference to fig. 2B that the channel arbitration module 211 manages power using a plurality of parameter tables according to temperature ranges to consider the temperature of the memory system, embodiments of the inventive concept are not limited thereto. For example, the channel arbitration module 211 may manage power according to a method of correcting an existing parameter table by using a reference temperature and a current temperature.

Fig. 3 is a table illustrating information related to operating states of a plurality of memory chips according to an exemplary embodiment of the inventive concepts.

Referring to fig. 3, the operation state information indicating the operation states of the eight memory chips Chip 1 to Chip 8 included in the memory device may be checked. Although eight memory chips have been shown and described with reference to FIG. 3, more or fewer than eight memory chips may be implemented.

According to an example embodiment, the information related to the operating state of the memory chip may include one or more bits. For example, when the operation state information has values of three or more bits for each memory chip, each of the values may represent at least one of a first program operation, a second program operation, a read operation, an erase operation, and an idle state.

Referring to fig. 3, the first and eighth chips Chip 1 and Chip 8 of the eight memory chips Chip 1 to Chip 8 are performing the first programming operation PG, the fourth Chip 4 is performing the read operation RD, and the remaining chips (i.e., the second, third, fifth, sixth, and seventh chips Chip 2, Chip 3, Chip 5, Chip 6, and Chip 7) are in an idle state (e.g., ID).

Fig. 4A to 4C illustrate a method of scheduling data transmission or reception of a channel for each operation of a memory chip. Fig. 4A to 4C illustrate that a command is transmitted for each of a plurality of channels (i.e., the first channel CH1 to the eighth channel CH8) according to time. The description given with reference to fig. 1 to 3 is equally applicable to the present embodiment.

Fig. 4A illustrates an embodiment in which a plurality of memory chips perform the first program operation PG. When the channel arbitration module 211 according to an exemplary embodiment of the inventive concept checks that the memory chip is performing the first program operation PG, the channel arbitration module 211 may check the parameter TABLE a to determine X1 as a parameter corresponding to the first program operation PG. The channel arbitration module 211 may authorize data transmission or reception through a number of channels corresponding to the parameter X1.

For example, when the parameter X1 corresponding to the first program operation PG is 6, the channel arbitration module 211 may approve transmission or reception through a total of 6 channels. Referring to fig. 4A, at a first time point t1, the channel arbitration module 211 receives a request signal for requesting approval of transmission or reception through the first channel CH1 and the fourth channel CH 4. Since there is no channel corresponding to the memory chip performing the first program operation PG at the first time point t1, the channel arbitration module 211 may approve transmission or reception through the first channel CH1 and the fourth channel CH 4. Between the first time point t1 and the second time point t2, the channel arbitration module 211 may sequentially approve transmission or reception through the third channel CH3, the sixth channel CH6, the seventh channel CH7, and the second channel CH 2. The memory chip corresponding to the channel through which transmission or reception has been approved may perform the first program operation PG.

Since a total of 6 channels correspond to the memory chip performing the first program operation PG at the second time point t2, the channel arbitration module 211 does not approve transmission or reception through the fifth channel CH5 and the eighth channel CH 8. Therefore, transmission of the command via the fifth channel CH5 and the eighth channel CH8 is suspended (pending).

At the third time point t3, the channel arbitration module 211 may determine that the first program operation PG of the memory chips corresponding to the first channel CH1 and the fourth channel CH4 has been completed. In other words, since a total of 4 channels correspond to the memory chip performing the first program operation PG at the third time point t3, the channel arbitration module 211 may approve transmission or reception of the fifth channel CH5 and the eighth channel CH8, the fifth channel CH5 and the eighth channel CH8 being channels through which command transmission has been suspended. For example, the channel arbitration module 211 may grant the transmission or reception of the fifth channel CH5 and the eighth channel CH8 at the third time point t3 or after the third time point t 3.

Fig. 4B illustrates an embodiment in which a plurality of memory chips perform a first program operation PG and a second program operation tPROG. When the channel arbitration module 211 according to an embodiment of the inventive concept determines that the memory chip is performing the second program operation tPROG, the channel arbitration module 211 may check the parameter TABLE a to determine X2 and W1 as parameters corresponding to the second program operation tPROG. The channel arbitration module 211 may grant transmission or reception of data associated with the first program operation PG for a number of channels corresponding to the checked parameter X2, and may grant transmission or reception of data associated with the second program operation tPROG for a number of channels corresponding to the checked parameter W1.

For example, when the parameter X2 corresponding to the first program operation PG is 1 and the parameter W1 corresponding to the second program operation tPROG is 3, the channel arbitration module 211 may grant transmission or reception of data associated with the first program operation PG for a total of one channel and may grant transmission or reception of data associated with the second program operation tPROG for a total of three channels.

Referring to fig. 4B, since there is no channel corresponding to the memory chip performing the second program operation tPROG at the fourth time point t4, the channel arbitration module 211 may grant transmission or reception of the first channel CH1 to the third channel CH 3. Since there is no channel corresponding to the memory chip performing the first program operation PG at the fourth time point t4, the channel arbitration module 211 may grant transmission or reception of the sixth channel CH 6.

Since a total of one channel corresponds to the memory chip performing the first program operation PG between the fifth time point t5 and the sixth time point t6, the channel arbitration module 211 does not approve transmission or reception through the fourth channel CH4, the fifth channel CH5, the seventh channel CH7, and the eighth channel CH 8. Therefore, the transmission of commands via the fourth channel CH4, the fifth channel CH5, the seventh channel CH7, and the eighth channel CH8 is suspended.

At the sixth time point t6, the channel arbitration module 211 determines that the first program operation PG of the memory chip corresponding to the sixth channel CH6 has been completed. In other words, since no channel corresponds to the memory chip performing the first program operation PG at the sixth time point t6, the channel arbitration module 211 may approve transmission or reception of one of the channels that has been suspended through command transmission therethrough. The channel arbitration module 211 may approve transmission or reception of channels that have been suspended through command transmission according to the order in which request signals for requesting approval of transmission or reception are received. For example, the channel arbitration module 211 may first grant transmission or reception of the fifth channel CH5 corresponding to the first received request signal among the fourth channel CH4, the fifth channel CH5, the seventh channel CH7, and the eighth channel CH8, the fourth channel CH4, the fifth channel CH5, the seventh channel CH7, and the eighth channel CH8 being channels via which command transmission has been suspended.

Fig. 4C illustrates an embodiment in which a plurality of memory chips perform the first program operation PG and the read operation RD. When the channel arbitration module 211 according to an embodiment of the inventive concept determines that the memory chip is performing the first program operation PG and the read operation RD, the channel arbitration module 211 may check the parameter TABLE a to determine X4 and Z3 as parameters corresponding to the first program operation PG and the read operation RD. In one exemplary embodiment, when at least one of the memory chips has been executing the first program operation PG at a specific time and at least one of the memory chips has been executing the read operation RD at a specific time, the channel arbitration module 211 determines that the memory chips are executing the first program operation PG and the read operation RD at the specific time. The channel arbitration module 211 may authorize transmission or reception of data associated with the first programming operation PG through a number of channels corresponding to the checked parameter X4, and may authorize transmission or reception of data associated with the read operation RD through a number of channels corresponding to the checked parameter Z3.

For example, when the parameter X4 corresponding to the first program operation PG is 3 and the parameter Z3 corresponding to the read operation RD is 3, the channel arbitration module 211 may approve transmission or reception through a total of 6 channels. Referring to fig. 4C, at a time point t7, the channel arbitration module 211 receives a request signal for requesting approval of transmission or reception through the first channel CH1, the fourth channel CH4, and the seventh channel CH 7. Since there is no channel corresponding to the memory chip performing the first program operation PG or the read operation RD at the seventh time point t7, the channel arbitration module 211 may approve transmission or reception through the first channel CH1, the fourth channel CH4, and the seventh channel CH 7. Between the time point t7 and the time point t8, the channel arbitration module 211 may sequentially approve transmission or reception through the third channel CH3, the sixth channel CH6, and the second channel CH 2. Accordingly, three memory chips have been approved to perform the first program operation PG, and three other memory chips have been approved to perform the read operation.

Since a total of 6 channels correspond to the memory chips performing the first program operation PG and the read operation RD at the time point t8, the channel arbitration module 211 does not grant transmission or reception through the fifth channel CH5 and the eighth channel CH 8. Therefore, the transmission of the commands via the fifth channel CH5 and the eighth channel CH8 is suspended.

At a time point t9, the channel arbitration module 211 may determine that the read operations corresponding to the channels CH4 and CH7 have been completed and that the program operation corresponding to the channel CH1 has been completed. In other words, since a total of 3 channels correspond to the memory chip performing the first program operation PG and/or the read operation RD at the time point t9, the channel arbitration module 211 may grant transmission or reception of the fifth channel CH5 and the eighth channel CH8, the fifth channel CH5 and the eighth channel CH8 being channels through which command transmission has been suspended. For example, the channel arbitration module 211 may grant the transmission or reception of the fifth channel CH5 and the eighth channel CH8 at the time point t9 or after the time point t 9.

Fig. 5 is a block diagram of a memory system 300 according to an exemplary embodiment of the inventive concepts.

Referring to fig. 1 to 5, a memory system 300 includes a memory controller 310 (e.g., a control circuit) and a memory device 320, the memory controller 310 includes a channel arbitration module 311 and a memory interface (I/F)313 (e.g., an interface circuit), and the memory device 320 may include n memory chips (NVMs) 321_1 to 321_ n. The channel arbitration module 311 may correspond to the channel arbitration module 211 of FIG. 1.

The memory I/F313 may transmit or receive data via the n channels CH1 to CHn respectively connecting the memory controller 310 to the n memory chips 321_1 to 321_ n of the memory device 320. The memory I/F313 may queue the command CMD for each of the n channels CH1 through CHn, and may transmit or receive the command CMD or the DATA through the n channels CH1 through CHn under the control of the memory controller 310. For example, the memory I/F313 may include a buffer that temporarily stores the commands CMD until they are executed.

According to an exemplary embodiment of the inventive concept, the memory I/F313 transmits a request signal Req for requesting approval of transmission or reception through the first channel CH1 to the channel arbitration module 311 before transmitting the queued command CMD through the first channel CH 1. When receiving the permission signal Grant corresponding to the request signal Req from the channel arbitration module 311, the memory I/F313 may transmit or receive the queued command CMD and the DATA related to the queued command CMD via the first channel CH 1. On the other hand, when the permission signal Grant corresponding to the request signal Req is not received from the channel arbitration module 311, the memory I/F313 defers transmission or reception via the first channel CH 1.

According to an exemplary embodiment of the inventive concept, the channel arbitration module 311 receives the request signal Req from the memory I/F313. In response to the request signal Req, the channel arbitration module 311 may obtain information Status about the respective operating states of the n memory chips 321_1 to 321_ n. The information Status related to the respective operating states of the n memory chips 321_1 to 321_ n may indicate which operating state each of the n memory chips 321_1 to 321_ n is in among a first program operation, a second program operation, a read operation, an erase operation, and an idle state.

The channel arbitration module 311 may obtain information Status about the respective operating states of the n memory chips 321_1 to 321_ n from the memory I/F313 via various methods. For example, the channel arbitration module 311 may transmit a request (e.g., a signal) for the information Status related to the respective operating state to the memory I/F313 in response to the request signal Req, and may receive the information Status related to the respective operating state from the memory I/F313 in response to the transmitted request. Alternatively, the channel arbitration module 311 may continuously receive signals representing respective operation states of the n memory chips 321_1 to 321_ n from the memory I/F313 via specific hardware components, and may generate information Status about the respective operation states by using the signals in response to the request signal Req. Alternatively, the channel arbitration module 311 may periodically receive information about the operation state from the memory I/F313 regardless of the request signal Req.

The channel arbitration module 311 may determine whether the first channel CH1 is approved based on the information Status about the respective operating states of the n memory chips 321_1 to 321_ n and the parameter 312 set based on the power consumption of each operation of the memory chips. The parameters 312 may include different parameters for each operation of the memory chip or a combination of operations of the memory chip. For example, as in the above example of fig. 2A or 2B, the parameter 312 may be the maximum number of memory chips capable of performing a program operation, a read operation, or an erase operation within the allowable amount of power, and may be the maximum number of memory chips capable of performing an operation included in each combination of a program operation, a read operation, and an erase operation within the allowable amount of power.

The parameters 312 may be stored in a memory (not shown) or buffer (not shown) within the memory controller 310 and read from by the channel arbitration module 311, or may be stored in a memory (not shown) within the channel arbitration module 311. The channel arbitration module 311 or the memory controller 310 may calculate the parameter 312 by using the power consumption of each operation and store the calculated parameter 312.

As an example of determining whether to approve or disapprove the first channel CH1 by using the information Status about the respective operating states of the n memory chips 321_1 to 321_ n and the parameter 312, the channel arbitration module 311 may first determine a parameter corresponding to the current operation of the memory chips 321_1 to 321_ n from the parameter 312 based on the information Status about the respective operating states of the memory chips 321_1 to 321_ n. For example, when the channel arbitration module 311 determines that the memory chips 321_1 to 321_ n perform the first program operation, the channel arbitration module 311 may determine a parameter corresponding to the first program operation.

The channel arbitration module 311 may compare the determined parameter with information Status about the respective operating states of the n memory chips 321_1 to 321_ n, and thus may determine whether the number of memory chips currently being operated has reached the maximum number. When the number of memory chips currently operating does not reach the maximum number, the total power consumption does not exceed the allowable power amount even when the memory chips additionally perform the operation of the queued command CMD, and therefore, the channel arbitration module 311 determines that the first channel CH1 is granted. On the other hand, when the number of memory chips currently operating reaches the maximum number, the channel arbitration module 311 determines not to approve the first channel CH1 to prevent the total power consumption from exceeding the allowable power amount.

The channel arbitration module 311 may send the result of the determination to the memory I/F313. For example, when the channel arbitration module 311 determines that the first channel CH1 is granted, the channel arbitration module 311 transmits the Grant signal Grant to the memory I/F313. On the other hand, when the channel arbitration module 311 determines that the first channel CH1 is not granted, the channel arbitration module 311 does not transmit the permission signal Grant to the memory I/F313.

According to an exemplary embodiment of the inventive concept, the memory I/F313 transmits the End signal End instead of the request signal Req to the channel arbitration module 311. For example, when the operation of one of the memory chips 321_1 to 321_ n has ended, the memory I/F313 transmits an End signal End to the channel arbitration module 311. In response to the End signal End, the channel arbitration module 311 may again determine whether to grant or not grant the first channel CH 1. For example, when it has been determined that the first channel CH1 is not approved in response to the request signal Req, since the operation of one of the memory chips 321_1 to 321 — n has ended, the channel arbitration module 311 newly determines whether the total power consumption does not exceed the allowable power amount even when the operation corresponding to the queued command CMD is performed for the first channel CH 1. When the channel arbitration module 311 has transmitted the permission signal Grant for the first channel CH1 in response to the request signal Req, the operation of re-determining whether to Grant or disapprove the first channel CH1 may be omitted. The operation of determining the approval or disapproval of the first channel CH1 in response to the End signal End performed by the channel arbitration module 311 is substantially the same as the above-described operation of determining the approval or disapproval of the first channel, and therefore, redundant description thereof is omitted.

Fig. 6 is a block diagram of a memory controller 400 according to an exemplary embodiment of the inventive concepts.

Referring to fig. 1 through 6, a memory controller 400 may include a host I/F410 (e.g., a circuit), a processor 420, a memory 430, a temperature sensor 440 (e.g., a thermocouple), and a memory I/F450. The memory 430 includes a channel arbitration module 431. The channel arbitration module 431 may correspond to one of the channel arbitration module 211 of fig. 1 and the channel arbitration module 311 of fig. 5.

HOST I/F410 may communicate with HOST HOST (e.g., a HOST device) via various I/Fs. According to one embodiment, HOST I/F410 may communicate with HOST via various I/fs such as Universal Serial Bus (USB), multimedia card (MMC), PCI express (PCI-E), AT attachment (ATA), serial AT attachment (SATA), parallel AT attachment (PATA), Small Computer System Interface (SCSI), serial attached SCSI (sas), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE). For example, a host I/F may implement non-volatile memory express (NVMe) as an I/F optimized for a memory system such as an SSD.

According to an exemplary embodiment of the inventive concept, HOST I/F410 receives specification information of HOST from HOST. The specification information may include, for example, information about the type of device, model information, and information about the required amount of power consumption of the memory system. The information included in the specification information is not limited thereto.

Channel arbitration module 431 may set parameters based on the received specification information for HOST HOST. For example, because the allowed power amount may vary according to the type of HOST, channel arbitration module 431 may set a parameter based on the allowed power amount corresponding to the specification information of HOST. For example, the channel arbitration module 431 may set different parameters for each host that it receives specification information.

The processor 420 may include a CPU or microprocessor, and may control the overall operation of the memory controller 400 by executing instructions stored in the memory 430. Fig. 6 shows a processor 420. However, embodiments of the inventive concept are not limited thereto, as the memory controller 400 may include a plurality of processors 420.

The memory 430 may operate under the control of the processor 420, and may be implemented as a volatile memory, such as a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM), or may be implemented as a non-volatile memory, such as a phase change random access memory (PRAM) or a flash memory. The channel arbitration module 431 may be implemented as firmware or software and may be loaded in the memory 430. Although the channel arbitration module 431 is loaded in the memory 430 in fig. 6, embodiments of the inventive concept are not limited thereto. For example, the channel arbitration module 431 may be loaded in a memory (not shown) located outside the memory controller 400, and may be arranged as a special component implemented as hardware inside or outside the memory controller 400.

The temperature sensor 440 may sense temperature. According to an exemplary embodiment, the temperature sensor 440 is disposed within the memory controller 400 to sense an ambient temperature and output a voltage corresponding to the sensed temperature as temperature information. Although the temperature sensor 440 is included in the memory controller 400 in fig. 6, embodiments of the inventive concept are not limited thereto. For example, the temperature sensor 440 may be disposed inside or near the memory device and may sense an ambient temperature around the memory device. Fig. 6 shows a temperature sensor 440. However, according to another embodiment, memory controller 400 includes a plurality of temperature sensors 440.

According to an exemplary embodiment of the inventive concept, the channel arbitration module 431 sets different parameters according to different temperature ranges. Since the allowable power amount may vary according to the temperature of the memory system, the channel arbitration module 431 may set different parameters according to the allowable power amounts respectively corresponding to different temperature ranges. For example, when the temperature is relatively high, the channel arbitration module 431 may set the parameters based on a relatively low amount of allowed power. In an exemplary embodiment, the channel arbitration module 431 sets a first parameter based on the first allowable power amount when the temperature is a first temperature value, and the channel arbitration module 431 sets a second parameter based on the second allowable power amount when the temperature is a second temperature value, wherein the first allowable power amount is lower than the second allowable power amount when the first temperature value is higher than the second temperature value.

When the channel arbitration module 431 receives a request signal for requesting approval of transmission or reception through a specific channel from the memory I/F450, the channel arbitration module 431 may obtain temperature information from the temperature sensor 440 and may obtain information on respective operation states of a plurality of memory chips of the memory device. The channel arbitration module 431 may determine a parameter corresponding to the temperature of the memory system from among a plurality of parameters by using the obtained temperature information, and may schedule transmission or reception of data through the plurality of channels by using the determined parameter and the operation states of the plurality of memory chips of the memory device. In fig. 6, memory controller 400 includes a temperature sensor 440. However, according to another embodiment, the temperature sensor 440 is omitted.

According to an exemplary embodiment of the inventive concept, parameters may be set by further considering specification information or temperature information of a host in addition to power consumption per operation of a memory chip, and data transmission or reception of a plurality of channels may be controlled using the parameters conforming to the condition (e.g., condition or state) of a memory system, resulting in more optimized power management of the memory system.

Fig. 7 is a block diagram of a channel arbitration module 500 according to an example embodiment of the present disclosure.

Referring to fig. 1 through 7, the channel arbitration module 500 includes a parameter 510, an arbitration core 520, a job scheduler 530, and a status checker 540. The parameter 510 is substantially the same as the parameter 312 of fig. 5, and thus a detailed description thereof will be omitted. When the channel arbitration module 500 is implemented as hardware or partially as hardware, the job scheduler 530 and/or the status checker 540 may each be implemented by logic circuitry.

According to one embodiment of the inventive concept, the memory I/F may transmit request signals Req 1 to Req n of commands queued for a plurality of channels respectively corresponding to n memory chips to the channel arbitration module 500. When the operation of each of the n memory chips has ended, the memory I/F may transmit End signals End 1 to End n to the channel arbitration module 500. Each of the request signal and the end signal may include: information on the number (or identifier) of the corresponding memory chip or information on a command (or memory operation) of the corresponding memory chip. For example, the identifier may uniquely identify a particular memory chip of the memory chips. For example, the information related to the command may indicate the type of operation completed (such as whether the operation is a read operation RD, a first program operation PG, etc.).

When the job scheduler 530 receives request signals Req 1 to Req n or End signals End 1 to End n for n memory chips from the memory I/F, the job scheduler 530 may generate a job schedule by using the received request signals Req 1 to Req n or the received End signals End 1 to End n.

For example, when the job scheduler 530 receives a plurality of request signals from the memory I/F, the job scheduler 530 may generate a job schedule of jobs corresponding to the plurality of request signals according to an order in which the request signals are received. When job scheduler 530 receives at least one end signal from memory I/F, job scheduler 530 may delete a job corresponding to the received end signal from the job schedule. The method of generating the job schedule performed by the job scheduler 530 will be described in detail later with reference to fig. 8A and 8B.

The state checker 540 may generate operating state information for each of the n memory chips. For example, the state checker 540 may receive signals Status1 to Status n indicating respective operation states of n memory chips from the memory I/F via specific hardware components, and may generate information on the operation states by using the received signals Status1 to Status n. The state checker 540 may provide the generated information regarding the operating state to the arbitration core 520.

The arbitration core 520 may determine which channel of the plurality of channels is to be granted permission to perform a transmission or reception. For example, when arbitration core 520 receives a job schedule from job scheduler 530, arbitration core 520 may identify a need to determine which of a plurality of channels is to be granted to perform a send or receive, and therefore arbitration core 520 may receive information regarding the status of operations from status checker 540. The arbitration core 520 may receive parameters corresponding to the operating state from the parameters 510 based on the received information about the operating state. The arbitration core 520 may check the number of channels corresponding to the received parameters according to the order of job scheduling. For example, each job in the job schedule may correspond to a different operation scheduled to be performed using a particular channel. When there is a channel that has not received the Grant signal Grant among the checked channels, the arbitration core 520 may transmit the Grant signal Grant to the channel.

For example, when the arbitration core 520 determines that the operation currently performed by the current memory chip is the first program operation based on the information about the operation state, the arbitration core 520 may check the parameter table of fig. 2A to determine the parameter X1 corresponding to the first program operation. The arbitration core 520 may sequentially check the X1 channels performing the first programming operation according to the order of job scheduling. When there is a channel that has not received the Grant signal Grant among the checked X1 channels, the arbitration core 520 may transmit the Grant signal Grant to the channel.

In fig. 7, the channel arbitration module 500 includes a status checker 540. However, according to another embodiment, the status checker 540 is omitted. In this case, the channel arbitration module 500 may indirectly check the operation state of the memory chip. For example, the channel arbitration module 500 may infer the operation state of the memory chip that is determined to be included in the job schedule and has received the permission signal Grant, based on the command information included in the job schedule. The channel arbitration module 500 may also infer that a memory chip included in the job schedule but not yet receiving the Grant signal Grant is in an idle state. Alternatively, the channel arbitration module 500 may infer the operating state of the memory chip by using the state in which the job requested from the HOST is queued.

According to an exemplary embodiment of the inventive concept, the channel arbitration module 500 generates a job schedule and determines whether to approve or disapprove transmission or reception of channels according to the order of the generated job schedule, thereby sequentially scheduling a plurality of channels even when operations of a plurality of memory chips are expected.

Fig. 8A and 8B illustrate a method of generating a job schedule according to an embodiment of the inventive concept.

The job scheduler 530 of fig. 7 according to an embodiment of the inventive concept may input request signals to a first-in first-out (FIFO)531 according to an order in which the request signals are received from the memory I/F. Job scheduler 530 may input end signals to FIFO 533 according to the order in which the end signals are received from memory I/F. Job scheduler 530 may generate job schedule 535 by using FIFO 531 for request signals and FIFO 533 for end signals.

For ease of explanation, such methods are described: on the premise that a plurality of request signals Req 1, Req3, Req8, and Req4 have been input to the FIFO 531 and that a job schedule has been generated in the order of Req 1, Req3, Req8, and Req4, the job scheduler 530 generates the job schedule 535 by additionally receiving a request signal or an end signal.

Referring to fig. 8A, the job scheduler 530 receives a second request signal Req2 (r) from the memory I/F and inputs a second request signal Req2 to a FIFO 531 (r) for request signals. Job scheduler 530 may generate job schedule 535 by using methods such as linked lists or search trees. For example, job scheduler 530 sequentially fetches request signals from FIFO 531 for request signals, checks whether the fetched request signals are included in existing job schedule 535, and creates a new request signal (or entry) in job schedule 535 for each fetched request signal that is not already in existing job schedule 535. In other words, the job scheduler 530 inserts the second request signal Req2 as a new request signal from the FIFO 531 for request signals into the job schedule 535 (c). Job scheduler 530 may provide job schedule 535 generated in this manner to channel arbitration module 500.

The channel arbitration module 500 may receive information on the operation state from the state checker 540 in response to receiving the job schedule 535, and may determine that the current memory chip is performing the first program operation PG and the read operation RD based on the received information on the operation state. The channel arbitration module 500 may determine the above-described parameters X4 and Z3 as parameters corresponding to the checked operation by checking the table of fig. 2A.

For example, the parameters X4 and Z3 may both be 3. The channel arbitration module 500 may check that the memory chips corresponding to the first request Req 1, the third request Req3, the eighth request Req8, and the fourth request Req4 have performed an operation in response to the permission signal Grant, based on the information on the operation state or the transmission history of the permission signal Grant. Accordingly, the channel arbitration module 500 may determine whether to approve or disapprove transmission or reception of a channel corresponding to the second request Req2 for which the Grant signal Grant has not been received according to the order of the job schedule 535. Since three channels are currently performing the first programming operation PG, the channel arbitration module 500 determines not to grant transmission or reception of the channel corresponding to the second request Req 2.

Referring to fig. 8B, the job scheduler 530 receives the third End signal End 3 from the memory I/F (r), and inputs the third End signal End 3 to the FIFO 533 for End signal (c). Job scheduler 530 may sequentially fetch end signals from FIFO 533 for end signals, and may delete request signals corresponding to the fetched end signals from the request signals included in job schedule 535. For example, the job scheduler 530 may fetch the third End signal End 3 as a new End signal from the FIFO 533 for End signal, and may delete the third request signal Req3 (or an entry associated with the request signal) included in the job schedule 535 (step (c)). Although not shown in fig. 8B, the job scheduler 530 may delete the third request signal Req3 from the FIFO for request signals 531 and delete the third End signal End 3 from the FIFO for End signals 533. Job scheduler 530 may provide job schedule 535 generated in this manner to channel arbitration module 500.

The channel arbitration module 500 may receive information on the operation state from the state checker 540 in response to the job schedule 535, and may check that the current memory chip is performing the first program operation PG and the read operation RD based on the received information on the operation state. The channel arbitration module 500 may determine the above-described parameters X4 and Z3 from the table of FIG. 2A as the parameters corresponding to the checked operation.

For example, the parameters X4 and Z3 may both be 3. The channel arbitration module 500 may check that the memory chips corresponding to the first request Req 1, the eighth request Req8, and the fourth request Req4 are performing an operation in response to the permission signal Grant based on the information on the operation state or the transmission history of the permission signal Grant. Accordingly, the channel arbitration module 500 may re-determine whether to approve or disapprove transmission or reception of a channel corresponding to the second request Req2 for which the Grant signal Grant has not been received according to the order of the job schedule 535. Since two channels are currently performing the first programming operation PG, the channel arbitration module 500 determines to grant transmission or reception of the channel corresponding to the second request Req 2.

Fig. 9 is a block diagram illustrating a method of scheduling data transmission or reception of a channel according to an exemplary embodiment of the inventive concept.

Referring to fig. 1 to 9, a memory system 700 includes a memory controller 710 and a memory device 720, and the memory controller 710 includes a channel arbitration module 711 and a memory I/F713. The memory device 720 may include n memory chips 721_1 to 721_ n (i.e., first to nth memory chips 721_1 to 721_ n). According to one embodiment, the memory I/F713 includes n pins 715_1 to 715_ n (i.e., first to nth pins 715_1 to 715_ n) for connecting a plurality of channels of the n memory chips 721_1 to 721_ n. The term "pin" may be referred to as a terminal or an output pin, depending on the embodiment.

According to an exemplary embodiment of the inventive concept, the channel arbitration module 711 determines a channel to be approved to perform transmission or reception among a plurality of channels, and determines whether there is a channel that has not received the Grant signal Grant among the channels to be approved to perform transmission or reception. When there is a channel that has not received the Grant signal Grant, the channel arbitration module 711 may transmit the Grant signal Grant to the channel. When the memory I/F713 receives the permission signal Grant from the channel arbitration module 711, the memory I/F713 may transmit a queued command CMD for a channel corresponding to the permission signal Grant to the memory device 720 via the channel.

For example, when the channel arbitration module 711 determines that the second channel CH2 among the channels through which transmission or reception has been approved is a channel through which the permission signal Grant has not been received, the channel arbitration module 711 transmits the permission signal Grant to the second pin 715_2, and the memory I/F713 transmits the queued command CMD for the second channel CH2 to the second memory chip 721_2 through the second pin 715_ 2. The second memory chip 721_2 may perform a memory operation corresponding to the received command, and may transmit data related to the performed memory operation to the memory controller 711 on the second channel CH2 via the second pin 715_ 2.

Fig. 10 is a flowchart of a method of scheduling data transmission or reception of a plurality of channels according to an exemplary embodiment of the inventive concepts.

The method of scheduling data transmission or reception of a plurality of channels according to the present embodiment may be performed in the memory system 200 of fig. 1, the memory system 300 of fig. 5, or the memory system 700 of fig. 9. The description given with reference to fig. 1 to 9 is equally applicable to the present embodiment.

Referring to fig. 10, the memory system sets parameters based on information on power consumption of each operation of the memory chip (S11). The information on power consumption of each operation of the memory chip may include a power consumption amount of at least one of a program operation, a read operation, an erase operation, and an idle state. The programming operation may be divided into a plurality of detailed operations. For example, the program operation may be divided into a data I/O operation (referred to as a first program operation for convenience of explanation) and a data write operation (referred to as a second program operation for convenience of explanation). The first program operation corresponds to an operation in which a program command and data are input to the memory chip through the channel and buffered (e.g., in an I/O buffer included in the memory chip). The second program operation corresponds to an operation of programming or writing buffered data (e.g., buffered in an I/O buffer included in the memory chip) to the memory cell array.

The memory system may set, as a parameter, the number of memory chips capable of performing each memory operation in parallel as long as the total power consumption does not exceed a preset power amount (i.e., an allowable power amount). The memory system may set parameters for each operation of the memory chip or for each combination of operations of the memory chip.

For example, the memory system may set, as parameters, the number of memory chips capable of performing the first programming operation in parallel as long as the total power consumption does not exceed the allowable power amount, the number of memory chips capable of performing the second programming operation in parallel as long as the total power consumption does not exceed the allowable power amount, the number of memory chips capable of performing the read operation in parallel as long as the total power consumption does not exceed the allowable power amount, and the number of memory chips capable of performing the erase operation in parallel as long as the total power consumption does not exceed the allowable power amount. The memory system may set, as a parameter, the number of memory chips capable of performing operations included in a combination of the first program operation, the second program operation, the read operation, and the erase operation in parallel as long as the total power consumption does not exceed the allowable amount of power.

The memory system may set different parameters according to different temperature ranges of the memory system. For example, when the temperature of the memory system is relatively high, the memory system may set the parameters based on a relatively low amount of allowed power.

The memory system may receive specification information of the host from the host, and may set parameters based on the received specification information and power consumption of each operation of the memory chip. The specification information may include, for example, information about the type of device, model information, and information about the required amount of power consumption of the memory system. The information included in the specification information is not limited thereto.

The memory system obtains information on the operating states of the plurality of memory chips (S12). The operating state of the memory chip may include at least one of a program operation, a read operation, an erase operation, and an idle state. The memory system controls transmission or reception through the plurality of channels based on the set parameters and the information on the operation states of the plurality of memory chips (S13). For example, the memory system may authorize transmission or reception over a number of channels corresponding to the parameter. For example, the memory system may authorize data transmission or reception through a number of channels corresponding to a parameter, including a channel corresponding to a memory chip that is considered to currently perform an operation, based on information regarding the operating states of a plurality of memory chips.

Fig. 11 is a flowchart of a method of scheduling data transmission or reception of a plurality of channels according to an exemplary embodiment of the inventive concepts. In detail, fig. 11 is a flowchart of an embodiment of operations S12 and S13 of fig. 10. The following operations may be performed by one of the channel arbitration module 211 of fig. 1, the channel arbitration module 311 of fig. 5, the channel arbitration module 431 of fig. 6, the channel arbitration module 500 of fig. 7, and the channel arbitration module 711 of fig. 9.

Referring to fig. 11, the channel arbitration module receives a request for approval of data transmission or reception via the first channel (S21). The channel arbitration module obtains information on the operation states of the plurality of memory chips (S22). For example, the channel arbitration module may request information regarding the operating state from the memory I/F in response to the request, and thus may receive the information regarding the operating state from the memory I/F. Alternatively, the channel arbitration module may successively receive signals representing respective operating states of the plurality of memory chips from the memory I/F via a specific hardware component, and may generate information on the operating states by using the received signals in response to the request. Alternatively, the channel arbitration module may periodically receive information about the operating state from the memory I/F regardless of whether a request is received.

The channel arbitration module determines whether to approve the first channel based on the set parameters and the information on the operation states of the plurality of memory chips (S23). The channel arbitration module provides the determination result as to whether the first channel is approved to the memory I/F (S24). When the transmission or reception of the first channel is approved, the memory I/F may transmit or receive data to or from the first memory chip via the first channel. When the transmission or reception of the first channel is not approved, the memory I/F delays the transmission or reception of data via the first channel. Operations S23 and S24 will now be described in more detail with reference to fig. 12 and 13.

Fig. 12 is a flowchart of a method of determining approval or disapproval of a target channel according to an exemplary embodiment of the inventive concept.

In detail, fig. 12 is a flowchart of an embodiment of operation S23 of fig. 11. The following operations may be performed by one of the channel arbitration module 211 of fig. 1, the channel arbitration module 311 of fig. 5, the channel arbitration module 431 of fig. 6, the channel arbitration module 500 of fig. 7, and the channel arbitration module 711 of fig. 9.

Referring to fig. 12, the channel arbitration module checks parameters corresponding to the operation of the plurality of memory chips (S31). For example, the channel arbitration module may check what operation is currently being performed by the plurality of memory chips based on information about the operating states of the plurality of memory chips. The channel arbitration module may check a parameter corresponding to the checked operation. For example, when the channel arbitration module determines that the plurality of memory chips are performing the first program operation, the channel arbitration module may check a parameter corresponding to the first program operation.

According to an exemplary embodiment, when the channel arbitration module has set different parameters according to different temperature ranges, the channel arbitration module may obtain temperature information of the memory system from the temperature sensor, and may check a parameter corresponding to the obtained temperature information.

The channel arbitration module checks whether the number of memory chips performing the checked operation is equal to the checked parameter (S32). When the number of memory chips performing the checked operation is equal to the checked parameter (S32-Y), this may indicate that the amount of power consumption of the memory chip currently performing the operation reaches the allowable amount of power. Therefore, in order to prevent excessive power consumption due to the execution of the additional operation of the memory chip, the channel arbitration module determines not to approve the first channel (S34).

On the other hand, when the number of memory chips performing the checked operation is not equal to (e.g., is smaller than) the checked parameter (S32-N), this may indicate that the amount of power consumption of the memory chip currently performing the operation does not reach the allowable amount of power. Therefore, the channel arbitration module determines to grant the first channel (S33).

Fig. 13 is a flowchart of a method of determining approval or disapproval of a target channel according to an exemplary embodiment of the inventive concept. In detail, fig. 13 is a modified embodiment of fig. 12.

Referring to fig. 13, the channel arbitration module obtains job schedules for a plurality of memory chips (S41). The channel arbitration module may generate the job schedule by using a request signal for requesting data transmission or reception via a channel corresponding to each of the plurality of memory chips from the memory I/F or an end signal indicating that an operation of each of the plurality of memory chips has ended.

For example, when the channel arbitration module receives a plurality of request signals from the memory I/F, the channel arbitration module may generate a job schedule of jobs corresponding to the request signals according to an order in which the request signals are received. When the channel arbitration module receives at least one end signal from the memory I/F, the channel arbitration module may delete a job (or an entry associated with a job) corresponding to the received end signal from the job schedule.

The channel arbitration module checks parameters corresponding to the operations of the plurality of memory chips (S42).

The channel arbitration module checks a channel to be approved to perform data transmission or reception by using the checked parameters and job schedule (S43). For example, the channel arbitration module may check the number of channels corresponding to the checked parameters in the order of job scheduling. For example, when the plurality of memory chips perform a first program operation and a value of a parameter corresponding to the first program operation is 3, the channel arbitration module may determine that 3 channels correspond to the first program operation according to an order of job scheduling.

The channel arbitration module checks whether the first channel is included in the channels to be granted (S44). When the first channel is not included in the granted channels (S44-N), the channel arbitration module determines not to grant the first channel (S46). On the other hand, when the first channel is included in the granted channels (S44-Y), the channel arbitration module determines to grant the first channel (S45).

Even when it is determined that the first channel is not granted, the channel arbitration module may re-determine whether to grant data transmission or reception of the first channel when a preset event occurs. The preset event may be an event in which a new request is received from the host and thus the channel arbitration module receives a request for data transmission or reception of a channel corresponding to the new request from the memory I/F. Alternatively, the preset event may be an event that: the channel arbitration module receives an end signal from the memory I/F when the operation of one of the plurality of memory chips has ended. In this case, the channel arbitration module may update the job schedule by considering the received request signal or end signal, and may re-determine whether to grant data transmission or reception of the first channel based on the updated job schedule.

Fig. 14 is a block diagram of a computing system 1000 according to an exemplary embodiment of the inventive concepts.

Referring to fig. 14, a computing system 1000 may include a host 1100 and a storage device 1200. For example, host 1100 may include a host controller 1110 and a host memory 1120. The memory device 1200 may include a memory controller 1210 and a non-volatile memory 1220. The host memory 1120 may be used as a buffer memory for temporarily storing data to be transmitted to the storage device 1200 or data transmitted by the storage device 1200.

For example, the computing system 1000 may correspond to any of various types of systems, such as server devices, computers, netbooks, network tablets, wireless phones, mobile phones, smart phones, electronic books, navigation devices, digital cameras, wearable devices, internet of things (IoT) devices, internet of everything (IoE) devices, Virtual Reality (VR) devices, and Augmented Reality (AR) devices.

The storage device 1200 may include a storage medium for storing data according to a request from the host 1100. For example, the storage device 1200 may include at least one of a Solid State Drive (SSD), an embedded memory, and a removable external memory. According to the present embodiment, the storage apparatus 1200 may be a memory system corresponding to one of the above-described embodiments. Accordingly, the computing system 1000 may control data transmission or reception through a plurality of channels based on information on the operation states of a plurality of chips within the memory device 1200 and information on power consumption of each operation of each memory chip (or a parameter set based on the information on power consumption of each operation), thereby preventing problems from occurring in the entire system when the overall power consumption exceeds an allowable power level.

The host controller 1110 may manage operations of storing data (e.g., write data) of the host memory 1120 in the non-volatile memory 1220 or storing data (e.g., read data) of the non-volatile memory 1220 in the host memory 1120.

The storage controller 1210 may include a host I/F1211, a memory I/F1212, and a processor 1213. The memory controller 1210 may also include a Flash Translation Layer (FTL)1214, a packet manager 1215, a buffer memory 1216, an Error Correction Code (ECC) engine 1217, an Advanced Encryption Standard (AES) engine 1218, and a memory 1219. The memory 1219 may include a channel arbitration module. The memory controller 1210 may further include a working memory (not shown) in which the FTL 1214 is loaded, and the processor 1213 may control writing and reading of data with respect to the nonvolatile memory 1220 by executing the FTL 1214. According to an embodiment, the storage controller 1210 may further include a modem (not shown), an I/O device (not shown), a power supply (not shown), and the like.

The host I/F1211 may transmit a packet to the host 1100 or receive a packet from the host 1100. The packets sent by the host 1100 to the host I/F1211 may include, for example, commands or data to be written to the non-volatile memory 1220, and the packets sent by the host I/F1211 to the host 1100 may include, for example, responses to commands or data read from the non-volatile memory 1220.

FTL 1214 may perform several functions such as address mapping, wear leveling, and garbage collection. The address mapping is an operation of changing a logical address received from the host into a physical address for actually storing data in the nonvolatile memory 1220. Wear leveling is a technique for preventing excessive deterioration of a specific block by allowing blocks included in the nonvolatile memory 1220 to be uniformly used, and may be implemented, for example, by a firmware technique of leveling erase counts of physical blocks. Garbage collection is a technique to ensure available capacity in the non-volatile memory 1220 by copying valid data of a block to a new block and then erasing an existing block.

The packet manager 1215 may generate a packet according to the protocol of the I/F negotiated with the host 1100 or parse various information from a packet received from the host 1100. The buffer memory 1216 may temporarily store data to be written to the nonvolatile memory 1220 or data to be read from the nonvolatile memory 1220. The buffer memory 1216 may be a component included in the storage controller 1210, but may be provided outside the storage controller 1210.

The ECC engine 1217 may perform error detection and correction on read data read from the non-volatile memory 1220. In more detail, the ECC engine 1217 may generate parity bits regarding write data to be written to the non-volatile memory 1220, and the generated parity bits may be stored in the non-volatile memory 1220 together with the write data. During the data is read from the non-volatile memory 1220, the ECC engine 1217 may correct an error of the read data by using the parity bits read from the non-volatile memory 1220 and the read data, and may output the error-corrected read data.

The AES engine 1218 may perform at least one of encryption and decryption with respect to data input to the storage controller 1210 by using a symmetric key algorithm. In one exemplary embodiment, a symmetric key algorithm uses the same cryptographic key to encrypt plaintext and decrypt ciphertext.

According to an embodiment of the inventive concept, the memory apparatus 1200 may be implemented according to the embodiments described above with reference to fig. 1 to 13. For example, the memory controller 1210 may correspond to the memory controller described above with reference to fig. 1 to 13, and the nonvolatile memory 1220 may correspond to the memory device described above with reference to fig. 1 to 13.

For example, the memory controller 1210 may include a channel arbitration module, and may support a function of arbitrating a plurality of channels connected to the nonvolatile memory 1220 by using the channel arbitration module. For example, the memory controller 1210 may check operation states of a plurality of memory devices included in the nonvolatile memory 1220, and may arbitrate a plurality of channels based on the checked operation states and information on power consumption of each operation. A detailed description thereof may be substantially the same as that given above with reference to fig. 1 to 13, and thus will be omitted.

Accordingly, the computing system 1000 may control data transmission or reception through a plurality of channels based on information on operation states of a plurality of chips within the memory device 1200 and information on power consumption of each operation of each memory chip (or a parameter set based on the information on power consumption of each operation), thereby preventing problems from occurring in the entire system when the overall power consumption exceeds an allowable power level.

Fig. 15 is a block diagram of a memory system 800 according to an embodiment of the inventive concepts. Referring to fig. 15, a memory system 800 may include a memory device 820 and a memory controller 810. The memory system 800 may support a plurality of channels CH1 through CHm, and the memory device 820 and the memory controller 810 may be connected to each other through a plurality of channels CH1 through CHm (where m denotes the number of channels and is a positive integer).

The memory device 820 may include a plurality of nonvolatile memories NVM11 to NVMmn (where n denotes the number of memory devices connected to one channel and is a positive integer). Each of the nonvolatile memories NVM11 through nvmn may be connected to one of the channels CH1 through CHm through a corresponding path to each of the nonvolatile memories NVM11 through nvmn. For example, nonvolatile memories NVM 11-NVM 1n may be connected to first channel CH1 through paths W11-W1 n, and nonvolatile memories NVM 21-NVM 2n may be connected to second channel CH2 through paths W21-W2 n.

Memory controller 810 may send signals to or receive signals from memory device 820 via a plurality of channels CH 1-CHm. For example, the memory controller 810 may send commands CMDa to CMDk, addresses ADDRa to ADDRk, and data DATAa to DATAk to the memory device 820 through the plurality of channels CH1 to CHm, or receive data DATAa to DATAm from the memory device 820.

The memory controller 810 may select one nonvolatile memory from among nonvolatile memories connected to each channel through the channel, and may transmit or receive a signal to or from the selected nonvolatile memory. For example, the memory controller 810 may select the nonvolatile storage device NVM11 from the nonvolatile memories NVM 11-NVM 1n connected to the first channel CH 1. The memory controller 810 may send a command CMDa, an address ADDRa, and data DATAa to the selected non-volatile memory device NVM11 through the first channel CH1 or receive data DATAa from the selected non-volatile memory NVM 11.

Memory controller 810 may send signals to memory device 820 or receive signals from memory device 820 in parallel over different channels. For example, when sending command CMDa to memory device 820 through first channel CH1, memory controller 810 may send command CMDb to memory device 820 through second channel CH 2.

Each of the non-volatile memories NVM11 through nvmnn may operate under the control of the memory controller 810. For example, the non-volatile memory device NVM11 may program the data DATAa according to the command CMDa, the address ADDRa and the data DATAa provided through the first channel CH 1.

In fig. 15, a memory device 820 communicates with the memory controller 810 through m channels and includes n nonvolatile memory devices for each channel. However, the number of channels and the number of non-volatile memory devices connected to one channel may vary.

According to an embodiment of the inventive concept, the memory system 800 may be implemented according to the above-described embodiment with reference to fig. 1 to 14. For example, the memory controller 810 may include a channel arbitration module, and may support a function of arbitrating the plurality of channels CH1 through CHm connected to the nonvolatile memory 820 by using the channel arbitration module. For example, the memory controller 810 may check the operating states of the plurality of memory devices NVM11 to NVMmn of the nonvolatile memory 820, and may arbitrate the plurality of channels CH1 to CHm based on the checked operating states and information on power consumption of each operation. A detailed description thereof may be substantially the same as that given above with reference to fig. 1 to 14, and thus will be omitted.

Fig. 16 is a block diagram of a memory system 900 according to an embodiment of the inventive concepts. Referring to fig. 16, a memory system 900 may include a memory device 920 and a memory controller 910. The memory device 920 may correspond to one of the non-volatile memories NVM11 through nvmnn of fig. 15 that communicates with the memory controller 810 based on one of the plurality of channels CH1 through CHm. Memory controller 910 may correspond to memory controller 810 of fig. 15.

The memory device 920 may include first to eighth pins P11 to P18, a memory I/F circuit 921, a control logic circuit 923, and a memory cell array 925.

The memory I/F circuit 921 may receive the chip enable signal nCE from the memory controller 910 through the first pin P11. The memory I/F circuit 921 may transmit signals to the memory controller 910 or receive signals from the memory controller 910 through the second through eighth pins P12 through P18 according to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., a low level), the memory I/F921 may transmit or receive a signal to or from the memory controller 910 through the second through eighth pins P12 through P18.

The memory I/F circuit 921 may receive the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE from the memory controller 910 through the second through fourth pins P12 through P14. The memory I/F circuit 921 may receive the data signal DQ from the memory controller 910 through the seventh pin P17 or transmit the data signal DQ to the memory controller 910. The command CMD, the address ADDR, and the DATA may be transferred by the DATA signal DQ. For example, the data signals DQ may be transmitted through a plurality of data signal lines. In this case, the seventh pin P17 may include a plurality of pins corresponding to a plurality of data signals.

The memory I/F circuit 921 may obtain the command CMD from the data signal DQ received in an enable section (e.g., a high-level state) of the command latch enable signal CLE based on a switching timing (toggle timing) of the write enable signal nWE. The memory I/F circuit 921 may obtain the address ADDR from the data signal DQ received in an enable section (e.g., a high state) of the address latch enable signal ALE based on the switching timing of the write enable signal nWE.

According to an embodiment, the write enable signal nWE maintains a static (or constant) state (e.g., high or low) for a period of time and then switches between high and low levels. For example, the write enable signal nWE may be switched in an interval in which the command CMD or the address ADDR is transmitted. Therefore, the memory I/F921 can obtain the command CMD or the address ADDR based on the switching timing of the write enable signal nWE.

The memory I/F circuit 921 may receive the read enable signal nRE from the memory controller 910 through the fifth pin P15. The memory I/F circuit 921 may receive the data strobe signal DQS from the memory controller 910 through the sixth pin P16 or may transmit the data strobe signal DQS to the memory controller 910.

In an operation of outputting the DATA of the memory device 920, the memory I/F921 may receive the switched read enable signal nRE through the fifth pin P15 before outputting the DATA. The memory I/F circuit 921 may generate the data strobe signal DQS that is toggled based on toggling of the read enable signal nRE. For example, the memory I/F circuit 921 may generate the data strobe signal DQS, which starts toggling after a predetermined delay (e.g., tDQSRE) based on a toggling start time point of the read enable signal nRE. The memory I/F circuit 921 may transmit the DATA signal DQ including the DATA based on the switching timing of the DATA strobe signal DQS. Accordingly, the DATA may be aligned with the switching timing of the DATA strobe signal DQS and transmitted to the memory controller 910.

In the operation of inputting the DATA of the memory device 920, the memory I/F circuit 921 may receive the toggled DATA strobe signal DQs and the DATA from the memory controller 910 when the DATA signal DQ including the DATA is received from the memory controller 910. The memory I/F circuit 921 may obtain the DATA from the DATA signal DQ based on the switching timing of the DATA strobe signal DQS. For example, the memory I/F circuit 921 may obtain the DATA by sampling the DATA signal DQ at the rising and falling edges of the DATA strobe signal DQS.

The memory I/F circuit 921 may send the ready/busy output signal nR/B to the memory controller 910 through the eighth pin P18. The memory I/F circuit 921 may send status information of the memory device 920 to the memory controller 910 through the ready/busy output signal nR/B. When the memory device 920 is in a busy state (i.e., when an internal operation of the memory device 920 is being performed), the memory I/F circuit 921 may send a ready/busy output signal nR/B indicating the busy state to the memory controller 910. When the memory device 920 is in a ready state (i.e., when internal operations of the memory device 920 are not performed or have been completed), the memory I/F circuit 921 may send a ready/busy output signal nR/B representing the ready state to the memory controller 910. For example, when the memory device 920 reads DATA from the memory cell array 925 in response to a page read command, the memory I/F circuit 921 may send a ready/busy output signal nR/B indicating a busy state (e.g., low level) to the memory controller 910. For example, when the memory device 920 programs DATA to the memory cell array 925 in response to a program command, the memory I/F circuit 921 may send a ready/busy output signal nR/B indicating a busy state to the memory controller 910.

The control logic circuit 923 may control various overall operations of the memory device 920. The control logic circuit 923 may receive the obtained command CMD/address ADDR from the memory I/F circuit 921. Control logic 923 may generate control signals to control the other components of memory device 920 in accordance with the received command CMD/address ADDR. For example, the control logic circuit 923 may generate various control signals for programming DATA to the memory cell array 925 or reading DATA from the memory cell array 925.

The memory cell array 925 can store DATA obtained from the memory I/F circuit 921 under the control of the control logic circuit 923. The memory cell array 925 can output the stored DATA to the memory I/F circuit 921 under the control of the control logic circuit 923. The memory controller 910 may include first to eighth pins P21 to P28 and a controller I/F circuit 911. The first to eighth pins P21 to P28 may correspond to the first to eighth pins P11 to P18 of the memory device 920.

The controller I/F circuit 911 may transmit the chip enable signal nCE to the memory controller 920 through the first pin P21. The controller I/F911 may transmit a signal to the memory device 920 selected by the chip enable signal nCE through the second through eighth pins P22 through P28 or receive a signal from the memory device 920.

The controller I/F circuit 911 may transmit the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device 920 through the second pin P22 to the fourth pin P24, respectively. The controller I/F circuit 911 may transmit a data signal DQ to the memory device 920 or receive the data signal DQ from the memory device 920 through the seventh pin P27.

The controller I/F circuit 911 may transmit a data signal DQ including a command CMD or an address ADDR to the memory device 920 together with the switched write enable signal nWE. The controller I/F circuit 911 may transmit a data signal DQ including a command CMD to the memory device 920 while transmitting a command latch enable signal CLE having an enable state, and may transmit a data signal DQ including an address ADDR to the memory device 920 while transmitting an address latch enable signal ALE having an enable state.

The controller I/F circuit 911 may send the read enable signal nRE to the memory device 920 through the fifth pin P25. The controller I/F circuit 911 may receive the data strobe signal DQS from the memory device 920 or transmit the data strobe signal DQS to the memory device 920 through the sixth pin P26.

In an operation of outputting the DATA of the memory device 920, the controller I/F circuit 911 may generate the switched read enable signal nRE and may transmit the read enable signal nRE to the memory device 920. For example, the controller I/F circuit 911 may generate the read enable signal nRE changing from a static state (e.g., high level or low level) to a switching state before outputting the DATA. Accordingly, the data strobe signal DQS may be generated in the memory device 920 to be toggled based on the read enable signal nRE. The controller I/F circuit 911 may receive a DATA signal DQ including DATA and a toggled DATA strobe signal DQs from the memory device 920. The controller I/F circuit 911 may obtain DATA from the DATA signal DQ based on the switching timing of the DATA strobe signal DQS.

In the operation of inputting the DATA of the memory device 920, the controller I/F911 may generate the toggled DATA strobe signal DQS. For example, the controller I/F circuit 911 may generate the DATA strobe signal DQS changing from a static state (e.g., high level or low level) to a toggle state before outputting the DATA. The controller I/F circuit 911 may transmit a DATA signal DQ including DATA to the memory device 920 based on the switching timing of the DATA strobe signal DQS.

The controller I/F circuit 911 may receive the ready/busy output signal nR/B from the memory device 920 through the eighth pin P28. The controller I/F circuit 911 may determine the state information of the memory device 920 based on the ready/busy output signal nR/B.

Fig. 17 is a block diagram of a memory device 600 according to an embodiment of the inventive concept. Referring to fig. 17, the memory device 600 may include a control logic circuit 620, a memory cell array 630, a page buffer unit 640, a voltage generator 650, and a row decoder 660. Although not shown in fig. 17, the memory device 600 may further include the memory I/F circuit 921 of fig. 16, and may further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like. According to an embodiment of the inventive concept, the memory device 600 may correspond to the memory device described above with reference to fig. 1 to 16.

The control logic 620 may control various overall operations of the memory device 600. The control logic circuit 620 may output various control signals in response to a command CMD and/or an address ADDR from the memory I/F circuit 921. For example, the control logic 620 may output voltage control signals CTRL _ vol, row addresses X ADDR, and column addresses Y ADDR.

The memory cell array 630 may include a plurality of memory blocks BLK1 through BLKz (where z is a positive integer), and each of the plurality of memory blocks BLK1 through BLKz may include a plurality of memory cells. The memory cell array 630 may be connected to the page buffer unit 640 via bit lines BL, and may be connected to the row decoder 660 via word lines WL, string select lines SSL, and ground select lines GSL.

According to an embodiment, the memory cell array 630 may include a three-dimensional (3D) memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. According to an embodiment, the memory cell array 630 may include a two-dimensional (2D) memory cell array, and the 2D memory cell array may include a plurality of NAND strings arranged in a column direction and a row direction.

The page buffer unit 640 may include a plurality of page buffers PB1 through PBn (where n is an integer equal to or greater than 3), and the plurality of page buffers PB1 through PBn may be connected to the memory cells via a plurality of bit lines BL, respectively. The page buffer unit 640 may select at least one bit line from the plurality of bit lines BL in response to the column address Y-ADDR. The page buffer circuit 640 may operate as a write driver or a sense amplifier according to an operation mode. For example, during a program operation, the page buffer circuit 640 may apply a bit line voltage corresponding to data to be programmed to a selected bit line. During a read operation, the page buffer circuit 640 may sense a current or voltage of a selected bit line to sense data stored in the memory cell. In alternative embodiments, the page buffer unit 640 may include fewer page buffers.

The voltage generator 650 may generate various types of voltages for performing program, read, and erase operations based on the voltage control signal CTRL _ vol. For example, the voltage generator 650 may generate a word line voltage VWL (e.g., a program voltage, a read voltage, a program verify voltage, and an erase voltage).

The row decoder 660 may select one word line from a plurality of word lines WL in response to a row address X-ADDR, and may select one string selection line from a plurality of string selection lines SSL. For example, during a program operation, the row decoder 660 may apply a program voltage and a program verify voltage to a selected word line, and during a read operation, the row decoder 660 may apply a read voltage to a selected word line.

Fig. 18 is a view for explaining a 3D V-NAND structure according to an embodiment of the inventive concept. When the memory device described above with reference to fig. 1 to 17 is implemented using a 3D V-NAND-type flash memory, each of a plurality of memory blocks included in the memory device may be represented as an equivalent circuit as shown in fig. 18.

The memory block BLKi of fig. 18 represents a 3D memory block formed on a substrate to have a 3D structure. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate (where i is a positive integer).

Referring to fig. 18, the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the plurality of memory NAND strings NS11 through NS33 may include a string selection transistor SST, a plurality of memory cells MC1, MC2 through MC8, and a ground selection transistor GST. Although each of the plurality of memory NAND strings NS11 through NS33 includes eight memory cells MC1, MC2 through MC8 in fig. 18, the embodiment is not limited thereto.

The string selection transistor SST may be connected to a corresponding one of string selection lines SSL1, SSL2, and SSL 3. The plurality of memory cells MC1, MC2 to MC8 may be connected to the gate lines, respectively. The gate lines may correspond to word lines, and some of the gate lines may correspond to dummy word lines. The ground selection transistor GST may be connected to a corresponding one of ground selection lines GSL1, GSL2, and GSL 3. The string selection transistor SST may be connected to a corresponding one of the bit lines BL1, BL2, and BL3, and the ground selection transistor GST may be connected to the common source line CSL.

A plurality of word lines (e.g., WL1) on the same level may be commonly connected to each other, and the ground select lines GSL1, GSL2, and GSL3 and the string select lines SSL1, SSL2, and SSL3 may be separated from each other. Although the memory block BLKi is connected to eight gate lines and three bit lines BL1, BL2, and BL3 in fig. 18, the embodiment is not limited thereto.

Fig. 19 is a view for explaining a BVNAND structure according to an embodiment of the inventive concept. Referring to fig. 19, the memory device 1200 may be a chip-to-chip (C2C) structure. The C2C structure may mean that an upper chip including a CELL region CELL is fabricated on a first wafer, a lower chip including a peripheral circuit region PERI is fabricated on a second wafer, and then the upper chip is connected to the lower chip by bonding. For example, bonding may refer to a method of electrically connecting a bonding metal formed on a topmost metal layer of an upper chip to a bonding metal formed on a topmost metal layer of a lower chip. For example, when the bonding metal is formed of copper (Cu), the bond may be a Cu-Cu bond, and the bonding metal may be formed of aluminum or tungsten. At least one of the memory devices described above with reference to fig. 1-17 may be implemented with the C2C structure of fig. 19.

Each of the peripheral circuit region PERI and the CELL region CELL of the memory device 1200 may include an external pad (pad) bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

The peripheral circuit region PERI may include a first substrate 1210, an interlayer insulating layer 1215, a plurality of circuit devices 1220a, 1220b, and 1220c formed on the first substrate 1210, first metal layers 1230a, 1230b, and 1230c connected to the plurality of circuit devices 1220a, 1220b, and 1220c, respectively, and second metal layers 1240a, 1240b, and 1240c formed on the first metal layers 1230a, 1230b, and 1230 c. According to an embodiment, the first metal layers 1230a, 1230b, and 1230c may be formed of tungsten having a relatively high resistance, and the second metal layers 1240a, 1240b, and 1240c may be formed of copper having a relatively low resistance.

In this specification, only the first metal layers 1230a, 1230b, and 1230c and the second metal layers 1240a, 1240b, and 1240c are shown and described. However, the embodiment is not limited thereto, and one or more metal layers may be further formed on the second metal layers 1240a, 1240b, and 1240 c. At least some of the one or more metal layers formed over the second metal layers 1240a, 1240b, and 1240c may be formed of copper or the like having a lower resistance than the aluminum used to form the second metal layers 1240a, 1240b, and 1240 c.

An interlayer insulating layer 1215 may be disposed on the first substrate 1210 to cover the plurality of circuit devices 1220a, 1220b, and 1220c, the first metal layers 1230a, 1230b, and 1230c, and the second metal layers 1240a, 1240b, and 1240c, and may include an insulating material such as silicon oxide or silicon nitride.

The lower bonding metals 1271b and 1272b may be formed on the second metal layer 1240b of the word line bonding area WLBA. In the word line bonding region WLBA, the lower bonding metals 1271b and 1272b of the peripheral circuit region PERI may be electrically connected to the upper bonding metals 1371b and 1372b of the CELL region CELL via bonding, and the lower bonding metals 1271b and 1272b and the upper bonding metals 1371b and 1372b may be formed of aluminum, copper, tungsten, or the like.

The CELL region CELL may provide at least one memory block. The CELL region CELL may include a second substrate 1310 and a common source line 1320. On the second substrate 1310, a plurality of word lines 1331-1338 (1330) may be stacked in a direction (Z-axis direction) perpendicular to the upper surface of the second substrate 1310. A string selection line and a ground selection line may be disposed above and below the plurality of word lines 1330, respectively, and the plurality of word lines 1330 may be disposed between the string selection line and the ground selection line.

In the bit line bonding area BLBA, the channel structure CH may extend in a direction perpendicular to the upper surface of the second substrate 1310, and may penetrate the word line 1330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulation layer, and the channel layer may be electrically connected to the first and second metal layers 1350c and 1360 c. For example, first metal layer 1350c may be a bit line contact and second metal layer 1360c may be a bit line 1360 c. According to an embodiment, the bit line 1360c may extend in a first direction (Y-axis direction) parallel to an upper surface of the second substrate 1310.

According to the embodiment of fig. 19, a region where the channel structure CH, the bit line 1360c, and the like are arranged may be defined as a bit line bonding region BLBA. Bit line 1360c may be electrically connected to circuit device 1220c, which provides page buffer 1393 in peripheral circuit region PERI in bit line bonding region BLBA. For example, the bit line 1360c may be connected to upper bonding metals 1371c and 1372c in the peripheral circuit region PERI, and the upper bonding metals 1371c and 1372c may be connected to lower bonding metals 1271c and 1272c, and the lower bonding metals 1271c and 1272c are connected to the circuit device 1220c of the page buffer 1393.

In the word line bonding area WLBA, the word lines 1330 may each extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 1310, and may be connected to a plurality of cell contact plugs 1341 to 1347 (1340). The word lines 1330 may be connected to the cell contact plugs 1340 in the pads, wherein at least some of the word lines 1330 extend and are disposed at different lengths in the second direction. The first and second metal layers 1350b and 1360b may be sequentially connected to the upper end of the cell contact plug 1340 connected to the wordline 1330. In the word line bonding region WLBA, the CELL contact plug 1340 may be connected to the peripheral circuit region PERI through the upper bonding metals 1371b and 1372b of the CELL region CELL and the lower bonding metals 1271b and 1272b of the peripheral circuit region PERI.

The cell contact plug 1340 may be electrically connected to the circuit device 1220b, and the circuit device 1220b provides the row decoder 1394 in the peripheral circuit region PERI. According to an embodiment, an operating voltage of the circuit device 1220b providing the row decoder 1394 may be different from an operating voltage of the circuit device 1220c providing the page buffer 1393. For example, the operating voltage of the circuit device 1220c providing the page buffer 1393 may be greater than the operating voltage of the circuit device 1220b providing the row decoder 1394.

In the outer pad bonding region PA, a common source line contact plug 1380 may be disposed. The common source line contact plug 1380 may be formed of a conductive material, such as a metal, a metal compound, or polysilicon, and may be electrically connected to the common source line 1320. A first metal layer 1350a and a second metal layer 1360a may be sequentially stacked over the common source line contact plug 1380. For example, a region where the common-source line contact plug 1380, the first metal layer 1350a, and the second metal layer 1360a are arranged may be defined as the outer pad bonding region PA.

In the outer pad bonding area PA, a first I/O pad 1205 and a second I/O pad 1305 may be arranged. Referring to fig. 19, a lower insulating layer 1201 covering a lower surface of a first substrate 1210 may be formed under the first substrate 1210, and a first I/O pad 1205 may be formed on the lower insulating layer 1201. The first I/O pad 1205 may be connected to at least one of the plurality of circuit devices 1220a, 1220b, and 1220c disposed in the peripheral circuit region PERI through a first I/O contact plug 1203, and may be separated from the first substrate 1210 by the lower insulating layer 1201. The lateral surface insulating layer may be disposed between the first I/O contact plug 1203 and the first substrate 1210, and may electrically separate the first I/O contact plug 1203 from the first substrate 1210.

Referring to fig. 19, an upper insulating layer 1301 covering an upper surface of a second substrate 1310 may be formed over the second substrate 1310, and a second I/O pad 1305 may be disposed on the upper insulating layer 1301. The second I/O pad 1305 may be connected to at least one of the plurality of circuit devices 1220a, 1220b, and 1220c arranged in the peripheral circuit region PERI through the second I/O contact plug 1303. For example, referring to fig. 19, lower bonding metals 1271a and 1272a may be disposed on a second metal layer 1240a connected to the circuit device 1220a via a first metal layer 1230a, and a second input-output contact plug 1303 connected to the second input-output pad 1305 may be electrically connected to the lower bonding metals 1271a and 1272a via an upper metal pattern disposed in an uppermost metal layer of the CELL region CELL, and thus connected to the circuit device 1220a, for example.

According to an embodiment, the second substrate 1310, the common source line 1320, and the like are not disposed in a region where the second I/O contact plug 1303 is disposed. In one embodiment, the second I/O pad 1305 does not overlap the word line 1330 in the third direction (the Z-axis direction). Referring to fig. 19, the second I/O contact plug 1303 may be separated from the second substrate 1310 in a direction parallel to the upper surface of the second substrate 1310, and may be connected to the second I/O pad 1305 by an interlayer insulating layer 1315 penetrating the CELL region CELL.

According to an embodiment, the first I/O pad 1205 and the second I/O pad 1305 may be selectively formed. For example, the memory device 1200 may include only a first I/O pad 1205 disposed over the first substrate 1201, or may include only a second I/O pad 1305 disposed over the second substrate 1301. Alternatively, the memory device 1200 may include both the first I/O pad 1205 and the second I/O pad 1305.

In the outer pad bonding area PA and the bit line bonding area BLBA included in each of the CELL area CELL and the peripheral circuit area PERI, the metal pattern of the topmost metal layer may exist as a dummy pattern, or the topmost metal layer may be empty.

In the outer pad bonding region PA, the memory device 1200 may form a lower metal pattern 1273a on the topmost metal layer of the peripheral circuit region PERI corresponding to an upper metal pattern 1372a formed on the topmost metal layer of the CELL region CELL, the lower metal pattern 1273a having the same shape as the upper metal pattern 1372a of the CELL region CELL. In one embodiment, the lower metal patterns 1273a formed in the topmost metal layer of the peripheral circuit region PERI are not connected to separate contacts in the peripheral circuit region PERI. Similarly, in the outer pad bonding region PA, the memory device 1200 may form an upper metal pattern on the topmost metal layer of the CELL region CELL, corresponding to a lower metal pattern formed on the topmost metal layer of the peripheral circuit region PERI, the upper metal pattern having the same shape as the lower metal pattern of the peripheral circuit region PERI. In the outer pad bonding region PA, a contact 1371a may be disposed on the upper metal pattern 1372a, and the upper metal pattern 1372a may be electrically connected to the common source line contact plug 1380 via the contact 1371a, a portion of the second metal layer 1360a, and a portion of the first metal layer 1350 a.

The lower bonding metals 1271b and 1272b may be formed on the second metal layer 1240b of the word line bonding area WLBA. In the word line bonding region WLBA, the lower bonding metals 1271b and 1272b of the peripheral circuit region PERI may be electrically connected to the upper bonding metals 1371b and 1372b of the CELL region CELL via bonding.

In the bit line bonding region BLBA, the memory device 1200 may form an upper metal pattern 1392 on the topmost metal layer of the CELL region CELL corresponding to the lower metal pattern 1252 formed on the topmost metal layer of the peripheral circuit region PERI, the upper metal pattern 1392 having the same shape as the lower metal pattern 1252 of the peripheral circuit region PERI. In one exemplary embodiment, no contact is formed on the upper metal pattern 1392 formed on the topmost metal layer of the CELL region CELL. In the bit line bonding area BLBA, a contact 1251 may be disposed on the lower metal pattern 1252, and the lower metal pattern 1252 may be connected to at least a portion of the second metal layer 1240c of the peripheral circuit area PERI through the contact 1251.

Fig. 20 is a block diagram of a system 2000 to which a storage device is applied according to an embodiment of the inventive concept. The system 2000 of fig. 20 may be, for example, a mobile system, such as a mobile phone, a smartphone, a tablet Personal Computer (PC), a wearable device, a healthcare device, or an internet of things (IOT) device. However, the system 2000 of fig. 20 is not limited to a mobile system, but may be a PC, laptop, server, media player, or automotive device (such as a navigation device).

Referring to fig. 20, the system 2000 may include a main processor 2100, memories 2200a and 2200b, and storage devices 2300a and 2300b, and may further include one or more of an image capture device (or optical input device) 2410, a user input device 2420, a sensor 2430, a communication device 2440, a display 2450, a speaker 2460, a power supply device 2470, and a connection interface 2480.

The main processor 2100 may control the overall operation of the system 2000, and more particularly, may control the operation of other components of the system 2000. The main processor 2100 may be implemented using a general purpose processor, a special purpose processor, an Application Processor (AP), or the like.

The main processor 2100 may include one or more CPU cores 2110 and may further include a controller 2120 for controlling the memories 2200a and 2200b and/or the storage devices 2300a and 2300 b. According to an embodiment, host processor 2100 may also include accelerator 2130 as a dedicated circuit for performing high-speed data operations, such as Artificial Intelligence (AI) data operations. Accelerators 2130 may include a Graphics Processor (GPU), a Neural Processor (NPU), and/or a Data Processor (DPU), and may be implemented using separate chips that are physically separate from other components of host processor 2100.

The memories 2200a and 2200b may be used as the main memory device of the system 2000, and may each include a nonvolatile memory (such as SRAM and/or DRAM), but may also include a nonvolatile memory such as flash memory, PRAM, and/or RRAM. The memories 2200a and 2200b may be implemented in the same package as the main processor 2100.

The memory devices 2300a and 2300b may be used as nonvolatile memory devices that store data regardless of whether power is supplied. The memory devices 2300a and 2300b may include memory controllers 2310a and 2310b, respectively, and nonvolatile memory (NVM) storage devices (or flash memories) 2320a and 2320b, respectively, which store data under the control of the memory controllers 2310a and 2310b, respectively.

For example, each of the memory controllers 2310a and 2310b may correspond to the memory controllers described above with reference to fig. 1-19, and each of the NVM storage devices 2320a and 2320b may correspond to the memory devices described above with reference to fig. 1-19. For example, each of the memory controllers 2310a and 2310b may include a channel arbitration module, and may support a function of arbitrating a plurality of channels connected to each of the NVM storage devices 2320a and 2320b by using the channel arbitration module. A detailed description thereof may be substantially the same as that given above with reference to fig. 1 to 19, and thus will be omitted.

Storage devices 2300a and 2300b may be included in system 2000 while being physically separate from main processor 2100 and may be implemented within the same package as main processor 2100. The memory devices 2300a and 2300b may be of a type such as a memory card so as to be detachably combined with other components of the system 2000 through an interface such as a connection interface 2480, which will be described later. Each of the storage devices 2300a and 2300b may be a device applying a standard rule, such as a universal flash memory (UFS), but the embodiment is not limited thereto.

The image capture device 2410 may capture still images or moving pictures and may be a camera, a video camera, and/or a webcam.

The user input device 2420 may receive various types of data input by a user of the system 2000 and may be a touch pad, keypad, keyboard, mouse, and/or microphone.

The sensor 2430 may sense various types of physical quantities available from outside the system 2000 and convert the sensed physical quantities into electrical signals. The sensor 2430 may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope.

The communication device 2440 may send and receive signals to and from other devices external to the system 2000 according to various communication protocols. The communication device 2440 may be implemented by including an antenna, a transceiver, and/or a modem.

The display 2450 and speaker 2460 may serve as output devices that output visual and audible information, respectively, to a user of the system 2000.

The power supply device 2470 may appropriately convert power supplied from a battery (not shown) built in the system 2000 and/or an external power source and supply the converted power to each component of the system 2000.

Connection interface 2480 may provide a connection between system 2000 and external devices connected to system 2000 and capable of exchanging data with system 2000. The connection interface 2480 may be implemented as various interface types (such as Advanced Technology Attachment (ATA), serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), serial attached SCSI (sas), Peripheral Component Interconnect (PCI), PCI express (PCIe), NVM express (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, multimedia card (MMC), embedded multimedia card (eMMC), Universal Flash (UFS), embedded universal flash (eUFS), and Compact Flash (CF) card interfaces).

Fig. 21 is a block diagram for explaining UFS system 3000 according to an embodiment of the inventive concept. The UFS system 3000 may be a system complying with the UFS standard issued by Joint Electron Device Engineering Council (JEDEC), and thus may include a UFS host 3100, a UFS device 3200, and a UFS I/F3300. The description of system 2000 of fig. 20 given above applies to UFS system 3000 of fig. 21 without conflicting with the following description of fig. 21.

Referring to fig. 21, UFS host 3100 and UFS device 3200 may be connected to each other via UFS I/F3300. When main processor 2100 of fig. 20 is an AP, UFS host 3100 may be implemented as part of the AP. The UFS host controller 3110 and the host memory 3140 may correspond to the controller 2120 of the main processor 2100 of fig. 20 and the memories 2200a and 2200b of fig. 20, respectively. The UFS device 3200 may correspond to the storage devices 2300a and 2300b of fig. 20, and the UFS device controller 3210 and the NVM storage device 3220 may correspond to the storage controllers 2310a and 2310b and the NVM storage devices 2320a and 2320b of fig. 20, respectively.

UFS host 3100 may include a UFS host controller 3110, applications 3120, UFS driver 3130, host memory 3140, and a UFS Interconnect (UIC) layer 3150. UFS device 3200 may include UFS device controller 3210, NVM storage 3220, storage I/F3230, device memory 3240, UIC layer 3250, and regulator 3260. The UFS device controller 3210 and the NVM storage 3220 may be connected to each other via a storage device I/F3230. The storage device I/F3230 may be implemented to conform to a standard protocol such as toggle or ONFI.

Application 3120 may represent a program that desires to communicate with UFS device 3200 in order to use the functionality of UFS device 3200. Application 3120 may send an input-output request (IOR) to UFS driver 3130 to complete input and output with respect to UFS device 3200. The IOR may represent a request to read data, a request to write data, and/or a request to discard data, but is not limited thereto.

The UFS driver 3130 may manage the UFS host controller 3110 through UFS-HCI (host controller interface). The UFS driver 3130 may convert IORs generated by the application 3120 into UFS commands defined in the UFS standard, and may send the UFS commands to the UFS host controller 3110. One IOR may be converted into multiple UFS commands. The UFS command may be basically a command defined by the SCSI standard, but may also be a command specific to the UFS standard.

UFS host controller 3110 may send UFS commands obtained by UFS driver 3130 through UIC layer 3150 and UFS I/F3300 to UIC layer 3250 of UFS device 3200. In this process, the UFS host register 3111 of the UFS host controller 3110 may function as a Command Queue (CQ).

UIC layer 3150 on UFS host 3100 side may include MIPI M-PHY 3151 and MIPI UniPro3152, and UIC layer 3250 on UFS device 3200 side may include MIPI M-PHY 3251 and MIPI UniPro 3252.

UFS I/F3300 may include a line for conveying a reference clock, REF _ CLK, a line for conveying a hardware RESET signal, RESET _ n, of UFS device 3200, a pair of lines for conveying a pair of differential input signals, DIN _ T and DIN _ C, and a pair of lines for conveying a pair of differential output signals, DOUT _ T and DOUT _ C.

The UFS device 3200 may generate clocks of various frequencies from a reference clock received from the UFS host 3100 by using a phase-locked loop (PLL) or the like. The UFS host 3100 may set a value of a data rate between the UFS host 3100 and the UFS device 3200 by referring to a frequency value of the clock REF _ CLK. In other words, the value of the data rate may depend on the frequency value of the reference clock REF _ CLK.

UFS I/F3300 may support multiple lanes (lanes), and each of the multiple lanes may be implemented as a differential pair. For example, in fig. 21, a pair of lines for transmitting two differential input signals DIN _ T and DIN _ C may constitute a receive path, and a pair of lines for transmitting two differential output signals DOUT _ T and DOUT _ C may constitute a transmit path. Although one transmission path and one reception path are shown in fig. 21, the number of transmission paths and the number of reception paths may vary.

The reception path and the transmission path may transmit data in a serial communication method, and a structure in which the reception path and the transmission path are separated from each other enables full-duplex type communication between the UFS host 3100 and the UFS device 3200. In other words, the UFS device 3200 may send data to the UFS host 3100 through a sending path while receiving data from the UFS host 3100 through a receiving path. Control data (such as commands from the UFS host 3100 to the UFS device 3200) and user data that the UFS host 3100 desires to store in the NVM storage 3220 of the UFS device 3200 or read from the NVM storage 3220 may be sent to the same path.

The UFS device controller 3210 of the UFS device 3200 may control the overall operation of the UFS device 3200. The UFS device controller 3210 may manage the NVM storage 3220 through a Logical Unit (LU)3211 as a logical data storage unit. The number of LUs 3211 may be, but is not limited to, eight. The UFS device controller 3210 may include a flash translation layer.

When a command from the UFS host 3100 is input to the UFS device 3200 through the UIC layer 3250, the UFS device controller 3210 may perform an operation according to the input command, and when the operation is completed, the UFS device controller 3210 may send a completion response to the UFS host 3100.

For example, when UFS host 3100 desires to store user data in UFS device 3200, UFS host 3100 may send a data storage command to UFS device 3200. When UFS host 3100 receives a response from UFS device 3200 indicating that UFS device 3200 is ready to transfer user data, UFS host 3100 may send the user data to UFS device 3200. The UFS device controller 3210 may temporarily store the received user data in the device memory 3240, and may store the user data temporarily stored in the device memory 3240 in a selected location of the NVM storage 3220 based on address mapping information of the FTL.

As another example, when UFS host 3100 intends to read user data from UFS device 3200, UFS host 3100 may send a data read command to UFS device 3200. The UFS device controller 3210 may read user data from the NVM storage 3220 based on the data read command, and may temporarily store the read user data in the device memory 3240. In this reading process, the UFS device controller 3210 may detect and correct errors of the read user data by using an embedded ECC circuit (not shown). The UFS device controller 3210 may send user data temporarily stored in the device memory 3240 to the UFS host 3100. The UFS device controller 3210 may further include an AES circuit (not shown).

The UFS host 3100 may sequentially store commands to be sent to the UFS device 3200 in a UFS host register 3111 that can serve as a command queue, and sequentially send the commands to the UFS device 3200. At this time, even when a previously sent command is still being processed by the UFS device 3200 (i.e., even before being notified that the previously sent command has been completely processed by the UFS device 3200), the UFS host 3100 can send a command waiting on the command queue to the UFS device 3200, and accordingly, the UFS device 3200 can receive the next command from the UFS host 3100 even while processing the previously sent command.

A power supply voltage such as VCC, VCCQ1, or VCCQ2 may be input to UFS device 3200. VCC is a main power supply voltage of the UFS device 3200, VCCQ1 is a power supply voltage for supplying a low range of voltage and is mainly used for the UFS device controller 321, and VCCQ2 is a power supply voltage for supplying a voltage lower than VCC and higher than the range of VCCQ1 and is mainly used for an I/O interface (such as MIPI M-PHY 3251). The power supply voltage may be supplied to the components of UFS device 3200 through regulator 3260. The regulator 3260 may be implemented as a set of unit regulators respectively connected to different ones of the power supply voltages described above.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure.