阅读说明：本技术 半导体存储装置 (Semiconductor memory device with a plurality of memory cells ) 是由 前嶋洋 于 2020-08-18 设计创作，主要内容包括：实施方式提供一种能够抑制消耗电力的半导体存储装置。实施方式的半导体存储装置具备存储器部及电路部。存储器部包含：第1及第2存储单元；第1字线,在第1方向上延伸,连接于第1存储单元的栅极；第2字线,在第1方向上延伸,连接于第2存储单元的栅极；第1位线,在与第1方向不同的第2方向上延伸,连接于第1存储单元；第2位线,在第2方向上延伸,连接于第2存储单元；第1接合金属,相对于第1位线位于与第1及第2方向不同的第3方向上的一侧,连接于第1位线；以及第2接合金属,相对于第2位线位于第3方向上的一侧,连接于第2位线。电路部包含：第1及第2感测放大器；第1锁存电路；第1配线,连接于第1感测放大器、第2感测放大器及第1锁存电路；第3接合金属,相对于第1感测放大器位于第3方向上的另一侧,与第1感测放大器连接,且与第1接合金属对向接合；以及第4接合金属,相对于第2感测放大器位于第3方向上的另一侧,与第2感测放大器连接,且与第2接合金属对向接合。(Embodiments provide a semiconductor memory device capable of suppressing power consumption. A semiconductor memory device according to an embodiment includes a memory unit and a circuit unit. The memory section includes: 1 st and 2 nd memory cells; a1 st word line extending in a1 st direction and connected to a gate of the 1 st memory cell; a2 nd word line extending in the 1 st direction and connected to the gate of the 2 nd memory cell; a1 st bit line extending in a2 nd direction different from the 1 st direction and connected to the 1 st memory cell; a2 nd bit line extending in the 2 nd direction and connected to the 2 nd memory cell; a1 st bonding metal located on one side of the 1 st bit line in a 3 rd direction different from the 1 st and 2 nd directions and connected to the 1 st bit line; and a2 nd bonding metal connected to the 2 nd bit line on the 3 rd direction side with respect to the 2 nd bit line. The circuit part includes: 1 st and 2 nd sense amplifiers; a1 st latch circuit; a1 st wiring connected to the 1 st sense amplifier, the 2 nd sense amplifier, and the 1 st latch circuit; a 3 rd bonding metal located on the other side in the 3 rd direction with respect to the 1 st sense amplifier, connected to the 1 st sense amplifier, and bonded to the 1 st bonding metal in an opposite direction; and a 4 th bonding metal located on the other side in the 3 rd direction with respect to the 2 nd sense amplifier, connected to the 2 nd sense amplifier, and bonded to the 2 nd bonding metal in an opposed manner.)

1. A semiconductor memory device, characterized by comprising: a memory part and a circuit part, wherein,

the memory section includes:

a1 st storage unit;

a2 nd storage unit;

a1 st word line extending in a1 st direction and connected to a gate of the 1 st memory cell;

a2 nd word line extending in the 1 st direction and connected to a gate of the 2 nd memory cell;

a1 st bit line extending in a2 nd direction different from the 1 st direction and connected to the 1 st memory cell;

a2 nd bit line extending in the 2 nd direction and connected to the 2 nd memory cell;

a1 st bonding metal located on one side of the 1 st bit line in a 3 rd direction different from the 1 st direction and the 2 nd direction, and connected to the 1 st bit line; and

a2 nd bonding metal located on the one side in the 3 rd direction with respect to the 2 nd bit line, connected to the 2 nd bit line; and is

The circuit section includes:

1 st sense amplifier;

a2 nd sense amplifier;

a1 st latch circuit;

a1 st wiring connected to the 1 st sense amplifier, the 2 nd sense amplifier, and the 1 st latch circuit;

a 3 rd bonding metal located on the other side in the 3 rd direction with respect to the 1 st sense amplifier, connected to the 1 st sense amplifier, and bonded to the 1 st bonding metal in an opposing manner; and

a 4 th bonding metal located on the other side in the 3 rd direction with respect to the 2 nd sense amplifier, connected to the 2 nd sense amplifier, and bonded to the 2 nd bonding metal in an opposing manner.

2. The semiconductor memory device according to claim 1, wherein: the 1 st bit line and the 2 nd bit line overlap when viewed from the 2 nd direction.

3. The semiconductor memory device according to claim 2, wherein:

the circuit section further includes:

an input-output circuit; and

and the output circuit is connected between the input-output circuit and the 1 st latch circuit.

4. The semiconductor memory device according to claim 3, wherein:

the circuit section further includes:

a1 st row decoder connected to the 1 st word line;

a2 nd row decoder connected to the 2 nd word line;

a signal line connected to the row 1 decoder and the row 2 decoder; and

and a drive circuit for supplying a voltage to the signal line.

5. The semiconductor memory device according to claim 1, wherein:

the circuit unit further includes a2 nd latch circuit connected to the 1 st wiring,

the 2 nd latch circuit is common to the 1 st and 2 nd sense amplifiers.

6. The semiconductor memory device according to claim 1, wherein:

the memory section further includes:

a 3 rd storage unit;

a 3 rd word line extending in the 1 st direction and connected to a gate of the 3 rd memory cell;

a 3 rd bit line extending in the 2 nd direction and connected to the 3 rd memory cell; and

a 5 th bonding metal located on the one side in the 3 rd direction with respect to the 3 rd bit line, connected to the 3 rd bit line; and is

The circuit section further includes:

a 3 rd sense amplifier unit connected to the 1 st wiring; and

and a 6 th bonding metal located on the other side in the 3 rd direction with respect to the 3 rd sense amplifier, connected to the 3 rd sense amplifier, and bonded to the 5 th bonding metal in an opposite direction.

7. The semiconductor memory device according to claim 1, wherein:

the 1 st word line is laminated in the 3 rd direction,

the 2 nd word line is laminated in the 3 rd direction,

the memory section further includes:

a1 st pillar extending in the 3 rd direction and penetrating the 1 st word lines; and

a2 nd pillar extending in the 3 rd direction and penetrating the plurality of 2 nd word lines;

the 1 st pillar and the 1 st word lines respectively function as the 1 st memory cell,

the 2 nd pillars and the intersections of the plurality of 2 nd word lines function as the 2 nd memory cells,

the 1 st bonding metal, the 2 nd bonding metal, the 3 rd bonding metal and the 4 th bonding metal respectively include copper.

8. A semiconductor memory device, characterized by comprising: a memory part and a circuit part, wherein,

the memory section includes:

a1 st storage unit;

a2 nd storage unit;

a1 st word line extending in a1 st direction and connected to a gate of the 1 st memory cell;

a2 nd word line extending in the 1 st direction and connected to a gate of the 2 nd memory cell;

a1 st bit line extending in a2 nd direction different from the 1 st direction and connected to the 1 st memory cell;

a2 nd bit line extending in the 2 nd direction and connected to the 2 nd memory cell;

a1 st bonding metal located on one side of the 1 st bit line in a 3 rd direction different from the 1 st direction and the 2 nd direction, and connected to the 1 st bit line; and

a2 nd bonding metal located on the one side in the 3 rd direction with respect to the 2 nd bit line, connected to the 2 nd bit line; and is

The circuit section includes:

1 st sense amplifier;

1 st local amplification part;

a2 nd local amplification part;

a global bit line connected to each of the 1 st sense amplifier, the 1 st local amplification block, and the 2 nd local amplification block;

a 3 rd bonding metal which is located on the other side in the 3 rd direction from the 1 st local amplification part, is connected to the 1 st local amplification part, and is bonded to the 1 st bonding metal in an opposed manner; and

and a 4 th bonding metal which is located on the other side in the 3 rd direction with respect to the 2 nd local amplification part, is connected to the 2 nd local amplification part, and is bonded to the 2 nd bonding metal in an opposed manner.

9. The semiconductor memory device according to claim 8, wherein:

the 1 st local amplification part includes:

a1 st transistor connected between the 1 st bit line and the global bit line; and

a2 nd transistor connected between the global bit line and a ground line, and having a gate connected to a1 st node between the 1 st bit line and the 1 st transistor;

the 2 nd local amplification part includes:

a 3 rd transistor connected between the 2 nd bit line and the global bit line; and

a 4 th transistor connected between the global bit line and a ground line, and having a gate connected to a2 nd node between the 2 nd bit line and the 3 rd transistor.

10. The semiconductor memory device according to claim 9, wherein:

the circuit part further includes a controller for executing a read operation,

the 1 st local amplification part further comprises a 5 th transistor connected to the 1 st node,

the 2 nd local amplification part further includes a 6 th transistor connected to the 2 nd node,

in a read operation in which the 1 st memory cell is selected, the controller applies a ground voltage to the 2 nd bit line via the 6 th transistor,

in a read operation in which the 2 nd memory cell is selected, the controller applies the ground voltage to the 1 st bit line via the 5 th transistor.

11. The semiconductor memory device according to claim 8, wherein:

the 1 st local amplification part includes:

a 7 th transistor connected between the 1 st bit line and the global bit line;

an 8 th transistor connected between the 1 st bit line and a power supply line;

a 9 th transistor connected between the 1 st bit line and a1 st sensing node;

a 10 th transistor having a gate connected to the 1 st sensing node; and

an 11 th transistor connected between the 10 th transistor and the global bit line;

the 2 nd local amplification part includes:

a 12 th transistor connected between the 2 nd bit line and the global bit line;

a 13 th transistor connected between the 2 nd bit line and the power supply line;

a 14 th transistor connected between the 1 st bit line and a2 nd sensing node;

a 15 th transistor having a gate connected to the 2 nd sensing node; and

a 16 th transistor connected between the 15 th transistor and the global bit line.

12. The semiconductor memory device according to claim 11, wherein:

the circuit portion further includes a controller for performing a write operation,

the controller is

In the write operation in which the 1 st memory cell is selected, the 7 th transistor and the 12 th transistor are controlled to be in an on state and an off state, respectively,

in the write operation in which the 2 nd memory cell is selected, the 7 th transistor and the 12 th transistor are controlled to be in an off state and an on state, respectively.

13. The semiconductor memory device according to claim 8, wherein:

the 1 st word line is laminated in the 3 rd direction,

the 2 nd word line is laminated in the 3 rd direction,

the memory section further includes:

a1 st pillar extending in the 3 rd direction and penetrating the 1 st word lines; and

a2 nd pillar extending in the 3 rd direction and penetrating the plurality of 2 nd word lines;

the 1 st pillar and the 1 st word line cross portions each functioning as the 1 st memory cell,

the 2 nd pillar and the 2 nd word line cross portions function as the 2 nd memory cell,

the 1 st bonding metal, the 2 nd bonding metal, the 3 rd bonding metal and the 4 th bonding metal respectively include copper.

14. A semiconductor memory device, characterized by comprising: a memory part and a circuit part, wherein,

the memory section includes:

a1 st storage unit;

a2 nd storage unit;

a1 st word line extending in a1 st direction and connected to a gate of the 1 st memory cell;

a2 nd word line extending in the 1 st direction and connected to a gate of the 2 nd memory cell;

a1 st bit line extending in a2 nd direction different from the 1 st direction and connected to the 1 st memory cell;

a2 nd bit line extending in the 2 nd direction and connected to the 2 nd memory cell;

a1 st bonding metal located on one side of the 1 st bit line in a 3 rd direction different from the 1 st direction and the 2 nd direction, and connected to the 1 st bit line; and

a2 nd bonding metal located on the one side in the 3 rd direction with respect to the 2 nd bit line, connected to the 2 nd bit line;

the circuit section includes:

1 st sense amplifier;

a1 st latch circuit;

a1 st wiring connected to the 1 st sense amplifier and the 1 st latch circuit;

a2 nd sense amplifier;

a2 nd latch circuit;

a2 nd wiring connected to the 2 nd sense amplifier and the 2 nd latch circuit;

an output circuit connected to the 1 st latch circuit and the 2 nd latch circuit;

an input-output circuit connected to the output circuit;

a 3 rd bonding metal located on the other side in the 3 rd direction with respect to the 1 st sense amplifier, connected to the 1 st sense amplifier, and bonded to the 1 st bonding metal in an opposing manner; and

a 4 th bonding metal located on the other side in the 3 rd direction with respect to the 2 nd sense amplifier, connected to the 2 nd sense amplifier, and bonded to the 2 nd bonding metal in an opposing manner; and is

The output circuit is disposed between the 1 st sense amplifier and the 2 nd sense amplifier in the 2 nd direction.

Technical Field

Embodiments relate to a semiconductor memory device.

Background

A NAND (Not And) type flash memory capable of nonvolatile storage of data is known.

Disclosure of Invention

Embodiments provide a semiconductor memory device capable of suppressing power consumption.

A semiconductor memory device according to an embodiment includes a memory unit and a circuit unit. The memory section includes: 1 st and 2 nd memory cells; a1 st word line extending in a1 st direction and connected to a gate of the 1 st memory cell; a2 nd word line extending in the 1 st direction and connected to the gate of the 2 nd memory cell; a1 st bit line extending in a2 nd direction different from the 1 st direction and connected to the 1 st memory cell; a2 nd bit line extending in the 2 nd direction and connected to the 2 nd memory cell; a1 st bonding metal located on one side of the 1 st bit line in a 3 rd direction different from the 1 st and 2 nd directions and connected to the 1 st bit line; and a2 nd bonding metal connected to the 2 nd bit line on the 3 rd direction side with respect to the 2 nd bit line. The circuit part includes: 1 st and 2 nd sense amplifiers; a1 st latch circuit; a1 st wiring connected to the 1 st sense amplifier, the 2 nd sense amplifier, and the 1 st latch circuit; a 3 rd bonding metal located on the other side in the 3 rd direction with respect to the 1 st sense amplifier, connected to the 1 st sense amplifier, and bonded to the 1 st bonding metal in an opposite direction; and a 4 th bonding metal located on the other side in the 3 rd direction with respect to the 2 nd sense amplifier, connected to the 2 nd sense amplifier, and bonded to the 2 nd bonding metal in an opposed manner.

Drawings

Fig. 1 is a block diagram of a semiconductor memory device according to embodiment 1.

Fig. 2 is a detailed block diagram of the memory cell array, the sense amplifier module, and the row decoder module included in the semiconductor memory device according to embodiment 1.

Fig. 3 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 4 is a circuit diagram showing an example of a circuit configuration of a sense amplifier module included in the semiconductor memory device according to embodiment 1.

Fig. 5 is a circuit diagram showing an example of a circuit configuration of a sense amplifier module in the semiconductor memory device according to embodiment 1.

Fig. 6 is a circuit diagram showing an example of a circuit configuration of a row decoder module included in the semiconductor memory device according to embodiment 1.

Fig. 7 is a perspective view showing an example of the structure of the semiconductor memory device according to embodiment 1.

Fig. 8 is a plan view showing an example of a planar layout of a memory chip provided in the semiconductor memory device according to embodiment 1.

Fig. 9 is a plan view showing an example of a planar layout in a memory region of a memory chip included in the semiconductor memory device according to embodiment 1.

Fig. 10 is a cross-sectional view taken along the X-X line of fig. 9, showing an example of a cross-sectional structure of a memory region of a memory chip included in the semiconductor memory device according to embodiment 1.

Fig. 11 is a cross-sectional view taken along line XI-XI of fig. 10, showing an example of a cross-sectional structure of a memory pillar in the semiconductor memory device according to embodiment 1.

Fig. 12 is a cross-sectional view showing an example of a cross-sectional structure in a lead-out region of a memory chip included in the semiconductor memory device according to embodiment 1.

Fig. 13 is a plan view showing an example of a planar layout of a CMOS (Complementary Metal Oxide Semiconductor) chip provided in the Semiconductor memory device according to embodiment 1.

Fig. 14 is a plan view showing an example of a planar layout in a sense amplifier region of a CMOS chip included in the semiconductor memory device according to embodiment 1.

Fig. 15 is a cross-sectional view showing an example of a cross-sectional structure of the semiconductor memory device according to embodiment 1.

Fig. 16 is a circuit diagram showing an outline of a read operation of the semiconductor memory device according to embodiment 1.

Fig. 17 is a plan view showing an example of a plan layout of the semiconductor memory device according to the comparative example of embodiment 2.

Fig. 18 is a detailed block diagram of the memory cell array, the sense amplifier module, and the row decoder module included in the semiconductor memory device according to embodiment 2.

Fig. 19 is a plan view showing an example of a planar layout in a sense amplifier region of a CMOS chip included in the semiconductor memory device according to embodiment 2.

Fig. 20 is a circuit diagram showing an outline of a read operation of the semiconductor memory device according to embodiment 2.

Fig. 21 is a circuit diagram showing an example of a circuit configuration of a sense amplifier module included in the semiconductor memory device according to embodiment 3.

Fig. 22 is a plan view showing an example of a planar layout in a sense amplifier region of a CMOS chip included in the semiconductor memory device according to embodiment 3.

Fig. 23 is a plan view showing an example of a planar layout in a sense amplifier region of a CMOS chip included in a semiconductor memory device according to a modification of embodiment 3.

Fig. 24 is a circuit diagram showing an example of a circuit configuration of a sense amplifier module included in the semiconductor memory device according to embodiment 4.

Fig. 25 is a circuit diagram showing an example of a circuit configuration of a sense amplifier element and a local amplifier element in the semiconductor memory device according to embodiment 4.

Fig. 26 is a plan view showing an example of a planar layout in a sense amplifier region of a CMOS chip included in the semiconductor memory device according to embodiment 4.

Fig. 27 is a circuit diagram showing an outline of a read operation of the semiconductor memory device according to embodiment 4.

Fig. 28 is a timing chart showing an example of a read operation of the semiconductor memory device according to embodiment 4.

Fig. 29 is a circuit diagram showing an example of a circuit configuration of a sense amplifier module included in the semiconductor memory device according to embodiment 5.

Fig. 30 is a circuit diagram showing an example of a circuit configuration of a local amplifier module in the semiconductor memory device according to embodiment 5.

Fig. 31 is a circuit diagram showing an example of a detailed circuit configuration of a local amplifier module in the semiconductor memory device according to embodiment 6.

Fig. 32 is a circuit diagram showing an outline of a read operation of the semiconductor memory device according to embodiment 6.

Fig. 33 is a circuit diagram showing an outline of a write operation of the semiconductor memory device according to embodiment 6.

Fig. 34 is a circuit diagram showing an example of a circuit configuration of a sense amplifier module included in the semiconductor memory device according to embodiment 7.

Fig. 35 is a circuit diagram showing an example of a circuit configuration of a local amplifier module in the semiconductor memory device according to embodiment 7.

Fig. 36 is a circuit diagram showing an outline of a read operation of the semiconductor memory device according to embodiment 7.

Fig. 37 is a timing chart showing an example of a read operation of the semiconductor memory device according to embodiment 7.

Fig. 38 is a circuit diagram showing an outline of a write operation of the semiconductor memory device according to embodiment 7.

Fig. 39 is a circuit diagram showing an example of a circuit configuration of a sense amplifier module included in the semiconductor memory device according to embodiment 8.

Fig. 40 is a plan view showing an example of a planar layout in a sense amplifier region of a CMOS chip included in a semiconductor memory device according to a modification of embodiment 1.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. Each embodiment exemplifies an apparatus or a method for embodying the technical idea of the invention. The drawings are schematic or conceptual views, and the dimensions, ratios, and the like of the drawings are not necessarily the same as actual ones. The technical idea of the present invention should not be specified by the shape, structure, arrangement, and the like of the constituent elements.

In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. The numbers or lower case letters following the capital letters constituting the reference symbols are referred to by the reference symbols including the same capital letters and are used to distinguish elements having the same constitution from each other. Similarly, the letters following the numbers that constitute the reference symbols are referred to by reference symbols that include the same numbers and are used to distinguish elements having the same configuration from each other. In the case where elements denoted by reference symbols including the same capital letters or numerals do not need to be distinguished from each other, the elements are referred to by reference symbols including only capital letters or numerals, respectively.

[1] Embodiment 1

The semiconductor memory device 1 according to embodiment 1 is, for example, a NAND flash memory. The semiconductor memory device 1 according to embodiment 1 will be described below.

[1-1] integral constitution of semiconductor memory device 1

Fig. 1 shows an example of the structure of a semiconductor memory device 1 according to embodiment 1. As shown in fig. 1, the semiconductor memory device 1 can be controlled by an external memory controller 2. The semiconductor memory device 1 includes, for example, a memory cell array 10, an instruction register 11, an address register 12, a sequencer 13, a sense amplifier module 14, a driver module 15, a row decoder module 16, an input/output circuit 17, and an input/output pad PD.

The memory cell array 10 includes a plurality of blocks BLK0 to BLK (n-1) (n is an integer of 1 or more). The block BLK is a set of a plurality of memory cells capable of nonvolatile storage of data, and is used, for example, as an erase unit of data. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell is associated with, for example, 1 bit line and 1 word line.

The command register 11 holds a command CMD received by the semiconductor memory apparatus 1 from the memory controller 2. The command CMD includes, for example, a command for causing the sequencer 13 to execute a read operation, a write operation, an erase operation, and the like.

The address register 12 holds address information ADD received by the semiconductor memory apparatus 1 from the memory controller 2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. For example, block address BAd, page address PAd, and column address Cad are used for selection of block BLK, word lines, and bit lines, respectively.

The sequencer 13 controls the overall operation of the semiconductor memory device 1. For example, the sequencer 13 controls the sense amplifier module 14, the driver module 15, the row decoder module 16, and the like based on the command CMD stored in the command register 11, and executes a read operation, a write operation, an erase operation, and the like.

In the write operation, the sense amplifier module 14 applies a specific voltage to each bit line in accordance with the write data DAT received from the memory controller 2. In the read operation, the sense amplifier module 14 determines data stored in the memory cell based on the voltage of the bit line, and transmits the determination result to the memory controller 2 as read data DAT.

The driver module 15 generates voltages to be used for a read operation, a write operation, an erase operation, and the like. The driver module 15 applies the generated voltage to the signal line corresponding to the selected word line, for example, based on the page address Pad stored in the address register 12.

Row decoder module 16 selects the corresponding 1 block BLK within memory cell array 10 based on block address BAd stored in address register 12. The row decoder block 16 transfers, for example, a voltage applied to a signal line corresponding to the selected word line in the selected block BLK.

The input-output circuit 17 receives a command CMD, an address ADD, and write data DAT from the memory controller 2 via the input-output pad PD, and sends them to the command register 11, the address register 12, and the sense amplifier module 14, respectively. In addition, the input-output circuit 17 receives readout data DAT from the sense amplifier module 14 and transmits it to the memory controller 2 via the input-output pad PD. A plurality of (e.g., 8) input-output pads PD may also be provided.

The semiconductor memory device 1 and the memory controller 2 described above may be combined to form 1 semiconductor device. Examples of such a semiconductor device include SD^TMA memory card such as a (Secure Digital) card, an SSD (solid state drive), or the like.

Fig. 2 shows a more detailed configuration example of the memory cell array 10, the sense amplifier module 14, and the row decoder module 16 included in the semiconductor memory device 1 according to embodiment 1. Hereinafter, a case where the memory cell array 10 includes 16 blocks BLK will be described. As shown in fig. 2, the memory cell array 10 is divided into, for example, memory cell arrays 10a and 10 b. The sense amplifier module 14 includes sense amplifier groups SASa and SASb, a cache memory CM, and a conversion circuit SD.

The memory cell array 10a includes blocks BLK 0-BLK 7. The memory cell array 10b includes blocks BLK 8-BLK 15. The number of blocks BLK included in each of the memory cell arrays 10a and 10b may be other numbers. The number of blocks BLK included in the memory cell array 10a may be the same as or different from the number of blocks BLK included in the memory cell array 10 b.

Bit lines BLa0 to BLa (m-1) (m is an integer of 1 or more) are connected to memory cell array 10 a. Bit lines BLb0 through BLb (m-1) are connected to memory cell array 10 b. In this way, the same number of bit lines BL are connected to the memory cell arrays 10a and 10b, respectively. The bit lines BLa and BLb denoted by the same reference numerals may be regarded as lines in which 1 bit line BL is divided into 2 lines corresponding to the memory cell arrays 10a and 10 b. The bit lines BLa and BLb labeled with the same number are associated with the same column address CAd, for example.

The sense amplifier groups SASa and SASb are associated with the memory cell arrays 10a and 10b, respectively. The sense amplifier group SASa includes sense amplifier elements SAUa < 0 > -SAUa < m-1 >. The sense amplifier set SASb includes sense amplifier elements SAUb < 0 > -SAUb < m-1 >. Each sense amplifier unit SAU is connected to at least 1 bit line BL. For example, sense amplifier modules SAUa < 0 > -SAUa < m-1 > are connected to bit lines BLa 0-BLa (m-1), respectively. Sense amplifier modules SAUb < 0 > -SAUb < m-1 > are connected to bit lines BLb 0-BLb (m-1), respectively.

The cache memory CM includes latch circuits XDL < 0 > -XDL < m-1 >. Each latch circuit XDL temporarily holds read data, write data, or the like, and is connected to a group of sense amplifier elements SAUa and SAUb via a different bus DBUS. Specifically, the latch circuit XDL < 0 > is connected to the sense amplifier module SAUa < 0 > and SAUb < 0 >. The latch circuit XDL < 1 > is connected to the sense amplifier modules SAUa < 1 > and SAUb < 1 >. Similarly, the latch circuit XDL < m-1 > is connected to the sense amplifier modules SAUa < m-1 > and SAUb < m-1 >.

The conversion circuit SD is a parallel-serial conversion circuit (SerDes). Specifically, the conversion circuit SD serially transfers the data DAT received in parallel from the cache memory CM to the input-output circuit 17 of the semiconductor memory apparatus 1. In addition, the conversion circuit SD transfers data DAT serially transferred from the input-output circuit 17 to the cache memory CM in parallel. The conversion circuit SD may also have a function of storing information associated with the column address CAd. Such information may also be assigned to the bit lines BLa and BLb, respectively.

The column decoder module 16 includes the same number of column decoders RD 0-RD 15 as the number of blocks BLK. Column decoders RD 0-RD 15 are associated with blocks BLK 0-BLK 15, respectively. Each row decoder RD has a function of decoding the block address BAd. Then, the column decoder RD corresponding to the selected block BLK applies a voltage to the wiring in the associated block BLK.

[1-2] Circuit configuration of semiconductor memory device 1

[1-2-1] Circuit configuration for memory cell array 10

Fig. 3 shows an example of a circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 according to embodiment 1, in which 1 block BLK out of a plurality of blocks BLK included in the memory cell array 10 is extracted. As shown in FIG. 3, the block BLK includes, for example, 4 string components SU 0-SU 3.

Each string component SU includes a plurality of NAND strings NS associated with bit lines BL 0-BL (m-1), respectively. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST 2. The memory cell transistor MT includes a control gate and a charge storage layer, and stores data in a nonvolatile manner. The selection transistors ST1 and ST2 are used to select the string unit SU in various operations.

In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. The drain of the select transistor ST1 is connected to the bit line BL establishing the association. The source of the selection transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. The drain of the selection transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The source of the selection transistor ST2 is connected to the source line SL.

In the same block BLK, the control gates of the memory cell transistors MT0 to MT7 are commonly connected to word lines WL0 to WL7, respectively. The gates of the select transistors ST1 in the string elements SU0 to SU3 are commonly connected to the select gate lines SGD0 to SGD3, respectively. The gate of the select transistor ST2 included in the same block BLK is commonly connected to the select gate line SGS.

Bit lines BL0 to BL (m-1) are assigned different column addresses. The bit line BLa is common to the NAND strings NS to which the same column address is assigned among the plurality of blocks BLK included in the memory cell array 10 a. The bit line BLb is shared by NAND strings NS to which the same column address is assigned among a plurality of blocks BLK included in the memory cell array 10 b. Word lines WL0 to WL7 are provided for each block BLK, respectively. The source lines SL are shared among the blocks BLK.

The set of the memory cell transistors MT connected to the common word line WL in the 1 string unit SU is referred to as a cell unit CU, for example. For example, the storage capacity of the cell unit CU including the memory cell transistors MT each storing 1-bit data is defined as "1-page data". The cell unit CU may have a storage capacity of 2 pages of data or more corresponding to the number of bits of data stored in the memory cell transistor MT.

The circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 according to embodiment 1 is not limited to the configuration described above. For example, the number of string elements SU included in each block BLK or the number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS may be designed to be arbitrary.

[1-2-2] Circuit constitution concerning sense Amplifier Module 14

Fig. 4 is an example of the circuit configuration of the sense amplifier module 14 included in the semiconductor memory device 1 according to embodiment 1, and shows a detailed circuit configuration of the sense amplifier modules SAUa and SAUb. As shown in fig. 4, each sense amplifier unit SAU includes, for example, a bit line connection BLHU, a sense amplifier unit SA, latch circuits SDL, ADL, and BDL, a bus line LBUS, and a transistor DTR. Hereinafter, the circuit configuration of the sense amplifier unit SAU will be described with attention paid to 1 sense amplifier unit SAU.

The bit line connection BLHU includes a high withstand voltage transistor connected between the bit line BL and the sense amplifier section SA, which establish the association. The sense amplifier unit SA determines that the read data is "0" or "1" based on the voltage of the bit line BL associated therewith, for example, in the read operation. In other words, the sense amplifier section SA senses data read to the bit line BL associated therewith, and determines the data stored in the selected memory cell.

The latch circuits SDL, ADL, and BDL temporarily hold read data, write data, and the like, respectively. The sense amplifier section SA can change the voltage applied to the bit line BL based on the data held in the latch circuit SDL. The bus LBUS is connected to the sense amplifier unit SA and the latch circuits SDL, ADL, and BDL. The sense amplifier section SA and the latch circuits SDL, ADL, and BDL can mutually transmit and receive data via the bus LBUS.

Transistor DTR is connected between bus LBUS and DBUS. The control signal DSWa is input to the gate of the transistor DTR within the sense amplifier module SAUa. The control signal DSWb is input to the gate of the transistor DTR in the sense amplifier module SAUb. The sequencer 13 can electrically connect between one of the sense amplifier components SAUa and SAUb and the latch circuit XDL by controlling one of the control signals DSWa and DSWb to an "H" level and the other to an "L" level.

Fig. 5 shows an example of a more detailed circuit configuration of the sense amplifier unit SAU in the semiconductor memory device 1 according to embodiment 1. As shown in fig. 5, the sense amplifier section SA includes transistors T0 to T10 and a capacitor CA, for example. The bit line connection BLHU includes transistors T20 and T21. The latch circuits SDL, ADL, and BDL have similar configurations, respectively, and include transistors T30 and T31, and inverters INV0 and INV1, for example.

The transistor T0 is a P-type MOS transistor. The transistors T1 to T10, T20, T21, T30, and T31 are N-type MOS transistors, respectively. The withstand voltage of each of the transistors T20 and T21 is higher than the withstand voltage of each of the transistors T1 to T10. Hereinafter, the transistors T0 to T10 are also referred to as low-voltage transistors, and the transistors T8 and T9 are also referred to as high-voltage transistors.

(connection relationship of elements in sense Amplifier section SA)

The source of the transistor T0 is connected to the power supply line. The drain of the transistor T0 is connected to the node ND 1. The gate of the transistor T0 is connected to the node SINV. The drain of the transistor T1 is connected to the node ND 1. The source of the transistor T1 is connected to the node ND 2. The control signal BLX is input to the gate of the transistor T1. The drain of the transistor T2 is connected to the node ND 1. The source of transistor T2 is connected to node SEN. The control signal HLL is input to the gate of the transistor T2. The drain of transistor T3 is connected to node SEN. The source of the transistor T3 is connected to the node ND 2. The control signal XXL is input to the gate of the transistor T3.

The drain of the transistor T4 is connected to the node ND 2. The control signal BLC is input to the gate of the transistor T4. The drain of the transistor T5 is connected to the node ND 2. The source of the transistor T5 is connected to the node SRC. The gate of the transistor T5 is connected to the node SINV. The drain of transistor T6 is connected to bus LBUS. The control signal STB is input to the gate of the transistor T6. The drain of the transistor T7 is connected to the source of the transistor T6. The source of transistor T7 is connected to node CLK. The gate of transistor T7 is connected to node SEN.

The drain of transistor T8 is connected to node SEN. The control signal LSL is input to the gate of the transistor T8. The drain of the transistor T9 is connected to the source of the transistor T8. The source of transistor T9 is connected to node VLSA. The gate of transistor T9 is connected to bus LBUS. The drain of transistor T10 is connected to bus LBUS. The source of transistor T10 is connected to node SEN. The control signal BLQ is input to the gate of the transistor T10. One electrode of the capacitor CA is connected to the node SEN. The other electrode of the capacitor CA is connected to the node CLK. A clock signal, for example, is input to the node CLK.

(connection relationship of elements in sense Amplifier section SA)

The drain of the transistor T20 is connected to the source of the transistor T4. The source of transistor T20 is connected to the bit line BL establishing the association. The control signal BLS is input to the gate of the transistor T20. The drain of the transistor T21 is connected to the node BLBIAS. The source of transistor T21 is connected to the bit line BL establishing the association. The control signal BIAS is input to the gate of the transistor T21.

(connection relationship of elements in latch circuits SDL, ADL, and BDL.)

The drain of transistor T30 is connected to bus LBUS. A source of the transistor T30 is connected to an output node of the inverter INV0 and an input node of the inverter INV 1. The drain of transistor T31 is connected to bus LBUS. A source of the transistor T31 is connected to an input node of the inverter INV0 and an output node of the inverter INV 1. The control signals STL and STI are input to the gates of the transistors T30 and T31 in the latch circuit SDL, respectively. The control signals ATL and ATI are input to the gates of the transistors T30 and T31 in the latch circuit ADL, respectively. The control signals BTL and BTI are input to the gates of the transistors T30 and T31 in the latch circuit BDL, respectively.

The input node and the output node of the inverter INV0 in the latch circuit SDL correspond to the nodes SINV and SLAT, respectively. The input node and the output node of the inverter INV0 in the latch circuit ADL correspond to the nodes AINV and ALAT, respectively. The input node and the output node of the inverter INV0 in the latch circuit BDL correspond to the nodes BINV and BLAT, respectively.

In the circuit configuration of the sense amplifier unit SAU described above, the power supply voltage VDD, for example, is applied to the power supply line connected to the source of the transistor T0. The nodes SRC, CLK, and VLSA are applied with, for example, the ground voltage VSS, respectively. An erase voltage VERA is applied to the node BLBIAS, for example. The voltage of the node SINV changes based on the data held by the latch circuit SDL. Control signals BLX, HLL, XXL, BLC, STB, LSL, BLQ, BLS, BIAS, STL, STI, ATL, ATI, BTL, and BTI are each generated, for example, by sequencer 13. In the read operation, the sense amplifier unit SA determines data to be read to the bit line BL, for example, based on the timing of the determination of the control signal STB.

The sense amplifier module 14 included in the semiconductor memory device 1 according to embodiment 1 is not limited to the circuit configuration described above. For example, the number of latch circuits provided in each sense amplifier unit SAU may be changed as appropriate based on the number of pages stored in 1 unit cell CU. The sense amplifier section SA may be configured with another circuit as long as it can determine data read to the bit line BL. The transistor T21 may be omitted from the bit line connection BLHU. The sense amplifier module 14 may also have a plurality of transistors capable of charging the buses LBUS and DBUS, etc.

[1-2-3] Circuit constitution for Row decoder Module 16

Fig. 6 shows an example of the circuit configuration of the row decoder module 16 included in the semiconductor memory device 1 according to embodiment 1, and shows a detailed circuit configuration of the row decoder RD 0. The circuit configuration of the other row decoder RD is the same as that of the row decoder RD 0. As shown in fig. 6, each row decoder RD includes, for example, a block decoder BD, transfer gate lines TG and bTG, and transistors TR0 to TR 17.

The block decoder BD decodes the block address BAd. The block decoder BD applies a specific voltage to each of the transfer gate lines TG and bTG based on the decoding result. Specifically, the block decoder BD applies an inverted signal of the signal applied to the transfer gate line TG to the transfer gate line bTG. That is, the voltage applied to the transfer gate line TG and the voltage applied to the transfer gate line bTG have a complementary relationship.

The transistors TR0 to TR17 are high-voltage N-type MOS transistors, respectively. The gates of the transistors TR0 to TR12 are commonly connected to the transfer gate line TG. The gates of the transistors TR13 to TR17 are commonly connected to the transfer gate line bTG. That is, each transistor TR is controlled by the block decoder BD. Each transistor TR is connected to the driver module 15 through a signal line shared between the blocks BLK.

The drain of the transistor TR0 is connected to the signal line SGSD. The signal line SGSD is shared among the blocks BLK and is used as a global transfer gate line corresponding to the selected block BLK. A source of the transistor TR0 is connected to the select gate line SGS. The select gate line SGS is used as a local transfer gate line provided in each block.

Drains of the transistors TR1 to TR8 are connected to the signal lines CG0 to CG7, respectively. The signal lines CG0 to CG7 are used as global word lines shared by the blocks BLK, respectively. The sources of the transistors TR1 to TR8 are connected to word lines WL0 to WL7, respectively. Word lines WL0 to WL7 are used as local word lines provided in the respective blocks.

Drains of the transistors TR9 to TR12 are connected to the signal lines SGDD0 to SGDD3, respectively. The signal lines SGDD0 to SGDD3 are shared by the blocks BLK, and are used as global transfer gate lines corresponding to the selected blocks BLK. Sources of the transistors TR9 to TR12 are connected to the select gate lines SGD0 to SGD3, respectively. The select gate lines SGD0 to SGD3 are used as local transfer gate lines provided in the respective blocks.

The drain of the transistor TR13 is connected to the signal line USGS. A source of the transistor TR13 is connected to the select gate line SGS. The drains of the transistors TR14 to TR17 are commonly connected to the signal line USGD. Sources of the transistors TR14 to TR17 are connected to the select gate lines SGD0 to SGD3, respectively. The signal lines USGS and USGD are respectively shared among the blocks BLK and used as global transfer gate lines corresponding to the non-selected blocks BLK.

According to the above constitution, the column decoder module 16 can select the block BLK. In brief, in various operations, the block decoder BD corresponding to the selected block BLK applies the voltages of the "H" level and the "L" level to the transfer gate lines TG and bTG, respectively, and the block decoder BD corresponding to the non-selected block BLK applies the voltages of the "L" level and the "H" level to the transfer gate lines TG and bTG, respectively.

The row decoder module 16 included in the semiconductor memory device 1 according to embodiment 1 is not limited to the circuit configuration described above. For example, the number of transistors TR included in the column decoder module 16 may be changed as appropriate based on the number of memory cell transistors, selection transistors, or the like provided in each block BLK.

[1-3] Structure of semiconductor memory device 1

An example of the structure of the semiconductor memory device 1 according to embodiment 1 will be described below. In the drawings referred to below, the X direction corresponds to the extending direction of the word line WL, the Y direction corresponds to the extending direction of the bit line BL, and the Z direction corresponds to the vertical direction with respect to the surface of the semiconductor substrate on which the semiconductor memory device 1 is formed. In the plan view, hatching is appropriately added to facilitate the view. The hatching attached to the top view is not necessarily related to the material or the characteristics of the hatching attached component. In each of the plan view and the cross-sectional view, the wiring, the contact, the interlayer insulating film, and the like are appropriately omitted for easy viewing of the drawings.

[1-3-1] relates to the overall configuration of a semiconductor memory device

Fig. 7 shows an example of the overall structure of the semiconductor memory device 1 according to embodiment 1. As shown in fig. 7, the semiconductor memory device 1 has the following configuration: the memory chip MC and the CMOS chip CC are provided, and for example, the lower surface of the memory chip MC is bonded to the upper surface of the CMOS chip CC. The memory chip MC includes a configuration corresponding to the memory cell array 10. The CMOS chip CC includes, for example, configurations corresponding to a sequencer 13, an instruction register 11, an address register 12, a sequencer 13, a sense amplifier module 14, a driver module 15, and a row decoder module 16.

The area of the memory chip MC is divided into, for example, a memory area MR, lead-out areas HR1 and HR2, and a pad area PR 1. The memory region MR occupies a large portion of the memory chip MC for storing data. For example, the memory area MR includes a plurality of NAND strings NS. The lead-out regions HR1 and HR2 are separated from the memory region MR in the X direction. The lead-out regions HR1 and HR2 are used to connect the build-up wiring in the memory chip MC and the row decoder module 16 in the CMOS chip CC. The pad region PR1 is adjacent to the memory region MR and the lead-out regions HR1 and HR2, respectively, in the Y direction. The pad region PR1 includes, for example, input/output pads PD of the semiconductor memory device 1 for connection to an external memory controller 2.

The memory chip MC has a plurality of bonding pads BP on the lower surfaces of the memory region MR, the lead-out regions HR1 and HR2, and the pad region PR 1. The bonding pad BP is also referred to as bonding metal, for example. The pad BP in the memory region MR is connected to the bit line BL that is associated with it. The bonding pads BP in the lead region HR are connected to wirings (for example, word lines WL) associated with the build-up wirings provided in the memory region MR. The bonding pad BP in the pad region PR1 is connected to the input/output pad PD provided on the upper surface of the memory chip MC. The input/output pads PD provided on the memory chip MC are used, for example, for connecting the semiconductor memory device 1 and the memory controller 2.

The area of the CMOS chip CC is divided into, for example, a sense amplifier region SR, a peripheral circuit region PERI, transfer regions XR1 and XR2, and a pad region PR 2. The sense amplifier region SR and the peripheral circuit region PERI in the CMOS chip CC are arranged adjacent to each other in the Y direction, and are arranged to overlap the memory region MR in the memory chip MC when viewed from the Z direction. The sense amplifier region SR includes the sense amplifier module 14. The peripheral circuit region PERI includes a sequencer 13 and the like. The transfer regions XR1 and XR2 in the CMOS chip CC are arranged to overlap with the lead-out regions HR1 and HR2 in the memory chip MC, respectively, with the group of the sense amplifier region SR and the peripheral circuit region PERI interposed therebetween in the X direction when viewed from the Z direction. The transfer regions XR1 and XR2 include a plurality of transistors TR within the row decoder module 16. The pad region PR2 in the CMOS chip CC is arranged to overlap with the pad region PR1 in the memory chip MC when viewed from the Z direction. The pad region PR2 includes the input/output circuit 17 and the like of the semiconductor memory device 1.

In addition, the CMOS chip CC has a plurality of bonding pads BP on the top surface of each of the sense amplifier region SR, the peripheral circuit region PERI, the transfer regions XR1 and XR2, and the pad region PR 2. The bonding pads BP in the sense amplifier region SR and the bonding pads BP in the memory region MR are respectively disposed in an overlapping manner. The plurality of bond pads BP in the transfer region XR1 are disposed to overlap the plurality of bond pads BP in the exit region HR1, respectively. The plurality of bond pads BP in the transfer region XR2 are disposed to overlap the plurality of bond pads BP in the exit region HR2, respectively. The bonding pads BP in the pad region PR1 and the bonding pads BP in the pad region PR2 are arranged to overlap each other.

Of the bonding pads BP provided in the semiconductor memory device 1, 2 bonding pads BP facing each other between the memory chip MC and the CMOS chip CC are bonded ("bonding" in fig. 7). Thus, the circuits in the memory chip MC and the circuits in the CMOS chip CC are electrically connected to each other. The pair of 2 bonding pads BP facing each other between the memory chip MC and the CMOS chip CC may have a boundary or may be integrated.

The semiconductor memory device 1 according to embodiment 1 is not limited to the structure described above. For example, at least 1 extraction region HR may be provided adjacent to the memory region MR. The semiconductor memory device 1 may include a plurality of groups of the memory region MR and the lead-out region HR. In this case, the group of the sense amplifier region SR, the transfer region XR, and the peripheral circuit region PERI is appropriately set corresponding to the arrangement of the memory region MR and the lead-out region HR. The memory chip MC and the CMOS chip CC may be arranged in reverse. In this case, a bonding pad BP provided on the upper surface of the memory chip MC and a bonding pad BP provided on the lower surface of the CMOS chip CC are bonded, and an input/output pad for connection to an external memory controller 2 is provided on the upper surface of the CMOS chip CC.

[1-3-2] Structure of memory chip MC

(plane layout of memory chip MC)

Fig. 8 shows an example of a plan layout of the memory chip MC included in the semiconductor memory device 1 according to embodiment 1, in which regions corresponding to the blocks BLK0 and BLK1 are drawn out. As shown in fig. 8, the memory chip MC includes a plurality of slits SLT, a plurality of memory pillars MP, a plurality of bit lines BL, and a plurality of contacts CT and CV.

The plurality of slits SLT are arranged in the Y direction. Each slit SLT extends in the X direction and crosses the memory region MR and the lead-out regions HR1 and HR 2. Each slit SLT divides and insulates adjacent conductor layers with the slit SLT therebetween. Specifically, the slits SLT divide and insulate a plurality of wiring layers corresponding to the word lines WL0 to WL7 and the select gate lines SGD and SGS, respectively.

Each memory pillar MP functions as, for example, 1 NAND string NS. The memory pillars MP are arranged in a 4-row zigzag manner in the memory region MR and in a region between the adjacent slits SLT. In this example, the regions partitioned by the slit SLT correspond to 1 string unit SU, respectively. The number and arrangement of the memory pillars MP between the adjacent slits SLT can be changed as appropriate. The slits SLT arranged at the boundary portion of the block BLK may be slits SLT that are separated from each other by at least the select gate line SGD.

The plurality of bit lines BL extend in the Y direction and are arranged in the X direction, respectively. Each bit line BL overlaps at least 1 memory pillar MP as viewed from the Z direction in each string component SU. In this example, 2 bit lines BL are arranged to overlap 1 memory pillar MP. A contact CV is provided between 1 bit line BL among the plurality of bit lines BL overlapping the memory pillars MP and the memory pillars MP. Each memory pillar MP is connected to the associated bit line BL via a contact CV.

In each of the lead-out regions HR1 and HR2, the select gate line SGS, the word lines WL0 to WL7, and the select gate line SGD have portions (step portions) that do not overlap the upper wiring layer (conductor layer). The shape of the portion of each of the extraction regions HR1 and HR2 which does not overlap with the upper wiring layer is similar to a step (step), a terrace (terrace), a curb (rimstone), or the like. Specifically, steps are provided between the select gate line SGS and the word line WL0, between the word line WL0 and the word line WL1, …, between the word line WL6 and the word line WL7, and between the word line WL7 and the select gate line SGD, respectively.

Each contact CT is used to connect word lines WL 0-WL 7 and select gate lines SGS and SGD, respectively, to row decoder module 16. Each contact CT is disposed on a step portion of one of the word lines WL0 to WL7 and the select gate lines SGS and SGD. The word line WL or the select gate line SGS, which is used as a common line in the same block BLK, is short-circuited via a wiring layer connected to the contact CT.

For example, the contact CT associated with the block BLK0 is disposed in the lead-out region HR1, and the contact CT associated with the block BLK1 is disposed in the lead-out region HR 2. In other words, for example, even numbered block BLK is connected to column decoder module 16 via contact CT in lead-out region HR1, and odd numbered block BLK is connected to column decoder module 16 via contact CT in lead-out region HR 2.

The planar layout of the memory chip MC described above is repeatedly arranged in the Y direction in the memory region MR and the lead-out regions HR1 and HR 2. The arrangement of the contacts CT with respect to each block BLK is not limited to the layout described above. For example, when one lead-out region HR is omitted, the contacts CT corresponding to each block BLK are collectively arranged in the lead-out region HR on one side in contact with the memory region MR. Contacts CT may be disposed on both sides of the lead-out regions HR1 and HR2, and a voltage may be applied from both sides of each block BLK. The lead-out regions HR may be disposed so as to be separated from the memory regions MR.

In addition, in the semiconductor memory device 1 of embodiment 1, the bit lines BL extending in the Y direction are divided into 2. Fig. 9 shows an example of a planar layout in the memory region MR of the memory chip MC included in the semiconductor memory device 1 according to embodiment 1, in which a region corresponding to a boundary between the memory cell arrays 10a and 10b is extracted and shown. Specifically, FIG. 9 shows an area that includes string component SU3 of block BLK7 and string component SU0 of block BLK 8.

As shown in fig. 9, in the semiconductor memory device 1 according to embodiment 1, the bit line BLa connected to the memory cell MP of the block BLK7 is separated from the bit line BLb connected to the memory cell MP of the block BLK 8. The width of the slit SLT disposed at the boundary between the memory cell arrays 10a and 10b, that is, the width of the slit SLT disposed between the blocks BLK7 and BLK8 is wider than the width of the slit SLT disposed between the adjacent blocks BLK in the memory cell array 10a or 10 b.

(Cross-sectional Structure of memory chip MC)

Fig. 10 is a cross-sectional view taken along line X-X of fig. 9, and shows an example of a cross-sectional structure in the memory region MR of the memory chip MC included in the semiconductor memory device 1 according to embodiment 1. The Z direction in fig. 10 is shown inverted with respect to fig. 7. That is, "upper" corresponds to the lower side of the paper, and "lower" corresponds to the upper side of the paper. As shown in FIG. 10, in the memory region MR, the memory chip MC further includes insulator layers 20-25, conductor layers 30-36, and contacts V1 and V2.

The insulator layer 20 is provided on the uppermost layer of the memory chip MC, for example. The present invention is not limited to this, and a wiring layer, an insulator layer, or the like may be provided on the insulator layer 20. An electrical conductor layer 30 is disposed below the insulator layer 20. The conductive layer 30 is formed in a plate shape extending along the XY plane, for example, and is used as the source line SL. The conductor layer 30 comprises, for example, polysilicon doped with phosphorus.

An insulator layer 21 is disposed under the conductor layer 30. An electrical conductor layer 31 is provided under the insulator layer 21. The conductive layer 31 is formed in a plate shape extending along the XY plane, for example, and is used as the selection gate line SGS. The selection gate line SGS may be formed of a plurality of conductor layers 31. The conductor layer 31 comprises, for example, polysilicon doped with phosphorus. When the select gate line SGS is formed of a plurality of conductor layers 31, the plurality of conductor layers 31 may be formed of different conductors.

An insulator layer 22 is disposed under the conductor layer 31. Under the insulator layer 22, the conductor layer 32 and the insulator layer 23 are alternately disposed. Each of the plurality of conductor layers 32 is formed in a plate shape extending along the XY plane, for example. The plurality of conductor layers 32 are used as word lines WL0 to WL7 in this order from the conductor layer 30 side. The conductor layer 32 contains, for example, tungsten.

An insulator layer 24 is disposed below the lowermost conductor layer 32. An electrical conductor layer 33 is disposed below the insulator layer 24. The conductive layer 33 is formed in a plate shape extending along the XY plane, for example, and is used as the selection gate line SGD. The selection gate line SGD may be formed of a plurality of conductor layers 33. The conductor layer 33 contains, for example, tungsten.

An insulator layer 25 is disposed under the conductor layer 33. An electrical conductor layer 34 is disposed below the insulator layer 25. The conductive layer 34 is formed in a linear shape extending in the Y direction, for example, and is used as a bit line BL. The conductor layer 34 is divided into 2 pieces corresponding to the bit lines BLa and BLb. The plurality of conductor layers 34 corresponding to the bit line BLa and the plurality of conductor layers 34 corresponding to the bit line BLb are arranged in the X direction in regions not shown. The conductor layer 34 contains copper, for example. Hereinafter, the wiring layer provided with the conductor layer 34 is referred to as M0.

Each memory pillar MP is extended along the Z direction, and penetrates through the insulator layers 21-24 and the conductor layers 31-33. The upper portion of the memory pillar MP is connected to the conductor layer 30. Each memory pillar MP includes, for example, a semiconductor layer 40, a tunnel insulating film 41, an insulating film 42, and a barrier insulating film 43.

The semiconductor layer 40 extends in the Z direction. For example, the lower end of the semiconductor layer 40 is included in the layer including the insulator layer 25, and the upper end of the semiconductor layer 40 is in contact with the conductor layer 30. The tunnel insulating film 41 covers the side surface of the semiconductor layer 40. The insulating film 42 covers the side surfaces of the tunnel insulating film 41. The barrier insulating film 43 covers the side surfaces of the insulating film 42.

The portion where the memory pillar MP intersects the conductor layer 31 (select gate line SGS) functions as a select transistor ST 2. The memory pillar MP and the portion where the conductor layer 32 (word line WL) intersects function as a memory cell transistor MT. The portion where the memory pillar MP intersects the conductor layer 33 (the select gate line SGD) functions as a select transistor ST 1. That is, the semiconductor layer 40 functions as channels of the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2, respectively. The insulating film 42 functions as a charge storage layer of the memory cell transistor MT.

A columnar contact CV is provided below the semiconductor layer 40 of each memory pillar MP. In the illustrated area, the contact CV corresponding to 1 memory rank MP of the 2 memory ranks MP is shown. The contact CV is connected to the region not shown in the memory column MP to which the contact CV is not connected in this region. Under the contact CV, 1 conductor layer 34 (bit line BL) is contacted.

The slit SLT is formed in a plate shape at least a part of which is extended along the XZ plane, and divides the insulator layers 21-24 and the conductor layers 31-33. The lower end of the slit SLT is included in the layer including the insulator layer 25. The upper end of the slit SLT is in contact with the conductor layer 30, for example. Example of slit SLTSuch as silicon oxide (SiO)₂)。

A columnar contact V1 is provided below the conductor layer 34. Conductor layer 35 is disposed below contact V1. The conductor layer 35 is a wiring for circuit connection in the semiconductor memory device 1. Hereinafter, the wiring layer provided with the conductor layer 35 is referred to as M1.

An electrical conductor layer 36 is disposed below the electrical conductor layer 35. The conductive layer 36 is in contact with the interface of the memory chip MC, and serves as a bonding pad BP. The conductor layer 36 contains copper, for example. Hereinafter, the wiring layer provided with the conductor layer 36 is referred to as M2.

Fig. 11 is a cross-sectional view taken along line XI-XI of fig. 10, showing an example of a cross-sectional structure of the memory pillar MP in the semiconductor memory device 1 according to embodiment 1. Specifically, fig. 11 is a cross section taken parallel to the surface of the semiconductor substrate including the memory pillar MP and the conductor layer 32 and used to form the semiconductor memory device 1.

As shown in fig. 11, the semiconductor layer 40 is provided in the center of the memory pillar MP, for example. The tunnel insulating film 41 surrounds the side surface of the semiconductor layer 40. The insulating film 42 surrounds the side surfaces of the tunnel insulating film 41. The barrier insulating film 43 surrounds the side surfaces of the insulating film 42. The conductor layer 32 surrounds the side surface of the barrier insulating film 43. The tunnel insulating film 41 and the barrier insulating film 43 each contain, for example, silicon oxide (SiO)₂). The insulating film 42 contains, for example, silicon nitride (SiN). Each memory pillar MP may further include an insulator layer inside the semiconductor layer 40, the insulator layer being located in the center of the memory pillar MP. That is, the semiconductor layer 40 may have a portion provided in a cylindrical shape.

Fig. 12 shows an example of a cross-sectional structure in the lead-out region HR1 of the CMOS chip CC included in the semiconductor memory device 1 according to embodiment 1, in which cross-sections corresponding to the even-numbered blocks BLK included in the lead-out region HR1 are extracted and shown. Note that the Z direction in fig. 12 is shown inverted with respect to fig. 7, as in fig. 10. As shown in fig. 12, in the lead-out region HR1, the end portions of the select gate line SGS, the word lines WL0 to WL7, and the select gate line SGD are stepped. In addition, in the lead region HR, the memory chip MC further includes contacts V1 and V2 and conductor layers 37 to 39.

Specifically, the conductor layer 31 has a step surface portion that does not overlap with the lower conductor layers 32 and 33. Each conductor layer 32 has a step surface portion that does not overlap with the lower conductor layers 32 and 33. The conductor layer 33 has a step surface portion in the lead-out region HR 1. The plurality of contacts are respectively disposed on the step surface portions of the conductor layers 31 to 33. For example, the lower portions of the plurality of contacts CT coincide with each other.

An electrical conductor layer 37 is provided under each contact CT. The conductor layer 37 is included in the wiring layer M0. Contact V1 is provided under conductor layer 37. Conductor layer 38 is disposed below contact V1. The conductor layer 38 is included in the wiring layer M1. Contact V2 is disposed below conductor layer 38. Conductor layer 39 is disposed below contact V2. The conductor layer 39 is included in the wiring layer M2. That is, the conductive layer 39 is in contact with the interface of the memory chip MC, and is used as the bonding pad BP. The conductor layer 39 contains copper, for example.

Fig. 12 shows only the sets of contacts V1 and V2 and conductor layers 38 and 39 corresponding to the word line WL 0. In the other conductor layer 37, the sets of contacts V1 and V2 and conductor layers 38 and 39 are connected in an area not shown. The configuration in the region within the lead-out region HR1 and corresponding to the odd-numbered block BLK is similar to the configuration in which the contact CT is omitted with respect to the configuration shown in fig. 12. The structure in the region corresponding to the odd-numbered block BLK in the lead-out region HR2 is similar to the structure shown in fig. 12 in which the Y direction is the axis of symmetry and is reversed.

[1-3-3] structures relating to CMOS chips CC

(planar layout of CMOS chip CC)

Fig. 13 is a plan view of an example of a CMOS chip CC provided in the semiconductor memory device 1 according to embodiment 1, and also shows a connection relationship between the block BLK and the column decoder RD. As shown in fig. 13, the transfer region XR1 includes even-numbered row decoders RD0, RD2, RD4, RD6, RD8, RD10, RD12, and RD 14. The transfer region XR2 includes odd-numbered row decoders RD1, RD3, RD5, RD7, RD9, RD11, RD13, and RD 15. The blocks BLK0 to BLK15 arranged in the Y direction include a block BLK overlapping the sense amplifier region SR when viewed from the Z direction, and a block BLK overlapping the peripheral circuit region PERI when viewed from the Z direction.

For example, the row decoders RD0, RD2, RD4, RD6, RD8, RD10, RD12, and RD14 face the row decoders RD1, RD3, RD5, RD7, RD9, RD11, RD13, and RD15, respectively, in the X direction with the sense amplifier region SR interposed therebetween. The width of each block BLK in the Y direction is, for example, half or less of the width of the column decoder RD in the Y direction. In this example, 2 blocks BLK0 and BLK1 are disposed between column decoders RD0 and RD 1. The 2 blocks BLK2 and BLK3 are arranged between the column decoders RD2 and RD 3. Hereinafter, the 2 blocks BLK are arranged between the 2 column decoders RD facing each other in the X direction.

In addition, the arrangement of the sense amplifier regions SR, the peripheral circuit regions PERI, and the transfer regions XR1 and XR2 described above is merely an example. For example, the ratio of the area occupied by the sense amplifier region SR to the area occupied by the peripheral circuit region PERI may be appropriately changed according to the circuit configuration of the sense amplifier module SAU and the latch circuit XDL or the manufacturing process of the CMOS chip CC. In addition, for example, the arrangement of the column decoder RD connected to each block BLK may be changed as appropriate within the transfer areas XR1 and XR 2. Each block BLK may also be connected to both the column decoder RD disposed in the transfer region XR1 and the column decoder RD disposed in the transfer region XR 2.

(detailed plan layout of sense Amplifier region SR)

Fig. 14 shows an example of a planar layout in the sense amplifier region SR of the CMOS chip CC provided in the semiconductor memory device 1 according to embodiment 1. As shown in fig. 14, in the sense amplifier region SR, the sense amplifier groups SASa and SASb, the cache memory CM, and the conversion circuit SD are respectively arranged in a region extending in the X direction, and are sequentially arranged in the Y direction.

In the region of the sense amplifier group SASa, for example, groups of 8 sense amplifier modules SAUa arranged in the Y direction are arranged in the X direction. Specifically, the sense amplifier elements SAUa < 0 > -SAUa < 7 > are arranged in the Y direction in the vicinity of the transfer region XR 1. The sense amplifier modules SAUa < 8 > -SAUa < 15 > are respectively arranged beside the sense amplifier modules SAUa < 0 > -SAUa < 7 >. Similarly, sense amplifier elements SAUa < 16 > -SAUa < 23 > - …, and sense amplifier elements SAUa < m-8 > -SAUa < m-1 > -are provided.

In the region of the sense amplifier group SASb, for example, groups of 8 sense amplifier modules SAUb arranged in the Y direction are arranged in the X direction. Specifically, the sense amplifier elements SAUb < 0 > -SAUb < 7 > are arranged in the Y direction in the vicinity of the transfer region XR 1. The sense amplifier modules SAUb < 8 > -SAUb < 15 > are respectively arranged beside the sense amplifier modules SAUb < 0 > -SAUb < 7 >. Similarly, sense amplifier modules SAUb & lt 16 > -SAUb & lt 23 > - …, and sense amplifier modules SAUa & lt m-8 > -SAUa & lt m-1 > -are provided.

In the area of the cache memory CM, for example, groups of 8 latch circuits XDL arranged in the Y direction are arranged in the X direction. Specifically, the latch circuits XDL < 0 > -XDL < 7 > are arranged in the Y direction in the vicinity of the transfer region XR 1. The latch circuits XDL < 8 > -XDL < 15 > are respectively arranged beside the latch circuits XDL < 0 > -XDL < 7 >. Similarly, latch circuits XDL < 16 > -XDL < 23 > - …, and latch circuits XDL < m-8 > -XDL < m-1 > -are provided.

In this specification, a group of the sense amplifier elements SAUa and SAUb and the latch circuit XDL arranged in the Y direction is referred to as a sense amplifier group SAG. The number of sense amplifier elements SAU included in 1 sense amplifier group SAG is designed based on the pitch of bit lines BL. For example, in the case where the width in the Y direction of the sense amplifier group SAG is designed according to the pitch of 8 bit lines BL, the sense amplifier group SAG includes 8 sense amplifier devices SAUa and 8 sense amplifier devices SAUb.

In the region overlapping each sense amplifier group SAG, a plurality of bus lines DBUS each having a portion extending in the Y direction are provided corresponding to the number of groups of sense amplifier elements SAUa and SAUb. The latch circuits XDL < 0 > -XDL < m-1 > in the cache memory CM are connected to the conversion circuit SD via wiring not shown. The sense amplifier unit SAU and the latch circuit XDL included in the sense amplifier group SAG may be connected so as to be at least communicable with each other.

(section structure of CMOS chip CC)

Fig. 15 shows an example of a cross-sectional structure of the semiconductor memory device 1 according to embodiment 1, and shows a structure in which the memory chip MC and the CMOS chip CC are bonded together. Fig. 15 shows a configuration in which a transistor T8 in the sense amplifier region SR and a transistor TR6 in the transfer region XR1 are extracted. As shown in fig. 15, CMOS chip CC includes, for example, semiconductor substrate 50, conductor layers GC and 51 to 58, and columnar contacts CS and C0 to C3.

The semiconductor substrate 50 is used for the formation of the CMOS chip CC, and contains, for example, P-type impurities. The semiconductor substrate 50 includes a plurality of well regions, which are not shown. In the plurality of well regions, for example, transistors are formed, respectively. Also, the plurality of well regions are separated from each other by, for example, STI (Shallow Trench Isolation).

In the sense amplifier region SR, a conductor layer GC is provided on the semiconductor substrate 50 through a gate insulating film. The conductor layer GC in the sense amplifier region SR is used as, for example, a gate electrode of the transistor T8 included in the sense amplifier element SAU. A contact C0 is provided above the conductor layer GC corresponding to the gate of the transistor T8, and 2 contacts CS are provided above the semiconductor substrate 50 corresponding to the source and drain of the transistor T8. For example, the upper surface of contact CS coincides with the upper surface of contact C0.

In the sense amplifier region SR, 1 conductor layer 51 is provided on each of the contact CS and the contact C0. Contact C1 is provided on conductor layer 51. An electrical conductor layer 52 is disposed over contact C1. Contact C2 is provided on conductor layer 52. An electrical conductor layer 53 is provided over the contact C2. Contact C3 is provided on conductor layer 53. Conductor layer 54 is disposed over contact C3.

The conductive layer 54 is connected to the interface of the CMOS chip CC and serves as a bonding pad BP. The conductive layer 54 in the sense amplifier region SR is bonded to the conductive layer 36 in the memory region MR disposed opposite to the conductive layer, and is electrically connected to 1 bit line BL. The conductor layer 54 contains copper, for example. The sense amplifier region SR includes a plurality of transistors having the same structure as the transistor T8, although not shown.

In the transfer region XR1, a conductor layer GC is provided on the semiconductor substrate 50 through a gate insulating film. The conductor layer GC within the transfer region XR1 is used, for example, as a gate electrode of the transistor TR6 included in the row decoder RD. A contact C0 is provided above the conductor layer GC corresponding to the gate of the transistor TR6, and 2 contacts CS are provided above the semiconductor substrate 50 corresponding to the source and drain of the transistor TR 6.

In addition, in the transmission region XR1, 1 conductive layer 55 is disposed on each of the contact CS and the contact C0. Contact C1 is provided over conductor layer 55. Conductor layer 56 is disposed over contact C1. Contact C2 is disposed above conductor layer 56. Conductor layer 57 is provided over contact C2. Contact C3 is provided above conductor layer 57. Conductor layer 58 is disposed over contact C3.

The conductive layer 58 is connected to the interface of the CMOS chip CC and serves as a bonding pad BP. The conductive layer 58 in the transfer region XR1 is bonded to the conductive layer 39 in the lead-out region HR1 disposed opposite to the conductive layer, and is electrically connected to the word line WL5, for example. The conductor layer 58 comprises copper, for example. The transfer region XR1 includes a plurality of transistors having the same configuration as the transistor TR6, although not shown. In addition, the configuration in the transfer region XR2 is the same as that of the transfer region XR 1.

Hereinafter, the wiring layer provided with the conductor layers 51 and 55 is referred to as D0. The wiring layer provided with the conductor layers 52 and 56 is referred to as D1. The wiring layer provided with the conductor layers 53 and 57 is referred to as D2. The wiring layer provided with the conductor layers 54 and 58 is referred to as D3. The node containing the conductor layer 53 is referred to as BLI. In addition, the number of wiring layers provided to the CMOS chip CC may be designed to be any number. The contacts connected to each of the conductor layers 51 to 53, 55 to 57 may be omitted depending on the design of the circuit.

[1-3] operation of semiconductor memory device 1

Fig. 16 shows an example of the configuration associated with the sense amplifier units SAUa and SAUb connected to the common bus DBUS and the current path during the read operation in the semiconductor memory device 1 according to embodiment 1. As shown in fig. 16, in the read operation of semiconductor memory device 1 according to embodiment 1, sequencer 13 charges bit line BL connected to NAND string NS included in selected block BLK, and omits charging of bit line BL connected only to NAND string NS included in non-selected block BLK.

Specifically, where block BLK is selected that includes NAND string NS connected to bit line BLb, sequencer 13 charges bit line BLb using sense amplifier component SAUb. As such, a current through the NAND string NS and the bit line BLb contained in the selected block BLK may flow from the sense amplifier component SAUb toward the source line SL. On the other hand, sequencer 13 omits charging (uncharged) of bit line BLa to which only NAND strings NS included in non-selected block BLK are connected. Likewise, in the case where the block BLK including the NAND string NS connected to the bit line BLa is selected, the bit line BLa is charged, and the charging of the bit line BLb is omitted.

In addition, the sequencer 13 can perform a write operation by appropriately charging one of the bit lines BLa and BLb in the same manner as the read operation. In various operations, the sequencer 13 may set the bit line BL connected to the NAND string NS included in the non-selected block BLK to a floating state, or may apply the ground voltage VSS to the bit line BL using the sense amplifier unit SAU.

[1-4] Effect of embodiment 1

According to the semiconductor memory device 1 of embodiment 1 described above, power consumption can be suppressed, and the operating speed can be improved. Hereinafter, the detailed effects of the semiconductor memory device 1 according to embodiment 1 will be described with reference to comparative examples.

In a semiconductor memory device, the pitch of wirings for driving memory cells tends to become narrower as the memory density becomes higher. For example, in the bit lines BL provided at a narrow pitch, the wiring capacitance and the wiring resistance become high. As a result, the RC (resistance-capacitance) time constant of the bit line BL increases, and therefore, the power consumption of the semiconductor memory device increases, and the operation speed of the semiconductor memory device (for example, the processing speed such as the read operation and the write operation) decreases.

As a method of reducing the RC time constant of the bit lines BL provided at a narrow pitch, it is considered to shorten the wiring length of the bit lines BL. For example, by dividing the memory cell array 10 into a plurality of pieces, the wiring length of the bit lines BL controlled by the sense amplifier module 14 can be shortened. In addition, for the divided memory cell array 10, a case where the sense amplifier modules 14 are separately provided and a case where the sense amplifier modules 14 are shared are considered. In the case where it is preferable to suppress the manufacturing cost of the semiconductor memory device, it is preferable to divide the bit lines BL and share the sense amplifier module 14 as much as possible.

An example of a case where the sense amplifier module 14 is shared and the bit lines BL are divided into 2 will be described below. Fig. 17 shows an example of a plan layout of a semiconductor memory device according to a comparative example of embodiment 1. As shown in fig. 17, the semiconductor memory device according to the comparative example of embodiment 1 includes memory cell arrays 10a and 10b and a sense amplifier module 14 on a semiconductor substrate. In the comparative example of embodiment 1, the sense amplifier module 14 is sandwiched between the memory cell arrays 10a and 10 b.

In the comparative example of embodiment 1, the sense amplifier module 14 includes a switch unit SW1 disposed in a portion adjacent to the memory cell array 10a and a switch unit SW2 disposed in a portion adjacent to the memory cell array 10 b. The sense amplifier module 14 selectively controls the bit line BLa connected to the memory cell array 10a and the bit line BLb connected to the memory cell array 10b by operating one of the switches SW1 and SW 2.

As a result, the semiconductor memory device according to the comparative example of embodiment 1 can make the RC time constant of the bit line BL about half, and can improve the operation speed while suppressing power consumption. Specifically, for example, the semiconductor memory device of the comparative example of embodiment 1 can reduce the amount of current necessary for charging the bit line BL by half. However, in the semiconductor memory device according to the comparative example of embodiment 1, the area of the sense amplifier module 14 is increased by the areas of the switch sections SW1 and SW2, and the chip area of the semiconductor memory device is increased.

On the other hand, the semiconductor memory device 1 of embodiment 1 has the following configuration: the memory chip MC and the CMOS chip CC are bonded by controlling the bit lines BLa and BLb divided into 2 by the sense amplifier module 14. Therefore, in the semiconductor memory device 1 according to embodiment 1, the peripheral circuits such as the sense amplifier module 14 overlap the memory cell array 10. In other words, the semiconductor memory device 1 of embodiment 1 can shield the sense amplifier region SR from the memory region MR.

Thus, the semiconductor memory device 1 according to embodiment 1 can make the ratio (cell occupancy ratio) of the area corresponding to the memory cell array 10 in the chip area of the semiconductor memory device larger than that of the comparative example, and can reduce the influence of the sense amplifier region SR on the chip area. In addition, in the semiconductor memory device 1 according to embodiment 1, since the degree of freedom in layout of the sense amplifier region SR is improved, the restriction on the wiring layout by dividing the bit lines BL is smaller than that in the comparative example.

As described above, the semiconductor memory device 1 according to embodiment 1 can make the RC time constant of the bit line BL about half, and thus can reduce the chip area. Therefore, the semiconductor memory device 1 according to embodiment 1 can improve the operation speed while suppressing power consumption as in the comparative example, and can suppress the manufacturing cost as compared with the comparative example.

Further, lowering the RC time constant of the bit line BL is also effective when the amount of current (cell current) flowing through the memory cell becomes small and reading becomes difficult. For example, in a semiconductor memory device in which memory cells are three-dimensionally stacked, if the number of stacked word lines WL increases, the cell current tends to decrease. The structure of the semiconductor memory device 1 according to embodiment 1 is effective in all cases where the cell current may decrease.

In embodiment 1, as a structure in which the memory cell array 10 is divided in the Y direction (the direction in which the bit lines BL extend) and the memory region MR and the sense amplifier region SR overlap each other when viewed from the Z direction, a structure in which the memory chip MC and the CMOS chip CC are bonded to each other has been described, but the structure is not limited to this. For example, a structure in which the memory cell array 10 is divided and the memory region MR overlaps the sense amplifier region SR may be formed using 1 semiconductor substrate. However, this configuration also requires a region containing the contacts that pass through the memory region MR. Therefore, as a structure in which the memory cell array 10 is divided and the memory region MR overlaps the sense amplifier region SR, a structure in which the memory chip MC and the CMOS chip CC are bonded as in embodiment 1 is preferable.

In embodiment 1, the case where the semiconductor memory device 1 includes 1 memory plane (for example, a combination of the memory cell array 10, the sense amplifier module 14, and the row decoder module 16) is illustrated, but the semiconductor memory device 1 may include a plurality of memory planes. In this case, the bit lines BL are divided into a plurality of memory planes, and a plurality of sense amplifier modules 14 for controlling the divided bit lines BL are provided in association with the plurality of memory planes.

[2] Embodiment 2

The semiconductor memory device 1 according to embodiment 2 has a configuration in which the number of bit line BL divisions is changed compared to the semiconductor memory device 1 according to embodiment 1. Differences from embodiment 1 of the semiconductor memory device 1 according to embodiment 2 will be described below.

[2-1] Overall Structure of semiconductor memory device 1

Fig. 18 shows an example of the configuration of the memory cell array 10, the sense amplifier module 14, and the row decoder module 16 included in the semiconductor memory device 1 according to embodiment 2. As shown in fig. 2, in the semiconductor memory device 1 according to embodiment 2, the memory cell array 10 is divided into memory cell arrays 10a, 10b, and 10c, and the sense amplifier module 14 includes sense amplifier groups SASa, SASb, and SASc.

The number of blocks BLK included in each of the memory cell arrays 10a, 10b, and 10c is designed to be arbitrary. The number of blocks BLK included in the memory cell array 10a, the number of blocks BLK included in the memory cell array 10b, and the number of blocks BLK included in the memory cell array 10c may be the same or different.

Bit lines BLc0 to BLc (m-1) are connected to memory cell array 10 c. The same number of bit lines BL may be connected to the memory cell arrays 10a, 10b, and 10c, respectively. The bit lines BLa, BLb, and BLc labeled with the same number may also be regarded as 1 bit line BL corresponding to a wiring in which the memory cell arrays 10a, 10b, and 10c are divided into 3. The bit lines BLa, BLb and BLc labeled with the same number are associated with the same column address CAd, for example.

The sense amplifier groups SASa, SASb, and SASc are respectively associated with the memory cell arrays 10a, 10b, and 10 c. The sense amplifier set SASc includes sense amplifier elements SAUc < 0 > -SAUc < m-1 >. Each sense amplifier unit SAUc is connected to at least 1 bit line BL. For example, sense amplifier modules SAUc < 0 > -SAUc < m-1 > are connected to bit lines BLc 0-BLc (m-1), respectively.

The latch circuits XDL < 0 > -XDL < m-1 > in the cache memory CM are connected to groups of sense amplifier elements SAUa, SAUb, and SAUc via different buses DBUS. Specifically, the latch circuit XDL < 0 > is connected to the sense amplifier modules SAUa < 0 >, SAUb < 0 > and SAUc < 0 >. The latch circuit XDL < 1 > is connected to the sense amplifier modules SAUa < 1 >, SAUb < 1 > and SAUc < 1 >. Similarly, the latch circuit XDL < m-1 > is connected to the sense amplifier modules SAUa < m-1 >, SAUb < m-1 > and SAUc < m-1 >.

[2-2] planar layout of sense Amplifier region SR

Fig. 19 shows an example of a plan layout in the sense amplifier region SR of the CMOS chip CC provided in the semiconductor memory device 1 according to embodiment 2. As shown in fig. 19, in the sense amplifier region SR, the sense amplifier groups SASa, SASb, and SASc, the cache memory CM, and the conversion circuit SD are respectively arranged in a region extending in the X direction, and are sequentially arranged in the Y direction. In the region of the sense amplifier group SASc, for example, groups of 8 sense amplifier elements SAUc arranged in the Y direction are arranged in the X direction.

Specifically, the sense amplifier elements SAUc < 0 > -SAUc < 7 > are arranged in the Y direction in the vicinity of the transfer region XR 1. The sense amplifier modules SAUc < 8 > -SAUc < 15 > are respectively arranged beside the sense amplifier modules SAUc < 0 > -SAUc < 7 >. Similarly, sense amplifier modules SAUc < 16 > -SAUc < 23 > - …, and sense amplifier modules SAUc < m-8 > -SAUc < m-1 > -are provided. In the semiconductor memory device 1 according to embodiment 2, the sense amplifier group SAG includes sense amplifier elements SAUa, SAUb, and SAUc, and a latch circuit XDL. The other configurations of the semiconductor memory device 1 according to embodiment 2 are the same as those of embodiment 1.

[2-3] operation of semiconductor memory device 1

Fig. 20 shows an example of the configuration associated with the sense amplifier modules SAUa, SAUb, and SAUc connected to the common bus DBUS and an example of the current path during the read operation in the semiconductor memory device 1 according to embodiment 2. As shown in fig. 20, in the read operation of semiconductor memory device 1 according to embodiment 2, sequencer 13 charges bit lines BL connected to NAND strings NS included in a selected block BLK, and omits charging of bit lines BL connected only to NAND strings NS included in non-selected blocks BLK, as in embodiment 1.

Specifically, where block BLK is selected that includes NAND string NS connected to bit line BLc, sequencer 13 charges bit line BLc using sense amplifier component SAUc. As such, current through the NAND string NS and the bit line BLc contained in the selected block BLK may flow from the sense amplifier component SAUc toward the source line SL. On the other hand, sequencer 13 omits charging (uncharged) of bit lines BLa and BLb to which only NAND strings NS included in the non-selected block BLK are connected. The operation when selecting the block BLK corresponding to the other bit line BL is the same as the operation when selecting the block BLK corresponding to the bit line BLc.

Similarly to the read operation, the sequencer 13 may also perform the write operation by appropriately charging any one of the bit lines BLa, BLb, and BLc. In various operations, the sequencer 13 may set the bit line BL connected to the NAND string NS included in the non-selected block BLK to a floating state, or may apply the ground voltage VSS to the bit line BL using the sense amplifier unit SAU.

[2-4] Effect of embodiment 2

As described above, the semiconductor memory device 1 according to embodiment 2 controls the bit lines BL divided into smaller sections than those according to embodiment 1 independently in the same memory plane. Thus, in the semiconductor memory device 1 according to embodiment 2, the wiring resistance and capacitance of the bit line BL are smaller than those of embodiment 1. Therefore, the semiconductor memory device 1 of embodiment 2 can suppress power consumption and improve operation speed compared to embodiment 1.

In embodiment 2, the case where the bit lines BL are divided into 3 is exemplified, but the bit lines BL may be divided into 4 or more. In this case, for example, 4 sense amplifier elements SAU are provided corresponding to the bit lines BL divided into 4, respectively. As described above, even if the number of bit lines BL divided is 4 or more, the semiconductor memory device 1 may be provided with a circuit capable of independently controlling the divided bit lines BL. As the number of divided bit lines BL increases, power consumption can be suppressed and the operation speed can be increased.

In addition, in the structure in which the memory cell array 10 and the sense amplifier module 14 are provided on the semiconductor substrate, the bit lines BL can be divided into 3 or more. However, when the bit lines BL are divided into 3 or more in such a structure, the layout of the wiring and the like become difficult. Therefore, when the bit lines BL divided into 3 or more parts in the same memory plane are provided, it is preferable to use a structure in which the memory chip MC and the CMOS chip CC are bonded as in the semiconductor memory device 1 according to embodiment 2.

[3] Embodiment 3

The semiconductor memory device 1 according to embodiment 3 has a configuration in which a part of latch circuits other than the latch circuit XDL is shared by the sense amplifier modules SAUa and SAUb, as compared with the semiconductor memory device 1 according to embodiment 1. Differences from embodiments 1 and 2 of the semiconductor memory device 1 according to embodiment 3 will be described below.

[3-1] Circuit configuration of sense Amplifier Module 14

Fig. 21 shows an example of the circuit configuration of the sense amplifier module 14 included in the semiconductor memory device 1 according to embodiment 3, and shows a detailed circuit configuration of the sense amplifier modules SAUa and SAUb. As shown in fig. 21, each sense amplifier unit SAU in embodiment 3 has a configuration in which latch circuits ADL and BDL are omitted from the sense amplifier unit SAU described in embodiment 1. Specifically, each sense amplifier element SAU includes a bit line connection portion BLHU, a sense amplifier portion SA, a latch circuit SDL, and a transistor DTR.

The sense amplifier module 14 included in the semiconductor memory device 1 according to embodiment 3 further includes a data latch group DLS. The data latch set DLS includes data latch components DLU < 0 > -DLU < m-1 >. For example, each data latch component DLU includes latch circuits ADL and BDL. The latch circuits ADL and BDL included in the data latch units DLU are connected to the associated bus DBUS, respectively. The data latch component DLU is less than 0 to m-1, and is respectively associated with the latch circuit XDL is less than 0 to m-1.

The data latch unit DLU < 0 > can transmit and receive data to and from the sense amplifier unit SAUa < 0 > and the sense amplifier unit SAUb < 0 > respectively via the associated bus DBUS. Similarly, the other data latch elements DLU can transmit and receive data to and from the sense amplifier elements SAUa and SAUb, respectively, via the associated bus DBUS. For example, when the operation of selecting the block BLK in the memory cell array 10a is performed, the sequencer 13 controls the control signals DSWa and DSWb to "H" and "L" levels, respectively. Similarly, when the operation of selecting the block BLK in the memory cell array 10b is performed, the sequencer 13 controls the control signals DSWa and DSWb to "L" and "H" levels, respectively.

[3-2] planar layout of sense Amplifier region SR

Fig. 22 shows an example of a plan layout in the sense amplifier region SR of the CMOS chip CC provided in the semiconductor memory device 1 according to embodiment 3. As shown in fig. 22, in the sense amplifier region SR, the sense amplifier groups SASa and SASb, the data latch group DLS, the cache memory CM, and the conversion circuit SD are arranged in a region extending in the X direction, and are sequentially arranged in the Y direction. In the area of the data latch group DLS, for example, groups of 8 data latch elements DLU arranged in the Y direction are arranged in the X direction.

Specifically, data latch elements DLU < 0 > -DLU < 7 > are arranged in the Y direction in the vicinity of transfer region XR 1. Data latch components DLU < 8 > -15 > are respectively arranged beside the data latch components DLU < 0 > -DLU < 7 >. Similarly, data latch elements DLU < 16 > -DLU < 23 >, …, and DLU < m-8 > -DLU < m-1 > -are configured. In the semiconductor memory device 1 according to embodiment 3, the sense amplifier group SAG includes sense amplifier elements SAUa and SAUb, a data latch element DLU, and a latch circuit XDL.

In addition, the data latch set DLS may also be disposed between the sense amplifier elements SAUa and SAUb. Fig. 23 shows an example of a plan layout in the sense amplifier region SR of the CMOS chip CC provided in the semiconductor memory device 1 according to the variation of embodiment 3. As shown in fig. 23, in the sense amplifier region SR, the sense amplifier group SASa, the data latch group DLS, the sense amplifier group SASb, the cache memory CM, and the conversion circuit SD are arranged in a region extending in the X direction, and are sequentially arranged in the Y direction. As described above, the sense amplifier unit SAU, the data latch unit DLU, and the latch circuit XDL included in the sense amplifier group SAG are connected so as to be at least communicable with each other. The other configurations of the semiconductor memory device 1 according to embodiment 3 are the same as those of embodiment 1.

[3-3] Effect of embodiment 3

As described above, in the semiconductor memory device 1 according to embodiment 3, the sense amplifier units SAU sharing the bus DBUS share some of the latch circuits ADL and BDL. Thus, in the semiconductor memory device 1 according to embodiment 3, the area occupied by the latch circuit in the sense amplifier region SR can be reduced. Therefore, the semiconductor memory device 1 according to embodiment 3 can reduce the chip area and suppress the manufacturing cost of the semiconductor memory device 1 as compared with embodiment 1.

[4] Embodiment 4

The semiconductor memory device 1 according to embodiment 4 has a configuration in which an amplifier circuit different from the sense amplifier unit SA is added to the semiconductor memory device 1 according to embodiment 3. Differences from embodiments 1 to 3 of the semiconductor memory device 1 according to embodiment 4 will be described below.

[4-1] Circuit configuration of sense Amplifier Module 14

Fig. 24 shows an example of a circuit configuration of the sense amplifier module 14 included in the semiconductor memory device 1 according to embodiment 4. As shown in fig. 24, the sense amplifier module 14 in embodiment 4 includes a sense amplifier group SAS, a data latch group DLS, a cache memory CM, a conversion circuit SD, and local amplifier groups las and las. In addition, in the sense amplifier module 14 according to embodiment 4, a plurality of global bit lines GBL are provided corresponding to the plurality of bus lines DBUS, respectively. The data latch group DLS, the cache memory CM, and the conversion circuit SD have the same configurations as those of embodiment 3, for example.

In the semiconductor memory device 1 according to embodiment 4, each sense amplifier unit SAU has a configuration in which the bit line connection portion BLHU is omitted from the sense amplifier unit SAU described in embodiment 3. The sense amplifier modules SAU < 0 > -SAU < m-1 > are connected to the latch circuits XDL < 0 > -XDL < m-1 > via the bus DBUS, respectively. In addition, in semiconductor memory device 1 according to embodiment 4, sense amplifier unit SA in sense amplifier unit SAU is connected to global bit line GBL instead of being connected to bit line connection BLHU.

The local amplifier groups las a and LASb are associated with the memory cell arrays 10a and 10b, respectively. The local amplifier set LASa includes local amplifier elements LAUa < 0 > -LAUa < m-1 >. The local amplifier group LASb includes local amplifier elements LAUb < 0 > -LAUb < m-1 >. Each local amplifier unit LAU includes an amplification circuit AC and a bit line connection BLHU.

The amplification circuit AC in each local amplifier unit LAU is connected to the associated global bit line GBL. Each amplification circuit AC is connected to the associated bit line BL via a bit line connection BLHU. Specifically, the bit line connections BLHU of the local amplifier modules LAUa < 0 > -LAUa < m-1 > are connected to the bit lines BLa 0-BLa (m-1), respectively. The local amplifier modules LAUb < 0 > -LAUb < m-1 > have their respective bit line connections BLHU connected to the bit lines BLb 0-BLb (m-1), respectively. In this way, a plurality of local amplifier units LAU are connected to each global bit line GBL.

Fig. 25 shows an example of a detailed circuit configuration of the sense amplifier unit SA and the local amplifier unit LAU in the semiconductor memory device 1 according to embodiment 4. Note that fig. 25 omits illustration of the transistor T21 in the bit line connection BLHU. As shown in fig. 25, the circuit configuration of the sense amplifier unit SA is the same as that of the sense amplifier unit SA described in embodiment 1, except that the global bit line GBL is connected to the transistor T4. The local amplifier modules LAUa and LAUb have similar configurations, respectively. For example, each local amplifier unit LAU includes transistors T40-T42. The transistors T40 to T42 are, for example, N-type MOS transistors.

In each local amplifier unit LAU, the drain of the transistor T40 is connected to the global bit line GBL. The source of the transistor T40 is connected to the node ND 3. The drain of the transistor T41 is connected to the global bit line GBL. The gate of the transistor T41 is connected to the node ND 3. The drain of the transistor T42 is connected to the source of the transistor T41. The source of the transistor T42 is connected to ground. The control signal GSW is input to the gate of the transistor T42.

The control signal BSWa is input to the gate of the transistor T40 in the local amplifier module LAUa. The node ND3 in the local amplifier module LAUa is connected to the bit line BLa via the transistor T20 to which the control signal BLSa is input. Similarly, the control signal BSWb is input to the gate of the transistor T40 in the local amplifier unit LAUb. The node ND3 in the local amplifier unit LAUb is connected to the bit line BLb via the transistor T20 to which the control signal BLSb is input.

In the circuit configuration of the sense amplifier unit SAU described above, the control signals BSWa, BSWb, GSW, BLSa, and BLSb are generated by the sequencer 13, respectively, for example. The control signals in the local amplifier modules LAUa and LAUb may be shared as appropriate as long as they can perform the following operations.

[4-2] planar layout of sense Amplifier region SR

Fig. 26 shows an example of a plan layout in the sense amplifier region SR of the CMOS chip CC provided in the semiconductor memory device 1 according to embodiment 4. As shown in fig. 26, in the sense amplifier region SR, the local amplifier groups las and LASb, the sense amplifier group SAS, the data latch group DLS, the cache memory CM, and the conversion circuit SD are arranged in a region extending in the X direction, and are arranged in the Y direction in order.

In the region of the local amplifier group las, for example, groups of 8 local amplifier modules LAUa arranged in the Y direction are arranged in the X direction. Specifically, the local amplifier assemblies LAUa < 0 > -LAUa < 7 > are arranged in the Y direction in the vicinity of the transfer region XR 1. Local amplifier modules LAUa < 8 > -LAUa < 15 > are respectively arranged beside the local amplifier modules LAUa < 0 > -LAUa < 7 >. Similarly, local amplifier modules LAUa < 16 > -LAUa < 23 > - …, and local amplifier modules LAUa < m-8 > -LAUa < m-1 > -are provided.

In the region of the local amplifier group LASb, for example, groups of 8 local amplifier modules LAUb arranged in the Y direction are arranged in the X direction. Specifically, the local amplifier assemblies LAUb < 0 > -LAUb < 7 > are arranged in the Y direction in the vicinity of the transfer region XR 1. Local amplifier modules LAUb < 8 > -LAUb < 15 > are respectively arranged beside the local amplifier modules LAUb < 0 > -LAUb < 7 >. Similarly, local amplifier modules LAUb < 16 > -LAUb < 23 > - …, and local amplifier modules LAUb < m-8 > -LAUb < m-1 > -are provided.

The configurations of the sense amplifier module SAU in the sense amplifier group SAS, the data latch module DLU in the data latch group DLS, and the latch circuit XDL in the cache memory CM are the same as those in embodiment 3. In the semiconductor memory device 1 according to embodiment 4, the sense amplifier group SAG includes local amplifier devices LAUa and LAUb, a sense amplifier device SAU, a data latch device DLU, and a latch circuit XDL.

In a region overlapping each sense amplifier group SAG, a plurality of global bit lines GBL each having a portion extending in the Y direction are provided corresponding to the number of local amplifier elements LAUa and LAUb. In the semiconductor memory device 1 according to embodiment 4, the pitch of the global bit lines GBL is designed to be the same as the pitch of the bit lines BL, for example. The sense amplifier unit SAU, the data latch unit DLU, and the latch circuit XDL included in the sense amplifier group SAG may be connected so as to be at least communicable with each other. The other configurations of the semiconductor memory device 1 according to embodiment 4 are the same as those of embodiment 1.

[4-3] operation of semiconductor memory device 1

Fig. 27 shows an example of the configuration associated with the local amplifier units LAUa and LAUb connected to the common global bit line GBL and the current path during the read operation in the semiconductor memory device 1 according to embodiment 4. As shown in fig. 27, in the read operation of semiconductor memory device 1 according to embodiment 4, sequencer 13 charges bit lines BL connected to NAND strings NS included in a selected block BLK, and omits charging of bit lines BL connected only to NAND strings NS included in non-selected blocks BLK, as in embodiment 1. Also, the sequencer 13 amplifies the sense current by using the local amplifier component LAU.

Specifically, in the case of selecting the block BLK including the NAND string NS connected to the bit line BLb, first, the sequencer 13 controls the transistors T20 and T40 within the local amplifier component LAUb to be on-state. Then, the sense amplifier component SAU charges the bit line BLb via the local amplifier component LAUb. Thereafter, the sequencer 13 controls the transistor T40 in the local amplifier module LAUb to be in an off state, and applies a read voltage to the selected word line WL.

Thus, the voltage of the node ND3 of the local amplifier component LAUb varies based on the state of the selected memory cell transistor MT. Specifically, when the selected memory cell transistor MT is in an on state, a current (1) flowing through the memory cell transistor MT flows from the node ND3 toward the source line SL. As a result, the voltage at the node ND3 drops to the "L" level. On the other hand, when the selected memory cell transistor MT is in the off state, the voltage of the node ND3 maintains the "H" level.

Then, the sequencer 13 brings the control signal GSW to the "H" level. When a voltage of "H" level is applied to the gate of the transistor T42, the transistor T41 in the local amplifier module LAUb becomes an on state or an off state based on the voltage of the node ND 3. When the voltage at the node ND3 is at "H" level, the current (2) flowing through the transistors T41 and T42 in the local amplifier unit LAUb flows from the sense amplifier unit SAU toward the ground line, and the voltage of the global bit line GBL drops. On the other hand, when the voltage at the node ND3 is at the "L" level, the global bit line GBL maintains a high voltage.

Thus, the sense amplifier unit SAU may determine read data of the selected memory cell transistor MT based on the voltage of the global bit line GBL. The operation when selecting the block BLK corresponding to the other bit line BL is the same as the operation when selecting the block BLK corresponding to the bit line BLb.

The following describes the details of the read operation of the semiconductor memory device 1 according to embodiment 4. Hereinafter, the selected word line WL is referred to as WLsel. The selected and unselected bit lines BL are referred to as BLsel and BLusel, respectively. The control signal BSW input to the transistor T40 in the local amplifier element LAU connected to the bitline BLsel is referred to as BSWsel. The control signal BSW input to the transistor T40 in the local amplifier unit LAU connected to the bit line blu is referred to as BSWusel. The voltage applied to the word line WL is controlled by a driver module 15 and a row decoder module 16.

Fig. 28 is an example of a timing chart of a read operation of the semiconductor memory device 1 according to embodiment 4, and shows changes in control signals and the like corresponding to the NAND string NS, the local amplifier unit LAU, and the sense amplifier unit SAU. As shown in fig. 28, in the reading operation, the sequencer 13 sequentially executes the processing from time t0 to time t 9. The voltage of each control signal and each wiring before the read operation is performed is VSS, for example.

At time t0, VCG is applied to word line WLsel and VSGS is applied to select gate line SGS. VCG is the readout voltage. VSGS is a voltage that can turn on the selection transistor ST2 in the read operation. In addition, sequencer 13 raises control signal HLL to, for example, 4V, and raises control signal XXL to, for example, 0.9V + Vt (the Vt corresponding to the threshold voltage of transistor T3). Then, the node SEN is charged, and the voltage of the node SEN rises to VDDSA.

At time T1, sequencer 13 raises control signal BLS to, for example, 4V, control signal BSWsel to, for example, 4V, and control signal BLC to, for example, 0.7V + Vt (which corresponds to the threshold voltage of transistor T4). Then, the voltages of the bit line BLsel and the global bit line GBL rise to, for example, 0.7V, respectively. On the other hand, in the local amplifier unit LAU connected to the bit line blu, the control signal BSWusel is VSS, for example. Therefore, the transistor T40 connected to the bit line BLusel is kept off, and the voltage on the bit line BLusel is kept VSS. Thus, in the operation at time t1, bit line BLsel is charged and bit line BLusel is not charged.

At time t2, sequencer 13 drops control signal BSWsel to VSS and control signal BLC to VSS. Thus, the voltage of the node SEN in the sense amplifier unit SAU connected to the bit line BLsel is fixed to VDDSA.

At time t3, VSGD is applied to the select gate line SGD. VSGD is a voltage that can turn on the selection transistor ST1 in the read operation. When the selection transistor ST1 is turned on, the voltage of the bit line BLsel changes based on data stored in the selected memory cell transistor MT. Specifically, the voltage of the bit line BLsel connected to the memory cell transistor MT (on cell) turned on by VCG is decreased, and the voltage of the bit line BLsel connected to the memory cell transistor MT (off cell) maintained in the off state by VCG is maintained at, for example, 0.7V.

At time t4, sequencer 13 raises control signal GSW to VDD. Then, in the local amplifier unit LAU connected to the bit line BLsel, when the voltage of the bit line BLsel is, for example, 0.7V, the transistors T41 and T42 are turned on, and the voltage of the global bit line GBL drops. On the other hand, when the voltage of bit line BLsel is VSS, for example, transistor T41 remains off, and the voltage of global bit line GBL is maintained. Thus, in the operation at time t4, the voltage of global bit line GBL connected to the on-cell is maintained, and the voltage of global bit line GBL connected to the off-cell is lowered.

At time t5, sequencer 13 drops control signal HLL to VSS. Thereby, the charging of the node SEN via the transistors T0 and T2 is stopped.

At time T6, sequencer 13 raises control signal BLC to 0.4V + Vt (which corresponds to the threshold voltage of transistor T4). Then, the voltage of node SEN changes based on the voltage of global bit line GBL. Specifically, the global bit line GBL connected to the on cell maintains a high voltage, and thus the voltage of the node SEN maintains a high voltage. On the other hand, global bit line GBL connected to the disconnection unit has a low voltage, and therefore, the voltage of node SEN decreases.

At time t7, sequencer 13 drops control signal BLC to VSS and control signal XXL to VSS. Then, the transistors T3 and T4 are turned off, and the voltage of the node SEN is fixed.

At time t8, sequencer 13 determines control signal STB. That is, the sequencer causes the control signal STB to temporarily rise to the "H" level. Thus, the voltage of bus LBUS varies based on the voltage of node SEN. Specifically, since the node SEN connected to the turn-on unit maintains a high voltage, the transistor T7 is turned on, and the voltage of the bus line LBUS drops. Since the node SEN connected to the disconnecting unit has a low voltage, the transistor T7 maintains the off state, and the voltage of the bus LBUS is maintained high. Then, the sequencer 13 holds data based on the voltage value of the bus LBUS in any latch circuit within the sense amplifier block 14.

At time t9, the voltage of word line WLsel and select gate lines SGS and SGD, respectively, drops to VSS. In addition, the sequencer 13 lowers the control signals GSW and BLS to VSS, respectively.

As described above, the semiconductor memory device 1 according to embodiment 4 can perform the read operation. Similarly to the read operation, the sequencer 13 may also perform the write operation by appropriately charging one of the bit lines BLa and BLb. In the write operation, the transistor T40 in the local amplifier unit LAU corresponding to the selected block BLK is controlled to be on. In various operations, the sequencer 13 may set the bit line BL connected to the NAND string NS included in the non-selected block BLK to a floating state, or may apply the ground voltage VSS to the bit line BL using the sense amplifier unit SAU.

[4-4] Effect of embodiment 4

As described above, the semiconductor memory device 1 according to embodiment 4 includes the plurality of local amplifier modules LAU each including the amplification circuit AC, and performs the 2-stage read operation using each of the local amplifier modules LAU and the sense amplifier modules SAU. Thus, the semiconductor memory device 1 according to embodiment 4 can amplify the cell current during the read operation, and can improve the accuracy of the read operation. Therefore, the semiconductor memory device 1 according to embodiment 4 can obtain the same effects as those of embodiment 1, and can reduce read errors.

[5] Embodiment 5

The semiconductor memory device 1 according to embodiment 5 has a configuration in which the number of local amplifier modules LAU connected to the global bit lines GBL is increased, compared to the semiconductor memory device 1 according to embodiment 1. Differences from embodiments 1 to 4 of the semiconductor memory device 1 according to embodiment 5 will be described below.

[5-1] Circuit constitution of sense Amplifier Module 14

Fig. 29 shows an example of a circuit configuration of the sense amplifier module 14 included in the semiconductor memory device 1 according to embodiment 5, in which a configuration associated with 1 global bit line GBL is extracted. As shown in FIG. 29, the sense amplifier module 14 includes a latch circuit XDL < k > (k is an even number), a data latch element DLU < k >, a sense amplifier element SAU < k >, local amplifier elements LAUa < k > and LAUa < k +1 >, and local amplifier elements LAUb < k > and LAUb < k +1 >.

The latch circuit XDL < k > is connected to the data latch element DLU < k > and the sense amplifier element SAU < k > via a bus DBUS. Sense amplifier units SA in sense amplifier units SAU < k > are connected to global bit lines GBL. The global bit-line GBL is connected to the respective amplification circuits AC of the local amplifier modules LAUa < k >, LAUa < k +1 >, LAUb < k > and LAU < k +1 >. That is, in embodiment 5, 4 local amplifier modules LAU are connected to 1 global bit line GBL. In the semiconductor memory device 1 of embodiment 5, the pitch of the global bit lines GBL may be designed to be wider than the pitch of the bit lines BL.

Fig. 30 shows an example of a detailed circuit configuration of the local amplifier module LAU in the semiconductor memory device 1 according to embodiment 5. As shown in fig. 30, the circuit configuration of the local amplifier module LAU is the same as that of the local amplifier module LAU described in embodiment 4. In the semiconductor memory device 1 according to embodiment 5, the control signal BSWa1 is input to the gate of the transistor T40 in the local amplifier module LAUa < k >. A control signal BSWa2 is input to the gate of the transistor T40 in the local amplifier element LAUa < k +1 >. The control signal BSWb1 is input to the gate of the transistor T40 in the local amplifier element LAUb < k >. The control signal BSWb2 is input to the gate of the transistor T40 in the local amplifier element LAUb < k +1 >. The other configurations of the semiconductor memory device 1 according to embodiment 5 are the same as those of embodiment 4.

[5-2] Effect of embodiment 5

As described above, the semiconductor memory device 1 according to embodiment 5 has a configuration in which more local amplifier modules LAU than those according to embodiment 4 are connected to the global bit lines GBL. In this case, the semiconductor memory device 1 according to embodiment 5 may perform a read operation in series on a plurality of bit lines BL sharing the global bit line GBL by independently controlling the local amplifier module LAU of the shared global bit line GBL, for example. In semiconductor memory device 1 according to embodiment 5, global bit lines GBL have a wider pitch than those according to embodiment 4. That is, semiconductor memory device 1 according to embodiment 5 can reduce the wiring capacitance and wiring resistance of global bit line GBL as compared with embodiment 4.

[6] Embodiment 6

The semiconductor memory device 1 according to embodiment 6 performs a read operation with a part of the bit lines BL shielded from the semiconductor memory device 1 according to embodiment 5. Differences from embodiments 1 to 5 of the semiconductor memory device 1 according to embodiment 6 will be described below.

[6-1] Circuit configuration of sense Amplifier Module 14

Fig. 31 shows an example of a detailed circuit configuration of the local amplifier module LAU in the semiconductor memory device 1 according to embodiment 6. As shown in fig. 31, the local amplifier module LAU according to embodiment 6 has a configuration in which a transistor T43 is added to the local amplifier module LAU described in embodiment 4.

Specifically, in each local amplifier unit LAU, the drain of the transistor T43 is connected to the node ND 3. The source of the transistor T43 is connected to the node RST. A control signal BRSTa1 is input to the gate of the transistor T43 in the local amplifier unit LAUa < k >. The control signal BRSTa2 is input to the gate of the transistor T43 in the local amplifier element LAUa < k +1 >. The control signal BRSTb1 is input to the gate of the transistor T43 in the local amplifier unit LAUb < k >. The control signal BRSTb2 is input to the gate of the transistor T43 in the local amplifier unit LAUb < k +1 >. The other configurations of the semiconductor memory device 1 according to embodiment 6 are the same as those of embodiment 5.

[6-2] operation of semiconductor memory device 1

The operation of the semiconductor memory device 1 according to embodiment 6 will be described below. Hereinafter, the local amplifier unit LAU connected to the odd-numbered bit line BL is referred to as a local amplifier unit LAUo, and the local amplifier unit LAU connected to the even-numbered bit line BL is referred to as a local amplifier unit LAUe.

The operation of the semiconductor memory device 1 according to embodiment 6 on the non-selected block BLK is the same as that according to embodiments 4 and 5, for example. On the other hand, in the semiconductor memory device 1 according to embodiment 6, the operation on the bit line BL connected to the selected block BLK differs between the local amplifier elements LAUo and LAUe. For example, in fig. 31, when the block BLK to which the bit line BLa is connected is selected, the bit line BLa < k > is set to an active state (for example, the bit line BL to be read), and the bit line BLa < k +1 > is set to a shield state. On the other hand, the unselected block BLK to which the bit line BLb is connected is set to a non-operating state (for example, the same state as the shielding state). The following description focuses on the operation of the bit line BL set to the active state.

(read operation)

In the read operation of semiconductor memory device 1 according to embodiment 6, sequencer 13 charges bit lines BL connected to NAND strings NS included in a selected block BLK, and omits charging of bit lines BL connected only to NAND strings NS included in a non-selected block BLK, as in embodiment 4. In the semiconductor memory device 1 according to embodiment 6, the odd-numbered bit lines BL and the even-numbered bit lines BL are grouped, and the sequencer 13 performs a read operation for each group of the bit lines BL.

Fig. 32 shows an example of the configuration associated with the local amplifier modules LAUo and LAUe connected to the common global bit line GBL and the current path during the read operation in the semiconductor memory device 1 according to embodiment 6. As shown in fig. 32, in the read operation, the sequencer 13 masks the even-numbered bit lines BL when selecting the memory cell transistors MT connected to the odd-numbered bit lines BL, and masks the odd-numbered bit lines BL when selecting the memory cell transistors MT connected to the even-numbered bit lines BL.

Specifically, the sequencer 13 makes the voltage of the node RST VSS. The sequencer 13 controls the transistor T43 of the local amplifier unit LAU corresponding to the shielded bit line BL to be in an on state, and controls the transistor T43 of the local amplifier unit LAU corresponding to the bit line BL connected to the selected memory cell transistor MT to be in an off state. Then, the sequencer 13 maintains this state and performs a read operation. Other operations in the read operation of the semiconductor memory device 1 according to embodiment 6 are the same as those according to embodiments 4 and 5.

(write action)

In the write operation of semiconductor memory device 1 according to embodiment 6, sequencer 13 charges bit lines BL connected to NAND strings NS included in a selected block BLK, and omits charging of bit lines BL connected only to NAND strings NS included in a non-selected block BLK, as in embodiment 4. In the semiconductor memory device 1 according to embodiment 6, the odd-numbered bit lines BL and the even-numbered bit lines BL are grouped, and the sequencer 13 performs a write operation for each group of the bit lines BL.

Fig. 33 shows an example of the configuration associated with the local amplifier modules LAUo and LAUe connected to the common global bit line GBL and the current path during the write operation in the semiconductor memory device 1 according to embodiment 6. As shown in fig. 33, in the write operation, the sequencer 13 sets the voltage of the node RST to VDD. The sequencer 13 controls the transistor T43 of the local amplifier unit LAU corresponding to the shielded bit line BL to be in an on state, and controls the transistor T43 in the local amplifier unit LAU corresponding to the bit line BL connected to the selected memory cell transistor MT to be in an off state.

Thus, the select transistor ST1 included in the selected block BLK and connected to the shielded bit line BL is turned off, and the channel in the NAND string NS is in a floating state. On the other hand, the selection transistor ST1 included in the selected block BLK and connected to the bit line BL to be written is turned on when a voltage corresponding to write data (for example, "0" data) is applied to the bit line BL, and is turned off when a voltage corresponding to non-write data (for example, "1" data) is applied thereto. Then, the sequencer 13 performs a write operation while maintaining this state as appropriate. Other operations in the write operation of the semiconductor memory device 1 according to embodiment 6 are the same as those in embodiments 4 and 5.

[6-3] Effect of embodiment 6

As described above, the semiconductor memory device 1 according to embodiment 6 can perform a read operation in which a part of the bit lines BL is shielded. Thus, the semiconductor memory device 1 according to embodiment 6 can suppress noise generated in the bit line BL during the read operation. Therefore, the semiconductor memory device 1 according to embodiment 6 can obtain the same effects as those of embodiment 5, and can reduce read errors.

[7] Embodiment 7

The semiconductor memory device 1 according to embodiment 7 has a configuration in which the amplifier circuit AC is replaced with a local sense amplifier, as compared with the semiconductor memory device 1 according to embodiment 4. Differences from embodiments 1 to 6 of the semiconductor memory device 1 according to embodiment 7 will be described below.

[7-1] Circuit constitution of sense Amplifier Module 14

Fig. 34 shows an example of a circuit configuration of the sense amplifier module 14 included in the semiconductor memory device 1 according to embodiment 7. As shown in fig. 34, the sense amplifier module 14 according to embodiment 7 has the same circuit configuration as the sense amplifier module 14 according to embodiment 4 described with reference to fig. 24. The local amplifier unit LAU according to embodiment 7 has a configuration in which the amplification circuit AC described in embodiment 4 is replaced with the local sense amplifier LSA. Local sense amplifier LSA is connected between global bit line GBL and bit line connection portion BLHU, as in embodiment 4. In the semiconductor memory device 1 according to embodiment 7, the pitch of the global bit lines GBL is designed to be the same as the pitch of the bit lines BL, for example.

Fig. 35 shows an example of a circuit configuration of a local sense amplifier LSA included in the semiconductor memory device 1 according to embodiment 7, in which a configuration associated with 1 global bit line GBL is extracted and shown. As shown in fig. 35, the local sense amplifiers LSAa and LSAb have similar circuit configurations, respectively. For example, each local sense amplifier LSA includes transistors T50 to T57 and a capacitor CA _ L. The transistors T50 to T57 are N-type MOS transistors.

In each local sense amplifier LSA, the source of the transistor T50 is connected to the node ND4 connected to the power supply line. The drain of the transistor T50 is connected to the node ND 5. The drain of the transistor T51 is connected to the node ND 4. The source of transistor T51 is connected to node SEN _ L. The drain of the transistor T52 is connected to the node SEN _ L. The source of the transistor T52 is connected to the node ND 5. The drain of the transistor T53 is connected to the node ND 5. The source of transistor T53 is connected to node BLI.

The drain of the transistor T54 is connected to the global bit line GBL. The drain of the transistor T55 is connected to the source of the transistor T54. The source of the transistor T55 is connected to the node CLK _ L. The gate of transistor T55 is connected to node SEN _ L. One electrode of the capacitor CA _ L is connected to the node SEN _ L. The other electrode of the capacitor CA _ L is connected to the node CLK _ L. The drain of the transistor T56 is connected to the node RST. The source of transistor T56 is connected to node BLI. The drain of the transistor T57 is connected to the global bit line GBL. The source of transistor T57 is connected to node BLI.

Control signals BLX _ La, HLL _ La, XXL _ La, BLC _ La, STB _ La, BRSTa, and BYPa are input to the gates of the transistors T50 to T54, T56, and T57 in the local sense amplifier LSAa, respectively. Similarly, control signals BLX _ Lb, HLL _ Lb, XXL _ Lb, BLC _ Lb, STB _ Lb, BRSTb, and BYPb are input to respective gates of the transistors T50 to T54, T56, and T57 in the local sense amplifier LSAb. The control signals in the local sense amplifiers LSAa and LSAb may be shared as appropriate as long as the following operations can be performed. The other configurations of the semiconductor memory device 1 according to embodiment 7 are the same as those of embodiment 4.

[7-2] operation of semiconductor memory device 1

(read operation)

Fig. 36 shows an example of the configuration associated with the local amplifier units LAUa and LAUb connected to the common global bit line GBL and the current path during the read operation in the semiconductor memory device 1 according to embodiment 7. As shown in fig. 36, in the read operation of semiconductor memory device 1 according to embodiment 7, sequencer 13 charges bit lines BL connected to NAND strings NS included in a selected block BLK, and omits charging of bit lines BL connected only to NAND strings NS included in a non-selected block BLK. Also, the sequencer 13 amplifies the sense current by using the local amplifier component LAU.

Specifically, in the case where block BLK including NAND string NS connected to bit line BLb is selected, first, sequencer 13 charges bit line BLb using local sense amplifier LSAb. Thereafter, a read voltage is applied to the selected word line WL, and the voltage of the node SEN _ L in the local amplifier assembly LAUb changes based on the state of the selected memory cell transistor MT. Specifically, when the selected memory cell transistor MT is in an on state, a current (1) flowing through the memory cell transistor MT flows from the node SEN _ L to the source line SL. As a result, the voltage of the node SEN _ L drops to the "L" level. On the other hand, when the selected memory cell transistor MT is in the off state, the voltage of the node SEN _ L maintains the "H" level.

Then, the sequencer 13 brings the control signal STB _ Lb to the "H" level. When a voltage of "H" level is applied to the gate of the transistor T54, the transistor T54 in the local amplifier module LAUb is turned on or off based on the voltage of the node SEN _ L. When the voltage of the node SEN _ L is at the "H" level, the current (2) through the transistors T54 and T55 in the local amplifier unit LAUb flows from the sense amplifier unit SAU toward the ground line, and the voltage of the global bit line GBL decreases. On the other hand, when the voltage of node SEN _ L is at the "L" level, global bit line GBL maintains a high voltage.

Thus, the sense amplifier unit SAU may determine read data of the selected memory cell transistor MT based on the voltage of the global bit line GBL. The operation when selecting the block BLK corresponding to the other bit line BL is the same as the operation when selecting the block BLK corresponding to the bit line BLb.

The following describes the details of the read operation of the semiconductor memory device 1 according to embodiment 7. In the read operation of the semiconductor memory device 1 according to embodiment 7, the selected bit lines BL are charged and the unselected bit lines BL are not charged, as in embodiment 4. Therefore, the following description will focus on the operation corresponding to the local amplifier module LAU connected to the selected bit line BL.

Fig. 37 is an example of a timing chart of a read operation of the semiconductor memory device 1 according to embodiment 7, and shows changes in control signals and the like corresponding to the NAND string NS, the local amplifier unit LAU, and the sense amplifier unit SAU. As shown in fig. 37, in the reading operation, the sequencer 13 sequentially executes the processing from time t0 to time t 8. The voltage of each control signal and each wiring before the read operation is performed is VSS, for example.

At time t0, VCG is applied to word line WLsel, VSGS is applied to select gate line SGS, and VSGD is applied to select gate line SGD. In addition, the sequencer 13 temporarily raises the control signal BRST to the "H" level. For example, VSS is applied to the node RST in the read operation, and thus the voltage of the node BLI is lowered to VSS by this operation.

At time T1, sequencer 13 raises control signal BLS to, for example, 4V, control signal BSWsel to, for example, 4V, control signal BLC _ L to, for example, 0.5V + Vt (which corresponds to the threshold voltage of transistor T53), control signal BLX _ L to, for example, 0.7V + Vt (which corresponds to the threshold voltage of transistor T50), control signal HLL _ L to, for example, 4V, control signal BLC to, for example, 0.5V + Vt (which corresponds to the threshold voltage of transistor T4), control signal BLX to, for example, 0.7V + Vt (which corresponds to the threshold voltage of transistor T1), and control signal HLL to, for example, 4V.

Then, the nodes SEN and SEN _ L are charged, and the voltages of the nodes SEN and SEN _ L rise to VDDSA. In addition, the voltage of global bit line GBL rises to, for example, 0.5V, and the voltage of bit line BL changes based on the data stored in selected memory cell transistor MT. Specifically, the voltage of the bit line BL connected to the disconnected cell is raised to, for example, 0.5V, that is, to a voltage equivalent to the global bit line GBL. On the other hand, the voltage of the bit line BL connected to the off cell rises to a voltage lower than the voltage of the bit line BL connected to the on cell.

At time T2, sequencer 13 drops control signal HLL _ L to VSS, raising XXL _ L to, for example, 0.9V + Vt (which corresponds to the threshold voltage of transistor T52). Accordingly, the voltage of the node SEN _ L varies based on the data stored in the selected memory cell transistor MT. Specifically, the voltage at the node SEN _ L connected to the on cell drops, and the node SEN _ L connected to the off cell maintains a high voltage.

At time t3, sequencer 13 drops control signal XXL _ L to VSS. Then, the transistor T52 is turned off, and the voltage of the node SEN _ L is fixed.

At time t4, the sequencer 13 raises the control signal STB _ L to the "H" level. Then, the voltage of global bit line GBL varies based on the voltage of node SEN _ L. Specifically, since the transistor T55 is maintained in the off state by the low voltage of the node SEN _ L, the voltage of the global bit line GBL connected to the on-cell is maintained at a high voltage. On the other hand, since the transistor T55 is turned on by the high voltage of the node SEN _ s, the voltage of the global bit line GBL connected to the off-cell decreases. Accordingly, the voltage of global bit line GBL connected to the off-cell is lower than the voltage of global bit line GBL connected to the on-cell.

At time T5, sequencer 13 lowers control signal HLL to VSS, raising the voltage of control signal XXL to 0.9V + Vt (which corresponds to the threshold voltage of transistor T3). Accordingly, the charging of the node SEN through the transistors T0 and T2 is stopped, and the voltage of the node SEN changes based on the voltage of the global bit line GBL. Specifically, since the global bit line GBL connected to the on cell maintains a high voltage, the voltage of the node SEN maintains a high voltage. On the other hand, the voltage of the node SEN decreases because the global bit line GBL connected to the disconnection unit has a low voltage.

At time t6, sequencer 13 drops control signal XXL to VSS. Then, the transistor T3 is turned off, and the voltage of the node SEN is fixed.

At time t7, sequencer 13 determines control signal STB. That is, the sequencer causes the control signal STB to temporarily rise to the "H" level. Thus, the voltage of bus LBUS varies based on the voltage of node SEN. Specifically, since the node SEN connected to the turn-on unit maintains a high voltage, the transistor T7 is turned on, and the voltage of the bus line LBUS drops. Since the node SEN connected to the disconnecting unit becomes a low voltage, the transistor T7 maintains the off state, and the voltage of the bus line LBUS is maintained high. Then, the sequencer 13 holds data based on the voltage value of the bus LBUS in any latch circuit within the sense amplifier block 14.

At time t8, the voltage of word line WLsel and select gate lines SGS and SGD, respectively, drops to VSS. In addition, the sequencer 13 lowers the control signals BLS, BLC _ L, BLX _ L, STB _ L, BLC _ L, and BLX to VSS ("L" level), respectively. As described above, the semiconductor memory device 1 according to embodiment 7 can perform the read operation.

(write action)

Fig. 38 shows an example of the configuration associated with the local amplifier units LAUa and LAUb connected to the common global bit line GBL and the current path during the write operation in the semiconductor memory device 1 according to embodiment 7. As shown in fig. 38, in the write operation of the semiconductor memory device 1 according to embodiment 7, the sequencer 13 turns on the transistor T57 in the local amplifier module LAU, thereby electrically connecting the global bit line GBL and the bit line BL. Also, the bit lines BL connected to the NAND strings NS included in the selected block BLK are appropriately charged, and charging of only the bit lines BL connected to the NAND strings NS included in the non-selected block BLK is omitted.

Specifically, in the case of selecting the block BLK including the NAND string NS connected to the bit line BLb, first, the sequencer 13 controls the transistor T57 included in the local sense amplifier LSA of the local amplifier component LAUb to be in an on state. Thereafter, the sequencer 13 executes a program loop (program loop) including a program action and a verify action. Thus, the sequencer 13 can write data to the memory cell transistor MT. The operation when selecting the block BLK corresponding to the other bit line BL is the same as the operation when selecting the block BLK corresponding to the bit line BLb.

[7-3] Effect of embodiment 7

As described above, the semiconductor memory device 1 according to embodiment 7 has the plurality of local amplifier elements LAU each including the local sense amplifier LSA, and performs the 2-stage read operation using the local sense amplifier LSA and the sense amplifier element SAU. Thus, the semiconductor memory device 1 according to embodiment 7 can amplify the cell current during the read operation, and can improve the accuracy of the read operation. Therefore, the semiconductor memory device according to embodiment 7 can obtain the same effects as those of embodiment 1, and can reduce read errors.

The circuit configuration in the local amplifier module LAU is mainly different between embodiment 7 and embodiment 4. Specifically, the local sense amplifier LSA in embodiment 7 has a configuration for applying a voltage to the bit line BL, unlike the amplification circuit AC in embodiment 4. Therefore, in order to shorten the time for charging the bit line BL, it is preferable to provide the local sense amplifier LSA as in embodiment 7. On the other hand, the amplification circuit AC is smaller than the local sense amplifier LSA with respect to the number of elements in the circuit. Therefore, in the case where the area of the sense amplifier region SR is reduced, the semiconductor memory device 1 preferably uses the amplification circuit AC as in embodiment 4.

[8] Embodiment 8

Semiconductor memory device 1 according to embodiment 8 has a configuration in which the number of local sense amplifiers LSA connected to global bit lines GBL is increased, compared to semiconductor memory device 1 according to embodiment 7. Differences from embodiments 1 to 7 of the semiconductor memory device 1 according to embodiment 8 will be described below.

[8-1] Circuit configuration of sense Amplifier Module 14

Fig. 39 shows an example of a circuit configuration of the sense amplifier module 14 included in the semiconductor memory device 1 according to embodiment 8, in which a configuration associated with 1 global bit line GBL is extracted. As shown in fig. 39, the sense amplifier module 14 according to embodiment 8 has the same circuit configuration as the sense amplifier module 14 according to embodiment 5 described with reference to fig. 29. The local amplifier unit LAU according to embodiment 8 has a structure in which the amplification circuit AC described in embodiment 5 is replaced with the local sense amplifier LSA. That is, in embodiment 8, 4 local sense amplifiers LSA are connected to 1 global bit line GBL. In the semiconductor memory device 1 of embodiment 8, the pitch of the global bit lines GBL may be designed to be wider than the pitch of the bit lines BL. The other configurations of the semiconductor memory device 1 according to embodiment 8 are the same as those of embodiment 7.

[8-2] Effect of embodiment 8

As described above, the semiconductor memory device 1 according to embodiment 8 has a configuration in which more local amplifier modules LAU than those according to embodiment 7 are connected to the global bit lines GBL. In this case, the semiconductor memory device 1 according to embodiment 8 may perform a read operation in series on a plurality of bit lines BL sharing the global bit line GBL by independently controlling the local amplifier unit LAU of the shared global bit line GBL, for example. In semiconductor memory device 1 according to embodiment 8, global bit lines GBL have a wider pitch than those according to embodiment 7. That is, semiconductor memory device 1 according to embodiment 8 can reduce the wiring capacitance and wiring resistance of global bit line GBL as compared with embodiment 7.

[9] Other variations and the like

The semiconductor memory device of an embodiment includes a memory portion and a circuit portion. The memory portion includes 1 st and 2 nd memory cells, 1 st and 2 nd bit lines connected to the 1 st and 2 nd memory cells, respectively, and 1 st and 2 nd bonding metals connected to the 1 st and 2 nd bit lines, respectively. The circuit section includes a sense amplifier section including a1 st wiring, and 3 rd and 4 th bonding metals connected to the 1 st wiring and opposed to the 1 st and 2 nd bonding metals, respectively. The circuit portion is joined to the memory portion. Thus, the semiconductor memory device of the embodiment can suppress power consumption and improve the operation speed.

In the above embodiment, the case where the conversion circuit SD is disposed at the end of the sense amplifier region SR is exemplified, but the present invention is not limited thereto. Fig. 40 shows an example of a planar layout in the sense amplifier region SR of the CMOS chip CC provided in the semiconductor memory device 1 according to the variation of embodiment 1. As shown in fig. 40, the conversion circuit SD may be disposed in the middle of the sense amplifier region SR, i.e., between the sense amplifier groups SASa and SASb. In this case, the sense amplifier module 14 may have a cache memory CMa disposed on the side of the sense amplifier group SASa and a cache memory CMb disposed on the side of the sense amplifier group SASa. For example, the latch circuits XDLa < 0 > -XDLa < m-1 > in the cache memory CMa are connected from the sense amplifier group SASa side to the conversion circuit SD, and the latch circuits XDLb < 0 > -XDLb < m-1 > in the cache memory CMb are connected from the sense amplifier group SASb side to the conversion circuit SD.

In the above embodiment, the case where the plurality of data latch modules DLU and latch circuits XDL included in the same sense amplifier group SAG are arranged in the Y direction is exemplified, but the present invention is not limited thereto. The plurality of data latch elements DLU included in the same sense amplifier group SAG may be arranged in the X direction. Similarly, a plurality of latch circuits XDL included in the same sense amplifier group SAG may be arranged in the X direction. In addition, an operational circuit may be inserted between the sense amplifier module SAU and the latch circuit XDL. Such an operational circuit may be common to a plurality of sense amplifier groups SAG. The number of sense amplifier elements SAU, latch circuits XDL, and the like included in each sense amplifier group SAG may be designed to be any number.

The embodiments can be combined to the extent possible. For example, embodiment 2 may be combined with the other embodiments, or bit lines BL extending in the Y direction may be divided into 3 or more in embodiments 3 to 8. In addition, although the sense amplifier module 14 includes the data latch group DLS in each of embodiments 4 to 8, the sense amplifier module SAU may include the latch circuits ABL and BDL in each of embodiments 4 to 8, as in embodiment 1.

In the above embodiment, the voltages for explaining the operation of the semiconductor memory device 1 are merely examples. The voltage value used may be other voltage values as long as the same operation as that described in each embodiment can be performed. The processing timing of the read operation described in embodiment 4 and embodiment 7 is merely an example. The processing at each time may not necessarily be performed at the same timing, and may be performed at different timings.

In the above embodiment, the memory column MP may have a structure in which a plurality of columns are connected to each other by 2 or more in the Z direction. The memory pillars MP may be connected to the pillars corresponding to the select gate lines SGD and the pillars corresponding to the word lines WL. The contacts CV, CP, CS, C0 to C3, V1, and V2 may have a structure in which a plurality of contacts are connected to each other. In this case, a wiring layer may be interposed between the connected contacts. The memory pillar MP and the contacts CV, CP, CS, C0 to C3, V1 and V2 may have a tapered shape or an inverted tapered shape, respectively, or may have a shape in which the middle portion bulges. Likewise, the slit SLT may have a tapered shape or an inverted tapered shape, and may have a shape in which a middle portion bulges. In addition, although the cross-sectional structure of the memory pillar MP is illustrated as a circle, the cross-sectional structure of the memory pillar MP may be an ellipse, and may be designed to have any shape.

In the above embodiment, the case where the multilayer wiring such as the word line WL has a stepped structure having a step in the Y direction in the lead region HR is exemplified, but the present invention is not limited thereto. For example, the end portions of the word line WL and the select gate lines SGD and SGS may be formed with a step in the X direction. The end portions of the word lines WL and the select gate lines SGD and SGS stacked in the lead-out region HR may be designed to have a step shape with an arbitrary number of rows. The staircase configuration formed may also differ between the select gate line SGS, the word line WL, and the select gate line SGD.

In the above-described embodiment, the case where the semiconductor memory device 1 is a NAND-type flash memory is exemplified, but the structure of the semiconductor memory device 1 in the above-described embodiment can be applied to other memory devices. For example, the semiconductor memory device 1 may be a resistance change memory using a resistance change element as a memory cell. As long as the memory device has at least a circuit for driving vertical (e.g., Y-direction) wiring and a circuit for driving horizontal (e.g., X-direction) wiring, the same configuration as that of the semiconductor memory device 1 in the above embodiment can be applied, and the same effects can be obtained.

In this specification, "connection" means electrical connection, and does not exclude a case where other elements are interposed therebetween, for example. The "electrical connection" may be through an insulating edge as long as it can operate in the same manner as the electrical connection. The "columnar shape" indicates a structure provided in a hole formed in the manufacturing process of the semiconductor memory device 1. The "H" level corresponds to the voltage at which the N-type and P-type transistors are turned on and off, respectively. The "L" level is a voltage at which the N-type and P-type transistors are turned off and on, respectively.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

[ description of symbols ]

1 semiconductor memory device

2 memory controller

10 memory cell array

11 instruction register

12 address register

13 sequencer

14 sense amplifier module

15 driver module

16-row decoder module

20 to 25 insulator layers

30-39 conductor layer

40 semiconductor layer

41 tunnel insulating film

42 insulating film

43 Barrier insulating film

50 semiconductor substrate

51 to 58,60 conductor layer

M0-M2, D0-D3 wiring layer

C0-C3, V1, V2, CT, CV joint

MR memory region

HR lead-out region

XR transport zone

SR sense Amplifier region

PERI peripheral circuit region

PR pad area

BL bit line

WL word line

SGD, SGS select gate lines

BLK Block

SU string assembly

MT memory cell transistor

ST1, ST2 selection transistor

SAU sense amplifier assembly

Transistors T0-T9, T20, T21, T30, T31, T40-T43 and T50-T57

RD row decoder

TR 0-TR 17 transistor

CG, SGDD, SGSD, USGD, USGS signal lines