阅读说明：本技术 用以提高固态驱动器的操作速度的nand接口设备 (NAND interface apparatus to increase operating speed of solid state drive ) 是由 翟书兵 许长喜 于 2020-10-28 设计创作，主要内容包括：本公开涉及一种用以提高固态驱动器的操作速度的NAND接口设备。一种装置包括前端口、多个后端口和多个开关。前端口可以被配置为向控制器发送数据和从控制器接收数据。多个后端口可以各自被配置为向存储器的多个逻辑单元中的发送数据和从所述一个逻辑单元接收数据。多个开关可以各自被配置为响应于输入而将前端口连接到后端口中的一个。输入可以从控制器被接收,并且也可以被提供给存储器。(The present disclosure relates to a NAND interface apparatus to increase the operating speed of a solid state drive. An apparatus includes a front port, a plurality of rear ports, and a plurality of switches. The front port may be configured to send and receive data to and from the controller. The plurality of back ports may each be configured to transmit data to and receive data from the one of the plurality of logical units of the memory. The plurality of switches may each be configured to connect the front port to one of the rear ports in response to an input. Inputs may be received from a controller and may also be provided to a memory.)

1. An apparatus, comprising:

a front port configured to transmit and receive data to and from a controller;

a plurality of back ports, each back port configured to transmit and receive the data to and from one of a plurality of logical units of a memory; and

a plurality of switches, each switch configured to connect the front port to one of the rear ports in response to an input,

wherein the input is (a) received from the controller and (b) also provided to the memory.

2. The apparatus of claim 1, wherein the front port is connected to one of the back ports such that a load seen by the controller is reduced from a lumped load corresponding to all of the plurality of logic cells to a single load corresponding to one of the logic cells.

3. The apparatus of claim 2, wherein the load comprises an input capacitance.

4. The apparatus of claim 1, wherein the input is a chip enable signal generated by the controller to select one of the logic cells.

5. The apparatus of claim 4, wherein (i) the chip enable signal is communicated from a pin of the controller, and (ii) the chip enable signal is communicated from a pin of the controller

(ii) The pin is used to convey the chip enable signal to the memory and the device.

6. The apparatus of claim 1, wherein (i) the controller is a flash controller for a solid state drive, (ii) the memory is a NAND flash memory, and (iii) each of the logic units comprises a NAND target die.

7. The apparatus of claim 6, wherein the solid state drive has an NVMe interface.

8. The apparatus of claim 1, wherein the input is configured to adjust the plurality of switches to (i) select one of the rear ports, and (ii) deselect each of the plurality of rear ports that have not been selected.

9. The apparatus of claim 8, wherein each of the back ports that have not been selected operate in at least one of: a bus hold state, a pull-up state, a pull-down state, and a high impedance state.

10. The apparatus of claim 1, wherein the apparatus is implemented on a channel bus for the memory.

11. The apparatus of claim 10, wherein (i) a solid state drive implements a plurality of the apparatuses, and (ii) each of the apparatuses is implemented on one of a plurality of memory channels implemented by the solid state drive.

12. The apparatus of claim 10, wherein connecting one of the back ports to the front port enables the channel bus to operate at approximately a maximum interface speed of one of the logic cells.

13. The apparatus of claim 12, wherein (i) the controller is configured to slow down communication on the channel bus in response to signal integrity of the data conveyed on the channel bus, (ii) the signal integrity is reduced by a load seen by the controller, and (iii) the bus operates at approximately the maximum interface speed in response to a fraction of a total load of the plurality of logic units seen by the controller.

14. The apparatus of claim 1, wherein the input is a signal defined by the ONFI standard.

15. An apparatus, comprising:

a front bridge circuit configured to convey signals in a first direction from a controller and a second direction to the controller;

a plurality of back bridge circuits, each back bridge circuit configured to convey the signal in the first direction to one of a plurality of logic cells of a memory and the second direction from one of the plurality of logic cells;

a first plurality of buffer circuits, each configured to connect the front bridge circuit to one of the rear bridge circuits in the first direction; and

a second plurality of buffer circuits, each configured to connect one of the rear bridge circuits to the front bridge circuit in the second direction, wherein (i) each of the plurality of rear bridge circuits is implemented such that the plurality of rear bridge circuits can have independent operation, (ii) the independent operation enables the rear bridge circuits to operate simultaneously, and (iii) the first and second plurality of buffer circuits enable the front bridge circuit to operate at a first throughput and the plurality of rear bridge circuits to operate at a second throughput.

16. The apparatus of claim 15, wherein the second throughput is a maximum interface speed of one of the logical units.

17. The apparatus of claim 15, wherein the first throughput is a sum of the second throughputs from each of the plurality of rear bridge circuits.

18. The apparatus of claim 15, wherein (i) the independent operation reduces an input capacitance seen by the controller as compared to each of the logic cells sharing a common bus between the memory and the controller, and (ii) reducing the input capacitance enables a higher transfer rate of the signal.

19. The apparatus of claim 15, wherein (i) the first and second pluralities of buffer circuits are configured to: the signal is buffered in a data path between the front bridge circuit and the plurality of rear bridge circuits, and (ii) the signal includes (a) a high speed command and (b) data.

20. The apparatus of claim 15, wherein (i) the controller is a flash controller for a solid state drive, (ii) the memory is a NAND flash memory, (iii) each of the logic units comprises a NAND target die, and (iv) the apparatus is implemented on a NAND bus between the controller and the memory.

Technical Field

The present invention relates generally to a solid state drive, and more particularly to a method and/or apparatus for implementing a NAND interface device to increase the operating speed of a solid state drive.

Background

Solid State Drives (SSDs) are a type of computer storage medium that have enhanced performance and reduced power consumption compared to hard disk drives. Solid State Drives (SSDs) typically consist of a flash controller that communicates with several NAND channels. Each NAND channel is connected to one or more NAND targets. Each target may include one or more Logical Units (LUNs).

There are inherent performance limits in the NAND channel where the flash controller is connected to the NAND target set.

All targets and LUNs share the same NAND bus. The flash controller may treat all LUNs as a lumped load. Since the LUN is considered a lumped load, the NAND bus cannot operate at the maximum rated speed at which the LUN can operate. Furthermore, only one of the LUNs can move data in or out of the flash controller at any time. Due to the increased loading of multiple LUNs and the issue of signal interference addressing multiple LUNs, the flash controller has to slow down the transfer speed of the NAND bus. Signal interference can be particularly problematic when there are reflections due to LUNs residing in 5 different packages or ports.

It is desirable to implement a NAND interface device to increase the operating speed of a solid state drive.

Disclosure of Invention

The present invention relates to an apparatus comprising a front port, a plurality of rear ports and a plurality of switches. The front port may be configured to transmit/receive data to/from the controller. The plurality of back ports may each be configured to transmit/receive data to/from one of the plurality of logical units of the memory. The plurality of switches may each be configured to connect the front port to one of the rear ports in response to an input. Inputs may be received from a controller and may also be provided to a memory.

Drawings

Embodiments of the invention will become apparent from the following detailed description, the appended claims and the accompanying drawings.

Fig. 1 is a diagram illustrating an embodiment of the present invention.

Fig. 2 is a block diagram illustrating an example embodiment of the invention.

Fig. 3 is a block diagram illustrating an alternative example embodiment of the present invention.

FIG. 4 is a block diagram illustrating a NAND interface apparatus to increase the operating speed of a solid state drive.

FIG. 5 is a block diagram illustrating a NAND flash multiplexer to increase the operating speed of a solid state drive.

FIG. 6 is a block diagram illustrating an embodiment of the present invention implemented in a per-channel multi-target solid state drive.

FIG. 7 is a block diagram illustrating a NAND flash bridge to increase the operating speed of a solid state drive.

Detailed Description

Embodiments of the present invention include providing a NAND interface device to increase the operating speed of a solid state drive, the solid state drive may (i) connect the flash controller to multiple flash memory targets, (ii) reuse the chip enable signal to select a flash memory target, (iii) be implemented without adding additional pins from the flash controller, (iv) enable the memory bus to operate at a speed closer to the maximum potential speed of the flash memory, (v) reduce the amount of load seen by the flash controller, (vi) enable the bus to the flash controller to operate at a speed different from the bus to the flash memory target, (vii) increase bandwidth based on the number of ports available, (viii) be implemented as a system-in-package, (ix) be implemented as a multi-chip component, and/or (x) be implemented as one or more integrated circuits.

Referring to fig. 1, a diagram illustrating an embodiment of the present invention is shown. An example embodiment of a Solid State Drive (SSD)50 is shown. In the illustrated example, the SSD 50 may implement a non-volatile memory express (NVMe) type of storage medium. While NVMe SSD 50 is shown, SSD 50 may be implemented in other form factors (e.g., SATA2, SATA3, PCie, etc.). The form factor of the SSD 50 may vary depending on the design criteria of a particular implementation.

The SSD 50 may include pin connectors 52 and notches 54. The pin connector 52 may be configured to connect the SSD 50 to a host device (e.g., a desktop computer, a laptop computer, a tablet computing device, a smartphone, etc.). The recess 54 may be a cut-out on the circuit board of the SSD 50. The recesses 54 may provide space for screws to secure the SSD 50 to another component. Screws may be inserted through the notches 54 and the heads of the screws may be placed on the SSD 50 to hold the SSD 50 in place on the motherboard (or pci e adapter board or USB adapter board, etc.).

Pin connectors 52 may be B-key and M-key type connectors. In some embodiments, pin connector 52 may be an M-key type connector. In some embodiments, the pin connector 52 may enable the SSD 50 to communicate with a host device using four channels (e.g., approximately 16GBps transmission speed) using the PCie 3.0 protocol. In some embodiments, the pin connector 52 may enable the SSD 50 to communicate with a host device using up to four channels (e.g., approximately 32GBps transmission speed) using the PCie 4.0 protocol. In an example, the SSD 50 may be a 2280 size drive (e.g., 22mm x 80 mm). In another example, the SSD 50 may be a 2260 sized drive (e.g., 22mm x 60 mm). Other sizes of SSD 50 may be implemented (e.g., 2242, 22110, etc.). The size of the SSD 50, the shape of the pin connectors 52, and/or the transport protocol implemented by the pin connectors 52 may vary depending on the design criteria of a particular implementation.

The SSD 50 may include a block (or circuit) 60, blocks (or circuits) 70a-70c, and/or a block (or circuit) 100. The circuit 60 may implement a flash controller. The circuits 70a-70c may implement a flash memory package. The circuit 100 may implement a memory interface device. The SSD 50 may include other components (not shown). In an example, the SSD 50 may include a RAM module.

The number, type, and/or arrangement of the components of the SSD 50 may vary depending on the design criteria of a particular implementation.

Flash controller 60 may implement a processor configured to control and/or manage input/output to/from flash memory packages 70a-70c and/or pin connectors 52 (e.g., in communication with a hose device). In some embodiments, the transfer rate achievable by flash controller 60 may determine how fast the data stored in flash memory packages 70a-70c is accessed and/or written. Flash controller 60 may be configured to transfer data from a host computer to flash memory packages 70a-70 c. Flash controller 60 may be configured to transfer data from flash memory packages 70a-70c to a host computer. Flash controller 60 may include a plurality of pins, each pin having a designated function. In one example, the flash controller 60 and/or the pin connector 52 may be configured to operate as an NVMe interface for the SSD 50.

The flash memory packages 70a-70c may be configured to store computer readable data. The flash memory packages 70a-70c may include non-volatile memory. In an example, the flash memory packages 70a-70c may include NAND memory. The flash memory packages 70a-70c may be configured to communicate with the flash controller 60 to store (write operations) and/or provide (read operations) computer readable data. In some embodiments, the transfer rate that the flash memory packages 70a-70c are capable of achieving may determine how fast data is written to the flash memory packages 70a-70c and/or read from the flash memory packages 70a-70 c. In the example shown, three flash memory packages 70a-70c are on one side of the SSD 50. In some embodiments, the SSD 50 may include additional flash memory packages on the backside of the SSD 50. The SSD 50 may include any number of flash memory packages (e.g., 70a-70 n).

The circuit 100 is shown implemented as a chip package separate from the flash controller 60 and the flash memory packages 70a-70 c. In the illustrated example, the circuit 100 is shown implemented between the flash controller 60 and the flash memory packages 70a-70 c. The circuit 100 may be configured to increase the operating speed of the SSD 50.

Referring to fig. 2, a block diagram illustrating an example embodiment of the present invention is shown. A system 80 is shown. The system 80 may be a block diagram of a data path for storing data to the SSD 50 and/or retrieving data from the SSD 50. The system 80 may include a flash memory package 70, a block (or circuit) 82, a block (or circuit) 84, and/or a block (or circuit) 102. The flash memory package 70 may be a representative example of the flash memory packages 70a-70n shown in association with fig. 1. The circuit 82 implements a host device (e.g., host computer, motherboard, processor, NVMe controller, etc.). The circuit 84 may be a bus. In an example, the bus 84 may be a channel bus (e.g., a NAND bus for a memory channel). The circuit 102 may implement a controller package. The system 80 may include other components (not shown). The number, type, and/or arrangement of the components of the system 80 may vary according to the design criteria of a particular implementation.

The controller package 102 may include the apparatus 100'. The apparatus 100' may have an implementation similar to the apparatus 100 shown in association with fig. 1. The controller package 102 may have an implementation similar to the flash controller 60 shown in association with fig. 1. Controller package 102 may be a multi-chip assembly that includes flash controller 60 and device 100'. Although system 80 is depicted in fig. 2 as having multichip assembly 102, the depiction of system 80 may be applicable to embodiments in which flash controller 60 and device 100 are implemented as separate components as shown in association with fig. 1.

The signals (e.g., REQ) and signals (e.g., DATA) are shown as being carried between the host 82 and the controller package 102.

Signals (e.g., I/O) and signals (e.g., CE) are shown being carried between the controller package 102 and the flash memory package 70.

Other signals may be communicated within the system 80 (not shown).

The number, type, and/or function of signals implemented within system 80 may vary according to the design criteria of a particular implementation.

The signal REQ is shown as being transmitted by the host 82 to the controller package 102. Signal REQ may be a request issued by host 82 to flash controller 60. In an example, the signal REQ may be a data request (e.g., indicating which data to retrieve from the flash memory package 70). The signal DATA is shown as a bi-directional signal that is delivered by the host 82 and the controller package 102. The signal DATA may include computer-readable DATA and/or high-speed commands. In one example, the signal DATA may be computer readable DATA retrieved from the flash memory package 70 by the flash controller 60 and delivered to the host 82. In another example, the signal DATA may be computer readable DATA delivered by the host 82 to the flash controller 60 for storage in the flash memory package 70. In yet another example, the signal DATA may include high-level commands that are communicated between the host 82 and the flash controller 60.

The signal I/O is shown as a bi-directional signal that is delivered by the controller package 102 to the flash memory package 70. The signal I/O may comprise computer readable data and/or commands. For example, signal I/O may provide data input to flash memory package 70 from flash controller 60. In another example, the signal I/O may provide a data output that is read from the flash memory package 70 to the flash controller 60. In yet another example, the signal I/O may include commands for the flash memory package 70 provided by the flash controller 60. The signal CE is shown provided by the controller package 102 to the flash memory package 70. Signal CE may be generated by flash controller 60. The signal CE may be a chip enable signal. The chip enable signal CE may select a particular storage location of the flash memory package 70 where the signal I/O is stored to and/or retrieved from. The signal I/O and the signal CE may be conveyed through the NAND bus 84.

The flash memory package 70 may include a plurality of blocks (or circuits) 90a-90 n. The circuits 90a-90n may be Logical Unit Numbers (LUNs) of the flash memory package 70. In an example, each of the circuits 90a-90n may be a flash memory die integrated in the NAND flash memory package 70.

Each of the flash memory packages 70a-70n may include multiple dies 90a-90n (e.g., for greater storage capacity). For a single die of the dies 90a-90n implemented in a single one of the NAND flash memory packages 70a-70n, the flash controller 60 may be able to achieve the highest speed (e.g., take it lower) supported by both the flash memory package 70 and the flash controller 60. In an example, if the flash controller supports 1.2GT/s and is paired with a die 90i that supports 0.8GT/s, the SSD 50 may operate at 0.8 GT/s. If multiple dies 90a-90n are implemented in the flash memory package 70 (as shown), and/or multiple packages 70a-70n are connected to the NAND channel to increase capacity, the additional load may reduce system speed (e.g., as compared to a single die implementation).

System 80 may represent a single NAND channel. Multiple NAND channels may be implemented in the SSD 50. In the example shown, the flash controller 60 may be connected to a single flash memory package 70. In some embodiments, flash controller 60 may be connected to a target group (e.g., flash memory packages 70a-70 n). Each flash memory package 70a-70n may have multiple LUNs 90a-90n (e.g., die). Each of the LUNs 90a-90n accessible to (or visible to or connected to) the flash controller 60 may increase the load on the NAND bus 84. Apparatus 100 (or 100') may be configured to reduce the load visible to flash controller 60. Reducing the load seen by the flash controller 60 may increase the performance of the SSD 50 to the throughput supported by the flash controller 60 and/or the flash memory packages 70-70 n.

Referring to fig. 3, a block diagram illustrating an alternative example embodiment of the present invention is shown. A system 80' is shown. The system 80' may have an implementation similar to the system 80 shown in association with fig. 2. The system 80 'may include a flash controller 80, a host 82, a NAND bus 84, and/or circuitry 102'.

The system 80' may be an example illustrating a single channel of the SSD 50. In the example shown, the circuit 102' may be a memory package. The memory package 102' may include the apparatus 100 "and/or the flash memory package 70. The flash memory package 70 may include LUNs 90a-90n (e.g., NAND dies). The memory package 102' may include other components (not shown).

The number, type, and/or arrangement of the components of the memory package 102' may vary according to the design criteria of a particular implementation.

The signal REQ is shown as being provided to flash controller 60 by host 82. The signal DATA is shown as a bi-directional signal provided/received by the host 82 and the flash controller 60. Signal I/O is shown as a bi-directional signal provided/received on NAND bus 84 by flash controller 60 and memory package 102'. The signal CE is shown provided by the flash controller 60 to the memory package 102' on the NAND bus 84.

In some embodiments, the apparatus 100 may be implemented as a single chip design. In the example SSD 50 shown in association with FIG. 1, the apparatus 100 is shown as a separate chip design (e.g., implemented as a separate package between the flash controller 60 and the flash memory packages 70a-70 n). In a single chip design, flash controller 60 may deliver signal I/O and/or signal CE to device 100, and device 100 may deliver signal I/O to flash memory packages 70a-70n (flash controller 60 may deliver signal CE to flash memory packages 70a-70 n). In a single chip design, flash memory packages 70a-70n may deliver signal I/O to device 100, and then device 100 may deliver signal I/O to flash controller 60, and flash controller 60 may deliver signal CE to device 100 and flash memory packages 70a-70 n.

In some embodiments, apparatus 100 may be implemented as a multi-chip and/or system-in-package with flash controller 60. In the example system 80 shown in association with FIG. 2, apparatus 100' is shown as part of multichip package 102 (e.g., implemented in the same package as flash controller 60 and separate from flash memory packages 70a-70 n). In a multichip design of controller package 102, flash controller 60 may deliver signal I/O and/or signal CE to device 100 'within controller package 102, and device 100' may deliver signal I/O to flash memory packages 70a-70n (flash controller 60 may deliver signal CE to flash memory packages 70a-70 n). In a multichip design of controller package 102, flash memory packages 70a-70n may deliver signal I/O to device 100 ', and device 100 ' may deliver signal I/O to flash controller 60 within controller package 102, and flash controller 60 may deliver signal CE to device 100 ' within controller package 102 and to flash memory packages 70a-70 n.

In some embodiments, the apparatus 100 may be implemented as a multi-chip and/or system-in-package with the flash memory package 70. In the example system 80 'shown in association with FIG. 3, apparatus 100 "is shown as part of multichip package 102' (e.g., implemented in the same package as flash memory package 70 and separate from flash controller 60). In a multichip design of memory package 102 ', flash controller 60 may deliver signal I/O and/or signal CE to device 100 "located in memory package 102', and device 100" may deliver signal I/O to flash memory package 70 (flash controller 60 may deliver signal CE to flash memory packages 70a-70 n). In a multichip design of memory package 102 ', flash memory packages 70a-70n may deliver signal I/O to device 100 "within memory package 102 ', and device 100" may deliver signal I/O to flash controller 60, and flash controller 60 may deliver signal CE to device 100 "and to flash memory package 70 located in memory package 102 '.

The apparatus 100 may be implemented as a single chip design. The apparatus 100 may be implemented as a monolithic integrated circuit package. The apparatus 100 may be integrated into the NAND memory packages 70a-70n in a multi-chip assembly and/or system-in-package fashion. In some embodiments, flash controller 60, device 100, and flash memory package 70 may be implemented as a single package. A single package may have an implementation similar to a single chip design, but with all signals and components implemented within the single package. The implementation of the apparatus 100 in the SSD 50 may vary depending on the design criteria of a particular implementation.

Referring to fig. 4, a block diagram illustrating a NAND interface device to increase the operating speed of a solid state drive is shown. The components for one NAND channel of the SSD 50 are shown. The components for one NAND channel of the SSD 50 may include: a flash controller 60, a flash memory package 70 (including LUNs 90a-90n), a NAND bus 84, and/or a device 100. In the example shown, the apparatus 100 may be a single chip design similar to the example shown in fig. 1.

The apparatus 100 may be implemented between the flash controller 60 and the flash memory package 70. The apparatus 100 may be implemented on a NAND channel bus 84. The apparatus 100 may be configured to increase the operating speed (e.g., throughput) of the SSD 50. In one example, the apparatus 100 may implement a NAND flash multiplexer configured to increase the operating speed of the SSD 50 without requiring an additional control pin from the flash controller 60. In another example, the apparatus 100 may implement a NAND flash bridge device configured to increase the operating speed of the SSD 50.

The apparatus 100 may include a block (or circuit) 110 and/or blocks (or circuits) 112a-112 n. The circuit 110 may implement a port. The circuits 112a-112n may each implement a port. The apparatus 100 may include other components (not shown). The number, type, and/or arrangement of the components of the apparatus 100 may vary according to the design criteria of a particular implementation.

Connections 114a-114n are shown. Connections 114a-114n may be implemented between device 100 and flash memory package 70. Connections 114a-114n may be discrete (e.g., separate or isolated) connections. The discrete connections 114a-114n may be a second portion of the NAND bus. For example, bus 84 may be a first portion of a NAND bus configured to transport data and/or commands between flash controller 60 and device 100, and discrete connections 114a-114n may be a second portion of the NAND bus configured to transport data and/or commands between device 100 and flash memory package 70. In an example, the bus 84, the apparatus 100, and the discrete connectors 114a-114n together may implement a NAND bus.

Port 110 may implement a front port. Front port 110 may be configured to communicate with flash controller 60.

The front port 110 may be configured to receive signal(s) from the NAND bus 84. The front port 110 may be configured to provide signal(s) to the NAND bus 84.

Ports 112a-112n may each implement a rear port. The rear ports 112a-112n may be configured to communicate with the flash memory package 70. Each of the rear ports 112a-112n may be connected to a respective one of the discrete connectors 114a-114 n. Each of the rear ports 112a-112n may be configured to receive signal(s) from the flash memory package 70 via a respective one of the discrete connectors 114a-114 n. Each of the rear ports 112a-112n may be configured to provide signal(s) from the flash memory package 70 via a respective one of the discrete connectors 114a-114 n.

The discrete connectors 114a-114n may be connected to a respective one of the LUNs 90a-90n in the flash memory package 70.

Discrete connectors 114a-114n may be configured to connect one of back ports 112a-112n to one of LUNs 90a-90 n. Front port 110 may be configured to communicate with each of rear ports 112a-112n (described in more detail in association with fig. 5-7). By communicating with one of the rear ports 112a-112n, the front port 110 may be configured to communicate with any of the LUNs 90a-90n individually via a respective one of the discrete connectors 114a-114 n. In an example, front port 110 can be connected to back port 112a, which can enable a path to LUN90a via discrete connector 114a, front port 110 can be connected to back port 112b, which can enable a path to LUN90 b via discrete connector 114b, and so on. Connecting the front port 110 to one of the LUNs 90a-90n may enable isolated connections from the flash controller 60 to one of the LUNs 90a-90 n.

Without the apparatus 100, the flash controller 60 may interface with the LUNs 90a-90n as a lumped load on the NAND bus 84 (e.g., the flash controller 60 treats the LUNs 90a-90n as lumped loads). Signal integrity may be degraded due to the lumped load seen by flash controller 60. In response to the increased loading of the plurality of LUNs 90a-90n, the flash controller 60 may slow down the speed of the NAND bus 84 (e.g., to ensure signal integrity). Furthermore, when LUNs 90a-90n reside on different enclosures/ports, there may be signal interference issues when addressing multiple LUNs 90a-90 n. In an example where four of LUNs 90a-90n are implemented, flash controller 60 may see a lumped input capacitance due to reflections (e.g., 4x Cin, where Cin is the input capacitance of each of LUNs 90a-90 n). To accommodate the lumped input capacitance, flash controller 60 may reduce the speed of NAND bus 84 to a speed that is less than the throughput capability of LUNs 90a-90n (e.g., flash controller 60 will not operate without potentially causing errors at the maximum speed at which one of LUNs 90a-90n may operate). Furthermore, without the apparatus 100, only one of the LUNs 90a-90n may move data to/from the flash controller 60, since all of the LUNs 90a-90n share the same NAND bus 84.

The apparatus 100 may be configured to reduce the load seen by the flash controller 60 from the LUNs 90a-90 n. In an example, the load may be an input capacitance. The apparatus 100 may be configured to cause the flash controller 60 to operate at a throughput speed that may be closer to the rated throughput speed of the LUN90a-90 n. In an example, since apparatus 100 reduces the load seen by flash controller 60, flash controller 60 may be able to operate at higher speeds on NAND bus 84 without signal interference affecting the integrity of the data and/or high speed commands being transmitted. The apparatus 100 may reduce reflections on the NAND bus 84 caused by addressing multiple LUNs 90a-90 n. In an example where apparatus 100 is implemented with four of LUNs 90a-90n, flash controller 60 may see the input capacitance due to reflection of one of LUNs 90a-90 (e.g., 1x Cin, where Cin is the input capacitance of each of LUNs 90a-90n) instead of the lumped input capacitance (e.g., 4x Cin). In an example, for n targets, the reduction in load seen by flash controller 60 may be approximately 1/n times the input impedance as device 100 is implemented.

Referring to FIG. 5, a block diagram illustrating a NAND flash multiplexer to increase the operating speed of a solid state drive is shown. An implementation 150 is shown. The implementation 150 may illustrate one channel of a data path of the SSD 50 similar to the example shown in association with fig. 4. Implementation 150 may include flash controller 60, flash memory package 70, and/or device 100. In implementation 150, device 100 may be configured as a NAND flash multiplexer. The NAND flash multiplexer 100 may be configured to increase the operation speed of the SSD 50.

Flash controller 60 is shown to include blocks (or circuits) 62a-62 n. Blocks 62a-62n may include pins/connectors of flash controller 60. Pins/connectors 62a-62n may enable flash controller 60 to send/receive data, commands, status signals (e.g., flags), voltages, etc. The pins/connectors 62a-62n may be implemented as surface mount pins, pins for a pin grid array, pins for connecting to a disk grid array, pads for a ball grid array, etc. Each of the pins/connectors 62a-62n may correspond to a predefined function. The predefined functions of the pins/connectors 62a-62n may correspond to: open NAND Flash Interface (ONFI) standards (e.g., ONFI 4.1), specifications defined by the manufacturer of the flash controller 60, specifications defined by the manufacturer of the flash memory packages 70a-70n, etc. The number, layout, and/or functionality of each of the pins/connectors 62a-62n may vary depending on the design criteria of a particular implementation.

The NAND flash multiplexer 100 may include a front port 110, back ports 112a-112n, and/or a plurality of blocks (or circuits) 160a-160 n. Circuits 160a-160n may implement switches. NAND flash multiplexer 100 may include an input 152. Input 152 may be configured to receive signal CE from flash controller 60. NAND flash multiplexer 100 may include other components, logic circuitry, and/or inputs/outputs (not shown). The number, type, and/or arrangement of the components, logic circuitry, and/or inputs/outputs of NAND flash multiplexer 100 may vary depending on the design criteria of a particular implementation.

Flash controller 60 may transfer signal I/O to/from NAND flash multiplexer 100. One or more of the pins/connectors 62a-62n may provide signal I/O to the front port 110. One or more of the pins/connectors 62a-62n may receive signal I/O from the front port 110.

The flash controller 60 may provide a signal CE to the NAND flash multiplexer 100 and the flash memory package 70. One of the pins/connectors 62a-62n may provide a signal CE to input 152 of NAND flash multiplexer 100 and input 92 of flash memory package 70. In the example shown, pin/connector 62i may provide signal CE.

Switches 160a-160n may be implemented between front port 110 and rear ports 112a-112 n. Each of the switches 160a-160n may be configured to connect the front port 110 to a respective one of the rear ports 112a-112 n. The switches 160a-160n may be implemented as high performance switches that connect the front port 110 and the rear ports 112a-112n to enable data and/or high speed commands to be transferred in both directions.

NAND flash multiplexer 100 may operate as a bus multiplexer having a front port 110 connected to flash controller 60 and a plurality of back ports 112a-112n connected to NAND targets 90a-90 n. Front port 110 may communicate with flash controller 60 over a first portion of NAND bus 84. Each of the back ports 112a-112n may communicate with the flash memory package 70 over a respective one of the discrete portions of the NAND bus 114a-114 n.

Signal CE may be used by flash controller 60 as a chip enable signal for flash package 70. Signal CE may achieve one of NAND targets 90a-90 n. Signal CE may also be provided to NAND flash multiplexer 100 at input 152. Signal CE may select, adjust, and/or activate one of switches 160a-160 n. NAND flash multiplexer 100 may also include logic circuitry to select, adjust and/or activate one of switches 160a-160n in response to signal CE. The switch selected by signal CE may correspond to the NAND target selected by signal CE. In an example, if signal CE is configured to select NAND target 90c in flash memory package 70, apparatus 100 may be configured to activate switch 160c in response to signal CE.

Implementation 150 may utilize the existing functionality of signal CE to implement the activation of one or more of switches 160a-160 n. The flash controller 60 of the SSD 50 may implement the pin/connector 62i to select one or more of the NAND targets 90a-90n, regardless of whether the device 100 is implemented. For example, the pin/connector 62i may provide a signal CE to the input 92 of the flash memory package 70. The signal CE provided to the input 152 may be received from a preexisting pin/connector 62 i. Implementing the apparatus 100 and/or one or more of the selection switches 160a-160n may not require the addition of an additional one of the pins/connectors 62a-62 n.

NAND flash multiplexer 100 may be configured to connect one of back ports 112a-112n to front side port 110 in response to signal CE to select one of switches 160a-160 n. In some embodiments, only one of switches 160a-160n may be activated at any one time, and only one of back ports 112a-112n may be connected to front port 110 at a time. In an example, in response to signal CE, NAND flash multiplexer 100 may adjust switches 160a-160n to select one of back ports 112a-112n and deselect each of back ports 112a-112n that have not been selected. The selection of the switches 160a-160n may be determined by a target select signal CE (e.g., commonly designated as CEn) that may have been used by the flash controller 60 and the flash package 70.

In an example, flash controller 60 may generate signal CE to select NAND target 90 c. Signal CE may be provided by pin 62i to input 92 of flash memory package 70 to select NAND target 90c, and to input 152 of NAND flash multiplexer 100 to select switch 160 c. Selection switch 160c may connect front port 110 to rear port 112 c. Connecting front port 110 to back port 112c may enable a path from flash controller 60 to device 100 via NAND bus 84, and then from device 100 to NAND target 90c via discrete connector 114 c. The path from flash controller 60 to front port 110, then to back port 112c, then to NAND target 90c may be an isolated path.

NAND flash multiplexer 100 may be configured to provide an isolated path from flash controller 60 to one of NAND targets 90a-90 n. The isolation path may enable flash controller 60 to communicate directly with a selected one of NAND targets 90a-90 n. The isolation path may prevent interference and/or noise caused by other (e.g., unselected) NAND targets 90a-90 n.

NAND flash multiplexer 100 may use signal CE to select a multiplexer channel. Signal CE may be used to simultaneously select one of switches 160a-160n and NAND targets 90a-90 n. Since the NAND flash multiplexer 100 can simultaneously use the same signal CE as the flash memory package 70, the flash controller 60 can be implemented without any additional control pin. NAND flash multiplexer 100 may utilize the functionality of existing pins 62a-62n for selecting switches 160a-160 n. NAND flash multiplexer 100 may be implemented using pre-existing and/or pre-defined functionality of flash controller 60.

NAND flash multiplexer 100 may select one of switches 160a-160n and deselect the remaining (e.g., unselected) switches in response to signal CE. When NAND flash multiplexer 100 selects one of switches 160a-160n in response to signal CE, the unselected switches 160a-160n and/or ports 112a-112n may operate in different states. The different operating states performed by the unselected switches 160a-160n and/or ports 112a-112n may be configured to prevent communication and/or interference by the unselected NAND targets 90a-90 n. In an example, the different states may include bus hold, pull-up, pull-down, high impedance, and the like. The types of different states implemented by NAND flash multiplexer 100 may vary according to the design criteria of a particular implementation.

Because NAND flash multiplexer 100 selects one of back ports 112a-112n and blocks the non-selected back ports 112a-112n, each of back ports 112a-112n may have fewer NAND targets 90a-90n to address (e.g., each of back ports 112a-112n may address one of LUNs 90a-90n, rather than implementing a single bus capable of addressing all LUNs 90a-90 n). The direct and/or isolated path to each of the target NAND's 90a-90n made possible by the NAND flash multiplexer 100 may enable the SSD 50 to operate closer to the maximum speed of the flash controller 60 and/or the NAND target 90a-90 n. For example, flash controller 60 may not have to reduce the speed of bus 84 to accommodate signal interference, as the isolation provided by NAND flash multiplexer 100 may reduce signal interference. Implementing the NAND flash multiplexer 100 may reduce the input impedance seen by the flash controller 60 to 1/n of the total input impedance of the NAND targets 90a-90 n. For example, connecting front port 110 to one of back ports 112a-112n may reduce the load seen by flash controller 60 from a lumped load corresponding to all NAND targets 90a-90n to a single load corresponding to one of NAND targets 90a-90 n.

In the example where there are four of the NAND targets 90a-90n, the flash controller can see the combined load (e.g., 4x Cn, where Cn is the input impedance) of the NAND targets 90a-90n without the device 100. For the example with four of the NAND targets 90a-90n, the NAND flash multiplexer 100 may be implemented with four of the back ports 112a-112 n. If flash controller 60 provides signal CE to select NAND target 90c, NAND flash multiplexer 100 may activate switch 160c in response to signal CE. NAND flash multiplexer 100 may select different (e.g., blocking) states for unselected switches 160a, 160b, and 160 d. NAND flash multiplexer 100 may connect front port 110 to back port 112c to enable an isolated path from flash controller 60 to NAND target 90c via connector 114 c. Since other NAND targets 90a, 90b and 90d may be blocked by the high impedance state of the unselected switches 160a, 160b and 160c, the flash controller 60 may see a reduced load. The flash controller 60 may see the input impedance Cn from the selected NAND target 90c, but may not see the impedance Cn from each of the unselected NAND targets 90a, 90b, and 90 d. By implementing NAND flash multiplexer 100 for a system having four of NAND targets 90a-90n, flash controller 60 can see 1/4 for the total load of NAND targets 90a-90 n. Flash controller 60 may not suffer from multiple dropped signal interference problems during wiring of the printed circuit board. In the case of a NAND flash multiplexer, the SSD 50 may operate at the maximum speed at which the LUN90 c may be able to operate.

In the example shown, each of switches 160a-160n may be configured to connect one of back ports 112a-112n to front port 110 (e.g., a 1-to-1 connection). Connecting one of the back ports 112a-112n to the front port 110 may enable one of the NAND targets 90a-90n to connect to the flash controller 60. In some embodiments, one or more of the switches 160a-160N may be configured to connect the front port 110 to more than one of the rear ports 112a-112N (e.g., a 1-to-N implementation). Connecting the front port 110 to more than one of the back ports 112a-112n may enable the controller 60 to access more than one of the NAND targets 90a-90n (e.g., to allow simultaneous transfers to multiple memory targets). Connecting the front port 110 to more than one of the back ports 112a-112n (e.g., but less than all of the back ports 112a-112n) may still reduce the combined load seen by the flash controller 60 as compared to connecting the NAND bus 84 to all of the NAND targets 90a-90 n.

Referring to fig. 6, a block diagram illustrating an embodiment of the present invention implemented in a per-channel multi-target solid state drive is shown. A system 200 is shown. The system 200 may be an illustrative example of multiple instances of the NAND flash multiplexer 100 implemented in a multi-channel embodiment of a data path of the SSD 50 described in association with fig. 5.

System 200 may include flash controller 60 and/or flash memory package 70. A plurality of data path channels (or memory channels) 202a-202n are shown. Each of the data path channels 202a-202n may have an implementation similar to the data path 150 described in association with fig. 5. Flash controller 60 may communicate independently with each of data path channels 202a-202 n. Each data path (or storage) channel 202a-202n may include one of the NAND buses 84a-84n and one of the NAND flash multiplexers 100a-100 n. Each of the NAND buses 84a-84n may have an implementation similar to the NAND bus 84 described in association with FIG. 5. Each of NAND flash multiplexers 100a-100n may have an implementation similar to NAND flash multiplexer 100 described in association with FIG. 5. In the example shown, NAND flash multiplexers 100a-100n may be separate chips. In some embodiments, the NAND flash multiplexers 100a-100n may be implemented as multiple circuits in a single chip package. Each of the data path channels 202a-202n may include other components (not shown). For example, each of the data path channels 202a-202n may include a discrete connection 114a-114n as part of a NAND bus from the NAND flash multiplexers 100a-100n to the flash memory package 70. The number, type, and/or arrangement of the components of the data path channels 202a-202n may vary depending on the design criteria of a particular implementation.

The NAND dies 90a-90n are shown implemented across multiple ones of the data path channels 202a-202 n. The NAND dies 90a-90n are each shown to include blocks (or circuits) 204a-204 n. The circuits 204a-204n may be data targets. Each of the data targets 204a-204n may correspond to one of the data path channels 202a-202 n. In the example shown, each of the data targets 204a of the NAND dies 90a-90n is part of the data path channel 202a, each of the data targets 204b of the NAND dies 90a-90n is part of the data path channel 202b, and so on. The NAND targets 204a-204n may include NAND chips, pages, blocks, and so forth.

The NAND buses 84a-84N may each include a respective one of the signal I/O and the chip enable signals CE _ A-CE _ N. The chip enable signals CE _ a-CE _ N may have a function similar to the signal CE described in association with fig. 5. Each of the chip enable signals CE _ a-CE _ N may be independently generated by flash controller 60. Each of the chip enable signals CE _ A-CE _ N may be configured to select one of the NAND dies 90 a-90N. For example, when chip enable CE _ A selects NAND die 90b, flash controller 60 may read/write from/to the NAND target 204a of NAND die 90b in data path channel 202 a.

The flash controller 60 may provide each of the chip enable signals CE _ A-CE _ N to the flash memory package 70 and to a corresponding one of the NAND flash multiplexers 100 a-100N. Each of the NAND flash multiplexers 100a-100n may be configured to: the path to a selected one of the NAND dies 90a-90n is isolated in a respective one of the data path channels 202a-202 n. In an example, the chip enable signal CE _ a may select the NAND die 90B and may be used by the NAMD flash multiplexer 100a to isolate a path between the NAND target 204a in the NAND die 90B to the flash controller 60, the chip enable signal CE _ B may select the NAND die 90i and may be used by the NAMD flash multiplexer l00B to isolate a path between the NAND target 204B in the NAND die 90i to the flash controller 60, the chip enable signal CE _ N may select the NAND die 90a and may be used by the NAMD flash multiplexer 100N to isolate a path between the NAND target 204N in the NAND die 90a to the flash controller 60, and so on.

Referring to FIG. 7, a block diagram illustrating a NAND flash bridge to increase the operating speed of a solid state drive is shown. An implementation 250 is shown. Implementation 250 may illustrate one channel of a data path similar to the SSD 50 of the example shown in association with fig. 4. Implementation 250 may include flash controller 60, flash memory package 70, and/or device 100 "'. In implementation 250, device 100' "may be configured as a NAND flash bridge. The NAND flash bridge 100' ″ may be configured to increase the operation speed of the SSD 50.

Flash controller 60 may transfer signal I/O to/from NAND flash bridge 100 "'. One or more of pins/connectors 62a-62n (not shown) of flash controller 60 may provide signal I/O to front port 110. One or more of pins/connectors 62a-62n of flash controller 60 may receive signal I/O from front port 110. The signal I/O may be conveyed on a portion of the NAND bus 84.

The flash memory package 70 may communicate with one or more of the rear ports 112a-112 n. Each of LUNs 90a-90n of flash memory package 70 may be connected to a respective one of back ports 112a-112n via discrete connectors 114a-114 n. Multiple back ports 112a-112n may be connected to multiple NAND targets 90a-90 n.

The NAND flash bridge 100' "may include a block (or circuit) 252, a plurality of blocks (or circuits) 254a-254n, a plurality of blocks (or circuits) 256a-256n, a plurality of blocks (or circuits) 258a-258n, a block (or circuit) 260, and/or a block (or circuit) 262. Circuit 252 may implement a front bridge circuit. Circuits 254a-254n may each implement a rear bridge circuit. Circuits 256a-256n may each implement a forward buffer. The circuits 258a-258n may each implement an inverting buffer. Block 260 may implement control logic. Circuit 262 may implement a sequential circuit. The NAND flash bridge 100 "' may include other components and/or inputs/outputs (not shown). The number, type, and/or arrangement of the components and/or inputs/outputs of the NAND flash bridge 100 "' may vary depending on the design criteria of a particular implementation.

The front bridge circuit 252 may include a front port 110, a block (or circuit) 266, and/or a block (or circuit) 268. Front port 110 may be configured to connect to flash controller 60. The circuitry 266 may be configured to convey data and/or commands in a forward direction (e.g., from the flash controller 60 to the flash memory package 70). Circuitry 268 may be configured to convey data and/or commands in a reverse direction (e.g., from flash memory package 70 to flash controller 60). The circuits 266 and 268 may implement a bridge. The bridge 266 and 268 may be configured to allow a signal to pass in one direction while blocking the signal from passing in the other direction. In an example, the bridge 266-268 can be implemented using an IO driver. The implementation of the bridges 266 and 268 can vary depending on the design criteria of a particular implementation.

Each of the back bridge circuits 254a-254n may include a respective one of the back ports 112a-112n, a respective one of the blocks (or circuits) 270a-270n, and/or a respective one of the blocks (or circuits) 272a-272 n. The rear ports 112a-112n may each be configured to connect to a flash memory package 70. Back ports 112a-112n may each be connected to a respective one of LUNs 90a-90n via discrete connectors 114a-114 n. The circuits 270 a-20270 n may each be configured to convey data and/or commands in a forward direction (e.g., from the flash controller 60 to the flash memory package 70). The circuits 272a-272n may each be configured to convey data and/or commands in a reverse direction (e.g., from the flash memory package 70 to the flash controller 60). The corresponding circuit pairs 270a/272a-270n/272n may each implement a bridge. Each bridge 270a/272a-270n/272n may be configured to enable signals to pass in one direction while blocking signals from passing in the other direction.

In an example, each of the bridges 270a/272a-270n/272n can be implemented using an IO driver. The implementation of the bridges 270a/272a-270n/272n may vary depending on the design criteria of a particular implementation.

The forward buffer circuits 256a-256n may be configured to temporarily store (e.g., buffer) data in the forward direction. The circuit 266 may be coupled to each of the forward buffer circuits 256a-256 n. Each of the forward buffer circuits 256a-256n may be coupled to a respective one of the circuits 270a-270 n. Forward buffer circuits 256a-256n may implement the following forward data paths: from the flash controller 60, to portions of the NAND data bus 84, to the front port 110, to the circuit 266, to the forward buffer circuits 256a-256n, to the circuits 270a-270n, to the back ports 112a-112n, to discrete portions of the NAND bus 114a-114n, and then to the LUNs 90a-90 n.

The reverse buffer circuits 258a-258n may be configured to temporarily store (e.g., buffer) data in the reverse direction. Each of the circuits 272a-272n may be coupled to a respective one of the inverse buffer circuits 258a-258 n. Each of the inverse buffer circuits 258a-258n may be connected to the circuit 268. The reverse buffer circuits 258a-258n may implement the following reverse data paths: from LUNs 90a-90n to discrete portions of NAND data buses 114a-114n, to back ports 112a-112n, to circuits 272a-272n, to inverse buffer circuits 258a-258n, to circuit 268, to front port 110, to portions of NAND bus 84, and then to flash controller 60.

The control logic circuit 260 may be configured to provide inputs to components of the NAND flash bridge 100' (e.g., the circuit 266, the circuit 268, the forward buffer circuits 256a-256n, the reverse buffer circuits 258a-258n, the circuits 270a-270n, and/or the circuits 272a-272 n). The input provided by the control logic circuit 260 may determine which component of the NAND flash bridge 100 '"may be enabled and which component of the NAND flash bridge 100'" may be disabled.

Timing circuit 262 may be configured to provide an input to control logic 260. Sequential circuit 262 may determine when components of NAND flash bridge 100 "' may be activated or deactivated. For example, timing circuit 100' "may determine that a particular one of forward buffers 256a-256n should be enabled and provide an input to control logic 260 to enable the particular one of forward buffers 256a-256 n.

Together, the control logic 260 and/or the timing circuit 262 may be configured to control the flow of data and/or commands through the NAND flash bridge 100'. In one example, by enabling/disabling one or more of forward buffers 256a-256n, control logic 260 and/or timing circuit 262 may determine which of back ports 112a-112n are connected to front port 110 to enable flash controller 60 to communicate with one of NAND targets 90a-90 n. In another example, by enabling/disabling one or more of the inverted buffers 258a-258n, the control logic 260 and/or the timing circuit 262 may determine which of the back ports 112a-112n are connected to the front port 110 to enable one of the NAND targets 90a-90n to communicate with the flash controller 60.

Front bridge circuit 252, rear bridge circuits 254a-254n, forward buffers 256a-256n, and reverse buffers 258a-258n may be configured to: enabling the front port 110 and the back ports 112a-112n to forward any commands and/or transactions between the flash controller 60 and the flash memory package 70 in both directions. The apparatus 100 "' may be configured such that each of the rear ports 112a-112n operates independently (e.g., has independent operation) simultaneously. Transaction data may be buffered in forward buffers 256a-256n and/or reverse buffers 258a-258n to allow front port 110 and back ports 112a-112n to operate at different speeds. For example, the portion of the NAND bus 84 to the flash controller 60 may operate at a different speed (or throughput) than the portion of the NAND bus that includes the discrete connectors 114a-114n to the flash memory package 70.

Since the back ports 112a-112n may have fewer NAND targets 90a-90n (e.g., targets in the illustrated example) to address than an implementation without the NAND flash bridge 100' ", each of the ports 112a-112n may operate at a throughput that is approximately the maximum interface speed of the flash memory package 70. High speed commands and/or data transfers may be cached in the data path of NAND flash bridge 100' "between front port 110 and back side ports 112a-112 n. By operating independently, the rear ports 112a-112n can be operated simultaneously. Since all of the back ports 112a-112n may be configured to transfer data simultaneously, the NAND flash bridge 100' "may provide aggregate bandwidth and/or transfer rate (or throughput) to the front ports 110. In the example shown, where NAND flash bridge 100 '"has n of back ports 112a-112n, NAND flash bridge 100'" may provide n (e.g., the number of ports) times the aggregate bandwidth to front side port 110.

In the example where the NAND flash bridge 100 '"implements four of the back ports 112a-112n, the components of the NAND flash bridge 100'" may enable the front port 110 to operate at four times the speed of one of the back ports 112a-112 n. Each of the four rear ports 112a-112n may address one of the four NAND targets 90a-90 n. The rear ports 112a-112n may operate at one speed (e.g., S _ back). In an example, the speed S _ back may be approximately the maximum speed at which one of the LUNs 90a-90n can be transported. The NAND flash bridge 100 "' may enable the front port 110 to operate at four times the speed S _ back. Implementing the NAND flash bridge 100 "' may enable two types of speed improvements for the SSD 50. One speed increase may be because the NAND flash bridge 100' "may enable the speed S _ back to reach the speed limit of the NAND targets 90a-90n due to reduced total load (e.g., input capacitance) and/or improved plate wiring topology. For example, an isolated discrete path 114a-114n may result in flash controller 60 not seeing the combined load of all LUNs 90a-90 n. Since each of the back ports 90a-90n may transmit data simultaneously, another speed increase may be because the NAND flash bridge 100' "may enable the speed of the front port 110 (e.g., S _ front) to potentially reach four times the speed S _ back (e.g., higher transmission rate) of the 4 back ports 112a-112 d.

The SSD 50 may be implemented with the apparatus 100, the apparatus 100 being configured as a NAND flash multiplexer (described in association with FIG. 5) or a NAND flash bridge (described in association with FIG. 7, for example). The SSD 50 may not implement both the NAND flash multiplexer 100 and the NAND flash bridge 100' ″ (e.g., one or the other may be implemented).

The NAND flash multiplexer 100 may improve the operation of the SSD 50 by reducing the system load and/or improving the topology. The NAND flash multiplexer 100 may achieve support from both the flash controller 60 and the flash memory packages 70a-70 n.

In one example, flash controller 60 and flash memory packages 70a-70n may support a 1GT/s data transfer speed. However, if there are multiple memories 90a-90n connected on the NAND bus 84 (e.g., without the NAND flash multiplexer 100), load and signal integrity issues may result in a lower practical speed of 0.5GT/s for the SSD 50. By implementing the NAND flash multiplexer 100, the flash controller 60 may see less direct load during operation and the SSD 50 may operate at speeds up to 1 GT/s.

The active NAND flash bridge 100' "may improve the operation of the SSD 50 by reducing system load, improving topology, and/or allowing all of the back ports 112a-112n to actively work independently. In one example, flash controller 60 may support a 1.6GT/s data transfer speed and may be connected to a plurality of LUNs 90a-90n each having a transfer speed of 0.8 GT/s. By implementing the NAND flash bridge 100', the aggregate bandwidth of data transfers of the SSD 50 may achieve 1.6GT/s (e.g., the maximum data transfer rate of the flash controller 60) by utilizing up to four times the 0.8GT/s transfer rate of the simultaneously operating LUNs 90a-90n (e.g., where four times the 0.8GT/s transfer rate is higher than 1.6GT/s, the SSD 50 may be limited to the maximum transfer rate of the fastest components).

The functions performed by fig. 1-7 may be implemented using the following as would be apparent to one of ordinary skill in the relevant art(s) programmed in accordance with the teachings of the specification: one or more conventional general purpose processors, digital computers, microprocessors, microcontrollers, RISC (reduced instruction set computer) processors, CISC (Complex instruction set computer) processors, SIMD (Single instruction multiple data) processors, signal processors, Central Processing Units (CPUs), Arithmetic Logic Units (ALUs), Video Digital Signal Processors (VDSPs), and/or the like. Appropriate software, firmware, code, routines, instructions, opcodes, microcode, and/or program modules may be readily prepared by the skilled programmer based on the teachings of the present disclosure, as will also be apparent to the relevant field(s). The software is typically executed by one or more of the machine-implemented processors from one or several media.

The invention may also be implemented by preparing the following modifications as described herein that will be apparent to those skilled in the art(s): ASICs (application specific integrated circuits), platform ASICs, FPGAs (field programmable gate arrays), PLDs (programmable logic devices), CPLDs (complex programmable logic devices), seaports, RF ICs (radio frequency integrated circuits), ASSPs (application specific standard products), one or more monolithic integrated circuits, one or more chips or dies arranged as flip-chip modules and/or multi-chip modules or by interconnecting an appropriate network of conventional component circuits.

Accordingly, the present invention may also include a computer product, which may be one or more storage media and/or one or more transmission media including instructions that may be used to program a machine to perform one or more processes or methods in accordance with the present invention. Execution of the instructions contained in the computer product by the machine and operation of the surrounding circuitry may convert input data into one or more files on a storage medium and/or one or more output signals representing physical objects or substances, such as audio and/or visual descriptions. The storage medium may include, but is not limited to, any type of magnetic disk (including floppy disks, hard disks, magnetic disks, optical disks, CD-ROMs, DVDs, and magneto-optical disks) and circuitry, such as ROMs (read only memories), RAMs (random access memories), EPROMs (erasable programmable ROMs), EEPROMs (electrically erasable programmable ROMs), UVPROMs (ultraviolet erasable programmable ROMs), flash memories, magnetic cards, optical cards, and/or any type of media suitable for storing electronic instructions.

Elements of the invention may form part or all of one or more devices, units, components, systems, machines and/or apparatuses. Devices may include, but are not limited to, servers, workstations, storage array controllers, storage systems, personal computers, laptop computers, notebook computers, palmtop computers, cloud servers, personal digital assistants, portable electronic devices, battery powered devices, set top boxes, encoders, decoders, transcoders, compressors, decompressors, preprocessors, postprocessors, transmitters, receivers, cryptographic circuits, mobile phones, digital cameras, positioning and/or navigation systems, medical equipment, heads-up displays, wireless devices, audio recording, audio storage and/or playback devices, video recording, video storage and/or playback devices, gaming platforms, peripherals, and/or multichip modules. One skilled in the relevant art(s) will appreciate that elements of the invention may be implemented in other types of devices to meet the criteria of a particular application.

The terms "may" and "generally" when used herein in conjunction with "is" and the verb are meant to convey the intent that the description is exemplary and is considered broad enough to encompass both the specific examples provided in this disclosure, as well as alternative examples that may be derived based on this disclosure. The terms "may" and "generally" as used herein should not be construed to necessarily imply a desire or possibility to omit corresponding elements.

While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention.