阅读说明：本技术 三维存储器结构及其制备方法 (Three-dimensional memory structure and preparation method thereof ) 是由 张坤 于 2021-01-14 设计创作，主要内容包括：本发明提供一种三维存储器结构及其制备方法,所述三维存储器结构包括第一半导体层；第二半导体层,设置于所述第一半导体层上；第一支撑结构,所述第一支撑结构贯穿所述第二半导体层,且所述第一支撑结构的位置与底部选择栅切槽和/或顶部选择栅切槽的位置相对应；栅堆叠结构,设置于所述第二半导体层上；垂直沟道结构,所述垂直沟道结构包括贯穿所述栅堆叠结构和所述第一支撑结构至所述第一半导体层内第一垂直沟道结构。利用本发明,在不影响器件存储容量的前提下,通过设置第一支撑结构可以加强三维存储器结构的应力,改善三维存储器结构的稳定性。(The invention provides a three-dimensional memory structure and a preparation method thereof, wherein the three-dimensional memory structure comprises a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; the first support structure penetrates through the second semiconductor layer, and the position of the first support structure corresponds to the position of the bottom selection grid cutting groove and/or the position of the top selection grid cutting groove; a gate stack structure disposed on the second semiconductor layer; a vertical channel structure including a first vertical channel structure penetrating through the gate stack structure and the first support structure into the first semiconductor layer. By using the invention, on the premise of not influencing the storage capacity of the device, the stress of the three-dimensional memory structure can be enhanced by arranging the first support structure, and the stability of the three-dimensional memory structure is improved.)

1. A three-dimensional memory structure, the three-dimensional memory structure comprising:

a first semiconductor layer;

a second semiconductor layer disposed on the first semiconductor layer;

the first support structure penetrates through the second semiconductor layer, and the position of the first support structure corresponds to the position of the bottom selection grid cutting groove and/or the position of the top selection grid cutting groove;

a gate stack structure disposed on the second semiconductor layer;

a vertical channel structure including a first vertical channel structure extending through the gate stack structure and the first support structure into the first semiconductor layer.

2. The three-dimensional memory structure of claim 1, further comprising a third semiconductor layer disposed between the second semiconductor layer and the gate stack, wherein the first support structure extends through the third semiconductor layer and the second semiconductor layer.

3. The three-dimensional memory structure of claim 1, wherein in the second direction, a width of the first support structure is greater than a bottom dimension of the vertical channel structure.

4. The three-dimensional memory structure of claim 1, wherein in the second direction, the bottom center-to-center spacing of the vertical channel structures in two alternate rows is greater than the width of the first support structure.

5. The three-dimensional memory structure of claim 1, wherein the gate stack structure comprises a bottom select gate stack structure and a storage gate stack structure, and the first support structure sequentially penetrates through the bottom select gate stack structure and the second semiconductor layer.

6. The three-dimensional memory structure of claim 1, wherein the vertical channel structure further comprises a second vertical channel structure extending through the gate stack structure into the second semiconductor layer.

7. The three-dimensional memory structure of claim 6, wherein a bottom end face and a side end face of the channel layer of the second vertical channel structure are both in contact with the second semiconductor layer.

8. The three-dimensional memory structure of claim 1, wherein the first support structure is a continuous structure or a discontinuous structure extending along the first direction.

9. The three-dimensional memory structure of any one of claims 1-8, further comprising a gate slit structure and a second support structure; the second support structure penetrates through the second semiconductor layer, and the gate gap structure penetrates through the gate stack structure and the second support structure in sequence.

10. The three-dimensional memory structure of claim 9, wherein in the second direction, a width of the second support structure is greater than a bottom width of the gate slit structure.

11. The three-dimensional memory structure of claim 9, wherein the second support structure sequentially penetrates a third semiconductor layer and the second semiconductor layer, wherein the third semiconductor layer is between the second semiconductor layer and the gate stack structure.

12. The three-dimensional memory structure of claim 9, wherein the material of the first support structure comprises silicon oxide, silicon oxynitride, silicon nitride, or aluminum oxide; the material of the second support structure comprises silicon oxide, silicon oxynitride, silicon nitride or aluminum oxide.

13. The three-dimensional memory structure of claim 9, wherein the second support structure comprises a plurality of second sub-support structures spaced apart along the first direction.

14. The three-dimensional memory structure of claim 13, wherein a length of the second sub-support structure in the first direction is greater than a bottom dimension of the vertical channel structure.

15. The three-dimensional memory structure of claim 13, wherein in the first direction, a distance between two adjacent second sub-support structures is larger than a bottom dimension of the vertical channel structure and smaller than a center-to-center distance between two columns of the vertical channel structures arranged at intervals.

16. A method for fabricating a three-dimensional memory structure, comprising:

providing a first semiconductor substrate, and sequentially forming a first semiconductor layer and a bottom sacrificial layer on the first semiconductor substrate;

forming a first groove penetrating through the bottom sacrificial layer, wherein the first groove exposes the first semiconductor layer;

filling an insulating material in the first groove to form a first supporting structure;

forming a gate sacrificial laminated structure consisting of alternately stacked interlayer dielectric layers and gate sacrificial layers on the bottom sacrificial layer;

forming a vertical channel structure including a first vertical channel structure extending through the gate sacrificial stack structure and the first support structure into the first semiconductor layer;

forming a gate line gap extending along a first direction and penetrating through the gate sacrificial stacked structure in the gate sacrificial stacked structure;

and removing the bottom sacrificial layer based on the grid line gap to form a sacrificial gap, and forming a second semiconductor layer in the sacrificial gap.

17. The method of claim 16, further comprising a step of forming a third semiconductor layer between the bottom sacrificial layer and the gate sacrificial stack structure, wherein in the step of forming a first trench penetrating the bottom sacrificial layer, the first trench penetrates the third semiconductor layer and the bottom sacrificial layer.

18. The method of claim 16, wherein a width of the first support structure in the second direction is greater than a bottom dimension of the vertical channel structure.

19. The method of claim 16, wherein in the second direction, the bottom center-to-center spacing of the two alternate rows of the vertical channel structures is greater than the width of the first support structure.

20. The method of fabricating a three-dimensional memory structure of claim 16, wherein the method of fabricating comprises:

forming a first gate sacrificial stack structure on the bottom sacrificial layer;

forming a first groove which sequentially penetrates through the first gate sacrificial laminated structure and the bottom sacrificial layer;

filling the first groove to form a first supporting structure;

and forming a second gate sacrificial laminated structure on the first gate sacrificial laminated structure, wherein the first gate sacrificial laminated structure and the second gate sacrificial laminated structure form the gate sacrificial laminated structure.

21. The method of claim 16, wherein in the step of forming a vertical channel structure, the vertical channel structure comprises a second vertical channel structure extending through the gate sacrificial stack structure into the bottom sacrificial layer.

22. The method of claim 21, wherein a functional sidewall at a bottom end of the second vertical channel structure is also removed when the bottom sacrificial layer is removed based on the gate line slit to form a sacrificial gap, such that a bottom end surface and a sidewall of a channel layer of the second vertical channel structure are exposed to contact the second semiconductor layer subsequently formed in the sacrificial gap.

23. The method of claim 16, wherein the step of forming the first trench through the bottom sacrificial layer is a continuous or discontinuous structure extending along the first direction.

24. The method of fabricating a three-dimensional memory structure of claim 16, further comprising the step of forming bottom select gate trenches and/or top select gate trenches, the first support structures corresponding to the bottom select gate trenches and/or top select gate trenches.

25. The method for fabricating a three-dimensional memory structure according to any one of claims 16 to 24, further comprising forming a second trench penetrating through the bottom sacrificial layer and filling the second trench to form a second support structure, wherein a gate gap structure subsequently formed in the gate line gap penetrates through the gate stack structure and the second support structure sequentially.

26. The method of claim 25, wherein a width of the second support structure is greater than a bottom width of the gate gap structure in a direction perpendicular to the first direction.

27. The method of claim 25, wherein when the third semiconductor layer is formed between the bottom sacrificial layer and the gate sacrificial stack structure, the step of forming a second trench penetrating the bottom sacrificial layer sequentially penetrates the third semiconductor layer and the bottom sacrificial layer.

28. The method of claim 25, wherein the material of the first support structure comprises silicon oxide, silicon oxynitride, silicon nitride, or aluminum oxide; the material of the second support structure comprises silicon oxide, silicon oxynitride, silicon nitride or aluminum oxide.

29. The method of claim 25, wherein in the steps of forming a second trench penetrating through the bottom sacrificial layer and filling the second trench with a second support structure, the second trench includes a plurality of second sub-trenches spaced along the first direction, and the second support structure includes a plurality of second sub-support structures formed in each of the sub-trenches.

30. The method of claim 29, wherein a length of the second sub-support structure in the first direction is greater than a bottom dimension of the vertical channel structure.

31. The method for fabricating a three-dimensional memory structure according to claim 29, wherein in the first direction, a distance between two adjacent second sub-support structures is larger than a bottom dimension of the vertical channel structure and smaller than a center-to-center distance between two columns of the vertical channel structures arranged at intervals.

Technical Field

The invention belongs to the field of semiconductor design and manufacture, and particularly relates to a three-dimensional memory structure and a preparation method thereof.

Background

In the chip manufacturing process, a silicon Substrate (Si Substrate) is used as a carrier for manufacturing a chip, and as the number of layers of the chip increases, more dielectric films (which may be made of tetraethoxysilane TEOS, titanium nitride SIN, or polysilicon POLY, for example) are needed. Taking 3D NAND as an example, more dielectric needs to be filled in the step region SS, the channel structure CH, and the gate gap region (GL Area) in the 3D NAND, and at the same time, the thin film structure becomes complicated, and in addition, during the annealing process in the manufacturing process, the thin film deforms, the silicon substrate hardly supports the Wafer (Wafer) deformation caused by the thin film stress, and finally the Wafer is deformed in an arc shape (arc) or the process steps cannot be performed in the machine because each machine has a limit (Limitation) on the Wafer bending (Wafer bow).

In the 3D NAND, the gate gap GL cuts the core region GB and the step region SS of the entire stacked structure into small pieces, and the structure may be unstable as the number of layers of the nitride-oxide thin Film (NO Film) increases, and at the same time, due to process limitations, the Bottom channel layer (CH Bottom POLY) of the channel structure needs to be laterally extracted, and after the sacrificial polysilicon at the Bottom is removed (SAC POLY Remove), the instability of the structure may be aggravated.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a three-dimensional memory structure and a method for fabricating the same, which are used to solve the technical problem of unstable structure of the three-dimensional memory device due to uneven stress distribution in the prior art.

To achieve the above and other related objects, the present invention provides a three-dimensional memory structure, comprising:

a first semiconductor layer;

a second semiconductor layer disposed on the first semiconductor layer;

the first support structure penetrates through the second semiconductor layer, and the position of the first support structure corresponds to the position of the bottom selection grid cutting groove and/or the position of the top selection grid cutting groove;

a gate stack structure disposed on the second semiconductor layer;

a vertical channel structure including a first vertical channel structure penetrating through the gate stack structure and the first support structure into the first semiconductor layer.

In an optional embodiment, the three-dimensional memory structure further includes a third semiconductor layer disposed between the second semiconductor layer and the gate stack structure, and the first support structure penetrates through the third semiconductor layer and the second semiconductor layer.

In an alternative embodiment, the first support structure penetrates the third semiconductor layer and the second semiconductor layer in sequence.

In an alternative embodiment, in the second direction, the width of the first support structure is greater than the bottom dimension of the vertical channel structure.

In an alternative embodiment, in the second direction, the bottom centers of the vertical channel structures spaced by two rows are spaced apart by a distance greater than the width of the first support structure.

In an alternative embodiment, both the bottom end face and the side end face of the channel layer of the vertical channel structure are in contact with the second semiconductor layer.

In an optional embodiment, the gate stack structure includes a bottom select gate stack structure and a storage gate stack structure, and the first support structure sequentially penetrates through the bottom select gate stack structure and the second semiconductor layer.

In an alternative embodiment, the vertical channel structure further comprises a second vertical channel structure extending through the gate stack structure into the second semiconductor layer.

In an alternative embodiment, both the bottom end face and the side end face of the channel layer of the second vertical channel structure are in contact with the second semiconductor layer.

In an alternative embodiment, the three-dimensional memory structure further comprises: a post process interconnect layer disposed on the gate stack structure; and

a peripheral circuit chip bonded to a surface of the next process interconnect layer distal from the gate stack structure.

In an alternative embodiment, the three-dimensional memory structure further comprises contact pads electrically connected to the peripheral circuit chip; the contact pad is arranged on one side of the first semiconductor layer far away from the peripheral circuit chip and/or one side of the peripheral circuit chip far away from the next-procedure interconnection layer.

In an optional embodiment, the three-dimensional memory structure further includes a back lead-out contact, one end of the back lead-out contact extends into the first semiconductor layer, and the other end of the back lead-out contact is electrically connected with the peripheral circuit chip.

In an alternative embodiment, the first support structure is a continuous structure or a discontinuous structure extending along the first direction.

In an alternative embodiment, the three-dimensional memory structure further comprises a gate slit structure and a second support structure; the second support structure penetrates through the second semiconductor layer, and the gate gap structure penetrates through the gate stack structure and the second support structure in sequence.

In an alternative embodiment, the width of the second support structure is greater than the width of the bottom of the gate slit structure in the second direction.

In an optional embodiment, the second support structure sequentially penetrates through a third semiconductor layer and the second semiconductor layer, wherein the third semiconductor layer is located between the second semiconductor layer and the gate stack structure.

In an alternative embodiment, the material of the first support structure comprises silicon oxide, silicon oxynitride, silicon nitride or aluminum oxide; the material of the second support structure comprises silicon oxide, silicon oxynitride, silicon nitride or aluminum oxide.

In an alternative embodiment, the second support structure comprises a plurality of second sub-support structures arranged at intervals along the first direction.

In an alternative embodiment, in the first direction, the length of the second sub-support structure is greater than the bottom dimension of the vertical channel structure.

In an alternative embodiment, in the first direction, the distance between two adjacent second sub-support structures is greater than the bottom dimension of the vertical channel structures and less than the center-to-center distance between two columns of the vertical channel structures arranged at intervals.

In order to achieve the above and other related objects, the present invention provides a method for manufacturing a three-dimensional memory structure, including:

providing a first semiconductor substrate, and sequentially forming a first semiconductor layer and a bottom sacrificial layer on the first semiconductor substrate;

forming a first groove penetrating through the bottom sacrificial layer, wherein the first groove exposes the first semiconductor layer;

filling an insulating material in the first groove to form a first supporting structure;

forming a gate sacrificial laminated structure consisting of alternately stacked interlayer dielectric layers and gate sacrificial layers on the bottom sacrificial layer;

forming a vertical channel structure including a first vertical channel structure extending through the gate sacrificial stack structure and the first support structure into the first semiconductor layer;

forming a gate line gap extending along a first direction and penetrating through the gate sacrificial stacked structure in the gate sacrificial stacked structure;

and removing the bottom sacrificial layer based on the grid line gap to form a sacrificial gap, and forming a second semiconductor layer in the sacrificial gap.

In an optional embodiment, the preparation method further includes a step of forming a third semiconductor layer between the bottom sacrificial layer and the gate sacrificial stack structure.

In an alternative embodiment, in the step of forming a first trench penetrating the bottom sacrificial layer, the first trench penetrates the third semiconductor layer and the bottom sacrificial layer.

In an alternative embodiment, in the second direction, the width of the first support structure is greater than the bottom dimension of the vertical channel structure.

In an alternative embodiment, in the second direction, the distance between the centers of the bottoms of the vertical channel structures in two rows is larger than the width of the first support structure

In an alternative embodiment, the material of the first support structure includes silicon oxide, silicon oxynitride, silicon nitride, or aluminum oxide.

In an alternative embodiment, the preparation method comprises:

forming a first gate sacrificial stack structure on the bottom sacrificial layer;

forming a first groove which sequentially penetrates through the first gate sacrificial laminated structure and the bottom sacrificial layer;

filling the first groove to form a first supporting structure;

and forming a second gate sacrificial laminated structure on the first gate sacrificial laminated structure, wherein the first gate sacrificial laminated structure and the second gate sacrificial laminated structure form the gate sacrificial laminated structure.

In an alternative embodiment, in the step of forming a vertical channel structure, the vertical channel structure includes a second vertical channel structure penetrating the gate sacrificial stack structure into the bottom sacrificial layer.

In an optional embodiment, the functional sidewall at the bottom end of the second vertical channel structure is also removed when the bottom sacrificial layer is removed based on the gate line gap to form a sacrificial gap, so that both the bottom end surface and the sidewall of the channel layer of the second vertical channel structure are exposed to contact the second semiconductor layer subsequently formed in the sacrificial gap.

In an optional embodiment, the manufacturing method further includes a step of forming a next process interconnection layer on the gate stack structure, and bonding a peripheral circuit chip on a surface of the next process interconnection layer, which is far away from the gate stack structure.

In an optional embodiment, the manufacturing method further includes a step of forming a contact pad electrically connected to the peripheral circuit chip, wherein the contact pad is disposed on a side of the first semiconductor layer away from the peripheral circuit chip and/or a side of the peripheral circuit chip away from the post-process interconnection layer.

In an optional embodiment, the manufacturing method further includes a step of forming a back lead-out contact, one end of the back lead-out contact extends into the first semiconductor layer, and the other end of the back lead-out contact is electrically connected with the peripheral circuit chip.

In an alternative embodiment, in the step of forming the first trench penetrating through the bottom sacrificial layer, the first trench is a continuous structure or a discontinuous structure extending along the first direction.

In an alternative embodiment, the method further comprises the step of forming bottom select gate trenches and/or top select gate trenches, the first support structure corresponding to the bottom select gate trenches and/or top select gate trenches.

In an optional embodiment, the manufacturing method further includes a step of forming a second trench penetrating through the bottom sacrificial layer and filling the second trench with a second support structure, and a gate gap structure formed in the gate line gap sequentially penetrates through the gate stack structure and the second support structure.

In an alternative embodiment, the width of the second support structure is greater than the width of the bottom of the gate slit structure in a direction perpendicular to the first direction.

In an optional embodiment, when the third semiconductor layer is formed between the bottom sacrificial layer and the gate sacrificial stack structure, in the step of forming a second trench penetrating through the bottom sacrificial layer, the second trench penetrates through the third semiconductor layer and the bottom sacrificial layer in sequence.

In an alternative embodiment, the material of the second support structure comprises silicon oxide, silicon oxynitride, silicon nitride or aluminum oxide.

In an optional embodiment, in the step of forming a second trench penetrating through the bottom sacrificial layer and filling the second trench with a second support structure, the second trench includes a plurality of second sub-trenches spaced apart along the first direction, and the second support structure includes a plurality of second sub-support structures formed in each of the sub-trenches.

In an alternative embodiment, in the first direction, the length of the second sub-support structure is greater than the bottom dimension of the vertical channel structure.

In an alternative embodiment, in the first direction, the distance between two adjacent second sub-support structures is greater than the bottom dimension of the vertical channel structures and less than the center-to-center distance between two columns of the vertical channel structures arranged at intervals.

In the preparation process of the three-dimensional memory, after a bottom sacrificial Layer (SAC Layer) is deposited, certain regions at the bottom of a vertical channel structure of a bottom selection gate cutting groove and/or a top selection gate cutting groove are formed in a core region and a step region to form a first groove, the first groove at least penetrates through the bottom sacrificial Layer, and then an oxide Layer or other insulating media are filled in the first groove; when the bottom sacrificial Layer (SAC Layer Remove) is removed, the oxide Layer or other insulating medium filled in the first trench can support the core region and the step region, and the first support structure is located in some regions at the bottom of the vertical channel structure of the bottom selection gate incision and/or the top selection gate incision, so that the stress of the three-dimensional memory structure can be enhanced and the stability of the three-dimensional memory structure can be improved on the premise of not affecting the storage capacity of the three-dimensional memory structure.

In the preparation process of the three-dimensional memory, after a bottom sacrificial Layer (SAC Layer) is deposited, certain areas at the bottom of a grid line gap are formed in a core area and a step area, a second groove is formed, the second groove at least penetrates through the bottom sacrificial Layer, then an oxide Layer or other insulating media are filled in the second groove, and when the bottom sacrificial Layer (SAC Layer Remove) is removed, the oxide Layer or other insulating media filled in the second groove can support the core area and the step area, so that the stress of the three-dimensional memory structure can be enhanced, and the stability of the three-dimensional memory structure is improved.

In the manufacturing process of the three-dimensional memory, because the first support structure can play a role of supporting to prevent the device from collapsing when the bottom sacrificial Layer (SAC Layer Remove) is removed to form the sacrificial gap, the bottom of the vertical channel structure can extend into the bottom sacrificial Layer (SAC Layer) when the vertical channel structure is formed, so that when the bottom sacrificial Layer is removed to form the sacrificial gap, the functional side wall (with the ONO structure) at the bottom of the vertical channel structure can be completely removed to expose the bottom side wall and the bottom surface of the channel Layer of the vertical channel structure, and then the second semiconductor Layer formed in the sacrificial gap can cover the channel Layer at the bottom of the vertical channel structure, the conductivity at the bottom of the channel structure can be better, and the performance of the three-dimensional memory can be improved.

The technical scheme of the invention has simple process, and can be carried out in the existing etching and depositing process steps without increasing extra cost when the etching of the groove and the deposition of the oxide layer or other insulating media in the groove are carried out as the supporting structure.

Drawings

FIG. 1 is a flow chart illustrating the fabrication of a three-dimensional memory structure according to the present invention.

Fig. 2 is a schematic cross-sectional view of the three-dimensional memory structure after forming a first trench penetrating through the bottom sacrificial layer.

Fig. 3 is a schematic cross-sectional view illustrating a gate sacrificial stack structure formed on a third semiconductor layer in the fabrication of a three-dimensional memory structure according to the present invention.

Fig. 4 is a schematic cross-sectional view illustrating a vertical channel structure formed in a gate sacrificial stack structure during fabrication of a three-dimensional memory structure according to the present invention.

Fig. 5 is a schematic cross-sectional view of the three-dimensional memory structure after a gate line gap is formed in the preparation process.

Fig. 6 is a schematic cross-sectional view of the three-dimensional memory structure after a gate sacrificial layer in the gate sacrificial stack structure is replaced with a conductive material based on the gate line gap to form a gate layer in the preparation of the three-dimensional memory structure according to the invention.

Fig. 7 is a schematic cross-sectional view of the three-dimensional memory structure according to the present invention after a gate line gap is filled in the gate line gap.

Fig. 8 is a schematic cross-sectional view of a three-dimensional memory structure according to the present invention after a post-process interconnect layer is formed on the gate stack structure.

Fig. 9 is a schematic cross-sectional view of the three-dimensional memory structure of the present invention after bonding a peripheral circuit chip on the surface of the gate stack structure away from the interconnect layer in the next step in the fabrication of the three-dimensional memory structure.

Figure 10 shows a schematic cross-sectional view of a first example of a fabricated three-dimensional memory structure of the present invention.

FIG. 11 is a top view of the second semiconductor layer of the three-dimensional memory structure of FIG. 10.

FIG. 12 is a schematic top view of another second semiconductor layer of the three-dimensional memory structure of FIG. 10.

Fig. 13-17 are cross-sectional schematic diagrams illustrating second-sixth examples of three-dimensional memory structures of the present invention.

Description of the element reference numerals

100 array chip

101 first semiconductor substrate

102 first semiconductor layer

103 bottom sacrificial layer

104 third semiconductor layer

105 first trench

106 gate sacrificial stack structure

107 gate sacrificial layer

108 interlayer dielectric layer

109 step coverage

110 first support structure

110a first sub-support structure

111 second support structure

111a second sub-support structure

112 vertical channel structure

113 grid line gap

114 second semiconductor layer

115 grid layer

116 gate stack structure

116a bottom select gate stack structure

116b memory gate stack structure

117 grid gap structure

118 post process interconnect layer

119 first connecting column

120 second connecting column

121 third connecting column

122 second trench

200 peripheral circuit chip

201 second semiconductor substrate

202 peripheral circuit dielectric layer

203 peripheral interconnect layer

204 CMOS structure

300 backside dielectric capping layer

400 back lead-out contact

500 pad protective layer

600 contact connection layer

700 through silicon via contact

800 contact sidewall spacer

900 contact pad

S10-S70

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

Fig. 1 shows a flow chart of the preparation of the three-dimensional memory structure of the present invention, fig. 2 to 10 show schematic cross-sectional views corresponding to different process steps in the preparation process of the three-dimensional memory structure of the present embodiment, and fig. 11 and 12 show two different top views of the second semiconductor layer of the three-dimensional memory structure prepared in the present embodiment, respectively. In fig. 2 to 10 and fig. 13 to 17, the left step region is a cross section in the X direction, and the right core region is a cross section in the Y direction.

Referring to fig. 1, a method for manufacturing a three-dimensional memory structure of the present embodiment includes:

step S10, providing a first semiconductor substrate, and sequentially forming a first semiconductor layer and a bottom sacrificial layer on the first semiconductor substrate;

step S20, forming a first trench penetrating through the bottom sacrificial layer, the first trench exposing the first semiconductor layer;

step S30, filling an insulating material in the first trench to form a first supporting structure;

step S40, forming a gate sacrificial laminated structure consisting of alternately stacked interlayer dielectric layers and gate sacrificial layers on the bottom sacrificial layer;

step S50, forming a vertical channel structure penetrating through the gate sacrificial stack structure, wherein at least part of the vertical channel structure also penetrates through the first support structure;

step S60, forming a gate line slit extending along a first direction and penetrating through the gate sacrificial stacked structure in the gate sacrificial stacked structure;

step S70, removing the bottom sacrificial layer based on the gate line slit to form a sacrificial gap, and forming a second semiconductor layer in the sacrificial gap, wherein the first support structure plays a supporting role.

The method for fabricating the semiconductor structure of the present embodiment will be described in detail with reference to the schematic diagrams corresponding to the respective steps.

First, referring to fig. 2, step S10 is executed: a first semiconductor substrate 101 is provided, and a first semiconductor layer 102, a bottom sacrificial layer 103 and a third semiconductor layer 104 are sequentially formed on the first semiconductor substrate 101. The first semiconductor substrate 101 may be selected according to actual requirements of devices, the first semiconductor substrate 101 may include a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, a GOI (Germanium-on-Insulator) substrate, and the like, in other embodiments, the first semiconductor substrate 101 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or Silicon carbide, and the like, and the first semiconductor substrate 101 may also be a stacked structure, such as a Silicon/Germanium-Silicon stacked layer, and the like. As an example, the first semiconductor substrate 101 may be a single crystal silicon wafer, for example.

In this embodiment, the first semiconductor layer 102 may be a semiconductor layer formed by ion implantation on the first semiconductor substrate 101, or may be a semiconductor layer formed directly on the first semiconductor substrate 101 by a deposition process, and the materials of the first semiconductor layer 102, the third semiconductor layer 104, and a second semiconductor layer 114 to be described later may be, for example, doped polysilicon. It should be noted that, when the first semiconductor layer 102 is formed on the first semiconductor substrate 101 through a deposition process, a thinning stop layer (not shown in the figure) may be further formed between the first semiconductor layer 102 and the first semiconductor substrate 101 through the deposition process, and the thinning stop layer may serve to remove the stop layer of the first semiconductor substrate 101 through a chemical mechanical polishing process, and the material of the thinning stop layer may be, for example, a stacked structure composed of silicon oxide-silicon nitride (or silicon oxynitride) -silicon oxide.

Next, referring to fig. 2 and fig. 3, step S20 and step S30 are executed: for example, the first trench 105 and the second trench 122 penetrating through the bottom sacrificial layer 103 may be formed simultaneously by an etching process, and the first trench 105 and the second trench 122 may be filled with an insulating material to form the first support structure 110 and the second support structure 111. The first trench 105 exposes the first semiconductor layer 102, and the first trench 105 corresponds to a bottom select gate incision (not shown) and/or a top select gate incision (not shown), and the second trench 122 corresponds to a gate line gap to be formed later; for example, a deposition process and a chemical mechanical polishing process may be used to simultaneously fill the first trench 105 and the second trench 122 with an insulating medium to form the first support structure 110 and the second support structure 111, where the material of the first support structure 110 may be, for example, an insulating medium such as silicon oxide, silicon oxynitride, silicon nitride, or aluminum oxide.

It should be noted that, for example, the first grooves 105 may adopt a continuous structure or a discontinuous structure (including a plurality of first sub-grooves arranged at intervals along the first direction), so that the first support structures 110 are also a continuous structure (see fig. 11) or a discontinuous structure (see fig. 12), which is described in the related parts below and is not described herein again; the second trench 122 has a discontinuous structure including a plurality of second sub-trenches spaced apart along a first direction, which is a direction parallel to the gate line gap filling layer 117 shown in fig. 11 and 12 or the gate line gap 113 shown in fig. 5 and will be described later, so that the second support structure 111 also has a discontinuous structure, as will be described later (see fig. 11 and 12).

In the present embodiment, referring to fig. 2 and fig. 3, after the first trench 105 and the second trench 122 are formed after the deposition of the third semiconductor layer 104, that is, the first trench 105 and the second trench 122 sequentially penetrate through the third semiconductor layer 104 and the bottom sacrificial layer 103, so that the first support structure 110 and the second support structure 111 subsequently formed in the first trench 105 and the second trench 122 sequentially penetrate through the third semiconductor layer 104 and the bottom sacrificial layer 103.

It should be noted that, since the vertical channel structure at the location of the bottom select gate trench and/or the top select gate trench cannot be used for storing data, the first trench 105 is disposed at a location corresponding to the location of the bottom select gate trench and/or the top select gate trench, which can ensure that the first support structure 110 formed in the first trench 105 can strengthen the stress of the three-dimensional memory structure without affecting the storage capacity of the three-dimensional memory structure, and improve the stability of the three-dimensional memory structure.

Referring to fig. 3 and 4, steps S40 and S50 are performed: forming a gate sacrificial stack structure 106 composed of alternately stacked interlayer dielectric layers 108 and gate sacrificial layers 107 on the bottom sacrificial layer 103, wherein the gate sacrificial stack structure 106 includes a core sequentially arranged along a first direction (corresponding to the X direction in fig. 11 and 12)A region and a step region, a vertical channel structure 112 is formed in the core region, the vertical channel structure 112 includes a functional sidewall and a channel layer sequentially arranged along a radial inward direction, the vertical channel structure 112 includes a first vertical channel structure penetrating through the gate sacrificial stack structure 106 and the first support structure 110 into the first semiconductor layer 102, and a second vertical channel structure penetrating through the gate sacrificial stack structure 106 into the bottom sacrificial layer 103. The interlayer dielectric layer 108 and the gate sacrificial layer 107 have a high etching selectivity ratio to ensure that the interlayer dielectric layer 108 is hardly removed when the gate sacrificial layer 107 is subsequently removed, and the material of the gate sacrificial layer 107 may include, but is not limited to, silicon nitride (Si)₃N₄) The material of the interlayer dielectric layer 108 may include, but is not limited to, silicon oxide (SiO)₂). It should be noted that, in the present invention, the number of layers of the gate sacrificial layer 107 in the gate sacrificial stack structure 106 may include 32 layers, 64 layers, 96 layers, 128 layers, and the like, and specifically, the number of layers of the gate sacrificial layer 107 and the interlayer dielectric layer 108 in the gate sacrificial stack structure 106 may be set according to actual needs, which is not limited herein. The gate sacrificial Layer 107 and the interlayer dielectric Layer 108 may be formed by a process including, but not limited to, a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process, such as a Chemical Vapor Deposition method.

Referring to fig. 5, step S60 is executed: for example, a gate line slit 113 extending along a first direction and penetrating through the gate sacrificial stack structure 106 may be formed in the gate sacrificial stack structure 106 through an etching process, the gate line slit 113 sequentially penetrates through the gate sacrificial stack structure 106 and the second support structure 111, and each gate line slit 113 may separate the second support structure 111 into two independent portions respectively located at two sides of the gate line slit 113.

Referring to fig. 6, step S70 is executed: the bottom sacrificial layer 103 is removed based on the gate line slit 113 to form a sacrificial gap, and a second semiconductor layer 114 is formed in the sacrificial gap. Specifically, a sidewall protection layer is formed on a sidewall of the gate line slit 113, and then the bottom sacrificial layer 103 and a functional sidewall of the vertical channel structure 112 surrounded by the bottom sacrificial layer 103 are removed based on the gate line slit 113 formed with the sidewall protection layer to form a sacrificial gap; finally, a conductive material (e.g., polysilicon) is filled in the sacrificial gap to form the second semiconductor layer 114, and the second semiconductor layer 114 is in contact with the bottom of the channel layer of the vertical channel structure 112.

In the prior art, the vertical channel structure 112 sequentially penetrates through the gate sacrificial stack structure 106, the third semiconductor layer 104 and the bottom sacrificial layer 103 and extends into the first semiconductor layer 102, so that when the bottom sacrificial layer 103 is removed based on the gate line slit 113 to form a sacrificial gap (the sacrificial gap exposes the bottom sidewall of the channel layer of the vertical channel structure 112), the third semiconductor layer 104 and the first semiconductor layer 102 are supported by the vertical channel structure 112, and then the second semiconductor layer 114 is contacted with the bottom sidewall of the channel layer when the sacrificial gap is filled with polysilicon as the second semiconductor layer 114, which results in poor conductivity. In the present embodiment, as shown in fig. 3-6, since the first support structure 110 can support and prevent device collapse when the bottom sacrificial Layer 103(SAC Layer Remove) is removed to form the sacrificial gap, the vertical channel structure 112 that does not penetrate through the first support structure 110 when forming the vertical channel structure 112 penetrates through the gate sacrificial stack structure 106 and the third semiconductor Layer 104 in sequence and then enters the bottom sacrificial Layer 103, thus, when the bottom sacrificial layer 103 and the functional sidewall of the vertical channel structure 112 surrounded by the bottom sacrificial layer 103 are removed based on the gate line slit 113 formed with the sidewall protection layer to form a sacrificial gap, the bottom functional sidewall (with the ONO structure) of the vertical channel structure 112 is completely removed, thereby exposing the bottom sidewall and the bottom surface of the trench layer of the vertical channel structure 112; the second semiconductor layer 114, which is subsequently formed in the sacrificial gap, wraps the bottom sidewall and the bottom surface of the channel layer at the bottom of the vertical channel structure 112, thereby improving the conductivity at the bottom of the channel structure and improving the performance of the three-dimensional memory. It is understood that, in other embodiments, the vertical channel structure 112 may also sequentially penetrate through the gate sacrificial stack structure 106, the third semiconductor layer 104 and the bottom sacrificial layer 103 and then enter the first semiconductor layer 102, so that only a part of the functional sidewall of the bottom sidewall of the vertical channel structure 112 surrounded by the bottom sacrificial layer 103 is removed when the bottom sacrificial layer 103 is removed based on the gate line slit 113.

Referring to fig. 6, the method further includes replacing the gate sacrificial layer 107 with a conductive material based on the gate line slit 113 to form a gate layer 115, so as to form a gate stack structure 116 formed by alternately stacking the interlayer dielectric layers 108 and the gate layer 115. Specifically, a wet etching process may be used to remove the gate sacrificial layer 107 in the gate sacrificial stack structure 106 to form a gate gap, and then the gate gap is filled with a conductive material to form the gate layer 115, where the material of the gate layer 115 includes, but is not limited to, any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped poly-Si (polysilicon), doped single-crystal Si, silicide, or any combination thereof, such as tungsten.

In this embodiment, referring to fig. 7, after the gate stack structure 116 is formed, a step of filling an insulating material in the gate line gap 113 to form a gate gap structure 117 is further included, the gate gap structure 117 sequentially penetrates through the gate stack structure 116 and the second support structure 111, and the gate gap structure 117 may be made of, for example, silicon nitride, silicon oxynitride, silicon oxide, or the like.

In this embodiment, the step of forming the gate gap structure 117 further includes forming a next process interconnect layer 118 on the gate stack structure 116 (as shown in fig. 8), and bonding a peripheral circuit chip 200 on a surface of the next process interconnect layer 118 away from the gate stack structure 116 (as shown in fig. 9).

In the present embodiment, referring to fig. 8, each gate layer 115 of the gate stack structure 116 is electrically connected to the peripheral circuit chip 200 through a first connection pillar 119 (word line connection pillar) formed at a step of an end portion and the next-process interconnection layer 118, and the top of the channel layer of the vertical channel structure 112 is electrically connected to the peripheral circuit chip 200 through a channel plug and the next-process interconnection layer 118. The peripheral circuit chip 200 includes a second semiconductor substrate 201 and any suitable digital, analog, and/or mixed signal peripheral circuits formed on the second semiconductor substrate 201 for facilitating operation of the three-dimensional memory device. For example, the peripheral circuitry may include one or more page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers, charge pumps, current or voltage reference sources, or any active or passive components of circuitry (e.g., transistors, diodes, resistors, or capacitors). As an example, the peripheral circuit chip 200 may be a CMOS chip, and transistors of a CMOS structure 204, a peripheral interconnection layer 203, and a peripheral circuit dielectric layer 202 are formed on the second semiconductor substrate 201, and the peripheral circuit dielectric layer 202 is filled around the CMOS structure 204 and in the peripheral interconnection layer 203.

In this embodiment, referring to fig. 10, the preparation method further includes a step of leading out a first semiconductor layer 102 and forming a contact pad 900, so as to finally form the three-dimensional memory structure shown in fig. 10, where the contact pad 900 is disposed on a Side of the first semiconductor layer 102 away from the peripheral circuit chip 200, and the first semiconductor layer 102 is led out from a Back Side Pick Up p of the array chip 100. Specifically, as shown in fig. 10, the steps of leading out the first semiconductor layer 102 and forming the contact pad 900 specifically include: the first semiconductor substrate 101 may be removed using a mechanical chemical polishing process (CMP) to reveal the first semiconductor layer 102; forming a first dielectric backside cap layer 300 on the surface of the first semiconductor layer 102; forming a back lead-out contact 400, wherein one end of the back lead-out contact 400 penetrates through the first back dielectric covering layer 300 and then extends into the first semiconductor layer 102; a contact pad 900 and a contact connection layer 600 are formed at the same time, the contact pad 900 is connected to the peripheral circuit chip 200 through the tsv contact 700, the third connection stud 121 and the next-process interconnection layer 118 which sequentially penetrate through the first back dielectric cover layer 300 and the first semiconductor layer 102, and the back lead-out contact 400 is connected to the peripheral circuit chip 200 through the contact connection layer 600 and the tsv contact 700, the second connection stud 120 and the next-process interconnection layer 118 which sequentially penetrate through the first back dielectric cover layer 300 and the first semiconductor layer 102. To isolate the through-silicon via contact 700 from the first semiconductor layer 102, a contact sidewall spacer 800 is formed between the through-silicon via contact 700 and the first semiconductor layer 102. In order to protect the contact pad 900 and the contact connection layer 600, a pad protection layer 500 is further formed on the surface of the first back dielectric cover layer 300 and the sidewall of the contact pad 900, and the material of the pad protection layer 500 may be, for example, a high dielectric constant material (such as aluminum oxide).

Referring to fig. 10, in the present embodiment, the three-dimensional memory structure includes an array chip 100 and a peripheral circuit chip 200 bonded to each other, the array chip 100 includes a first semiconductor layer 102, a second semiconductor layer 114, a third semiconductor, a gate stack structure 116, a next-process interconnection layer 118, a first support structure 110 and a second support structure 111 sequentially penetrating through the third semiconductor layer 104 and the second semiconductor layer 114, a gate slit structure 117, and the peripheral circuit chip 200 is bonded to the next-process interconnection layer 118. The gate stack structure 116 includes a core region and a step region sequentially arranged along a first direction, wherein a vertical channel structure 112 is formed in the core region; the position of the first support structure 110 corresponds to the position of a bottom select gate incision and/or a top select gate incision, at least a portion of the vertical channel structure 112 located at the position of the bottom select gate incision and/or the top select gate incision sequentially penetrates through the gate stack structure 116 and the first support structure 110, and the gate slit structure 117 sequentially penetrates through the gate stack structure 116 and the second support structure 111. For details of the structure, please refer to the description of the preparation method above, which is not repeated herein.

Referring to fig. 10, in the present embodiment, the vertical channel structure 112 includes a functional sidewall and a channel layer sequentially disposed along a radially inward direction; the vertical channel structure 112 that does not penetrate the first support structure 110 penetrates the gate stack structure 116 and then enters the second semiconductor layer 114, in other words, the second semiconductor layer 114 covers the channel layer at the bottom of the vertical channel structure 112, so that the conductivity at the bottom of the channel structure is better, and the performance of the three-dimensional memory is improved.

It should be noted that, according to whether the first support structure 110 is a continuous structure, the top surface view of the second semiconductor layer 114 of the three-dimensional memory structure shown in fig. 10 is shown in fig. 11 and 12, where in fig. 11, the first support structure 110 is a continuous structure, and in fig. 12, the first support structure 110 is a discontinuous structure, and the first support structure 110 is composed of a plurality of first sub-support structures 110a arranged at intervals along the X-direction. Referring to fig. 11 and 12, in a specific example, in order to achieve better supporting effect, the width C (defined as the dimension along the Y direction) of the first supporting structure 110 needs to be greater than B and smaller than the difference between a and B, where a is defined as the width occupied by the bottoms of two rows of vertical channel structures 112 spaced apart in the Y direction, B is defined as the dimension of the bottoms of the vertical channel structures 112 along the Y direction, and a-B is defined as the bottom center distance between two rows of vertical channel structures 112 spaced apart in a second direction, where the X direction is perpendicular to the Y direction.

Referring to fig. 11 and 12, the second support structure 111 is a discontinuous structure, the second support structure 111 includes a plurality of second sub-support structures 111a spaced apart along the length direction of the gate line slit 113, and the bottom sacrificial layer 103 can be removed by etching based on the gate line slit 113 by using the discontinuous second support structure 111. Referring to fig. 11 and 12, in a specific example, to achieve a better supporting effect, the second supporting structure 111 includes a plurality of second sub-supporting structures 111a disposed at equal intervals along a length direction of the gate line slit 113, and a width E of the second supporting structure 111 is greater than a bottom dimension F of the gate slit structure 117 in a Y direction; in the X direction, the distance G between two adjacent second sub-support structures 111a is greater than the bottom dimension I of the vertical channel structures 112 and less than the center-to-center distance H between two columns of vertical channel structures 112, and the length J of the second sub-support structures 111a in the X direction is greater than the bottom dimension I of the vertical channel structures 112 in the X direction. As an example, when the vertical channel structure 112 has a circular cross-section, B and I are the bottom diameters of the vertical channel structure 112 and are equal.

It should be noted that, in the method for fabricating a three-dimensional memory according to this embodiment, after depositing the bottom sacrificial Layer 103(SAC Layer), certain regions at the bottom of the vertical channel structure 112 of the bottom select gate incision and/or the top select gate incision are formed in the core region and the step region, the first trench 105 is formed, the first trench 105 at least penetrates through the bottom sacrificial Layer 103, then the first trench 105 is filled with an oxide Layer or other insulating medium, when removing the bottom sacrificial Layer 103(SAC Layer Remove), the oxide Layer or other insulating medium filled in the first trench 105 will support the core region and the step region, and since the first support structure 110 is located at certain regions at the bottom of the vertical channel structure 112 of the bottom select gate incision and/or the top select gate incision, the first support structure 110 is arranged to strengthen the three-dimensional memory without affecting the storage capacity of the three-dimensional memory structure And (4) stress, and the stability of the three-dimensional memory structure is improved.

It should be noted that, in the method for manufacturing a three-dimensional memory of this embodiment, after depositing the bottom sacrificial Layer 103(SAC Layer), a second trench 122 is formed in some regions at the bottom of the gate line gap in the core region and the step region, the second trench 122 at least penetrates through the bottom sacrificial Layer 103, and then an oxide Layer or other insulating medium is filled in the second trench 122, so that when the bottom sacrificial Layer 103(SAC Layer Remove) is removed, the oxide Layer or other insulating medium filled in the second trench 122 can support the core region and the step region, thereby enhancing the stress of the three-dimensional memory structure and improving the stability of the three-dimensional memory structure.

It should be noted that, the three-dimensional memory structure may also be a structure as shown in fig. 13 to 15, depending on the lead-out manner of the first semiconductor layer 102 and the formation position of the contact pad 900. Specifically, in fig. 13, the contact pad 900 is disposed on the Side of the peripheral circuit chip 200 away from the next-process interconnect layer 118, while the first semiconductor layer 102 is led out (Front Side Pick Up) from the Front surface of the array chip 100, the first semiconductor layer 102 is connected to the peripheral circuit chip 200 through the second connection post 120 penetrating through the step cover layer 109 and the next-process interconnect layer 118; in fig. 14, the contact pad 900 is disposed on a side of the first semiconductor layer 102 away from the peripheral circuit chip 200, and the first semiconductor layer 102 is led out from the front surface of the array chip 100; as shown in fig. 15, the contact pads 900 are disposed on a side of the peripheral circuit chip 200 away from the next-process interconnect layer 118, and the first semiconductor layer 102 is led out from the back surface of the array chip 100.

It should be noted that, in some embodiments, the first trench 105 and the second trench 122 may also be formed before the deposition of the third semiconductor layer 104, that is, the first trench 105 and the second trench 122 penetrate through the bottom sacrificial layer 103, and the third semiconductor layer 104 is deposited on the bottom sacrificial layer 103 after the first support structure 110 and the second support structure 111 are formed in the first trench 105 and the second trench 122, so that the finally formed three-dimensional memory structure is as shown in fig. 16.

In some embodiments, as shown in fig. 17, the gate stack structure 116 may further include a bottom selection gate stack structure 116a and a storage gate stack structure 116b, and the first support structure 110 and the second support structure 111 sequentially penetrate through the bottom selection gate stack structure 116a of the gate stack structure 116, the third semiconductor layer 104, and the second semiconductor layer 114, and are formed by the following steps: forming a first semiconductor layer 102, a bottom sacrificial layer 103 (which is subsequently replaced by a second semiconductor layer 114), a third semiconductor layer 104 and a first gate sacrificial stacked structure (corresponding to a bottom select gate stacked structure 116a) on a first semiconductor substrate 101 in sequence; then, forming a first trench 105 and a second trench 122 sequentially penetrating through the first gate sacrificial stack structure, the third semiconductor layer 104 and the bottom sacrificial layer 103 at corresponding positions by an etching process; then, filling the first trench 105 and the second trench 122 to form a first support structure and a second support structure 111; then, forming a second gate sacrificial stacked structure (corresponding to the storage gate stacked structure 116b) on the surface of the first gate sacrificial stacked structure, wherein the first gate sacrificial stacked structure and the second gate sacrificial stacked structure jointly form a gate sacrificial stacked structure 106; finally, the three-dimensional memory structure shown in fig. 17 can be finally formed according to the above step S50 and similar steps following the above step.

Although the first support structure 110 and the second support structure 111 are formed in the three-dimensional memory structure in the present embodiment, it is understood that in some embodiments, only the first support structure 110 or only the second support structure 111 may be formed in the three-dimensional memory structure.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.