阅读说明：本技术 用于ssd的总线多路复用器网格的高级ce编码 (Advanced CE encoding for a bus multiplexer grid of an SSD ) 是由 D·沃斯曼 H·博鲁霍夫 L·明兹 R·泽昌斯基 于 2020-06-29 设计创作，主要内容包括：本公开总体涉及一种用于在数据存储设备中的每个通道访问更多管芯的方法和设备。每个闪存接口模块(FIM)可以具有与其耦合的任何数量的总线多路复用器,并且每个总线多路复用器可以具有与其耦合的任何数量的存储器设备。总线多路复用器可以串联或并联连接到FIM。各个总线多路复用器可以通过芯片使能(CE)命令进行寻址,该命令标识特定总线多路复用器以及特定总线多路复用器的特定存储器设备。CE命令中的信息允许每个通道更多的管芯,而不产生信号干扰(SI)或限制传输性能。(The present disclosure relates generally to a method and apparatus for accessing more dies per channel in a data storage device. Each Flash Interface Module (FIM) may have any number of bus multiplexers coupled thereto, and each bus multiplexer may have any number of memory devices coupled thereto. The bus multiplexers may be connected to the FIM in series or in parallel. Each bus multiplexer may be addressed by a Chip Enable (CE) command that identifies the particular bus multiplexer and the particular memory device of the particular bus multiplexer. The information in the CE commands allows more dies per channel without generating Signal Interference (SI) or limiting transmission performance.)

1. A data storage device, comprising:

a plurality of memory devices;

a plurality of bus multiplexers, wherein each bus multiplexer is coupled to one or more of the plurality of memory devices; and

a flash interface module coupled to the plurality of bus multiplexers; and

a controller coupled to the flash interface module, the controller configured to:

sending, by the flash interface controller, a chip enable command, wherein the chip enable command includes a bus multiplexer identifier and a memory device identifier.

2. The data storage device of claim 1, wherein each bus multiplexer is configured to ignore chip enable commands directed to a different bus multiplexer.

3. The data storage device of claim 1, wherein each bus multiplexer is configured to direct a chip enable command to a particular memory device coupled thereto.

4. The data storage device of claim 1, wherein the controller is configured to send the chip enable command as part of a larger command comprising a read command or a write command.

5. The data storage device of claim 4, wherein the chip enable command comprises 8 bits.

6. The data storage device of claim 4, wherein the larger command includes a prefix portion, and wherein the chip enable command is between the prefix portion within the larger command and the read command or write command.

7. The data storage device of claim 1, wherein the flash interface module is a first flash interface module, wherein the data storage device comprises a plurality of flash interface modules, and wherein each of the plurality of flash interface modules is coupled to a plurality of bus multiplexers.

8. The data storage device of claim 1, wherein the chip enable command is sent with a bus multiplexer signal and a memory device signal.

9. A data storage device, comprising:

a controller;

a plurality of flash memory interface modules coupled to the controller;

a plurality of bus multiplexers coupled to at least a first flash interface module of the plurality of flash interface modules; and

a plurality of memory devices coupled to a first bus multiplexer of the plurality of bus multiplexers, wherein the controller is configured to:

sending a first signal to the first flash memory interface module;

sending a second signal to the first flash interface module, wherein the second signal is lower than the first flash signal; and is

Sending a command signal to the first flash interface module, wherein the first signal, the second signal, and the command signal are different.

10. The data storage device of claim 9, wherein the first signal identifies the first bus multiplexer.

11. The data storage device of claim 10, wherein the second signal identifies the first memory device.

12. The data storage device of claim 9, wherein the plurality of bus multiplexers are connected in parallel to the first flash interface module.

13. The data storage device of claim 9, wherein the plurality of bus multiplexers are connected in series to the first flash interface module.

14. The data storage device of claim 13, wherein the plurality of bus multiplexers, other than the first bus multiplexer, are configured to ignore the first signal, the second signal, and the command signal.

15. The data storage device of claim 9, wherein each bus multiplexer has a unique ID number that is static or given after discovery by the controller.

16. A data storage device, comprising:

a plurality of memory devices;

a plurality of bus multiplexers, wherein each bus multiplexer is coupled to at least one memory device of the plurality of memory devices;

a flash interface module coupled to the plurality of bus multiplexers; and

means for delivering a chip enable command signal to a first memory device of the plurality of memory devices, wherein the chip enable command signal includes a bus multiplexer identifier and a memory device identifier.

17. The data storage device of claim 16, further comprising means for delivering two different signals to the flash interface module.

18. The data storage device of claim 17, wherein the two different signals are different voltages.

19. The data storage device of claim 16, wherein the flash interface module further comprises means for ignoring the chip enable command.

20. The data storage device of claim 16, further comprising means for allowing the chip enable command to pass through a bus multiplexer of the plurality of bus multiplexers.

Technical Field

Embodiments of the present disclosure generally relate to a method and apparatus for accessing more dies per channel in a data storage device.

Background

Supporting high capacity configurations is problematic when extending client SSD architectures to entry level enterprise architectures. In particular, NAND selection and high capacitive loading are problematic due to the parallel connection of multiple dies, resulting in signal integrity issues.

With regard to NAND selection, a typical high-side controller has 8 NAND channels, referred to as a Flash Interface Module (FIM). Each FIM has two chip enable pins (CEs) that allow two NAND groups to be selected. Due to space limitations, the maximum capacity of a die is, for example, eight die. As the demand for higher capacity continues to increase, the controller should support more dies per FIM. However, Application Specific Integrated Circuits (ASICs) are limited by 2 CEs.

With respect to capacitive loading, the transmission speed should be limited to a limit in order to support the required host performance. The maximum number of die "connected" to a channel cannot exceed a certain number of die, such as eight die, due to Signal Integrity (SI) issues. In some cases, fewer dies may create serious SI problems and limit transmission performance.

Therefore, there is a need in the art to access more dies per channel in a data storage device while maintaining SI and not limiting transmission performance.

Disclosure of Invention

The present disclosure relates generally to a method and apparatus for accessing more dies per channel in a data storage device. Each Flash Interface Module (FIM) may have any number of bus multiplexers coupled thereto, and each bus multiplexer may have any number of memory devices coupled thereto. The bus multiplexers may be connected to the FIM in series or in parallel. Each bus multiplexer may be addressed by a Chip Enable (CE) command that identifies the particular bus multiplexer and the particular memory device of the particular bus multiplexer. The information in the CE commands allows more dies per channel without generating Signal Interference (SI) or limiting transmission performance.

In one embodiment, a data storage device comprises: a plurality of memory devices; a plurality of bus multiplexers, wherein each bus multiplexer is coupled to one or more of the plurality of memory devices; and a flash interface module coupled to the plurality of bus multiplexers; and a controller coupled to the flash interface module, wherein the controller is configured to: a chip enable command is sent through the flash interface controller, wherein the chip enable command includes a bus multiplexer identifier and a memory device identifier.

In another embodiment, a data storage device comprises: a controller; a plurality of flash memory interface modules coupled to the controller; a plurality of bus multiplexers coupled to at least a first flash interface module of the plurality of flash interface modules; and a plurality of memory devices coupled to a first bus multiplexer of the plurality of bus multiplexers, wherein the controller is configured to: sending the first signal to a first flash memory interface module; sending a second signal to the first flash memory interface module, wherein the second signal is lower than the first flash memory signal; and sending a command signal to the first flash interface module, wherein the first signal, the second signal, and the command signal are different.

In another embodiment, a data storage device comprises: a plurality of memory devices; a plurality of bus multiplexers, wherein each bus multiplexer is coupled to at least one memory device of the plurality of memory devices; a flash interface module coupled to the plurality of bus multiplexers; and means for delivering a chip enable command signal to a first memory device of the plurality of memory devices, wherein the chip enable command signal includes a bus multiplexer identifier and a memory device identifier.

Drawings

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some examples of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

FIG. 1 is a schematic block diagram illustrating a storage system in which a storage device may function as a storage device for a host device in accordance with one or more techniques of the present disclosure.

Fig. 2 is a schematic diagram of a standard solution to maximize FIM capacity according to one embodiment.

FIG. 3 is a schematic diagram of a standard system showing the connection between the FIM and the memory device.

Fig. 4 is a schematic diagram of a solution to maximize FIM capacity according to one embodiment.

Fig. 5 is a schematic diagram of an implementation of fig. 4.

FIG. 6 is a graph illustrating a command state diagram and the timing of a high signal.

FIG. 7 is a graph illustrating a command state diagram and the timing of a low signal.

FIG. 8 is a flow chart illustrating a method of operating a device that maximizes FIM capacity.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.

Detailed Description

In the following, reference is made to embodiments of the disclosure. It should be understood, however, that the disclosure is not limited to the specifically described embodiments. Rather, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the present disclosure. Moreover, although embodiments of the disclosure may achieve advantages over other possible solutions and/or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the disclosure. Thus, the following aspects, features, embodiments and advantages are merely exemplary and should not be considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, references to "the present disclosure" should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).

The present disclosure relates generally to a method and apparatus for accessing more dies per channel in a data storage device. Each Flash Interface Module (FIM) may have any number of bus multiplexers coupled thereto, and each bus multiplexer may have any number of memory devices coupled thereto. The bus multiplexers may be connected to the FIM in series or in parallel. Each bus multiplexer may be addressed by a Chip Enable (CE) command that identifies the particular bus multiplexer and the particular memory device of the particular bus multiplexer. The information in the CE commands allows more dies per channel without generating Signal Interference (SI) or limiting transmission performance.

Fig. 1 is a schematic block diagram illustrating a storage system 100 in which a data storage device 106 may serve as a storage device for a host device 104 in accordance with one or more techniques of the present disclosure. For example, the host device 104 may utilize non-volatile memory 110 included in the data storage device 106 to store and retrieve data. Host device 104 includes host DRAM 138. In some examples, storage system 100 may include a plurality of storage devices, such as data storage device 106, that may operate as a storage array. For example, the storage system 100 may include a plurality of data storage devices 106, the plurality of data storage devices 106 configured as a redundant array of inexpensive/independent disks (RAID) that collectively acts as a mass storage device for the host device 104.

The storage system 100 includes a host device 104, which host device 104 may store data to and/or retrieve data from one or more storage devices, such as data storage device 106. As shown in FIG. 1, host device 104 may communicate with data storage device 106 via interface 114. Host device 104 may comprise any of a variety of devices, including a computer server, a Network Attached Storage (NAS) unit, a desktop computer, a notebook (i.e., handheld) computer, a tablet computer, a set-top box, a telephone handset (such as a so-called "smart" phone), a so-called "smart" keyboard, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, and so forth.

The data storage device 106 includes a controller 108, a non-volatile memory 110(NVM 110), a power supply 111, a volatile memory 112, and an interface 114. The controller 108 includes an internal memory or buffer (not shown). In some examples, data storage device 106 may include additional components that are not shown in fig. 1 for clarity. For example, data storage device 106 may include a Printed Board (PB) to which components of data storage device 106 are mechanically attached, and which includes conductive traces or the like that electrically interconnect components of data storage device 106. In some examples, the physical dimensions and connector configuration of the data storage device 106 may conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5 inch data storage devices (e.g., HDD or SSD), 2.5 inch data storage devices, 1.8 inch data storage devices, Peripheral Component Interconnect (PCI), PCI Express (PCI-X), PCI Express (PCIe) (e.g., PCIe X1, X4, X8, X16, PCIe mini-card, mini-PCI, etc.). In some examples, data storage device 106 may be directly coupled (e.g., directly soldered) to the motherboard of host device 104.

The interface 114 of the data storage device 106 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: advanced Technology Attachment (ATA) (e.g., serial ATA (sata) and parallel ATA (pata)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), serial attached SCSI (sas), PCI and PCIe, non-volatile memory express (nvme), OpenCAPI, GenZ, cache coherence interface accelerator (CCIX), open channel ssd (ocsscd), and the like. The electrical connections of interface 114 (e.g., a data bus, a control bus, or both) are electrically connected to controller 108, thereby providing an electrical connection between host device 104 and controller 108, allowing data to be exchanged between host device 114 and controller 108. In some examples, the electrical connection of interface 114 may also permit data storage device 106 to receive power from host device 104. For example, as shown in fig. 1, power supply 111 may receive power from host device 104 via interface 114.

The data storage device 106 includes an NVM 110, which NVM 110 may include multiple memory devices or memory cells. The NVM 110 can be configured to store and/or retrieve data. For example, a memory cell of the NVM 110 can receive data and a message from the controller 108 indicating that the memory cell stores data. Similarly, the memory units of the NVM 110 can receive a message from the controller 108 instructing the memory units to retrieve data. In some examples, each memory cell may be referred to as a die. In some examples, a single physical chip may include multiple dies (i.e., multiple memory units). In some examples, each memory cell may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

In some examples, each memory cell of the NVM 110 can include any type of non-volatile memory device, such as a flash memory device, a Phase Change Memory (PCM) device, a resistive random access memory (ReRAM) device, a Magnetoresistive Random Access Memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

The NVM 110 may include multiple flash memory devices or memory cells. The flash memory device may include a NAND or NOR based flash memory device and may store data based on the charge contained in the floating gate of the transistor of each flash memory cell. In a NAND flash memory device, the flash memory device may be divided into a plurality of blocks, and the blocks may be divided into a plurality of pages. Each of the plurality of blocks within a particular memory device may include a plurality of NAND cells. The rows of NAND cells can be electrically connected using word lines to define one of a plurality of pages. The respective cells in each of the plurality of pages may be electrically connected to a respective bit line. Further, the NAND flash memory device may be a 2D or 3D device, and may be a Single Level Cell (SLC), a multi-level cell (MLC), a Third Level Cell (TLC), or a fourth level cell (QLC). The controller 108 may write data to and read data from the NAND flash memory devices at the page level and may erase data from the NAND flash memory devices at the block level.

The data storage device 106 includes a power supply 111, which power supply 111 may provide power to one or more components of the data storage device 106. When operating in the standard mode, power supply 111 may provide power to the one or more components using power provided by an external device, such as host device 104. For example, the power supply 111 may provide power to one or more components using power received from the host device 104 via the interface 114. In some examples, the power source 111 may include one or more power storage components configured to provide power to the one or more components when operating in an off mode, such as without receiving power from an external device. In this manner, power supply 111 may be used as an on-board backup power supply. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, and the like. In some examples, the amount of power that one or more power storage components may store may be a function of the cost and/or size (e.g., area/volume) of the one or more power storage components. In other words, as the amount of power stored by the one or more power storage components increases, the cost and/or size of the one or more power storage components also increases.

The data storage device 106 also includes volatile memory 112, and the controller 108 may use the volatile memory 112 to store information. The volatile memory 112 may include one or more volatile memory devices. In some examples, the controller 108 may use the volatile memory 112 as a cache. For example, the controller 108 may store the cached information in the volatile memory 112 until the cached information is written to the non-volatile memory 110. As shown in fig. 1, the volatile memory 112 may consume power received from the power supply 111. Examples of volatile memory 112 include, but are not limited to, Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)).

The data storage device 106 includes a controller 108, and the controller 108 may manage one or more operations of the data storage device 106. For example, the controller 108 can manage reading data from the NVM 110 and/or writing data to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 can initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command. The controller 108 can determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores data associated with the write command in internal memory before sending the data to the NVM 110. The controller 108 may also include eight NAND channels, each of which may be considered a Flash Interface Module (FIM) (not shown). The number of NAND channels listed is not intended to be limiting, and the controller 108 may include more or fewer NAND channels than the number of NAND channels listed.

Fig. 2 is a schematic diagram of a standard solution to maximize FIM capacity according to one embodiment. Each FIM has two Chip Enable (CE) pins. Each CE pin is associated with a NAND bank. The maximum NAND bank capacity may be eight die. Thus, the FIMs may have a total of 2 dies, with 8 FIMs having a total of 16 dies. The maximum values listed are not intended to be limiting and other embodiments exist. To increase the capacity of a memory device, a controller (such as controller 108 of FIG. 1) needs to support more dies for each FIM. However, the increased die per FIM may result in high capacitive loading, which may reduce the reliability of the memory device. In addition, high capacitive loading can cause Signal Integrity (SI) degradation and limit TM performance. However, the problem of high capacitive loading can be solved by including a Bus Multiplexer (BM) that divides a single channel into four sub-channels. The bus multiplexer distributes the total number of dies per channel to the sub-channels.

A data storage device, such as data storage device 106 of fig. 1, may include a controller, such as controller 108 of fig. 1, coupled to an Application Specific Integrated Circuit (ASIC). The ASIC may include a flash interface module and communicate with the DRAM. By encoding the CE of the ASIC, each subchannel in the ASIC may be selected. CE is an input, which when true permits active operations including data I/O; when false, it blocks active operation and puts the memory in low power standby mode and the output floating. By combining the CE with the ASIC, the high capacitive load can be reduced, thereby achieving better reliability with greater memory capacity.

FIG. 2 depicts an ASIC including eight FIMs (denoted as FIM0-FIM 7). Each FIM is associated with a BM that divides each channel into four sub-channels. Each subchannel is associated with a NAND group that may include one or more NAND dies. However, since the ASIC is limited to two CEs, the subchannels are grouped into two groups. For example, FIM0 is associated with the following sub-channels: CH0 and CH 1. By combining BMs, the maximum die capacity is 8FIM 4 die/FIM 32 die. Further, the bus multiplexing architecture may allow eight FIM systems to contain more than 32 dies (such as 1024 dies).

FIG. 3 is a schematic diagram of a standard system showing the connection between the FIM and the memory device. The memory device may be the non-volatile memory of fig. 1 and may include a NAND package. Each NAND package includes a NAND stack, and each NAND stack is associated with a CE pin. To determine that a read or write references the correct NAND stack, the CE control must be decoded. CEn <1:0> is a 2-bit signal that corresponds to two CE pins for each available FIM. The following table describes an example of CE control to NAND bank decoding.

Watch (A)

The FIM architecture utilizes a 16-bit signal to communicate with the bus multiplexer to determine the location of a read command or a write command in the NAND. Signals travel from FIM to BM along the high speed path. Since the BM is limited by the two chip enables, there are four subchannels due to the four unique combinations of the two-bit signals. In addition, the line decoder takes the n-bit binary number and decodes it into 2^ n data lines. The decoder in the BM is a 4-to-16 data line decoder, where each of the four CE controls is associated with 4 bits, allowing a total of 16 different data bit combinations. A bank of 4 data bits is associated with a NAND bank, such as NAND GR0 with CEn0(0), CEn1(1), CEn2(1), and CEn3(1), as shown in the above table. Furthermore, to obtain the data bits, ASIC FIMx is associated with a 2-bit signal corresponding to BM. For example, ASICs FIMx of CEn1(0) and CEn0(0) correspond to BM a. Since bit data from the decoder corresponds to CEn0(0) and CEn1(1) of bits of NAND package 1 and CEn2(1) and CEn3(1) of NAND package 2, BM a corresponds to NAND GR 0.

Fig. 4 is a schematic diagram of a solution to maximize FIM capacity according to one embodiment. To access more dies on each channel and optionally scale the performance or capacity of the Test and Maintenance (TM) bus architecture, BMs may be connected in parallel or in series to the same FIM. Each BM can have n subchannels. Furthermore, the ASIC FIMx may have m BMs. Likewise, there may be x ASIC FIMs. The CE architecture allows multiple BMs to be connected in series without the high capacitive load problem. The CE selects a particular BM to be used for data transfer while the remaining BMs are in idle or low power modes.

Further, every n subchannels are NAND groups. The NAND bank may be scaled by capacity, where it may include, but is limited to, about 8 NAND dies. If the NAND bank is scaled by performance, the NAND bank can include, but is not limited to, about 2 NAND dies. The configuration of a single CE may be required for both capacity-scaled NAND strings and performance-scaled NAND strings. A single CE may have the capability of selecting at most, but not limited to, about 1024 die per channel.

Fig. 5 is a schematic diagram of an implementation of fig. 4. To select a particular subchannel for a read command or a write command, FIMx sends a unique command "CE command" that corresponds to the encoded BM identifier and NAND group identifier. The combination of identifiers consists of a concatenation of data bits within each BM. The size of the "CE command" may be approximately 8 bits. The size of the "CE command" is not intended to be limiting. The "CE command" is a code word such as "01 h".

The first number from the first signal corresponds to the BM identifier, where "0" is associated with bus multiplexer 0. The second number from the second signal corresponds to the NAND string number, where a "1" is associated with the NAND GR 1. In this example, the number of subchannels is 2 (i.e., n — 2), which corresponds to two NAND groups (NAND GR0 and NAND GR 1). Further, the number of BMs is 8 (i.e., m is 8).

Further, a codeword of "71 h" refers to BM7 (i.e., the eighth BM in the sequence) and NAND GR 1. When a CE command is sent from ASIC FIMx, the irrelevant BM ignores the command. CE commands are passed from BM to make the commands sequentially travel to the target BM and NAND bank.

Each BM is assigned an ID or code word, either statically or after discovery (which may be at system power-up). One benefit of the command ID or codeword is that the ID or codeword is compatible with or native to the FIM process connected to the NAND interface. Due to the "CE command", compatibility can be used for standard NAND devices. Furthermore, compatibility may enable flexibility in hardware and firmware design at many capacity points with or without BMs. When the corresponding BM and NAND group receive a "CE command", the relevant data is selected and the other NAND groups and BMs are in an idle state.

FIG. 6 is a graph illustrating a command state diagram and the timing of a high signal. The high signal corresponds to the BM address. The high signal is associated with the BM address and therefore the signal may not involve multiple processes (such as when the NANDs share the same data bus or when firmware and/or hardware is used in a multi-capacity configuration with or without BMs).

Further, when a CE command is first received, the NAND location is not selected. The end of the period of "unselected NAND" is determined by the first falling edge of ASIC _ WEn (i.e., when ASIC _ WEn goes low). When ASIC _ CLE goes low and ASIC _ CEn signal is high, indicating the beginning of the time period of BM address search, NAND access is disabled. During this time period, the ASIC _ CLE signal is also high. The high ASIC _ CEn signal corresponds to the BM address dependent on the first signal (i.e. the signal strength determines the BM address). The BM address may be "7" of the codeword "71 h" of fig. 5. "7" refers to the eighth BM, i.e., "bus multiplexer 7" of fig. 5. The end of the BM address search is indicated by the falling edge of ASIC _ CLE.

The NAND access data line is enabled when ASIC _ CEn goes low and is terminated when ASIC _ CEn goes high. Further, the strength of the ASIC _ CEn1 signal may indicate which NAND bank to access. The NAND access is represented by a codeword or a second number in the CE command. For example, the NAND group location may be "1" of codeword "71 h" of FIG. 5. "1" refers to the second NAND group, namely "NAND GR 1" of FIG. 5. By utilizing additional address cycles within the NAND command, multiple NAND addresses can be accessed during a NAND access period.

After completing the read or write command to the NAND location, ASIC _ CEn goes high. Since ASIC _ CLE is low, ASIC _ CEn is high, and ASIC _ WEn is high, NAND is not selected during this period. Other combinations of signals not listed may be suitable for read commands or write commands for high CEn signals.

FIG. 7 is a graph illustrating a command state diagram and the timing of a low signal. The low CEn signal corresponds to a NAND bank address. The first time a CE command is received, the NAND location is not selected. FIMx is accessing BM addresses when ASIC _ CEn0, ASIC _ CEn1, and ASIC _ WEn go low and ASIC _ CLE goes high. The high ASIC _ CLE signal and the low ASIC _ WEn signal may indicate that BM addresses may be accessed. The ASIC _ CEn signal corresponds to a BM address that depends on the first signal (i.e., the signal strength determines the BM address). The BM address may be "7" of the codeword "71 h" of fig. 5. "7" refers to the eighth BM, i.e., "bus multiplexer 7" of fig. 5.

Further, the end of the BM address period is indicated by the ASIC _ CLE falling edge. When addressing a NAND access, ASIC _ CEn1 is low. Further, the strength of the ASIC _ CEn1 signal may indicate which NAND bank to access. The NAND access is represented by a codeword or a second number in the CE command. For example, the NAND group location may be "1" of codeword "71 h" of FIG. 5. "1" refers to the second NAND group, namely "NAND GR 1" of FIG. 5. By utilizing additional address cycles within the NAND command, multiple NAND addresses can be accessed during a NAND access period.

After completing the read or write command to the NAND location, ASIC _ CEn goes high. Since ASIC _ CLE is low, ASIC _ CEn is high, and ASIC _ WEn is high, NAND is not selected during this period. Other combinations of signals not listed may be suitable for read commands or write commands for the low CEn signal.

Fig. 8 is a flow chart illustrating a method 800 of operating a device that maximizes FIM capacity. Method 800 may utilize a controller (such as controller 108 of data storage device 106 of fig. 1) coupled with an ASIC that includes one or more FIMs coupled to one or more BMs coupled to one or more NAND banks. Aspects of fig. 4, 5, 6, and 7 may be addressed in method 800. At block 802, the ASIC transmits a CE command signal. The CE command signal may be similar to the CE command signals of fig. 5, 6, and/or 7. After sending the CE command, at block 804, the controller 108 determines whether the data storage device 106 includes a BM in the memory architecture.

If the data storage device 106 does not have BM capability at block 804, then at block 820, the NAND, such as the NVM 110 of FIG. 1, ignores the CE command. At block 816, a read command or a write command associated with the CE command is executed on the relevant or selected NAND bank.

However, if the data storage device 106 does have BM capability at block 804, then the BM receives a CE command from the ASIC at block 806. At block 806, the CE command is decoded and at block 812, the relevant BM is selected. As shown in fig. 6 and 7, the associated BM is selected based on the active portion of the CE command signal. The BM address may be "7" of the codeword "71 h" of fig. 5. "7" refers to the eighth BM, i.e., "bus multiplexer 7" of fig. 5.

After selecting the BM at block 812, the relevant NAND bank is selected at block 814. Similar to the selection of the BM, the NAND bank is selected based on the active portion of the CE command signal corresponding to the NAND bank selection, as shown in fig. 6 and 7. For example, the NAND address may be a NAND group whose position may be represented by "1" of the codeword "71 h" of fig. 5. "1" refers to the second NAND group, namely "NAND GR 1" of FIG. 5. After selecting the BM address at block 812 and the NAND address at block 814, a read command or a write command is performed on the relevant NAND location at block 816.

By addressing a single bus multiplexer, more dies can be used per channel without generating SI or limiting transmission performance by addressing through Chip Enable (CE) commands that identify the particular bus multiplexer and the particular memory device of the particular bus multiplexer.

In one embodiment, a data storage device comprises: a plurality of memory devices; a plurality of bus multiplexers, wherein each bus multiplexer is coupled to one or more of the plurality of memory devices; and a flash interface module coupled to the plurality of bus multiplexers; and a controller coupled to the flash interface module, wherein the controller is configured to: a chip enable command is sent through the flash interface controller, wherein the chip enable command includes a bus multiplexer identifier and a memory device identifier. Each bus multiplexer is configured to ignore chip enable commands directed to a different bus multiplexer. Each bus multiplexer is configured to direct a chip enable command to a particular memory device coupled thereto. The controller is configured to send the chip enable command as part of a larger command including a read command or a write command. The chip enable command includes 8 bits. The larger command includes a prefix portion, and wherein the chip enable command is between the prefix portion within the larger command and the read command or the write command. The flash memory interface module is a first flash memory interface module, wherein the data storage device includes a plurality of flash memory interface modules, and wherein each flash memory interface module of the plurality of flash memory interface modules is coupled to the plurality of bus multiplexers. The chip enable command is sent along with the bus multiplexer signals and the memory device signals.

In another embodiment, a data storage device comprises: a controller; a plurality of flash memory interface modules coupled to the controller; a plurality of bus multiplexers coupled to at least a first flash interface module of the plurality of flash interface modules; and a plurality of memory devices coupled to a first bus multiplexer of the plurality of bus multiplexers, wherein the controller is configured to: sending the first signal to a first flash memory interface module; sending a second signal to the first flash memory interface module, wherein the second signal is lower than the first flash memory signal; and sending a command signal to the first flash interface module, wherein the first signal, the second signal, and the command signal are different. The first signal identifies a first bus multiplexer. The second signal identifies the first memory device. The plurality of bus multiplexers are connected in parallel to the first flash memory interface module. The plurality of bus multiplexers are serially connected to the first flash memory interface module. The plurality of bus multiplexers, other than the first bus multiplexer, are configured to ignore the first signal, the second signal, and the command signal. Each bus multiplexer has a unique ID number that is either static or given after controller discovery.

In another embodiment, a data storage device comprises: a plurality of memory devices; a plurality of bus multiplexers, wherein each bus multiplexer is coupled to at least one memory device of the plurality of memory devices; a flash interface module coupled to the plurality of bus multiplexers; and means for delivering a chip enable command signal to a first memory device of the plurality of memory devices, wherein the chip enable command signal includes a bus multiplexer identifier and a memory device identifier. The data storage device further comprises means for delivering two different signals to the flash interface module. The two different signals are different voltages. The flash memory interface module further comprises means for ignoring the chip enable command. The data storage device further includes means for permitting the chip enable command to pass through a bus multiplexer of the plurality of bus multiplexers.

While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.