阅读说明：本技术 基于内嵌空腔soi衬底的多栅mos器件及其制备方法 (Multi-gate MOS device based on embedded cavity SOI substrate and preparation method thereof ) 是由 母志强 刘强 俞文杰 于 2021-07-02 设计创作，主要内容包括：本发明提供一种基于内嵌空腔SOI衬底的多栅MOS器件及其制备方法,器件包括：内嵌空腔SOI衬底,包括硅衬底、绝缘层及顶层硅,绝缘层中形成有沿器件的源漏方向间隔排布的多个空腔,空腔上方的顶层硅中形成有沟道区；多个全包围栅极结构,分别形成在多个空腔上方的沟道区四周,全包围栅极结构包括全包围栅介质层和全包围栅极层,且多个全包围栅极结构间隔排布,以使得沟道区包括被多个全包围栅极结构包围的多个控制部和未被全包围栅极结构包围的多个间隔部；源电极和漏电极,分别形成在沟道区两端的源区和漏区上。本发明制备的多个全包围栅极结构可以实现相应沟道区域的独立控制,从而在一个MOS管内实现大于或等于两位的字节运算。(The invention provides a multi-gate MOS device based on an embedded cavity SOI substrate and a preparation method thereof, wherein the device comprises the following steps: the embedded cavity SOI substrate comprises a silicon substrate, an insulating layer and top silicon, wherein a plurality of cavities which are arranged at intervals along the source-drain direction of a device are formed in the insulating layer, and a channel region is formed in the top silicon above the cavities; the fully-surrounded gate structures are respectively formed around the channel region above the cavities, and comprise fully-surrounded gate dielectric layers and fully-surrounded gate layers, and the fully-surrounded gate structures are arranged at intervals, so that the channel region comprises a plurality of control parts surrounded by the fully-surrounded gate structures and a plurality of interval parts not surrounded by the fully-surrounded gate structures; and a source electrode and a drain electrode formed on the source region and the drain region at both ends of the channel region, respectively. The multiple fully-surrounded gate structures prepared by the method can realize independent control of corresponding channel regions, so that byte operation of more than or equal to two bits can be realized in one MOS tube.)

1. A preparation method of a multi-gate MOS device based on an embedded cavity SOI substrate is characterized by comprising the following steps:

1) preparing an embedded cavity SOI substrate, wherein the embedded cavity SOI substrate comprises a silicon substrate, an insulating layer and top silicon which are sequentially laminated, a plurality of cavities which are arranged at intervals along the source-drain direction of a device are formed in the insulating layer, the tops of the cavities are connected with the top silicon, and a channel region is formed in the top silicon above the cavities;

2) forming a plurality of fully-surrounded gate structures around a channel region above the plurality of cavities, wherein the fully-surrounded gate structures comprise fully-surrounded gate dielectric layers and fully-surrounded gate layers, and the plurality of fully-surrounded gate structures are arranged at intervals, so that the channel region comprises a plurality of control parts surrounded by the plurality of fully-surrounded gate structures and a plurality of interval parts not surrounded by the fully-surrounded gate structures;

3) and respectively forming a source electrode and a drain electrode on the source region and the drain region at two ends of the channel region.

2. The method for preparing a multi-gate MOS device based on an embedded cavity SOI substrate according to claim 1, wherein: the insulating layer is reserved below the cavity, and the thickness of the insulating layer reserved below the cavity is greater than or equal to 20 nanometers.

3. The method for preparing a multi-gate MOS device based on an embedded cavity SOI substrate according to claim 1, wherein: the width of the cavity is less than or equal to 100 nanometers, and the interval between two adjacent cavities is less than or equal to 50 nanometers.

4. The method for preparing a multi-gate MOS device based on an embedded cavity SOI substrate according to claim 1, wherein: the number of the cavities corresponding to the channel region is 2-10, and the number of the fully-surrounded gate structures corresponding to the channel region is 2-10.

5. The method for preparing a multi-gate MOS device based on an embedded cavity SOI substrate according to claim 1, wherein: the control parts are independently controlled, so that the multi-grid MOS device realizes two-bit or more byte operation.

6. The method for preparing a multi-gate MOS device based on an embedded cavity SOI substrate according to claim 1, wherein: the gate dielectric layer comprises SiO₂、HfO₂、HfLaO₂And Al₂O₃The gate layer comprises one of polysilicon, TiN, TaN and TiAl.

7. The method for preparing a multi-gate MOS device based on an embedded cavity SOI substrate according to claim 1, wherein: and the doping types of the plurality of spacing parts which are not surrounded by the fully-surrounded gate structure are the same as those of the source region and the drain region.

8. The method for preparing a multi-gate MOS device based on an embedded cavity SOI substrate according to claim 1, wherein: and the doping concentrations of the plurality of spacing parts which are not surrounded by the fully-surrounded gate structure are the same as those of the source region and the drain region.

9. A multi-gate MOS device based on an embedded cavity SOI substrate is characterized by comprising:

the SOI substrate with the embedded cavity comprises a silicon substrate, an insulating layer and top silicon which are sequentially stacked, wherein a plurality of cavities which are arranged at intervals along the source-drain direction of a device are formed in the insulating layer, the tops of the cavities are connected with the top silicon, and a channel region is formed in the top silicon above the cavities;

the fully-surrounded gate structures are respectively formed around the channel regions above the cavities, each fully-surrounded gate structure comprises a fully-surrounded gate dielectric layer and a fully-surrounded gate layer, and the fully-surrounded gate structures are arranged at intervals, so that the channel regions comprise a plurality of control parts surrounded by the fully-surrounded gate structures and a plurality of interval parts not surrounded by the fully-surrounded gate structures;

and the source electrode and the drain electrode are respectively formed on the source region and the drain region at two ends of the channel region.

10. The multiple-gate MOS device based on an embedded cavity SOI substrate of claim 9, wherein: the insulating layer is reserved below the cavities, the thickness of the insulating layer reserved below the cavities is greater than or equal to 20 nanometers, the width of each cavity is less than or equal to 100 nanometers, and the interval between every two adjacent cavities is less than or equal to 50 nanometers.

11. The multiple-gate MOS device based on an embedded cavity SOI substrate of claim 9, wherein: the number of the cavities corresponding to the channel region is 2-10, and the number of the fully-surrounded gate structures corresponding to the channel region is 2-10.

12. The multiple-gate MOS device based on an embedded cavity SOI substrate of claim 9, wherein: the control parts are independently controlled, so that the multi-grid MOS device realizes two-bit or more byte operation.

13. The multiple-gate MOS device based on an embedded cavity SOI substrate of claim 9, wherein: the gate dielectric layer comprises SiO₂、HfO₂、HfLaO₂And Al₂O₃The gate layer comprises one of polysilicon, TiN, TaN and TiAl.

14. The multiple-gate MOS device based on an embedded cavity SOI substrate of claim 9, wherein: and the doping types and doping concentrations of the plurality of spacing parts which are not surrounded by the fully-surrounded gate structure are the same as those of the source region and the drain region.

Technical Field

The invention belongs to the field of design and manufacture of semiconductor devices, and particularly relates to a multi-gate MOS device based on an embedded cavity SOI substrate and a preparation method thereof.

Background

In the prior integrated circuit technology, only the switch control of a single grid can be realized by one transistor, so that the operation (0 and 1) of one byte is realized. In practical applications, it is often necessary to implement a multi-input operation function and output a result, and a plurality of transistors are required to be connected in series and in parallel to implement a multi-byte operation function, which requires an increasing number of transistors in one chip.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a multi-gate MOS device based on an SOI substrate with embedded cavities and a method for manufacturing the same, so as to solve the problem that only a single gate can be controlled by one transistor in the prior art.

In order to achieve the above objects and other related objects, the present invention provides a method for fabricating a multi-gate MOS device based on an SOI substrate with embedded cavities, the method comprising the steps of: 1) preparing an embedded cavity SOI substrate, wherein the embedded cavity SOI substrate comprises a silicon substrate, an insulating layer and top silicon which are sequentially laminated, a plurality of cavities which are arranged at intervals along the source-drain direction of a device are formed in the insulating layer, the tops of the cavities are connected with the top silicon, and a channel region is formed in the top silicon above the cavities; 2) forming a plurality of fully-surrounded gate structures around a channel region above the plurality of cavities, wherein the fully-surrounded gate structures comprise fully-surrounded gate dielectric layers and fully-surrounded gate layers, and the plurality of fully-surrounded gate structures are arranged at intervals, so that the channel region comprises a plurality of control parts surrounded by the plurality of fully-surrounded gate structures and a plurality of interval parts not surrounded by the fully-surrounded gate structures; 3) and respectively forming a source electrode and a drain electrode on the source region and the drain region at two ends of the channel region.

Optionally, the insulating layer is retained below the cavity, and a thickness of the insulating layer retained below the cavity is greater than or equal to 20 nanometers.

Optionally, the width of the cavity is less than or equal to 100 nm, and the interval between two adjacent cavities is less than or equal to 50 nm.

Optionally, the number of the cavities corresponding to the channel region is 2-10, and the number of the fully-surrounded gate structures correspondingly arranged to the channel region is 2-10.

The control parts are independently controlled, so that the multi-grid MOS device realizes more than two-bit byte operation.

Optionally, the gate dielectric layer includes SiO₂、HfO₂、HfLaO₂And Al₂O₃The gate layer comprises one of polysilicon, TiN, TaN and TiAl.

Optionally, the doping types of the plurality of spacers not surrounded by the fully-surrounding gate structure are the same as those of the source region and the drain region.

Optionally, the doping concentrations of the plurality of spacers, the source region and the drain region, which are not surrounded by the fully-surrounded gate structure, are the same.

The invention also provides a multi-gate MOS device based on the embedded cavity SOI substrate, which comprises: the SOI substrate with the embedded cavity comprises a silicon substrate, an insulating layer and top silicon which are sequentially stacked, wherein a plurality of cavities which are arranged at intervals along the source-drain direction of a device are formed in the insulating layer, the tops of the cavities are connected with the top silicon, and a channel region is formed in the top silicon above the cavities; the fully-surrounded gate structures are respectively formed around the channel regions above the cavities, each fully-surrounded gate structure comprises a fully-surrounded gate dielectric layer and a fully-surrounded gate layer, and the fully-surrounded gate structures are arranged at intervals, so that the channel regions comprise a plurality of control parts surrounded by the fully-surrounded gate structures and a plurality of interval parts not surrounded by the fully-surrounded gate structures; and the source electrode and the drain electrode are respectively formed on the source region and the drain region at two ends of the channel region.

Optionally, the insulating layer is reserved below the cavity, the thickness of the insulating layer reserved below the cavity is greater than or equal to 20 nanometers, the width of the cavity is less than or equal to 100 nanometers, and the interval between two adjacent cavities is less than or equal to 50 nanometers.

Optionally, the number of the cavities corresponding to the channel region is 2-10, and the number of the fully-surrounded gate structures correspondingly arranged to the channel region is 2-10.

Optionally, the plurality of control portions are independently controlled, so that the multi-gate MOS device realizes two-bit or more byte operations.

Optionally, the gate dielectric layer includes SiO₂、HfO₂、HfLaO₂And Al₂O₃The gate layer comprises one of polysilicon, TiN, TaN and TiAl.

Optionally, the doping type and doping concentration of the plurality of spacers, the source region and the drain region which are not surrounded by the fully-surrounded gate structure are the same.

As described above, the multi-gate MOS device based on the SOI substrate with embedded cavity and the method for manufacturing the same of the present invention have the following advantages:

the invention introduces the SOI substrate embedded with a plurality of cavities into the preparation process of the multi-gate device, and realizes a plurality of fully-enclosed device structures of the same device. The channel regions and the source and drain regions of the multiple spacing parts of the multi-gate MOS device not surrounded by the fully-surrounded gate structure adopt the same type of high-concentration doping to reduce the resistance, and the multi-byte operation function in the same MOS device is realized. Meanwhile, the invention can obviously reduce the difficulty and cost of the preparation process of a plurality of all-surrounding gate structures of the MOS device, and simultaneously can obviously reduce the power consumption of the device and optimize the switching characteristic of the device.

The multiple fully-surrounded gate structures prepared by the invention can realize independent control of corresponding channel regions, thereby realizing byte operation of more than or equal to two bits in one MOS tube, for example, realizing 'AND' operation function of multiple bytes in the same MOS tube.

Drawings

Fig. 1 to fig. 6 are schematic structural diagrams of steps of a method for manufacturing a multi-gate MOS device based on an embedded cavity SOI substrate according to an embodiment of the present invention, where fig. 6 is a schematic structural diagram of a multi-gate MOS device based on an embedded cavity SOI substrate according to an embodiment of the present invention.

Fig. 7 is a graph showing output results obtained after different input signals are applied to different control parts by the multi-gate MOS device based on the SOI substrate with embedded cavities according to the embodiment of the present invention.

Description of the element reference numerals

101 silicon substrate

102 insulating layer

103 top layer silicon

104 channel region

105 cavity

106 gate dielectric layer

107 gate layer

108 grid side wall

109 control unit

110 spacer part

111 source electrode

112 drain electrode

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

In the prior integrated circuit technology, only the switch control of a single grid can be realized by one transistor, so that the operation (0 and 1) of one byte is realized. In practical applications, it is often necessary to implement a multi-input operation function and output a result, and a plurality of transistors are required to be connected in series and in parallel to implement a multi-byte operation function, which requires an increasing number of transistors in one chip. If the multi-byte operation function can be realized in one transistor, the requirement of the same functional chip on the number of the transistors can be greatly reduced, so that the size and the power consumption of the chip are obviously reduced.

As shown in fig. 1 to 6, the present embodiment provides a method for manufacturing a multi-gate MOS device based on an embedded cavity 105SOI substrate, the method comprising the steps of:

as shown in fig. 1, step 1) is firstly performed to prepare an embedded cavity 105SOI substrate, where the embedded cavity 105SOI substrate includes a silicon substrate 101, an insulating layer 102, and a top layer silicon 103, which are sequentially stacked, a plurality of cavities 105 are formed in the insulating layer 102 and are arranged at intervals in a source-drain direction of a device, tops of the plurality of cavities 105 are connected to the top layer silicon 103, and a channel region 104 is formed in the top layer silicon 103 above the cavities 105.

In this embodiment, the insulating layer 102 is remained under the cavity 105, and the thickness of the insulating layer 102 remained under the cavity 105 is greater than or equal to 20 nm. In this embodiment, the insulating layer 102 with a certain thickness is reserved below the cavity 105, so that the insulation between the silicon substrate 101 and the subsequently prepared gate layer 107 can be ensured, the coupling capacitance is reduced, and the electrical stability of the device is improved.

In this embodiment, the width of the cavity 105 is less than or equal to 100 nm, and the interval between two adjacent cavities 105 is less than or equal to 50 nm, and by setting the width and the interval of the cavity 105, the density of the fully-surrounded gate structure in a single multi-gate MOS device can be increased on the premise of ensuring the process stability.

In a specific embodiment, the preparation of the embedded cavity 105SOI substrate comprises the steps of:

1-1) providing a silicon substrate 101, and forming an insulating layer 102 with a certain thickness on the surface of the silicon substrate 101, for example, a thermal oxidation process or a plasma enhanced chemical vapor deposition process may be used to form a silicon dioxide layer on the silicon substrate 101 as the insulating layer 102, and the thickness of the insulating layer 102 may be 50 nm to 100 nm, but is not limited to this range.

1-2) forming a plurality of grooves arranged at intervals along the source-drain direction of the device in the insulating layer 102 through a photoetching process and an etching process, wherein the depth of the grooves can be 30-50 nanometers, and the insulating layer 102 with the depth not less than 20 nanometers is reserved at the bottom.

1-3) providing a silicon wafer, bonding the silicon wafer with the insulating layer 102 through a bonding process to seal the groove into a cavity 105, and thinning the silicon wafer to form top silicon 103; the thinning process may be a grinding process, such as a chemical mechanical polishing process CMP, or an ion stripping process ion-cut, etc.

1-4) patterning the top silicon layer 103 through a photolithography process and an etching process to form a channel region 104 in the top silicon layer 103 above the cavity 105, where the channel region 104 may be, for example, a silicon nanowire or a strip-shaped silicon with a certain width, and two sides of the channel region 104 preferably expose the cavity 105 to facilitate subsequent deposition of a gate dielectric layer 106 and a gate electrode layer 107.

In this embodiment, the method further includes the step of doping the top silicon 103 in bulk. The doping may be N-type doping or P-type doping. In this embodiment, the doping types of the source region and the drain region of the multi-gate MOS device and the plurality of spacers 110 not surrounded by the all-around gate structure are the same, and at the same time, the doping concentrations of the source region and the drain region of the multi-gate MOS device and the plurality of spacers 110 not surrounded by the all-around gate structure are the same, so as to reduce the device resistance.

As shown in fig. 2 to 5, fig. 4 is a schematic cross-sectional structure diagram at a-a' in fig. 3, and then step 2) is performed to form a plurality of fully-surrounded gate structures around the channel region 104 above the plurality of cavities 105, where the fully-surrounded gate structures include a fully-surrounded gate dielectric layer 106 and a fully-surrounded gate layer 107, and the plurality of fully-surrounded gate structures are arranged at intervals, so that the channel region 104 includes a plurality of control portions 109 surrounded by the plurality of fully-surrounded gate structures and a plurality of spacing portions 110 not surrounded by the fully-surrounded gate structures.

By way of example, the number of the cavities 105 corresponding to the channel region 104 is 2 to 10, and the number of the fully-wrapped-around gate structures arranged corresponding to the cavities is 2 to 10. In this embodiment, the number of the cavities 105 corresponding to the channel region 104 is 3, and the number of the fully-wrapped-around gate structures disposed corresponding to the cavities is 3.

By way of example, the gate dielectric layer 106 comprises SiO₂、HfO₂、HfLaO₂And Al₂O₃The gate layer 107 comprises one of polysilicon, TiN, TaN and TiAl. In a specific implementation, the gate dielectric layer 106 is SiO₂The gate layer 107 is polysilicon, and in another specific implementation process, the gate dielectric layer 106 is HfO₂The gate layer 107 is TiN.

As shown in fig. 5, in this embodiment, after the fully-surrounded gate structure is prepared, a step of forming a gate sidewall 108 on a sidewall of the fully-surrounded gate structure is further included to further improve the structural strength of the gate structure and the insulation between the plurality of fully-surrounded gate structures.

As shown in fig. 6, step 3) is finally performed to form a source electrode 111 and a drain electrode 112 on the source region and the drain region at both ends of the channel region 104, respectively.

In this embodiment, the plurality of control units 109 are independently controlled to enable the multi-gate MOS device to implement a byte operation of two or more bits.

For example, in the present embodiment, taking an example that one multi-Gate MOS device includes 3 Gate structures of a Gate1, a Gate2, and a Gate3, the control units 109 are independently controlled, and output results obtained after different input signals are applied to different control units 109 are shown in fig. 7. It can be seen that the multiple fully-wrapped-around gate structures prepared by the method can realize independent control of the corresponding channel region 104, and can realize byte operation of more than or equal to two bits in one MOS tube.

As shown in fig. 6, the present embodiment further provides a multi-gate MOS device based on the embedded cavity 105SOI substrate, where the multi-gate MOS device includes: an embedded cavity 105SOI substrate, wherein the embedded cavity 105SOI substrate comprises a silicon substrate 101, an insulating layer 102 and a top layer silicon 103 which are sequentially stacked, a plurality of cavities 105 which are arranged at intervals along the source-drain direction of a device are formed in the insulating layer 102, the tops of the cavities 105 are connected with the top layer silicon 103, and a channel region 104 is formed in the top layer silicon 103 above the cavities 105; a plurality of fully-surrounded gate structures respectively formed around the channel region 104 above the plurality of cavities 105, wherein the fully-surrounded gate structures include a fully-surrounded gate dielectric layer 106 and a fully-surrounded gate layer 107, and the plurality of fully-surrounded gate structures are arranged at intervals, so that the channel region 104 includes a plurality of control portions 109 surrounded by the plurality of fully-surrounded gate structures and a plurality of spacing portions 110 not surrounded by the fully-surrounded gate structures; and a source electrode 111 and a drain electrode 112 respectively formed on the source region and the drain region at both ends of the channel region 104.

As an example, the channel region 104 may be, for example, a silicon nanowire or a strip-shaped silicon having a certain width.

As an example, the insulating layer 102 is remained under the cavity 105, the thickness of the insulating layer 102 remained under the cavity 105 is greater than or equal to 20 nanometers, the width of the cavity 105 is less than or equal to 100 nanometers, and the interval between two adjacent cavities 105 is less than or equal to 50 nanometers. In the embodiment, the insulating layer 102 with a certain thickness is reserved below the cavity 105, so that the insulation between the silicon substrate 101 and the subsequently prepared gate layer 107 can be ensured, the coupling capacitance is reduced, and the electrical stability of the device is improved. Meanwhile, in the embodiment, by setting the width and the interval of the cavity 105, the density of the fully-surrounded gate structure in a single multi-gate MOS device can be improved on the premise of ensuring the process stability.

By way of example, the number of the cavities 105 corresponding to the channel region 104 is 2 to 10, and the number of the fully-wrapped-around gate structures arranged corresponding to the cavities is 2 to 10. In this embodiment, the number of the cavities 105 corresponding to the channel region 104 is 3, and the number of the fully-wrapped-around gate structures disposed corresponding to the cavities is 3.

For example, the plurality of control units 109 are independently controlled to implement a byte operation of two or more bits in the multi-gate MOS device. For example, in this embodiment, taking an example that one multi-Gate MOS device includes 3 Gate structures of a Gate1, a Gate2, and a Gate3, each control unit 109 is independently controlled, and output results obtained after different input signals are applied to different control units 109 are shown in fig. 7. It can be seen that the multiple fully-wrapped-around gate structures prepared by the method can realize independent control of the corresponding channel region 104, and can realize byte operation of more than or equal to two bits in one MOS tube.

By way of example, the gate dielectric layer 106 comprises SiO₂、HfO₂、HfLaO₂And Al₂O₃The gate layer 107 comprises one of polysilicon, TiN, TaN and TiAl. In a specific implementation, the gate dielectric layer 106 is SiO₂The gate layer 107 is polysilicon, and in another specific implementation process, the gate dielectric layer 106 is HfO₂The gate layer 107 is TiN.

As an example, the doping types of the source region, the drain region and the plurality of spacers 110 not surrounded by the all-around gate structure are the same, and the doping concentrations of the source region, the drain region and the plurality of spacers 110 not surrounded by the all-around gate structure are the same.

In this embodiment, the multi-gate MOS device further includes a gate sidewall 108 located on the sidewall of the fully-enclosed gate structure, so as to further improve the structural strength of the gate structure and the insulation between the plurality of fully-enclosed gate structures.

As described above, the multi-gate MOS device based on the embedded cavity 105SOI substrate and the method for manufacturing the same of the present invention have the following advantages:

the invention introduces the SOI substrate embedded with a plurality of cavities 105 into the preparation process of the multi-gate device, and realizes a plurality of fully-enclosed device structures of the same device. The multiple spacers 110 and the source-drain regions of the multi-gate MOS device not surrounded by the fully-surrounded gate structure adopt the same type of high-concentration doping to reduce the resistance, and the multi-byte operation function in the same MOS device is realized. Meanwhile, the invention can obviously reduce the difficulty and cost of the preparation process of a plurality of all-surrounding gate structures of the MOS device, and simultaneously can obviously reduce the power consumption of the device and optimize the switching characteristic of the device.

The multiple fully-surrounded gate structures prepared by the invention can realize independent control of the corresponding channel region 104, thereby realizing byte operation of more than or equal to two bits in one MOS tube, for example, the 'AND' operation function of multiple bytes in the same MOS tube.

Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.