阅读说明：本技术 可阻挡逆电流的金属氧化物半导体晶体管 (Metal oxide semiconductor transistor capable of blocking reverse current ) 是由 黄宗义 许峻铭 黄炯福 于 2019-10-16 设计创作，主要内容包括：本发明公开一种可阻挡逆电流的金属氧化物半导体晶体管。在一实施例中提供一高压半导体元件,包含有一金属氧化物半导体晶体管以及一肖特基二极管。该金属氧化物半导体晶体管的一半导体基底为一第一类型。一第二类型的一深井形成于该半导体基底上。该第一类型的一基体形成于该深井上。该第二类型的一重掺杂源设于该基体上,且该重掺杂源与该基体电性上相短路。该肖特基二极管具有一金属层,作为该肖特基二极管的一阳极,形成于该深井上。该金属层与该深井形成一肖特基接面。(The invention discloses a metal oxide semiconductor transistor capable of blocking reverse current. In one embodiment, a high voltage semiconductor device is provided, which includes a metal oxide semiconductor transistor and a schottky diode. A semiconductor substrate of the MOS transistor is of a first type. A deep well of a second type is formed in the semiconductor substrate. A substrate of the first type is formed in the deep well. A heavily doped source of the second type is disposed on the substrate and electrically shorted to the substrate. The Schottky diode is provided with a metal layer which is used as an anode of the Schottky diode and is formed on the deep well. The metal layer and the deep well form a Schottky junction.)

1. A high voltage semiconductor device includes:

a metal oxide semiconductor transistor, comprising:

a semiconductor substrate of a first type;

a deep well of a second type opposite to the first type formed on the semiconductor substrate;

a body of the first type formed in the deep well;

the heavy doping source is of the second type, is arranged on the substrate and is electrically short-circuited with the substrate; and

a control gate formed on the substrate for controlling the electrical connection between the heavily doped source and the deep well; and

a Schottky Diode (Schottky Diode) comprising:

and the metal layer is used as the anode of the Schottky diode and is formed on the deep well, and the metal layer and the deep well form a Schottky junction.

2. The high voltage semiconductor device as claimed in claim 1, wherein the MOS transistor comprises:

the heavily doped drain is of the second type and is electrically formed on the deep well in a floating manner.

3. The high voltage semiconductor device as claimed in claim 2, wherein the schottky diode is formed in a schottky region and the heavily doped drain surrounds the schottky diode in a top view.

4. The high voltage semiconductor device as claimed in claim 2, wherein in the top view, the heavily doped drain surrounds an isolation region that surrounds the schottky region.

5. The high voltage semiconductor device as claimed in claim 4, wherein the isolation region is a first isolation region, and in the top view, the Schottky region comprises a second isolation region surrounded by the first isolation region.

6. The device of claim 2, wherein the control gate at least partially overlaps the isolation region, the deep well, the body, and the heavily doped source in a top view.

7. The high voltage semiconductor device as claimed in claim 2, wherein in a top view, the schottky diode is formed in a schottky region, further comprising a lightly doped region of the first type surrounding the schottky junction.

8. The high voltage semiconductor device of claim 7, wherein in a cross-sectional view, the Schottky diode further comprises a deeply buried doped layer of the first type formed below the lightly doped region.

9. The high voltage semiconductor device of claim 8, wherein the deep buried doped layer is substantially aligned with the lightly doped region.

10. A synchronous rectification controller, an integrated circuit, for a power supply (power supply), comprising a transformer and a synchronous rectification switch, the transformer comprising a primary winding and a secondary winding inductively coupled to each other, the synchronous rectification switch being connected in series with the secondary winding, the synchronous rectification controller comprising:

the driving pin is coupled to the synchronous rectification switch, and the synchronous rectification controller controls the electrical connection between the secondary side coil and the power line through the driving pin;

a high voltage charging pin coupled to a junction between the secondary side coil and the synchronous rectification switch; and

the high voltage semiconductor device of claim 1, wherein the high voltage charging pin is electrically connected to the anode, the substrate is electrically connected to an operating power capacitor;

the synchronous rectification controller can charge the operating power supply capacitor through the high-voltage semiconductor element.

Technical Field

The present invention relates generally to high voltage tolerant mos transistors, and more particularly to mos transistors incorporating a schottky diode that blocks reverse current.

Background

A high voltage MOSFET is a semiconductor device, and generally refers to a MOSFET capable of withstanding a drain-to-source voltage (i.e., a voltage) exceeding 5V. In application, it can be used to switch loads, or used for switching between different voltage levels in power management, or used as a power element in a high power amplifier.

Based on specification requirements, high voltage MOSFETs need to have a breakdown voltage with a relatively high drain-source cross voltage. In addition, high voltage MOSFETs are often required to have some special specifications due to application differences. For example, some high voltage MOSFETs require a low gate-to-source capacitance (gate-to-source capacitance) that is suitable for high speed switching.

Disclosure of Invention

The embodiment of the invention provides a high-voltage semiconductor element which comprises a metal oxide semiconductor transistor and a Schottky diode. A semiconductor substrate of the MOS transistor is of a first type. A deep well of a second type is formed in the semiconductor substrate. A substrate of the first type is formed in the deep well. A heavily doped source of the second type is disposed on the substrate and electrically shorted to the substrate. The Schottky diode is provided with a metal layer which is used as an anode of the Schottky diode and is formed on the deep well. The metal layer and the deep well form a Schottky junction.

Drawings

Fig. 1 shows a synchronous rectification controller 12 implemented in accordance with the present invention.

The top half of fig. 2A shows a top view of the high voltage semiconductor device 100a, and the bottom half shows a cross-sectional view of the high voltage semiconductor device 100a along line AA in the top view.

The upper half of fig. 2B also shows a top view of the high voltage semiconductor device 100a, but the lower half shows a cross-sectional view of the high voltage semiconductor device 100a along the line BB in the top view.

Fig. 3 shows a power supply 10 implemented in accordance with the present invention.

FIG. 4 shows the signal S of FIG. 3 on the primary side_FLBKWith signal V of the secondary side_HVRThe signal waveform of (2).

The upper half of fig. 5 shows a top view of the high voltage semiconductor device 100b, and the lower half shows a cross-sectional view of the high voltage semiconductor device 100b along the CC line in the top view.

Fig. 6 shows a cross-sectional view of the high voltage semiconductor device 100 c.

[ notation ] to show

10 power supply

12 synchronous rectification controller

14 primary side controller

16 load

18 transformer

28 ground wire

62a, 62b, 62c isolation regions

66P type heavily doped region

68a, 68b N type heavy doping source

68c N type heavily doped drain

70a, 70b control door

72 metal layer

78A, 78G, 78SB metal plugs

80P type lightly doped region

82 hollow

84P type deep buried light doped layer

100. 100a, 100b, 100c high voltage semiconductor element

102 MOS

104 Schottky diode

106P type semiconductor substrate

108P type matrix

110N type deep well

A anode

CVCC operation power supply capacitor

D drain electrode

D1, D2 diode

DET detection pin

DM DMOS region

DRV drive pin

GATE grid

GND grounding pin

HVR high voltage charging pin

I-_PRIElectric current

I_SECElectric current

LP primary side coil

LS secondary side coil

NMP main power switch

NMS synchronous rectification switch

Pth main route

RDT resistor

SD schottky area

S_FLBKSignal

SPK_NENegative surge

S_SYNControl signal

S/B source base

T_CYCPeriod of switching

T-_OFFClosing time

T_ONTime of opening

VCC operation power supply pin

V_DSChannel voltage

V_HVRSignal

V_INInput voltage VIN input power pin

V-_OUTOutput voltage

Detailed Description

In this specification, there are some common symbols representing components having the same or similar structures, functions, principles, and being understood by those skilled in the art based on the teachings of this specification. For the sake of brevity of the description, elements having the same reference numerals will not be repeated.

An embodiment of the present invention provides a high voltage MOSFET that integrates a metal oxide semiconductor field effect transistor (MOS) and a Schottky Diode (Schottky Diode) with a common semiconductor layer that serves as a cathode of the Schottky Diode and also as a drain of the MOS transistor. When the Schottky diode is forward biased, the MOS can endure the high drain-source cross voltage. The schottky diode blocks reverse current that may be generated by forward biasing of the diode in the high voltage MOSFET when the schottky diode is reverse biased.

Fig. 1 shows a synchronous rectification controller 12 implemented according to the present invention, which can be produced by a single chip package. As shown in fig. 1, the synchronous rectification controller 12 has, but is not limited to, a driving pin DRV, a high-voltage charging pin HVR, a detection pin DET, an input power supply pin VIN, an operation power supply pin VCC, and a ground pin GND.

The synchronous rectification controller 12 may have a high voltage semiconductor device 100 fabricated by semiconductor process technology therein. The high voltage semiconductor device 100 may be a high voltage MOSFET, as shown in fig. 1, which incorporates a MOS 102 and a schottky diode 104. In fig. 1, the MOS 102 is an N-type MOS, and the source (source) and the base (base) are electrically connected together, referred to as source base S/B, and electrically connected to the operating power pin VCC. A diode D1 is connected to the drain D of the MOS 102 to the source base S/B, a diode D2 is arranged between the drain D and the grounding pin GND, and a Schottky diode 104 is arranged between the drain D of the MOS 102 and the high-voltage charging pin HVR. Anode a of schottky diode 104 is electrically connected to high voltage charge pin HVR. When signal V on high voltage charging pin HVR_HVRWhen the voltage is negative, the schottky diode 104 blocks the reverse current from the diodes D1 and D2, thereby preventing the synchronous rectification controller 12 from being burnt.

The top half of fig. 2A shows a top view of the high voltage semiconductor device 100a, and the bottom half shows a cross-sectional view of the high voltage semiconductor device 100a along line AA in the top view. The upper half of fig. 2B also shows a top view of the high voltage semiconductor device 100a, but the lower half shows a cross-sectional view of the high voltage semiconductor device 100a along the line BB in the top view. Fig. 2A and 2B are dashed lines to illustrate the position relationship of corresponding elements or structures in the top view and the cross-sectional view. In one embodiment, the high voltage semiconductor device 100 is implemented as a high voltage semiconductor device 100 a.

The top view of the high voltage semiconductor device 100a can be roughly divided into two main regions: schottky region SD and DMOS region DM. The schottky region SD is surrounded by isolation regions 62a and is used primarily to form the schottky diode 104 of fig. 1. DMOS region DM extends substantially from the boundary of isolation region 62A to the far right of fig. 2A, primarily to structure MOS 102 in fig. 1.

Please refer to the cross-sectional view in fig. 2A. An N-type deep well 110 is formed in the P-type semiconductor substrate 106. In the DMOS area DM, the P-body 108 is disposed on the N-deep well 110, and the N-heavily doped sources 68a, 68b and the P-heavily doped region 66 are formed in the P-body 108. In the top view, the isolation region 62c surrounds the region with a portion of the N-type deep well 110, the P-type body 108, the N-type heavily doped sources 68a, 68b, and the P-type heavily doped region 66. The gate 70a, which may be a patterned polysilicon, is electrically isolated from the heavily doped N-type source 68a, the P-type body 108, and the deep N-type well 110, and also covers a portion of the isolation region 62 c. The control gate 70b is electrically isolated from the N-type heavily doped source 68b, the P-type body 108, and the N-type deep well 110, and also covers a portion of the isolation region 62 c. Isolation region 62c surrounds heavily N-doped drain 68c, which surrounds isolation region 62 a. The heavily N-doped sources 68a, 68B and the heavily P-doped region 66 are shorted together by a metal connection to serve as the source base S/B of the MOS 102. The N-type heavily doped sources 68a, 68b are electrically shorted to the P-type body 108 by the P-type heavily doped region 66. The heavily N-doped drain 68c serves as the drain D of the MOS 102. The control GATE 70a, which is the GATE GATE of the MOS 102, controls the electrical connection between the N-type heavy doped source 68a and the N-type deep well 110. Control gate 70b may be shorted together with control gate 70a by a metal connection to increase the current driving force of MOS 102.

Although the N-type heavily doped sources 68a, 68B and the N-type heavily doped drain 68c are respectively located at different positions in the top view in fig. 2A and 2B, they are all produced simultaneously by the same manufacturing process, and therefore share many common characteristics. For example, they all have the same dopant, the same dopant concentration, and the same depth. Similarly, the isolation regions 62a, 62b, 62c are also created simultaneously with each other through the same manufacturing process, sharing the same insulation and thickness. As is known in the general semiconductor process, the control gates 70a, 70b have only different positions and sizes in a plan view, and they are simultaneously produced through the same manufacturing process, so they share many common characteristics.

The schottky region SD is surrounded by isolation regions 62A, and in the top view of fig. 2A, includes three unconnected isolation regions 62 b. A metal layer 72 is formed on the surface of the N-type deep well 110 in the schottky region SD as an anode a of the schottky diode 104. The metal layer 72 and the N-type deep well 110 form a Schottky junction to provide a rectifying function. The N-type deep well 110 in the schottky region SD serves as the cathode of the schottky diode 104. The cathode of the schottky diode 104 is shorted to the drain D of the MOS 102 by the deep well 110. In other words, the deep well 110 is a semiconductor layer shared by the schottky diode 104 and the MOS 102.

The metal layer 72 may be a metal silicide (silicide) generated in a self-aligned silicide (silicide) process, or a metal plug (metal plug) in a contact hole (contact hole). A Resistor Protection Oxide (RPO) may be selectively formed in the schottky region SD. When there is no RPO in the schottky region SD, a schottky junction is generated by the contact between the metal silicide and the N-type deep well 110. When there is RPO in the schottky region SD, a schottky junction is generated by the metal plug contacting the N-type deep well 110.

The distance between the isolation region 62b and the isolation region 62a can be optimized to set the breakdown voltage (breakdown voltage) of the schottky diode 104. The closer the distance between isolation region 62b to isolation region 62a, the higher the breakdown voltage of schottky diode 104.

The heavily doped N-type drain 68c is floating, meaning that there is no metal connection above the heavily doped N-type drain 68c, making it electrically connected to a fixed potential. However, the heavily doped N-type drain 68c is electrically shorted to the deep N-type well 110, so the heavily doped N-type drain 68c may be influenced by the deep N-type well 110 and has a fixed potential.

Also shown in fig. 2A is the main path Pth of electron flow from the N-type highly doped source 68a, through the P-type body 108, the N-type deep well 110, to the metal layer 72 in the schottky region SD when the GATE is appropriately biased. The presence of the floating heavily doped N-type drain 68c can adjust the position of the main path Pth, reducing the equivalent resistance of the main path Pth.

The top views of fig. 2A and 2B also show a plurality of metal plugs 78A, 78G, 78SB that provide metal connections outside the GATE of the anode A, MOS 102 of schottky diode 104 and the source base S/B pair of MOS 102.

When the high voltage semiconductor device 100 of fig. 1 is implemented as the high voltage semiconductor device 100a of fig. 2A and 2B, the P-type semiconductor substrate 106 is electrically connected to the ground pin GND, the anode a is electrically connected to the high voltage charging pin HVR, and the source base S/B is electrically connected to the operation power pin VCC. The diode D1 in fig. 1 is parasitic at the junction between the P-body 108 and the N-well 110, and the diode D2 is parasitic at the junction between the P-semiconductor substrate 106 and the N-well 110.

Fig. 3 shows a power supply 10 implemented according to the present invention, which employs the synchronous rectification controller 12 of fig. 1.

The power supply 10 has a transformer 18 having a primary winding LP and a secondary winding LS inductively coupled to each other, and divided into a primary side and a secondary side which are dc-isolated from each other. On the primary side, there is a primary-side controller 14 which receives the signal S_FLBKSwitching the main power switch NMP to control the current I-_PRI. The synchronous rectification controller 12 on the secondary side controls the synchronous rectification switch NMS for the current I flowing through the secondary side coil LS_SECRectifying to generate an output voltage V-_OUTAnd supplies power to load 16.

The drive pin DRV of the synchronous rectification controller 12 provides a control signal S_SYNThe synchronous rectification switch NMS is turned on or off to control the electrical connection between the secondary winding LS and the secondary ground line 28. For correct rectification, therefore when the channel voltage V of the synchronous rectifier switch NMS_DSWhen negative, the synchronous rectification switch NMS should be turned on to short-circuit the secondary winding LS to the ground line 28. When the channel voltage V of the synchronous rectification switch NMS_DSFor the right time, the synchronous rectification switch NMS should be turned off to avoid the loss of the output voltage V-_OUTThe electric energy of (1).

High-voltage charging pinThe HVR is electrically connected to the contact point between the secondary winding LS and the synchronous rectifier switch NMS, and has a signal V thereon_HVR. A resistor RDT is connected between the detection pin DET and the high-voltage charging pin HVR. Input power supply pin VIN receives output voltage V-_OUT. The operating supply pin VCC is connected to an operating supply capacitor CVCC. The ground pin GND is connected to the ground line 28.

FIG. 4 shows the signal S of FIG. 3 on the primary side_FLBKWith signal V of the secondary side_HVRThe signal waveform of (2).

Signal S_FLBKThe switching period T can be defined_CYCOpening time T_ONAnd closing time T-_OFF. At a turn-on time T_ONTime, signal V_HVRVoltage ratio of output voltage V_OUTMuch higher reflecting the input voltage V of the primary side_IN. Closing time T-_OFFInitially, signal V is due to some parasitic element effect_HVRNegative surge SPK capable of first generating large negative voltage_NE. Thereafter, as the transformer 18 discharges, the signal V_HVRWould be negative but very close to 0V. After the transformer 18 is discharged, the signal V_HVROscillate until the next on-time T_ONAnd starting.

At a turn-on time T_ONThe synchronous rectification controller 12 may provide a proper bias voltage to the GATE GATE to turn on the high voltage semiconductor device 100 according to the signal V_HVRDraws current to charge an operating supply capacitor CVCC connected to an operating supply pin VCC to provide the power required by the synchronous rectification controller 12. The high voltage semiconductor device 100 can also withstand the turn-on time T_ONTime, signal V_HVRThe high voltage that occurs.

At the closing time T-_OFFThe schottky diode 104 in the synchronous rectification controller 12 can block the signal V_HVRNegative spike SPK of_NEThe resulting reverse current may be induced. If no Schottky diode 104 is present, the signal V is blocked_HVRNegative spike SPK of_NEThis may cause forward biasing of diodes D1 and D2, which may generate a significant reverse current that may burn components in synchronous rectifier controller 12. Because of the Schottky of twoPresence of pole tube 104 when the negative spike SPK_NEWhen present, the schottky diode 104 is reverse biased, so the occurrence of reverse current is blocked.

The upper half of fig. 5 shows a top view of the high voltage semiconductor device 100b, and the lower half shows a cross-sectional view of the high voltage semiconductor device 100b along the CC line in the top view. The high voltage semiconductor element 100b may be the high voltage semiconductor element 100 in fig. 1. Fig. 5 is similar to or identical to fig. 2A and 2B, and reference is made to the previous description of the high voltage semiconductor device 100a, which will not be repeated herein.

The high voltage semiconductor device 100B in fig. 5 differs from the high voltage semiconductor device 100a in fig. 2A and 2B only in the structure in the schottky region SD. There are several exclusion zones 62B within schottky region SD of fig. 2A, 2B. Unlike the schottky region SD of fig. 2A and 2B, the schottky region SD of fig. 5 has a P-type lightly doped region 80. The P-type lightly doped regions 80 may be formed together with the P-type lightly doped regions formed by reducing the electric field of the PMOS transistor in a lightly-doped drain (LDD) process. In the top view of fig. 5, the P-type lightly doped region 80 is surrounded by a plurality of voids (void)82 where the P-type lightly doped region is not formed. In the cross-sectional view of fig. 5, the metal layer 72 in the void 82 forms a schottky junction with the N-type deep well 110, and the P-type lightly doped region 80 forms a PN junction with the N-type deep well 110. The size of the void 82 may set the breakdown voltage (breakdown voltage) of the schottky diode 104. The smaller the void 82, the easier the depletion regions formed by the PN junctions on either side of the void 82 will connect together, and the higher the breakdown voltage of the schottky diode 104.

A resistance protection oxide may be selectively formed in the schottky region SD in fig. 5. When there is no RPO in the schottky region SD, a schottky junction is generated by the contact between the metal silicide and the N-type deep well 110. When there is RPO in the schottky region SD, a schottky junction is generated by the metal plug contacting the N-type deep well 110.

Fig. 6 shows a cross-sectional view of the high voltage semiconductor device 100 c. Fig. 6 is similar to or the same as fig. 5, and reference may be made to the previous descriptions of the high voltage semiconductor devices 100a and 100b, which will not be repeated herein. The high voltage semiconductor device 100c of fig. 6 may share a top view with the high voltage semiconductor device 100b of fig. 5. Compared to the high voltage semiconductor device 100b of fig. 5, the high voltage semiconductor device 100c of fig. 6 has more P-type deeply buried lightly doped layers 84 formed in the N-type deep well 110 below the P-type lightly doped region 80 and substantially aligned with the P-type lightly doped region 80. The P-type deeply buried lightly doped layer 84 can increase the depth of the depletion region formed by the PN junctions on both sides under the cavity 82, and further increase the breakdown voltage of the schottky diode 104. A resistance protection oxide may be selectively formed in the schottky region SD in fig. 6.

Although the isolation regions 62a, 62b, and 62c are shown as STI (shallow trench isolation) in the above embodiments, the invention is not limited thereto. The isolation regions 62a, 62b, 62c may also be implemented using field oxide (field oxide).

In the above embodiments, the heavily doped N-type sources 68a, 68b and the heavily doped N-type drain 68c may be formed simultaneously when the heavily doped source-drain regions of the NMOS transistor are formed. The heavily P-doped regions 66 may be formed simultaneously with the heavily source and drain doped regions of the PMOS transistors.

The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.