阅读说明：本技术 振动器件 (Vibration device ) 是由 水垣浩一 于 2020-09-28 设计创作，主要内容包括：提供振动器件,该振动器件是小型的。振动器件具有：半导体衬底,其具有处于正反关系的第1面和第2面；集成电路,其设置于所述第1面；第1端子,其设置于所述第2面,被施加衬底电位；第2端子,其设置于所述第2面,被施加与所述衬底电位不同的电位；第1贯通电极,其贯通所述半导体衬底,将所述第1端子与所述集成电路电连接；第2贯通电极,其贯通所述半导体衬底,将所述第2端子与所述集成电路电连接；框部,其贯通所述半导体衬底,具有绝缘性；振动片,其配置于所述第1面；以及盖,其与所述第1面接合,所述第1贯通电极位于所述框部的外侧,所述第2贯通电极位于所述框部的内侧。(A vibration device is provided which is compact. The vibration device has: a semiconductor substrate having a 1 st surface and a 2 nd surface in a positive-negative relationship; an integrated circuit provided on the 1 st surface; a 1 st terminal provided on the 2 nd surface to which a substrate potential is applied; a 2 nd terminal provided on the 2 nd surface and to which a potential different from the substrate potential is applied; a 1 st through electrode penetrating the semiconductor substrate and electrically connecting the 1 st terminal to the integrated circuit; a 2 nd through electrode penetrating the semiconductor substrate and electrically connecting the 2 nd terminal to the integrated circuit; a frame portion penetrating the semiconductor substrate and having an insulating property; a vibrating reed disposed on the 1 st surface; and a cover bonded to the 1 st surface, wherein the 1 st through-electrode is located outside the frame portion, and the 2 nd through-electrode is located inside the frame portion.)

1. A vibration device, characterized by having:

a semiconductor substrate having a 1 st surface and a 2 nd surface in a positive-negative relationship;

an integrated circuit provided on the 1 st surface;

a 1 st terminal provided on the 2 nd surface to which a substrate potential is applied;

a 2 nd terminal provided on the 2 nd surface and to which a potential different from the substrate potential is applied;

a 1 st through electrode penetrating the semiconductor substrate and electrically connecting the 1 st terminal to the integrated circuit;

a 2 nd through electrode penetrating the semiconductor substrate and electrically connecting the 2 nd terminal to the integrated circuit;

a frame portion penetrating the semiconductor substrate and having an insulating property;

a vibrating reed disposed on the 1 st surface; and

a cover engaged with the 1 st face,

the 1 st through electrode is positioned outside the frame portion,

the 2 nd through electrode is located inside the frame portion.

2. The vibration device of claim 1,

the vibrating device has an insulating film having a through hole and disposed between the 2 nd surface and the 2 nd terminal,

the 2 nd terminal is electrically connected to the 2 nd through electrode via the through hole.

3. The vibration device of claim 2,

the width of the via hole is greater than the width of the 2 nd through electrode,

the through hole is surrounded by the frame portion in a plan view,

the 2 nd terminal is electrically connected to an inner region of the frame portion of the semiconductor substrate via the through hole.

4. The vibration device according to any one of claims 1 to 3, wherein,

the frame portion has:

a hole penetrating the semiconductor substrate;

an insulating film disposed on an inner surface of the hole; and

a conductive material filled in the hole.

5. The vibration device of claim 4,

supplying power to the integrated circuit via the 2 nd terminal,

the 2 nd through electrode is electrically connected to the conductive material.

6. The vibration device of claim 4,

outputting a signal from the integrated circuit via the 2 nd terminal,

the 2 nd through electrode is not electrically connected to the conductive material.

7. The vibration device of claim 1,

the length of the 2 nd through via electrode is larger than the width of the 2 nd through via electrode.

Technical Field

The present invention relates to a vibration device.

Background

The semiconductor device described in patent document 1 includes a silicon substrate. A cylindrical through-electrode penetrating the silicon substrate, a first insulating film covering a sidewall of the cylindrical through-electrode, and a stripe-shaped through-electrode located inside the cylindrical through-electrode and penetrating the silicon substrate are formed on the silicon substrate. Therefore, if the bump connected to the through-hole is brought into contact with not only the through-hole but also the silicon substrate around the through-hole, insulation failure is less likely to occur even if current leaks from the terminal to the silicon substrate via the contact portion. Therefore, a decrease in reliability of the semiconductor device can be suppressed.

Patent document 1: japanese patent laid-open publication No. 2006-019431

However, if the cylindrical through-electrodes and the insulating film as in patent document 1 are arranged around all the through-electrodes, the semiconductor device becomes large.

Disclosure of Invention

The vibration device of the present application example is characterized by having: a semiconductor substrate having a 1 st surface and a 2 nd surface in a positive-negative relationship; an integrated circuit provided on the 1 st surface; a 1 st terminal provided on the 2 nd surface to which a substrate potential is applied; a 2 nd terminal provided on the 2 nd surface and to which a potential different from the substrate potential is applied; a 1 st through electrode penetrating the semiconductor substrate and electrically connecting the 1 st terminal to the integrated circuit; a 2 nd through electrode penetrating the semiconductor substrate and electrically connecting the 2 nd terminal to the integrated circuit; a frame portion penetrating the semiconductor substrate and having an insulating property; a vibrating reed disposed on the 1 st surface; and a cover bonded to the 1 st surface, wherein the 1 st through-electrode is located outside the frame portion, and the 2 nd through-electrode is located inside the frame portion.

In the vibration device of the present application example, it is preferable that the vibration device includes an insulating film having a through hole and disposed between the 2 nd surface and the 2 nd terminal, and the 2 nd terminal is electrically connected to the 2 nd through electrode via the through hole.

In the vibration device of the present application example, it is preferable that the width of the through hole is larger than the width of the 2 nd through electrode, the through hole is surrounded by the frame portion in a plan view, and the 2 nd terminal is electrically connected to an inner region of the frame portion of the semiconductor substrate via the through hole.

In the vibration device of the present application example, it is preferable that the frame portion has: a hole penetrating the semiconductor substrate; an insulating film disposed on an inner surface of the hole; and a conductive material filled in the hole.

In the vibration device of the present application example, it is preferable that power is supplied to the integrated circuit through the 2 nd terminal, and the 2 nd through electrode is electrically connected to the conductive material.

In the vibration device according to the application example, it is preferable that a signal from the integrated circuit is output through the 2 nd terminal, and the 2 nd through electrode is not electrically connected to the conductive material.

In the vibration device of the present application example, it is preferable that the length of the 2 nd through hole electrode is larger than the width of the 2 nd through hole electrode.

Drawings

Fig. 1 is a sectional view showing a vibration device of embodiment 1.

Fig. 2 is a bottom view of the base substrate.

Fig. 3 is a cross-sectional view showing a connection state of the through electrode and the terminal.

Fig. 4 is a cross-sectional view showing a capacitor formed in a base substrate.

Fig. 5 is a plan view showing the vibrating piece.

Fig. 6 is a diagram illustrating a manufacturing process of the vibration device of fig. 1.

Fig. 7 is a sectional view for explaining a manufacturing method of the vibration device.

Fig. 8 is a sectional view for explaining a manufacturing method of the vibration device.

Fig. 9 is a sectional view for explaining a manufacturing method of the vibration device.

Fig. 10 is a sectional view for explaining a manufacturing method of the vibration device.

Fig. 11 is a sectional view for explaining a manufacturing method of the vibration device.

Fig. 12 is a sectional view for explaining a manufacturing method of the vibration device.

Fig. 13 is a sectional view for explaining a manufacturing method of the vibration device.

Fig. 14 is a sectional view for explaining a manufacturing method of the vibration device.

Fig. 15 is a sectional view for explaining a manufacturing method of the vibration device.

Description of the reference symbols

1: a vibrating device; 2: a base substrate; 2 a: an upper surface; 2 b: a lower surface; 20: an insulating film; 201. 202, 203: a through hole; 21. 23: an aperture; 24: a conductive portion; 3: a vibrating piece; 31: vibrating the substrate; 321. 322: an excitation electrode; 323. 324: a terminal; 325. 326: wiring; 4: a cover; 41: a recess; 5: an integrated circuit; 50: a laminate; 51: an insulating layer; 52: a wiring layer; 53: an insulating layer; 54: a passivation film; 55: a terminal layer; 551. 552: a terminal; 56. 561, 562, 563: a terminal; 571. 572, 573: a through electrode; 6: an engaging member; 92. 93: a frame portion; b1, B2: an engaging member; c1: a capacitor; GND: a ground; p: a contact portion; q1, Q2: an area; s: a storage space; s1: a hole forming step; s2: an insulating film forming step; s3: a through electrode forming step; s4: an integrated circuit forming process; s5: a vibrating piece configuration procedure; s6: a cap bonding step; s7: a substrate thinning step; s8: a terminal forming step; s9: a step of singulation; t1: an element separating region; t2: an activation region; VDD: a drive voltage; l1, L2: a length; w1, W2: width.

Detailed Description

Hereinafter, a vibration device according to the present application example will be described in detail with reference to embodiments shown in the drawings.

< embodiment 1>

Fig. 1 is a sectional view showing a vibration device of embodiment 1. Fig. 2 is a bottom view of the base substrate. Fig. 3 is a cross-sectional view showing a connection state of the through electrode and the terminal. Fig. 4 is a cross-sectional view showing a capacitor formed in a base substrate. Fig. 5 is a plan view showing the vibrating piece. Fig. 6 is a diagram illustrating a manufacturing process of the vibration device of fig. 1. Fig. 7 to 15 are sectional views for explaining a method of manufacturing the vibration device, respectively. In addition, for convenience of explanation, in fig. 1 to 5, 3 axes perpendicular to each other are illustrated as an X axis, a Y axis, and a Z axis. The side toward which the arrow in the Z-axis direction is directed is also referred to as "up" and the opposite side as "down". In addition, a plan view along the Z axis is also simply referred to as a "plan view". In the following description, "formed on the upper surface" and "disposed on the upper surface" include not only the case where the substrate is directly formed or disposed on the upper surface but also the case where the substrate is formed or disposed at a position spaced apart from the upper surface by a predetermined distance, that is, the case where the substrate is "formed on the upper surface" and "disposed on the upper surface". The same is true with respect to the lower surface.

The vibration device 1 shown in fig. 1 has: a base substrate 2; a vibrating reed 3 disposed on the upper surface of the base substrate 2; and a lid 4 bonded to the upper surface of the base substrate 2 so as to cover the vibrating reed 3.

The base substrate 2 is a silicon substrate as a semiconductor substrate. However, the base substrate 2 is not particularly limited, and a semiconductor substrate other than silicon, for example, a semiconductor substrate such as Ge, GaP, GaAs, InP, or the like may be used.

The base substrate 2 has an upper surface 2a as a 1 st surface and a lower surface 2b as a 2 nd surface in a front-back relationship, and the surface of the base substrate 2 is covered with an insulating film 20. Further, an integrated circuit 5 electrically connected to the vibrating piece 3 is formed on the upper surface 2 a. The integrated circuit 5 includes an element isolation region T1 and an active region T2, the active region T2 is surrounded by the element isolation region T1, and an active element not shown, such as a transistor, is formed in the active region T2. By forming the integrated circuit 5 on the base substrate 2, the space of the base substrate 2 can be effectively used. In particular, by forming the integrated circuit 5 on the upper surface 2a, the integrated circuit 5 can be disposed in the housing space S described later, and the integrated circuit 5 can be protected from the external environment. The integrated circuit 5 is not particularly limited, and for example, an oscillation circuit that oscillates the oscillator 3 and generates a frequency of a reference signal such as a clock signal is given.

A laminate 50 in which an insulating layer 51, a wiring layer 52, an insulating layer 53, a passivation film 54, and a terminal layer 55 are laminated is provided on the upper surface 2a of the base substrate 2, and the laminate 50 is electrically connected to a plurality of active elements, not shown, formed on the upper surface 2a via wirings included in the wiring layer 52, thereby forming the integrated circuit 5. The terminal layer 55 is electrically connected to the wiring layer 52, and includes a pair of terminals 551 and 552 for electrically connecting to the vibrating reed 3. For convenience of explanation, the stacked body 50 is configured to include one wiring layer 52, but the present invention is not limited thereto, and a plurality of wiring layers 52 may be stacked via the insulating layer 53. That is, the wiring layer 52 and the insulating layer 53 may be alternately laminated a plurality of times between the insulating layer 51 and the passivation film 54.

A plurality of terminals 56 are provided on the lower surface 2b of the base substrate 2. These terminals 56 function as external connection terminals for electrically connecting to external electronic devices such as circuit boards. Further, the plurality of terminals 56 include a terminal 561 as a 1 st terminal and terminals 562 and 563 as 2 nd terminals. The terminal 561 is a terminal connected to a substrate potential, the terminal 562 is a terminal connected to a power supply of the integrated circuit 5, and the terminal 563 is a terminal which outputs an oscillation signal from the integrated circuit 5. However, the number and use of the terminals 56 are not particularly limited, and can be set as appropriate according to the structure of the integrated circuit 5. When the base substrate 2 is a P-type silicon substrate having P-type conductivity, the terminal 561 is connected to the ground GND, and the driving voltage VDD is applied to the terminal 562. Conversely, when the base substrate 2 is an N-type silicon substrate having N-type conductivity, the terminal 562 is connected to the ground GND, and the driving voltage VDD is applied to the terminal 561. In this embodiment, the base substrate 2 is formed of a P-type silicon substrate.

The terminal 561 is electrically connected to the integrated circuit 5 through a through electrode 571 that is a 1 st through electrode penetrating the base substrate 2 in the thickness direction, the terminal 562 is electrically connected to the integrated circuit 5 through a through electrode 572 that is a 2 nd through electrode penetrating the base substrate 2 in the thickness direction, and the terminal 563 is electrically connected to the integrated circuit 5 through a through electrode 573 that is a 2 nd through electrode penetrating the base substrate 2 in the thickness direction. The through-electrode 571 is electrically connected to the region to which the substrate potential is supplied via the wiring layer 52, and the through-electrodes 572 and 573 are electrically connected to the circuit elements in the activation region T2 via the wiring layer 52. These through electrodes 571, 572, 573 are formed by penetrating the base substrate 2 in the thickness direction and filling a hole 21 with a conductive material, and the hole 21 is formed with the insulating film 20 on the inner wall. Further, the through electrodes 571, 572, 573 are formed so as to overlap the activation region T2 and not overlap the element separation region T1, respectively.

As shown in fig. 2, the length L1 of the through-electrodes 571, 572, 573 in the direction along the Y axis is larger than the width W1 which is the length in the direction along the X axis when viewed from above in the direction along the Z axis, and particularly in the present embodiment, the through-electrodes 571, 572, 573 are elongated. Namely, L1> W1. By forming the through-electrodes 571, 572, 573 in such a shape, the cross-sectional area can be increased while suppressing an increase in size of the vibration device 1, and the resistance of the through-electrodes 571, 572, 573 can be reduced.

However, the structure of the through electrodes 571, 572, 573 is not particularly limited. For example, at least one of the through-electrodes 571, 572, 573 may be bent or curved halfway, or may change in width halfway. At least one of the through electrodes 571, 572, 573 may have a different longitudinal axis. For example, the length axis may be along the X-axis, or intersect both the X-axis and the Y-axis. At least one of the through-electrodes 571, 572, 573 may have a shape having the same length and width, for example, a square shape or a circular shape.

Next, connection portions between the terminals 561, 562, and 563 and the through electrodes 571, 572, and 573 will be described. As described above, the insulating film 20 is formed on the lower surface 2b of the base substrate 2, and the terminals 561, 562, and 563 are arranged on the lower surface of the insulating film 20. As shown in fig. 1 and 2, through holes 201, 202, and 203 as through holes are formed in the insulating film 20 at portions overlapping the through electrodes 571, 572, and 573, and the terminals 561, 562, and 563 are electrically connected to the through electrodes 571, 572, and 573 through the through holes 201, 202, and 203.

As shown in fig. 2, the length of the through holes 201, 202, 203 in the direction along the X axis, i.e., the width W2, is larger than the width W1 of the through electrodes 571, 572, 573. W2> W1 is provided to allow positional deviation of the through holes 201, 202, 203. Specifically, although the through holes 201, 202, and 203 are formed by etching the insulating film 20 formed on the entire lower surface 2b, the through holes 201, 202, and 203 are formed at positions overlapping the through electrodes 571, 572, and 573 even if the mask used at this time is slightly shifted in the direction along the X axis from the set position. On the other hand, the length L2 of the through holes 201, 202, 203 in the direction along the Y axis is shorter than the length L1 of the through electrodes 571, 572, 573. Since L2< L1 is provided to form the through-electrodes 571, 572, 573 in a long shape extending along the Y axis, even if the mask is slightly displaced in the direction along the Y axis, the through-holes 201, 202, 203 can be formed at positions overlapping the through-electrodes 571, 572, 573, and therefore, it is not necessary to secure a large length L1.

If W2> W1 is set as described above, the terminals 561, 562, 563 can be electrically connected to the through-electrodes 571, 572, 573 more reliably through the through-holes 201, 202, 203, but the following problems occur. That is, if W2> W1 is set, as shown in fig. 3, the terminals 561, 562, and 563 are in contact with not only the through electrodes 571, 572, and 573 but also the base substrate 2, and the terminals 561, 562, and 563 are electrically connected to the base substrate 2. Therefore, currents of the driving signal and the oscillation signal leak from the terminals 561, 562, and 563 to the base substrate 2 via the contact portion P, and the characteristics and reliability of the integrated circuit 5 deteriorate. Therefore, in the vibration device 1, a design is performed such that the current leakage to the base substrate 2 does not adversely affect the characteristics and reliability of the integrated circuit 5. The following description is made in detail.

As shown in fig. 1 and 2, frame portions 92 and 93 are formed on the base substrate 2, and the frame portions 92 and 93 surround a part of the base substrate 2 when viewed from a plane along the Z axis, penetrate the base substrate 2 in the thickness direction, and have insulating properties. These frame portions 92 and 93 insulate the inside region Q1 and the outside region Q2 in the base substrate 2.

The frame portions 92 and 93 respectively have: a hole 23 penetrating the base substrate 2 in the thickness direction; an insulating film 20 disposed on an inner wall of the hole 23; and a conductive portion 24 made of a conductive material filled in the hole 23. That is, the frame portions 92 and 93 have the same structure as the through electrodes 571, 572, and 573. Therefore, the frame portions 92 and 93 can be formed together with the through electrodes 571, 572, and 573, and complication of the manufacture of the vibration device 1 can be suppressed. However, the structures of the frames 92 and 93 are not particularly limited as long as the regions Q1 and Q2 can be insulated from each other. For example, the hole 23 may be filled with an insulating material instead of the conductive material. Further, the hole 23 may be filled with only the insulating film 20 without filling the hole 23 with the conductive material.

As shown in fig. 2, a through electrode 572 for supplying power to the integrated circuit 5 is disposed in the frame portion 92. Further, the entire region of the through hole 202 overlapping the through electrode 572 is located inside the frame 92 when viewed from the top in the direction along the Z axis. Therefore, the terminal 562 is electrically connected to the region Q1 in the frame portion 92 of the base substrate 2 via the through hole 202. Therefore, even if power leaks to the base substrate 2 via the terminal 562, the leakage is confined within the region Q1, and leakage to the outside of the region Q1, i.e., the region Q2, can be effectively suppressed. The frame portion 92 is formed to be large enough to arrange the entire range of the through hole 202 inside even if the through hole 202 is misaligned.

Similarly, a through electrode 573 for extracting an oscillation signal from the integrated circuit 5 is disposed in the frame portion 93. Further, the entire region of the through hole 203 overlapping with the through electrode 573 is located inside the frame 93 when viewed in a plan view from the direction along the Z axis. Therefore, the terminal 563 is electrically connected to the region Q1 located in the frame portion 93 of the base substrate 2 via the through hole 203. Therefore, even if the oscillation signal leaks to the base substrate 2 via the terminal 563, the leakage is confined to the region Q1, and the leakage to the outside of the region Q1, that is, the region Q2 can be effectively suppressed. The frame portion 92 is formed to be large enough to allow the entire range of the through hole 203 to be disposed inside even if the through hole 203 is misaligned.

By surrounding the through electrodes 572 and 573 with the frame portions 92 and 93 in this way, leakage of the power supply and the oscillation signal to the region Q2 can be suppressed. Therefore, by forming each circuit element included in the integrated circuit 5 in the region Q2 of the activation region T2, the characteristics and reliability of the integrated circuit 5 can be ensured.

On the other hand, through electrodes 571 for supplying a substrate potential to the integrated circuit 5 are disposed outside the frame portions 92, 93. Therefore, the terminal 561 is electrically connected to the region Q2 outside the frame portions 92 and 93 of the base substrate 2 through the through hole 203. Therefore, the substrate potential leaks to the region Q2 of the base substrate 2 via the terminal 561, but the leaked substrate potential is the same as the potential of the base substrate 2, and therefore there is no problem. In this way, the terminal 561 and the through electrode 571, which have no problem even if they leak, are not surrounded by a frame portion, and thus the vibration device 1 can be miniaturized. That is, according to the vibration device 1 of the present embodiment, the characteristics and reliability of the integrated circuit 5 can be ensured, and miniaturization can also be achieved.

In particular, in the present embodiment, as shown in fig. 2, the through electrode 572 is connected to the frame portion 92 at both end portions and is electrically connected to the conductive portion 24. Thus, as shown in fig. 4, a capacitor C1 functioning as a bypass capacitor is formed between the conductive portion 24 and a region Q2 of the submount substrate 2 connected to GND serving as the substrate potential. Therefore, the power supply to the integrated circuit 5 is stabilized. However, the through electrode 572 is not limited to this, and may be connected to the frame 92 at one end, for example. The through electrode 572 may be insulated from the conductive portion 24 without being connected to the frame portion 92.

On the other hand, as shown in fig. 2, the through electrode 573 is not in contact with the frame portion 93 and is not connected to the frame portion 93. Therefore, the through electrode 573 is electrically insulated from the conductive portion 24 in the frame portion 93. Thus, a capacitor such as the capacitor C1 is not formed between the conductive portion 24 and the region Q2 of the base substrate 2. Therefore, Noise is less likely to be mixed into the oscillation Signal extracted from the terminal 563, and an oscillation Signal having a high S/N Ratio (Signal to Noise Ratio) can be obtained. However, the through electrode 573 is not limited to this, and may be electrically connected to the conductive portion 24 in the frame portion 93.

As described above, the through-electrodes 572 and 573 can be configured to be changed according to the application thereof, and the through-electrodes 572 and 573 are the same in arrangement in the frame portions 92 and 93, thereby obtaining the vibration device 1 with higher accuracy.

The cover 4 as a cover portion is a silicon substrate, as in the base substrate 2. Thus, the base substrate 2 and the cover 4 have the same linear expansion coefficient, and the occurrence of thermal stress due to thermal expansion can be suppressed, thereby obtaining the vibration device 1 having excellent vibration characteristics. Further, since the vibration device 1 can be formed by a semiconductor process, the vibration device 1 can be manufactured with high accuracy and can be miniaturized. However, the lid 4 is not particularly limited, and a semiconductor substrate other than silicon, for example, a semiconductor substrate of Ge, GaP, GaAs, InP, or the like may be used.

The lid 4 has a bottomed recess 41, and the recess 41 is opened to the lower surface of the lid 4 and accommodates the vibrating reed 3 therein. The lid 4 is joined to the upper surface 2a of the base substrate 2 via a joining member 6 on the lower surface thereof. Thereby, a housing space S is formed between the lid 4 and the base substrate 2, and the vibrating piece 3 is housed in the housing space S. The storage space S is airtight and is in a reduced pressure state, preferably a state closer to vacuum. This improves the oscillation characteristics of the vibrating reed 3. However, the environment of the housing space S is not particularly limited, and may be, for example, an environment in which an inert gas such as nitrogen or Ar is sealed, or may be in an atmospheric pressure state or a pressurized state instead of a reduced pressure state.

As shown in fig. 5, the vibrating reed 3 includes a vibrating substrate 31 and electrodes disposed on the surface of the vibrating substrate 31. The vibration base plate 31 has a thickness shear vibration mode, and is formed of an AT-cut quartz substrate in the present embodiment. The AT-cut quartz substrate has third-order frequency temperature characteristics, and thus the vibrating piece 3 having excellent temperature characteristics is obtained. Further, the electrode has: an excitation electrode 321 disposed on the upper surface of the vibration substrate 31; and an excitation electrode 322 disposed on the lower surface of the vibration substrate 31 so as to face the excitation electrode 321. Further, the electrode has: a pair of terminals 323 and 324 disposed on the lower surface of vibration substrate 31; a wiring 325 electrically connecting the terminal 323 and the excitation electrode 321; and a wiring 326 electrically connecting the terminal 324 and the excitation electrode 322.

In addition, the structure of the vibrating reed 3 is not limited to the above-described structure. For example, the vibrating reed 3 may be a mesa type in which a vibration region sandwiched by the excitation electrodes 321 and 322 protrudes from the periphery of the vibrating reed 3, or conversely, a reverse mesa type in which a vibration region is recessed from the periphery of the vibrating reed 3. Further, a bevel process of grinding the periphery of the vibration substrate 31 or a convex process of making the upper surface and the lower surface convex may be performed.

The vibrating reed 3 is not limited to a vibrating reed that vibrates in a thickness shear vibration mode, and may be a vibrating reed in which a plurality of vibrating arms are flexural-vibrated in an in-plane direction, for example. That is, the vibration base plate 31 is not limited to being formed of an AT-cut quartz substrate, and may be formed of a quartz substrate other than an AT-cut quartz substrate, for example, an X-cut quartz substrate, a Y-cut quartz substrate, a Z-cut quartz substrate, a BT-cut quartz substrate, an SC-cut quartz substrate, an ST-cut quartz substrate, or the like. In the present embodiment, the vibration substrate 31 is made of quartz, but is not limited to this, and may be made of a piezoelectric single crystal such as lithium niobate, lithium tantalate, lithium tetraborate, langasite, potassium niobate, gallium phosphate, or other piezoelectric single crystals. The vibrating reed 3 is not limited to the piezoelectric driving type, and may be an electrostatic driving type using an electrostatic force.

The vibrating reed 3 is fixed to the upper surface 2a of the base substrate 2, more specifically, the upper surface of the stacked body 50, by conductive bonding members B1 and B2. The bonding member B1 electrically connects the terminal 551 of the laminate 50 and the terminal 323 of the vibrating reed 3, and the bonding member B2 electrically connects the terminal 552 of the laminate 50 and the terminal 324 of the vibrating reed 3. Thereby, the vibrating reed 3 is electrically connected to the integrated circuit 5.

The bonding members B1 and B2 are not particularly limited as long as they have both conductivity and bondability, and for example, various metal bumps such as gold bumps, silver bumps, copper bumps, and solder bumps, and a conductive adhesive in which a conductive filler such as a silver filler is dispersed in various adhesives such as polyimide, epoxy, silicone, and acrylic adhesives can be used. When the former metal bumps are used as the bonding members B1 and B2, generation of gas from the bonding members B1 and B2 can be suppressed, and changes in the environment of the housing space S, particularly, increases in pressure can be effectively suppressed. On the other hand, when the latter conductive adhesive is used as the bonding members B1, B2, the bonding members B1, B2 are softer than the metal bumps, and it is difficult to transmit stress to the vibrating piece 3.

The vibration device 1 has been explained briefly above. As described above, such a vibration device 1 has: a base substrate 2 as a semiconductor substrate having an upper surface 2a as a 1 st surface and a lower surface 2b as a 2 nd surface in a front-back relationship; an integrated circuit 5 provided on the upper surface 2 a; a terminal 561 as a 1 st terminal provided on the lower surface 2b to which a substrate potential is applied; terminals 562 and 563 as the 2 nd terminal provided on the lower surface 2b and applied with a potential different from the substrate potential; a through electrode 571 serving as a 1 st through electrode penetrating the base substrate 2 and electrically connecting the terminal 561 to the integrated circuit 5; through-electrodes 572 and 573 as the 2 nd through-electrodes that penetrate the base substrate 2 and electrically connect the terminals 562 and 563 to the integrated circuit 5; frame portions 92 and 93 penetrating the base substrate 2 and having insulation properties; a vibrating reed 3 disposed on the upper surface 2 a; and a cover 4 as a lid portion that is joined to the upper surface 2 a. The through-electrode 571 is located outside the frame portions 92 and 93, and the through-electrodes 572 and 573 are located inside the frame portions 92 and 93.

By disposing the through electrodes 572 and 573 connected to the terminals 562 and 563 having a potential different from the substrate potential inside the frame portions 92 and 93 in this way, even if a current leaks from the terminals 562 and 563 and the through electrodes 572 and 573 to the base substrate 2, the leakage is confined within the inner region Q1 of the frame portions 92 and 93, and the leakage to the outer region Q2 of the frame portions 92 and 93, which is outside the region Q1, can be effectively suppressed. Therefore, the characteristics and reliability of the integrated circuit 5 can be ensured. Further, even if the substrate potential leaks from the terminal 561 and the through electrode 571 to the base substrate 2, there is no problem, and therefore, by not disposing the frame portion around the through electrode 571, the vibration device 1 can be downsized.

As described above, the vibration device 1 includes the insulating film 20, the insulating film 20 has the through holes 202 and 203, and is disposed between the lower surface 2b and the terminals 562 and 563, and the terminals 562 and 563 are electrically connected to the through electrodes 571 and 572 through the through holes 202 and 203. This allows the terminals 562 and 563 to be insulated from the base substrate 2, and the terminals 562 and 563 to be electrically connected to the through electrodes 572 and 573.

As described above, the width W2 of the through holes 202 and 203 is larger than the width W1 of the through electrodes 572 and 573, and the through holes 202 and 203 are surrounded by the frame portions 92 and 93 in a plan view, and the terminals 562 and 563 are electrically connected to the inner regions Q1 of the frame portions 92 and 93 of the base substrate 2 through the through holes 202 and 203. In this way, by setting W2> W1, positional deviation of the through holes 202 and 203 can be allowed, and the terminals 562 and 563 can be electrically connected to the through electrodes 571 and 572 more reliably. Although current leaks from the portions of the terminals 562 and 563 which are in contact with the base substrate 2 to the base substrate 2, since the through holes 202 and 203 are surrounded by the frame portions 92 and 93, the leakage is limited to the region Q1, and the leakage to the region Q2 which is outside the region Q1 can be effectively suppressed. Therefore, the degradation of the characteristics and reliability of the integrated circuit can be suppressed.

As described above, the frame portions 92 and 93 include: a hole 23 penetrating the base substrate 2; an insulating film 20 disposed on an inner surface of the hole 23; and a conductive portion 24 made of a conductive material filled in the hole 23. This simplifies the structure of the frame portions 92 and 93. Further, since the frame portions 92 and 93 can be formed at once by the same process as the through electrodes 571, 572, and 573, complication of the manufacturing of the vibration device 1 can be suppressed.

As described above, power is supplied to the integrated circuit 5 via the terminal 562, and the through electrode 572 is electrically connected to the conductive portion 24 of the frame portion 92. Thus, since the capacitor C1 functioning as a bypass capacitor is formed between the conductive portion 24 and the region Q2, power can be stably supplied to the integrated circuit 5.

As described above, a signal (oscillation signal in the present embodiment) from the integrated circuit 5 is output via the terminal 563, and the through electrode 573 is not electrically connected to the conductive portion 24 of the frame portion 93. Thus, noise is less likely to be mixed into the oscillation signal, and an oscillation signal with a high S/N ratio can be obtained.

As described above, the through-electrodes 572 and 573 are elongated in a plan view of the base substrate 2. That is, the length L1 of the through-electrodes 572, 573 is longer than the width W1 of the through-electrodes 572, 573. By forming the shape in this manner, the cross-sectional area of the through-electrodes 572 and 573 can be increased and the resistance of the through-electrodes 572 and 573 can be reduced while suppressing an increase in size of the vibration device 1.

Next, a method for manufacturing the vibration device 1 will be described with reference to fig. 6 to 15. As shown in fig. 6, the method of manufacturing the vibration device 1 includes: a hole forming step S1 of forming holes 21 and 23, the holes 21 and 23 being opened toward the upper surface 2a of the base substrate 2; an insulating film forming step S2 of forming the insulating film 20 on the inner surfaces of the holes 21 and 23; a through-electrode forming step S3 of filling the holes 21 and 23 with a conductive material to form through-electrodes 571, 572, and 573 and a conductive portion 24; an integrated circuit forming step S4 of forming an integrated circuit 5 on the upper surface 2a of the base substrate 2; a vibrating reed disposing step S5 of disposing the vibrating reed 3 on the upper surface 2a of the base substrate 2; a lid bonding step S6 of bonding the lid 4 covering the vibrating piece 3 to the base substrate 2; a substrate thinning step S7 of thinning the base substrate 2; a terminal forming step S8 of forming terminals 561, 562, and 563 on the lower surface 2b of the base substrate 2; and a singulation step S9. The respective steps S1 to S9 will be described in detail in order. In addition, the broken lines in fig. 7 to 14 indicate portions that are cut or removed before the completion of the vibration device 1.

< hole Forming Process S1>

As shown in fig. 7, a base substrate 2 included in a silicon wafer is prepared, and holes 21 and 23 are formed in the base substrate 2. The holes 21, 23 are open to the upper surface 2a of the base substrate 2. The base substrate 2 to be prepared in this way is thicker than the thickness of the base substrate 2 in the finished state shown in fig. 1. This increases the strength of the base substrate 2, and improves the handleability during manufacturing. The holes 21 and 23 are formed as bottomed recesses deeper than the thickness of the base substrate 2 in the finished state shown in fig. 1, and do not penetrate through the lower surface 2b of the base substrate 2. By forming the hole 21 as a bottomed recess, the formation time of the hole 21 is shortened as compared with a case where the hole 21 penetrates the lower surface 2b, for example. In the through-electrode forming step S3, the holes 21 and 23 are easily filled with a conductive material, and the through-electrodes 571, 572, 573 and the conductive portion 24 are easily formed.

The method for forming the holes 21 and 23 is not particularly limited, but the holes can be formed by, for example, dry etching, particularly, Bosch process. This enables the formation of the holes 21 and 23 having a high aspect ratio, and the vibration device 1 can be miniaturized. In addition, the present step is not limited to this, and the hole 21 may penetrate the lower surface 2 b. Further, the widths of the holes 21 and 23 are preferably made equal. This makes it possible to form holes 21 and 23 at equal etching rates and with good balance.

< insulating film Forming Process S2>

As shown in FIG. 8, the base substrate 2 is thermally oxidized to form silicon dioxide (SiO) on the surface of the base substrate 2, particularly on the inner surfaces of the holes 21 and 23₂) And an insulating film 20. By forming the insulating film 20 by thermal oxidation, a dense and homogeneous insulating film 20 can be formed on the surface of the base substrate 2. Further, the difference in linear expansion coefficient between the insulating film 20 and the base substrate 2 can be reduced. Therefore, the vibration device 1 having excellent oscillation characteristics in which thermal stress is hardly generated can be obtained. However, the material of the insulating film 20 is not particularly limited, and may be silicon nitride (SiN), for example. The method of forming the insulating film 20 is not limited to thermal oxidation, and may be formed by CVD, for example.

< through-electrode Forming Process S3>

As shown in fig. 9, the holes 21 and 23 are filled with a conductive material, and through electrodes 571, 572, and 573 that do not penetrate in this state but penetrate the base substrate 2 when completed, and a conductive portion 24 are formed. In addition, although the conductive material is not particularly limited, in the present embodiment, conductive polysilicon is used. The conductive polysilicon is, for example, polysilicon doped with impurities such As phosphorus (P), boron (B), and arsenic (As) to impart conductivity. By using polysilicon as the conductive material, the through-electrodes 571, 572, 573 and the conductive portion 24 having sufficient resistance to heat applied in the integrated circuit forming step S4 can be obtained. Therefore, it is difficult to generate electrical defects due to the through electrodes 571, 572, 573. Further, the difference in linear expansion coefficient with the base substrate 2 can also be reduced. Therefore, the vibration device 1 having excellent oscillation characteristics in which thermal stress is hardly generated can be obtained. However, the conductive material is not particularly limited, and for example, a metal material having excellent heat resistance such as tungsten (W) can be used.

< Integrated Circuit Forming Process S4>

As shown in fig. 10, an element isolation region T1 and an active region T2 are formed on the upper surface 2a side of the base substrate 2, at least one active element, not shown, such as a transistor is formed in the active region T2, and the active region T2 is surrounded by the element isolation region T1. In addition, the through electrodes 571, 572, 573 are positioned so as not to overlap the element separation region T1, in other words, the activation region T2. Next, the insulating layer 51, the wiring layer 52, the insulating layer 53, the passivation film 54, and the terminal layer 55 are sequentially stacked on the upper surface 2a of the base substrate 2 to form a stacked body 50. The stacked body 50 is formed by removing a bonding portion of the upper surface 2a of the base substrate 2 to which the cover 4 is bonded. The integrated circuit 5 is formed as described above.

By forming the integrated circuit 5 after forming the through-electrodes 571, 572, 573 and the conductive portions 24 in this way, thermal damage (thermal history) to the integrated circuit 5 during manufacturing can be reduced. Specifically, in the method of forming the through-electrodes 571, 572, 573 and the conductive portions 24 after forming the integrated circuit 5, heat at the time of forming the insulating film 20 and heat at the time of forming the through-electrodes 571, 572, 573 and the conductive portions 24 are applied to the integrated circuit 5, but in the method of the present embodiment, at least heat at the time of forming the insulating film 20 and heat at the time of forming the through-electrodes 571, 572, 573 and the conductive portions 24 are not applied to the integrated circuit 5. Therefore, a decrease in reliability of the integrated circuit 5 can be suppressed. Further, by forming the through electrodes 571, 572, 573 and the conductive portions 24 before forming the integrated circuit 5, the insulating film 20, the through electrodes 571, 572, 573 and the conductive portions 24 can be formed at an appropriate temperature without considering thermal damage of the integrated circuit 5. Therefore, formation defects of the insulating film 20, the through electrodes 571, 572, 573, and the conductive portion 24 are less likely to occur.

Each layer of the stacked body 50 can be formed by film formation by CVD or patterning by etching, for example. In thatIn this embodiment, the insulating layers 51 and 53 are made of silicon oxide (SiO)₂) The wiring layer 52 and the terminal layer 55 are made of conductive polysilicon, and the passivation film 54 is made of silicon nitride (SiN). By forming each layer with a silicon-based material in this manner, the difference in linear expansion coefficient between the laminate 50 and the base substrate 2 can be reduced. Therefore, the vibration device 1 having excellent oscillation characteristics in which thermal stress is hardly generated can be obtained. However, the constituent material of each layer is not particularly limited.

< vibrating reed placing step S5>

As shown in fig. 11, the vibrating reed 3 is prepared, and the vibrating reed 3 is bonded to the upper surface 2a of the base substrate 2 (specifically, the upper surface of the stacked body 50) via the bonding members B1 and B2. The terminal 551 of the laminate 50 and the terminal 323 of the vibrating reed 3 are electrically connected via the bonding member B1, and the terminal 552 of the laminate 50 and the terminal 324 of the vibrating reed 3 are electrically connected via the bonding member B2. Thereby, the vibrating reed 3 is electrically connected to the integrated circuit 5.

< Cap bonding step S6>

As shown in fig. 12, a cap 4 included in a silicon wafer is prepared and bonded to the upper surface 2a of the base substrate 2 via a bonding member 6 in a reduced-pressure atmosphere. Note that, the lid 4 to be prepared here may be made thicker than the lid 4 in the finished state shown in fig. 1, and the lid 4 may be thinned from the upper surface side of the lid 4 after the terminal forming step S8 and before the singulation step S9. This increases the strength of the cap 4 during manufacture, and improves the handleability.

< substrate thinning step S7>

As shown in fig. 13, the base substrate 2 is thinned from the lower surface 2b side of the base substrate 2, and holes 21 and 23 penetrate the lower surface 2b of the base substrate 2. The method for thinning is not particularly limited, and for example, cutting, grinding, polishing, etching, and the like can be used. As a method of grinding and polishing, for example, back grinding, CMP (chemical mechanical grinding), dry polishing, and the like can be used in combination.

< terminal Forming Process S8>

As shown in fig. 14, after the insulating film 20 is formed on the lower surface 2b of the base substrate 2, terminals 561, 562, and 563 are formed at positions overlapping the through-electrodes 571, 572, and 573. Thereby, the through electrodes 571, 572, 573 are electrically connected to the terminals 561, 562, 563. Through the above steps, the plurality of vibration devices 1 are integrally formed on the silicon wafer.

< singulation step S9>

As shown in fig. 15, the individual vibrating devices 1 are cut out and singulated by dicing with a dicing saw or the like. Through the above steps, the vibration device 1 can be obtained.

Although the vibration device of the present application example has been described above with reference to the embodiments shown in the drawings, the present application example is not limited to this, and the structure of each part may be replaced with any structure having the same function. In addition, other arbitrary structures may be added to the present application example. In addition, in the present application example, arbitrary 2 or more configurations in the above embodiments may be combined.