阅读说明：本技术 一种动态配置通道的总线互联系统 (Bus interconnection system with dynamically configured channels ) 是由 方新嘉 陈雷 乐立鹏 安印龙 刘亚鹏 魏星 王佩 于 2020-12-11 设计创作，主要内容包括：本发明涉及一种动态配置通道的总线互联系统,属于总线互联结构设计领域；包括输入多路模块IN MUX、输出多路模块OUT MUX、0-m号通道模块Channel和通道控制器Channel CTRL；本发明与现有互联总线相比,可以根据需要传输的数据量动态的开启或关闭合适数据通道数目,可以实现兼顾高吞吐率和低功耗的优点。(The invention relates to a bus interconnection system for dynamically configuring a channel, belonging to the field of bus interconnection structure design; the system comprises an input multi-path module IN MUX, an output multi-path module OUT MUX, a Channel module Channel of0-m and a Channel controller Channel CTRL; compared with the existing interconnection bus, the invention can dynamically open or close the appropriate number of data channels according to the data volume to be transmitted, and can realize the advantages of high throughput rate and low power consumption.)

1. A bus interconnect system for dynamically configuring channels, comprising: the system comprises an input multi-path module IN MUX, an output multi-path module OUT MUX, a Channel module Channel of0-m and a Channel controller Channel CTRL; wherein the content of the first and second substances,

input multiplexing module IN MUX: a plurality of bus multiplexers and arbiters IN MUX ARB are arranged inside the bus multiplexer; each bus multiplexer selects corresponding main equipment from the bus of the external No. 0-n main equipment Master according to the arbitration result of the arbiter IN MUX ARB and connects the main equipment to the input multi-channel module IN MUX;

output MUX of the MUX block OUT: a plurality of bus multiplexers and arbiters OUT MUX ARB are arranged inside the bus multiplexer; each bus multiplexer selects 1 Channel module Channel from the Channel module Channel output bus of No. 0-m to be connected to the corresponding external Slave device Slave according to the arbitration result of the arbiter OUT MUX ARB;

channel module Channel: realizing data transmission, monitoring the quantity of the transmitted data, and feeding back a monitoring result to a Channel controller CTRL;

channel controller Channel CTRL: receiving a monitoring result transmitted by a Channel module; and (3) closing a Channel power supply or a clock of the Channel module, realizing scheduling of the Channel modules of m +1, and realizing closing or opening of the Channel modules.

2. The bus interconnect system for dynamically configuring channels of claim 1, wherein: the output bus of the external 0-n number Master is connected to the bus inputs M0-Mn of the input multi-path module IN MUX; the bus outputs InC 0-InCm of the input multi-path module IN MUX are respectively connected to the bus inputs of channels Chanel 0-m; the bus output of the Channel module 0-m is connected to the bus inputs OuC 0-OuCm of the output multi-Channel module OUT MUX; bus outputs S0-Sj of an output multi-path module OUT MUX are output to an input bus of an external Slave device Slave number 0-j;

the input multiplex module IN MUX is connected to the interconnection bus control module Channel CTRL through an arbiter IN MUX ARB control bus; the output multiplexer block OUT MUX is connected to the interconnection bus control block Channel CTRL through an OUT MUX ARB control bus;

the Channel controller Channel CTRL is respectively connected to the input interfaces of the power management modules of the Channel modules Channel 0-m through Pof0-m power control circuits; the control of the on or off of Channel power supplies of all Channel modules is realized;

the Channel controller ChannelCTRL is respectively connected to the clock gating pins of the Channel modules Channel 0-m through Chn 0-m clock control lines; the Channel clock of each Channel module is controlled to be turned on or turned off;

the Channel controller Channel CTRL is respectively connected to the interfaces of the traffic monitoring modules of the Channel modules Channel 0-m through Mon 0-m traffic monitoring lines; and monitoring the Channel flow of each Channel module.

3. The bus interconnect system for dynamically configuring channels of claim 2, wherein: the Channel module comprises a Power supply control module Power, a Channel flow monitoring module Monitor and a Bus Channel module Bus Channel; a Power supply control circuit of the Channel CTRL is connected to the Power supply control module Power; a clock control line Chn of the Channel control module Channel CTRL is connected with a Bus Channel module Bus Channel; the input and output buffer consumption output of the Bus Channel module is connected to the Channel flow monitoring module Monitor; the Channel traffic monitoring module Monitor is connected to the Channel controller Channel CTRL via a traffic monitoring line Mon.

4. The bus interconnect system for dynamically configuring channels of claim 3, wherein: the Channel controller Channel CTRL comprises a configuration register REG, a state machine FSM, a controller module CTRL, a clock module TIME and a global history cache module GHB;

external configuration information enters a configuration register REG, and the configuration register REG is connected to the controller module CTRL through a signal line; the configuration register REG is connected to the state machine FSM through a signal line; the state machine FSM module is connected to a CTRL on the controller through a signal line; the controller CTRL module is connected to an arbiter IN MUX ARB IN the input multi-way module IN MUX module through an IN _ MUX _ ARB bus; the controller module CTRL module is connected to an arbiter OUT MUX ARB in the output multiplexer module OUT MUX through an OUT _ MUX _ ARB bus; the controller module CTRL is connected to the POWER control modules POWER of the Channel modules Channel 0-m via POWER control lines Pof0-m, respectively; the controller module CTRL is connected via clock control lines Chn 0-m to the Bus Channel of the Channel modules Channel 0-m; the controller module CTRL is connected with the Channel flow monitoring module Monitor of the Channel module channels 0-m through a power supply control line Pof 0-m; the controller module CTRL is connected to the clock module TIME via a signal line; the controller module CTRL is connected to the global history buffer module GHB via signal lines.

5. The bus interconnect system for dynamically configuring channels of claim 4, wherein: the bus interconnection system comprises 3 working modes, namely a low-power-consumption working mode, a high-performance working mode and a dynamic configuration working mode; after the bus interconnection system is started, the bus interconnection system defaults to enter a high-performance working mode; and after configuration is written through the configuration bus, the low-power-consumption working mode, the dynamic configuration working mode or the high-performance working mode is selected to enter again.

6. The bus interconnect system for dynamically configuring channels of claim 5, wherein: the low-power consumption working mode is as follows: opening a channel 0, and closing channels 1-m; m is the maximum number of channels, and a Channel control module Channel CTRL schedules all traffic to go to Channel 0;

the high-performance operating mode is as follows: all channels 0-m are opened, and each channel corresponds to a Master device; m takes the Master as the minimum number as the standard;

all channels 0-j are opened, and each channel corresponds to a Slave device Slave; j is subject to the minimum number of Slave devices Slave.

7. The bus interconnect system for dynamically configuring channels of claim 6, wherein: the dynamic configuration working mode is as follows: the Channel controller ChannelCTRL schedules the flow on the Channel module to be closed with the flow lower than a preset lower threshold value to other Channel modules according to the flow statistical information transmitted by the Channel flow monitoring module Monitor of each Channel module, and closes the clock of a BUS Channel in the Channel module after the flow on the Channel module to be closed is cleared; and the power supply of the Channel module Channel is closed according to the configuration information of whether the Channel power supply is closed in the configuration register REG; when the flow on the Channel module to be adjusted exceeds a preset upper limit, the Channel controller ChannelCTRL monitors the flow on the Channel of other Channel modules, and when the flow on the Channel of other Channel modules is lower, the flow on the Channel module to be adjusted is dispatched to the Channel of other Channel modules; when the flow rate of other Channel modules is higher, the Channel controller CTRL inquires whether a closed Channel module Channel exists, if so, the Channel module Channel is opened, the flow rate is scheduled to the newly opened Channel module Channel, if not, the flow rate is scheduled among the opened Channel modules Channel to keep the flow rate balance among the Channel modules Channel, and the process is circulated; through configuration information in the configuration register REG, the Channel controller Channel CTRL reads information from the clock module TIME and the global history buffer GHB, and periodically turns on or off a part of the channels.

Technical Field

The invention belongs to the field of bus interconnection structure design, and relates to a bus interconnection system with dynamically configured channels.

Background

The currently mainstream CPU bus structures are mainly classified into simple single bus structures and complex switching matrices. A single bus architecture, on which all master devices (master) and all slave devices (slave) are mounted. The method is commonly used in a simple CPU system, has the advantages of simplicity, low power consumption and the like, and has the defect that each master must apply for the use right of a bus when accessing different slave, and cannot simultaneously perform the access. The performance of the system is low. In the bus structure of the switching matrix, all the masters and all the slave are mounted on different interfaces, and a point-to-point channel is established between the masters and the slave in the communication process. The respective masters can access different slave simultaneously, so the performance is high. There are cases where power consumption is high.

Disclosure of Invention

The technical problem solved by the invention is as follows: the defects in the prior art are overcome, the bus interconnection system with the dynamically configured channels is provided, the appropriate number of data channels can be dynamically opened or closed according to the data volume to be transmitted, and the advantages of high throughput rate and low power consumption can be achieved.

The technical scheme of the invention is as follows:

a bus interconnection system for dynamically configuring channels comprises an input multi-Channel module IN MUX, an output multi-Channel module OUT MUX, a Channel module Channel of0-m and a Channel controller Channel CTRL; wherein the content of the first and second substances,

input multiplexing module IN MUX: a plurality of bus multiplexers and arbiters IN MUX ARB are arranged inside the bus multiplexer; each bus multiplexer selects corresponding main equipment from the bus of the external No. 0-n main equipment Master according to the arbitration result of the arbiter IN MUX ARB and connects the main equipment to the input multi-channel module IN MUX;

output MUX of the MUX block OUT: a plurality of bus multiplexers and arbiters OUT MUX ARB are arranged inside the bus multiplexer; each bus multiplexer selects 1 Channel module Channel from the Channel module Channel output bus of No. 0-m to be connected to the corresponding external Slave device Slave according to the arbitration result of the arbiter OUT MUX ARB;

channel module Channel: realizing data transmission, monitoring the quantity of the transmitted data, and feeding back a monitoring result to a Channel controller CTRL;

channel controller Channel CTRL: receiving a monitoring result transmitted by a Channel module; and (3) closing a Channel power supply or a clock of the Channel module, realizing scheduling of the Channel modules of m +1, and realizing closing or opening of the Channel modules.

IN the bus interconnection system with dynamically configured channels, the output bus of the external 0-n number Master is connected to the bus inputs M0-Mn of the input multi-path module IN MUX; the bus outputs InC 0-InCm of the input multi-path module IN MUX are respectively connected to the bus inputs of channels Chanel 0-m; the bus output of the Channel module 0-m is connected to the bus inputs OuC 0-OuCm of the output multi-Channel module OUT MUX; bus outputs S0-Sj of an output multi-path module OUT MUX are output to an input bus of an external Slave device Slave number 0-j;

the input multiplex module IN MUX is connected to the interconnection bus control module Channel CTRL through an arbiter IN MUX ARB control bus; the output multiplexer block OUT MUX is connected to the interconnection bus control block Channel CTRL through an OUT MUX ARB control bus;

the Channel controller Channel CTRL is respectively connected to the input interfaces of the power management modules of the Channel modules Channel 0-m through Pof0-m power control circuits; the control of the on or off of Channel power supplies of all Channel modules is realized;

the Channel controller Channel CTRL is respectively connected to the clock gating pins of the Channel modules Channel 0-m through Chn 0-m clock control lines; the Channel clock of each Channel module is controlled to be turned on or turned off;

the Channel controller Channel CTRL is respectively connected to the interfaces of the traffic monitoring modules of the Channel modules Channel 0-m through Mon 0-m traffic monitoring lines; and monitoring the Channel flow of each Channel module.

In the Bus interconnection system with dynamically configured channels, the Channel module Channel includes a Power control module Power, a Channel traffic monitoring module Monitor and a Bus Channel module Bus Channel; a Power supply control circuit of the Channel CTRL is connected to the Power supply control module Power; a clock control line Chn of the Channel control module Channel CTRL is connected with a Bus Channel module Bus Channel; the input and output buffer consumption output of the Bus Channel module is connected to the Channel flow monitoring module Monitor; the Channel traffic monitoring module Monitor is connected to the Channel controller Channel CTRL via a traffic monitoring line Mon.

In the bus interconnection system for dynamically configuring the Channel, the Channel controller CTRL includes a configuration register REG, a state machine FSM, a controller module CTRL, a clock module TIME, and a global history buffer module GHB;

external configuration information enters a configuration register REG, and the configuration register REG is connected to the controller module CTRL through a signal line; the configuration register REG is connected to the state machine FSM through a signal line; the state machine FSM module is connected to a CTRL on the controller through a signal line; the controller CTRL module is connected to an arbiter IN MUX ARB IN the input multi-way module IN MUX module through an IN _ MUX _ ARB bus; the controller module CTRL module is connected to an arbiter OUT MUX ARB in the output multiplexer module OUT MUX through an OUT _ MUX _ ARB bus; the controller module CTRL is connected to the POWER control modules POWER of the Channel modules Channel 0-m via POWER control lines Pof0-m, respectively; the controller module CTRL is connected via clock control lines Chn 0-m to the Bus Channel of the Channel modules Channel 0-m; the controller module CTRL is connected with the Channel flow monitoring module Monitor of the Channel module channels 0-m through a power supply control line Pof 0-m; the controller module CTRL is connected to the clock module TIME via a signal line; the controller module CTRL is connected to the global history buffer module GHB via signal lines.

In the bus interconnection system with the dynamically configured channel, the bus interconnection system includes 3 working modes, which are a low power consumption working mode, a high performance working mode and a dynamically configured working mode, respectively; after the bus interconnection system is started, the bus interconnection system defaults to enter a high-performance working mode; and after configuration is written through the configuration bus, the low-power-consumption working mode, the dynamic configuration working mode or the high-performance working mode is selected to enter again.

In the bus interconnection system with dynamically configured channels, the low power consumption operating mode is as follows: opening a channel 0, and closing channels 1-m; m is the maximum number of channels, and a Channel control module Channel CTRL schedules all traffic to go to Channel 0;

the high-performance operating mode is as follows: all channels 0-m are opened, and each channel corresponds to a Master device; m takes the Master as the minimum number as the standard;

all channels 0-j are opened, and each channel corresponds to a Slave device Slave; j is subject to the minimum number of Slave devices Slave.

In the bus interconnection system with a dynamically configured channel, the dynamically configured operating mode is as follows: the Channel controller Channel CTRL schedules the flow on the Channel module Channel to be closed with the flow lower than a preset lower threshold value to other Channel modules according to the flow statistical information transmitted by the Channel flow monitoring module Monitor of each Channel module Channel, and closes the clock of a BUS Channel in the Channel module Channel after the flow on the Channel module Channel to be closed is cleared; and the power supply of the Channel module Channel is closed according to the configuration information of whether the Channel power supply is closed in the configuration register REG; when the flow on the Channel module to be adjusted exceeds a preset upper limit, a Channel controller, namely, a Channel CTRL, monitors the flow on the Channel of other Channel modules, and when the flow on the Channel of other Channel modules is lower, the flow on the Channel module to be adjusted is dispatched to the Channel of other Channel modules; when the flow rate of other Channel modules is higher, the Channel controller CTRL inquires whether a closed Channel module Channel exists, if so, the Channel module Channel is opened, the flow rate is scheduled to the newly opened Channel module Channel, if not, the flow rate is scheduled among the opened Channel modules Channel to keep the flow rate balance among the Channel modules Channel, and the process is circulated; through configuration information in the configuration register REG, the Channel controller Channel CTRL reads information from the clock module TIME and the global history buffer GHB, and periodically turns on or off a part of the channels.

Compared with the prior art, the invention has the beneficial effects that:

(1) the invention has a plurality of data channels, and can realize that different masters simultaneously access different slave to realize the parallel of bus level under the setting of high performance;

(2) compared with the existing switching matrix, the invention can reduce the number of channels in time according to the data flow on the channels, thereby realizing low power consumption;

(3) the reduced channels of the invention can realize power-off, thereby reducing the static power consumption of the circuit;

(4) in the dynamic channel mode, the opening condition of the channel is counted according to the statistics, and the channel is opened in advance according to the period condition.

Drawings

FIG. 1 is a schematic diagram of a bus interconnect system according to the present invention;

FIG. 2 is a schematic diagram of a Channel module of the present invention;

fig. 3 is a schematic diagram of the Channel controller CTRL according to the present invention.

Detailed Description

The invention is further illustrated by the following examples.

The bus interconnection structure provided by the invention absorbs the advantages of a single bus and an interaction matrix, realizes the switching between the advantages and the disadvantages of two bus structures by means of engineering technology, and realizes a balance. Therefore, the CPU system has high performance and low power consumption at the same time.

A bus interconnection system for dynamically configuring channels, as shown IN fig. 1, includes an input MUX, an output MUX, an OUT MUX, a Channel module Channel 0-m, and a Channel controller Channel CTRL; wherein the content of the first and second substances,

input multiplexing module IN MUX: a plurality of bus multiplexers and arbiters IN MUX ARB are arranged inside the bus multiplexer; each bus multiplexer selects corresponding main equipment from the bus of the external No. 0-n main equipment Master according to the arbitration result of the arbiter IN MUX ARB and connects the main equipment to the input multi-channel module IN MUX;

output MUX of the MUX block OUT: a plurality of bus multiplexers and arbiters OUT MUX ARB are arranged inside the bus multiplexer; each bus multiplexer selects 1 Channel module Channel from the Channel module Channel output bus of No. 0-m to be connected to the corresponding external Slave device Slave according to the arbitration result of the arbiter OUT MUX ARB;

channel module Channel: realizing data transmission, monitoring the quantity of the transmitted data, and feeding back a monitoring result to a Channel controller CTRL;

channel controller Channel CTRL: receiving a monitoring result transmitted by a Channel module; and (3) closing a Channel power supply or a clock of the Channel module, realizing scheduling of the Channel modules of m +1, and realizing closing or opening of the Channel modules.

The output bus of the external 0-n number Master is connected to the bus inputs M0-Mn of the input multi-path module IN MUX; the bus outputs InC 0-InCm of the input multi-path module IN MUX are respectively connected to the bus inputs of channels Chanel 0-m; the bus output of the Channel module 0-m is connected to the bus inputs OuC 0-OuCm of the output multi-Channel module OUT MUX; bus outputs S0-Sj of an output multi-path module OUT MUX are output to an input bus of an external Slave device Slave number 0-j;

the input multiplex module IN MUX is connected to the interconnection bus control module Channel CTRL through an arbiter IN MUX ARB control bus; the output multiplexer block OUT MUX is connected to the interconnection bus control block Channel CTRL through an OUT MUX ARB control bus;

the Channel controller Channel CTRL is respectively connected to the input interfaces of the power management modules of the Channel modules Channel 0-m through Pof0-m power control circuits; the control of the on or off of Channel power supplies of all Channel modules is realized;

the Channel controller Channel CTRL is respectively connected to the clock gating pins of the Channel modules Channel 0-m through Chn 0-m clock control lines; the Channel clock of each Channel module is controlled to be turned on or turned off;

the Channel controller Channel CTRL is respectively connected to the interfaces of the traffic monitoring modules of the Channel modules Channel 0-m through Mon 0-m traffic monitoring lines; and monitoring the Channel flow of each Channel module.

As shown in fig. 2, the Channel module Channel includes a Power control module Power, a Channel traffic monitoring module Monitor, and a Bus Channel module Bus Channel; a Power supply control circuit of the Channel CTRL is connected to the Power supply control module Power; a clock control line Chn of the Channel control module Channel CTRL is connected with a Bus Channel module Bus Channel; the input and output buffer consumption output of the Bus Channel module is connected to the Channel flow monitoring module Monitor; the Channel traffic monitoring module Monitor is connected to the Channel controller Channel CTRL via a traffic monitoring line Mon.

The Pof signal line from the Channel control module Channel CTRL is connected to the switch of the Power domain where the Power module controls the current Channel, and the Chn signal line from the Channel control module Channel CTRL is connected to the Bus Channel, and can control the clock of the data Channel Bus Channel to be turned off. The input and output buffers of the Bus Channel of the data Channel are connected to the traffic monitoring module Monitor. For monitoring data traffic and traffic being transmitted on the Bus Channel of the data Channel.

As shown in fig. 3, the Channel controller Channel CTRL comprises a configuration register REG, a state machine FSM, a controller module CTRL, a clock module TIME, and a global history buffer module GHB;

external configuration information enters a configuration register REG, and the configuration register REG is connected to the controller module CTRL through a signal line; the configuration register REG is connected to the state machine FSM through a signal line; the state machine FSM module is connected to a CTRL on the controller through a signal line; the controller CTRL module is connected to an arbiter IN MUX ARB IN the input multi-way module IN MUX module through an IN _ MUX _ ARB bus; the controller module CTRL module is connected to an arbiter OUT MUX ARB in the output multiplexer module OUT MUX through an OUT _ MUX _ ARB bus; the controller module CTRL is connected to the POWER control modules POWER of the Channel modules Channel 0-m via POWER control lines Pof0-m, respectively; the controller module CTRL is connected via clock control lines Chn 0-m to the Bus Channel of the Channel modules Channel 0-m; the controller module CTRL is connected with the Channel flow monitoring module Monitor of the Channel module channels 0-m through a power supply control line Pof 0-m; the controller module CTRL is connected to the clock module TIME via a signal line; the controller module CTRL is connected to the global history buffer module GHB via signal lines.

The configuration information is connected via a configuration bus Config to a configuration register REG, which is connected via a set of signal lines to the controller module CTRL and the state machine FSM, respectively. The configuration information is transmitted to the controller CTRL and the state machine FSM, respectively. The state machine FSM module is connected to the controller CTRL via a set of signal lines. The controller CTRL block is connected via the IN _ MUX _ ARB bus to the respective ARBs IN the input multiplex IN MUX block. The controller CTRL block is connected via the OUT MUX ARB bus to the respective ARBs in the output MUX block. The controller CTRL module is connected to the POWER control module POWER of each channel via signal line Pof 0. The controller CTRL block is connected via signal lines Chn 0.. m to the Bus Channel of the respective Channel. The controller CTRL module is connected to the monitoring modules for each channel via bus Pof 0. The controller CTRL block is connected to the clock block TIME via a set of signal lines. The controller CTRL module is connected to the global history buffer module GHB via a set of signal lines.

The bus interconnection system comprises 3 working modes, namely a low-power-consumption working mode, a high-performance working mode and a dynamic configuration working mode; after the bus interconnection system is started, the bus interconnection system defaults to enter a high-performance working mode; and after configuration is written through the configuration bus, the low-power-consumption working mode, the dynamic configuration working mode or the high-performance working mode is selected to enter again.

The low-power consumption working mode is as follows: opening a channel 0, and closing channels 1-m; m is the maximum number of channels, and a Channel control module Channel CTRL schedules all traffic to go to Channel 0;

the high-performance operating mode is as follows: all channels 0-m are opened, and each channel corresponds to a Master device; m takes the Master as the minimum number as the standard;

all channels 0-j are opened, and each channel corresponds to a Slave device Slave; j is subject to the minimum number of Slave devices Slave.

The dynamic configuration working mode is as follows: the Channel controller Channel CTRL schedules the flow on the Channel module Channel to be closed with the flow lower than a preset lower threshold value to other Channel modules according to the flow statistical information transmitted by the Channel flow monitoring module Monitor of each Channel module Channel, and closes the clock of a BUS Channel in the Channel module Channel after the flow on the Channel module Channel to be closed is cleared; and the power supply of the Channel module Channel is closed according to the configuration information of whether the Channel power supply is closed in the configuration register REG; when the flow on the Channel module to be adjusted exceeds a preset upper limit, a Channel controller, namely, a Channel CTRL, monitors the flow on the Channel of other Channel modules, and when the flow on the Channel of other Channel modules is lower, the flow on the Channel module to be adjusted is dispatched to the Channel of other Channel modules; when the flow rate of other Channel modules is higher, the Channel controller CTRL inquires whether a closed Channel module Channel exists, if so, the Channel module Channel is opened, the flow rate is scheduled to the newly opened Channel module Channel, if not, the flow rate is scheduled among the opened Channel modules Channel to keep the flow rate balance among the Channel modules Channel, and the process is circulated; through configuration information in the configuration register REG, the Channel controller Channel CTRL reads information from the clock module TIME and the global history buffer GHB, and periodically turns on or off a part of the channels.

After the system is powered on, the initial state of the bus system is in a high-performance mode, all channels are completely started, and the initialization of the system is accelerated. Writing configuration information into the bus system by the system through the configuration bus in the initialization process comprises: the working mode of the bus system, relevant parameters required by the dynamic configuration of the bus system, the upper and lower thresholds of the flow switch on the channel, whether the master/Slave is locked to use a certain channel and the like.

If the mode of operation of the configured bus system is high performance, the bus system will continue to use all channels until the next configuration.

If the configured working mode of the bus system is low power consumption, the bus system can dispatch all the flow to the channel 0, and the channel is closed after the data transmission on other channels is finished.

If the working mode of the configured BUS system is dynamic configuration, the Channel controller Channel CTRL schedules the flow on the Channel to be closed with the Channel flow lower than the lower threshold value to other channels according to the flow statistical information uploaded by each Channel monitoring module Monitor, and closes the clock of the BUS Channel in the Channel after the flow on the Channel to be closed is cleared, and closes the Channel power supply according to the configuration information of whether the Channel power supply is closed or not. When the flow on a certain Channel to be adjusted exceeds a set upper limit, the Channel controller Channel CTRL monitors the flow on other channels, and if the flow on other channels is relatively low, the flow on the Channel to be adjusted is scheduled to the other channels. If the flow rate on other channels is higher, the Channel controller Channel CTRL will inquire whether there is a closed Channel, if so, open the Channel, and schedule the flow rate to the past, if not, keep the current situation. And the process is circulated.

The flow control of the bus system is performed by writing the weights of the masters IN the ARBs on the respective multi-paths IN the IN MUX and writing the weights of the channels IN the ARBs on the respective multi-paths IN the OUT MUX through the Channel controller Channel CTRL via the IN MUX ARB bus. If the flow on a certain channel is to be reduced, the write weight of the partial master on the input multiplexer corresponding to the channel is reduced to 0, and the weight of the channel in the ARB on all the multiplexers on the output multiplexer is increased.

Since the program in the CPU system has periodicity, a clock module and a global history buffer are set at the Channel controller Channel CTRL. By configuring the corresponding configuration registers, certain channels can be periodically switched on and off by the bus system.

Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.