阅读说明：本技术 一种深紫外led集成芯片及其制备方法 (Deep ultraviolet LED integrated chip and preparation method thereof ) 是由 张会雪 郑志华 吴峰 戴江南 陈长清 于 2020-12-01 设计创作，主要内容包括：本发明属于深紫外LED芯片领域公开了一种深紫外LED集成芯片及其制备方法,该芯片是以单一一片外延生长有AlGaN外延片的晶圆衬底为基底,集成有至少2个PN结单元；每一个PN结单元作为一个深紫外LED发光单元,能够实现发光波长λ<280nm的深紫外发光；每一个PN结单元均具有N电极焊盘和P电极焊盘,这些PN结单元彼此构成并联关系和/或串联关系。本发明通过对芯片的集成设计及相应的制备方法等进行改进,在单一一片晶圆基底上进行若干发光单元串联和/或并联的集成,为现有技术中的模组封装提供了另一替代途径。且能够降低每个发光单元所对应的封装材料和人力成本,同时可以大大的减小器件的体积,适用于各种深紫外LED倒装芯片的集成。(The invention belongs to the field of deep ultraviolet LED chips and discloses a deep ultraviolet LED integrated chip and a preparation method thereof, wherein the chip takes a single wafer substrate epitaxially grown with an AlGaN epitaxial wafer as a base and is integrated with at least 2 PN junction units; each PN junction unit is used as a deep ultraviolet LED light emitting unit, and can realize deep ultraviolet light emission with the light emitting wavelength lambda less than 280 nm; each PN junction unit is provided with an N electrode pad and a P electrode pad, and the PN junction units are in parallel connection and/or series connection with each other. The invention improves the chip integration design and the corresponding preparation method, and the like, and integrates a plurality of light-emitting units in series and/or in parallel on a single wafer substrate, thereby providing another alternative way for the module packaging in the prior art. And the packaging material and labor cost corresponding to each light-emitting unit can be reduced, and the size of the device can be greatly reduced, so that the device is suitable for integration of various deep ultraviolet LED flip chips.)

1. A deep ultraviolet LED integrated chip is characterized in that the chip takes a single wafer substrate epitaxially grown with an AlGaN epitaxial wafer as a base and is integrated with at least 2 PN junction units; each PN junction unit is used as a deep ultraviolet LED light emitting unit, each PN junction unit is provided with an independent flip bonding pad, and the deep ultraviolet light emitting with the light emitting wavelength lambda less than 280nm can be realized; any 2 adjacent PN junction units are electrically isolated through a deep groove, and the depth of the deep groove reaches the contact interface of the epitaxial wafer and the wafer substrate;

the whole chip is provided with a total P pole flip bonding pad and a total N pole flip bonding pad, each PN junction unit is also provided with an independent N electrode bonding pad and an independent P electrode bonding pad, the PN junction units form a parallel connection relation and/or a series connection relation, and power supply to the PN junction units can be realized through the total P pole flip bonding pad and the total N pole flip bonding pad; wherein the content of the first and second substances,

when a certain 2 PN junction units meet the condition that an N electrode bonding pad of one PN junction unit is connected with a P electrode bonding pad of another PN junction unit in an equipotential manner, the 2 PN junction units are in a series connection relationship, and the chip has an integration mode corresponding to the series connection relationship;

when 2 PN junction units meet the condition that an N electrode bonding pad of one PN junction unit is connected with an N electrode bonding pad of another PN junction unit in an equipotential manner or a P electrode bonding pad of one PN junction unit is connected with a P electrode bonding pad of another PN junction unit in an equipotential manner, the 2 PN junction units are in a parallel connection relationship, and the chip has an integration mode corresponding to the parallel connection relationship.

2. The deep ultraviolet LED integrated chip of claim 1, wherein the chip has an integration corresponding to both a series connection relationship and a parallel connection relationship, the chip is integrated with m × n PN junction units, n parallel branches are correspondingly formed, and each parallel branch is formed by m PN junction units through the series connection relationship; wherein m and n are integers more than or equal to 2;

preferably, the total P-pole flip pad and the total N-pole flip pad on the integrated chip are respectively located at the connection intersection of the N parallel branches.

3. The deep ultraviolet LED integrated chip of claim 1, wherein the N electrode pad of one PN junction unit is connected to the P electrode pad of another PN junction unit at an equipotential, specifically by a conductive metal material, to correspondingly form an electrically connected metal layer;

the N electrode bonding pad of one PN junction unit is connected with the N electrode bonding pad of the other PN junction unit in an equipotential manner, specifically, the N electrode bonding pads are connected through a conductive metal material to correspondingly form an electric connection metal layer;

the P electrode bonding pad of one PN junction unit is connected with the P electrode bonding pad of the other PN junction unit in an equipotential manner, specifically, the P electrode bonding pad of one PN junction unit is connected with the P electrode bonding pad of the other PN junction unit through a conductive metal material, and an electric connection metal layer is correspondingly formed;

further, 2 of these electrical connection metal layers are as the total P-pole flip chip pad and the total N-pole flip chip pad.

4. The deep ultraviolet LED integrated chip of claim 1, wherein the electrical connection metal layer is located outside the AlGaN epitaxial wafer and is connected to the AlGaN epitaxial wafer through a passivation material; the passivation material is selected from SiO₂、Si₃N₄、HfO₂A DBR structure of the Bragg reflector, wherein the DBR structure of the Bragg reflector is made of SiO₂And Ti₂O₅And (3) arranging the components periodically.

5. The deep ultraviolet LED integrated chip of claim 1, wherein the N electrode terminal and the P electrode terminal of any one of the PN junction units are both located in the AlGaN epitaxial wafer, and are formed by etching an AlGaN material and evaporating an electrode material.

6. The deep ultraviolet LED integrated chip of claim 1, wherein an N electrode terminal and a P electrode terminal of any one of the PN junction units are subjected to electrode thickening processing, so that the N electrode terminal and the P electrode terminal protrude from a plane where an upper surface of the AlGaN epitaxial wafer is located and are connected to a PAD electrode above the AlGaN epitaxial wafer, where the PAD electrode is a PAD electrode.

7. The deep ultraviolet LED integrated chip of claim 6, wherein a passivation material is filled between adjacent PAD electrodes; the upper part of any PAD electrode is connected with the electric connection metal layer; the passivation material is selected from SiO₂、Si₃N₄、HfO₂A DBR structure of the Bragg reflector, wherein the DBR structure of the Bragg reflector is made of SiO₂And Ti₂O₅And (3) arranging the components periodically.

8. The deep ultraviolet LED integrated chip of claim 1, wherein the wafer substrate is a sapphire wafer or an AlN single crystal wafer.

9. The method for preparing the deep ultraviolet LED integrated chip as claimed in any one of claims 1 to 8, comprising the following steps:

(S1) taking a clean wafer substrate with the AlGaN deep ultraviolet epitaxial wafer epitaxially grown as a substrate, and forming an N electrode end and a P electrode end in the AlGaN deep ultraviolet epitaxial wafer in a target area of the AlGaN deep ultraviolet epitaxial wafer through photoetching, etching and metal evaporation processes; then, carrying out electrode thickening treatment on the N electrode end and the P electrode end to enable the N electrode end and the P electrode end to protrude out of the plane of the upper surface of the AlGaN deep ultraviolet epitaxial wafer;

(S2) forming a deep groove in the target area of the substrate through photoetching and etching processes, wherein the depth of the deep groove reaches the contact interface of the deep ultraviolet epitaxial wafer and the wafer substrate; then, depositing passivation materials, and enabling the passivation materials to fill the deep groove and cover the deep ultraviolet epitaxial wafer to form a passivation layer; then, photoetching and etching are carried out on the target area of the passivation layer to form an opening, photoetching is carried out on the position of the opening, and then metal evaporation is carried out to form a PAD electrode, namely a PAD electrode, so that the manufacturing of the single PN junction functional unit is finished;

(S3) next, depositing a second time of passivation materials so that the passivation materials cover the substrate to form a second passivation layer; then, photoetching and etching are carried out on the target area of the second passivation layer to form an opening, photoetching is carried out on the position of the opening, and then metal evaporation is carried out to form an electric connection metal layer, so that the preparation of the deep ultraviolet LED integrated chip is completed; 2 of these electrically connecting metal layers serve as a total P-pole flip-chip pad and a total N-pole flip-chip pad.

Technical Field

The invention belongs to the field of deep ultraviolet LED chips, and particularly relates to a deep ultraviolet LED integrated chip and a preparation method thereof.

Background

AlGaN based deep ultraviolet LEDs (λ <280nm) are of interest to many scientists for a wide range of applications such as disinfection, air and water purification, biochemical detection and optical communication. With the big outbreak of novel coronavirus pneumonia, the market of the deep ultraviolet disinfection product of disinfecting is more and more exploded, however, deep ultraviolet LED's luminous power is lower, still can not satisfy the requirement of present high power disinfection application product of disinfecting, this is mainly because deep ultraviolet LED's material defect density is too big, and the technical threshold is very high, and this is difficult to make the single chip of high power at present, leads to the high power to disinfect the product and must use the module that many lamp pearls are constituteed, just can reach the effect of anticipated disinfection of disinfecting.

Disclosure of Invention

In view of the above defects or improvement requirements of the prior art, an object of the present invention is to provide a deep ultraviolet LED integrated chip and a manufacturing method thereof, in which an integration design and a corresponding manufacturing method of the chip are improved, and a plurality of light emitting units are integrated in series and/or in parallel on a single wafer substrate (i.e., a plurality of PN junction units on the same substrate are integrated and designed in parallel and/or in series), so as to provide another alternative for module packaging in the prior art, and reduce the packaging material and labor cost corresponding to each light emitting unit, and at the same time, greatly reduce the volume of the device, and is suitable for integration of various deep ultraviolet LED flip chips.

In order to achieve the above object, according to one aspect of the present invention, there is provided a deep ultraviolet LED integrated chip, wherein the chip is based on a single wafer substrate epitaxially grown with an AlGaN epitaxial wafer, and is integrated with at least 2 PN junction units; each PN junction unit is used as a deep ultraviolet LED light emitting unit, each PN junction unit is provided with an independent flip bonding pad, and the deep ultraviolet light emitting with the light emitting wavelength lambda less than 280nm can be realized; any 2 adjacent PN junction units are electrically isolated through a deep groove, and the depth of the deep groove reaches the contact interface of the epitaxial wafer and the wafer substrate;

the whole chip is provided with a total P pole flip bonding pad and a total N pole flip bonding pad, each PN junction unit is also provided with an independent N electrode bonding pad and an independent P electrode bonding pad, the PN junction units form a parallel connection relation and/or a series connection relation, and power supply to the PN junction units can be realized through the total P pole flip bonding pad and the total N pole flip bonding pad; wherein the content of the first and second substances,

when a certain 2 PN junction units meet the condition that an N electrode bonding pad of one PN junction unit is connected with a P electrode bonding pad of another PN junction unit in an equipotential manner, the 2 PN junction units are in a series connection relationship, and the chip has an integration mode corresponding to the series connection relationship;

when 2 PN junction units meet the condition that an N electrode bonding pad of one PN junction unit is connected with an N electrode bonding pad of another PN junction unit in an equipotential manner or a P electrode bonding pad of one PN junction unit is connected with a P electrode bonding pad of another PN junction unit in an equipotential manner, the 2 PN junction units are in a parallel connection relationship, and the chip has an integration mode corresponding to the parallel connection relationship.

As a further preferred aspect of the present invention, the chip has an integration mode corresponding to both a series relationship and a parallel relationship, the chip integrates m × n PN junction units, n parallel branches are correspondingly formed, and each parallel branch is formed by m PN junction units through the series relationship; wherein m and n are integers more than or equal to 2;

preferably, the total P-pole flip pad and the total N-pole flip pad on the integrated chip are respectively located at the connection intersection of the N parallel branches.

As a further preferred aspect of the present invention, the N electrode pad of one PN junction unit is equipotentially connected to the P electrode pad of another PN junction unit, specifically, connected by a conductive metal material, and an electrical connection metal layer is correspondingly formed;

the N electrode bonding pad of one PN junction unit is connected with the N electrode bonding pad of the other PN junction unit in an equipotential manner, specifically, the N electrode bonding pads are connected through a conductive metal material to correspondingly form an electric connection metal layer;

the P electrode bonding pad of one PN junction unit is connected with the P electrode bonding pad of the other PN junction unit in an equipotential manner, specifically, the P electrode bonding pad of one PN junction unit is connected with the P electrode bonding pad of the other PN junction unit through a conductive metal material, and an electric connection metal layer is correspondingly formed;

further, 2 of these electrical connection metal layers are as the total P-pole flip chip pad and the total N-pole flip chip pad.

In a further preferred embodiment of the present invention, the electrically connecting metal layer is located outside the AlGaN epitaxial wafer and is connected to the AlGaN epitaxial wafer through a passivation material; the passivation material is selected from SiO₂、Si₃N₄、HfO₂A DBR structure of the Bragg reflector, wherein the DBR structure of the Bragg reflector is made of SiO₂And Ti₂O₅And (3) arranging the components periodically.

In a further preferred embodiment of the present invention, both the N electrode terminal and the P electrode terminal of any one of the PN junction units are located in the AlGaN epitaxial wafer, and are formed by etching an AlGaN material and depositing an electrode material.

As a further preferred aspect of the present invention, the N-electrode terminal and the P-electrode terminal of any one of the PN junction units are subjected to electrode thickening processing, so that the N-electrode terminal and the P-electrode terminal protrude from a plane where the upper surface of the AlGaN epitaxial wafer is located, and are connected to a PAD electrode above the AlGaN epitaxial wafer, where the PAD electrode is a PAD electrode.

As a further preferred aspect of the present invention, a passivation material is filled between adjacent PAD electrodes; the upper part of any PAD electrode is connected with the electric connection metal layer; the passivation material is selected from SiO₂、Si₃N₄、HfO₂A DBR structure of the Bragg reflector, wherein the DBR structure of the Bragg reflector is made of SiO₂And Ti₂O₅And (3) arranging the components periodically.

As a further preferred aspect of the present invention, the wafer substrate is a sapphire wafer or an AlN single crystal wafer.

According to another aspect of the present invention, the present invention provides a method for preparing the deep ultraviolet LED integrated chip, which includes the following steps:

(S1) taking a clean wafer substrate with the AlGaN deep ultraviolet epitaxial wafer epitaxially grown as a substrate, and forming an N electrode end and a P electrode end in the AlGaN deep ultraviolet epitaxial wafer in a target area of the AlGaN deep ultraviolet epitaxial wafer through photoetching, etching and metal evaporation processes; then, carrying out electrode thickening treatment on the N electrode end and the P electrode end to enable the N electrode end and the P electrode end to protrude out of the plane of the upper surface of the AlGaN deep ultraviolet epitaxial wafer;

(S2) forming a deep groove in the target area of the substrate through photoetching and etching processes, wherein the depth of the deep groove reaches the contact interface of the deep ultraviolet epitaxial wafer and the wafer substrate; then, depositing passivation materials, and enabling the passivation materials to fill the deep groove and cover the deep ultraviolet epitaxial wafer to form a passivation layer; then, photoetching and etching are carried out on the target area of the passivation layer to form an opening, photoetching is carried out on the position of the opening, and then metal evaporation is carried out to form a PAD electrode, namely a PAD electrode, so that the manufacturing of the single PN junction functional unit is finished;

(S3) next, depositing a second time of passivation materials so that the passivation materials cover the substrate to form a second passivation layer; then, photoetching and etching are carried out on the target area of the second passivation layer to form an opening, photoetching is carried out on the position of the opening, and then metal evaporation is carried out to form an electric connection metal layer, so that the preparation of the deep ultraviolet LED integrated chip is completed; 2 of these electrically connecting metal layers serve as a total P-pole flip-chip pad and a total N-pole flip-chip pad.

Through the technical scheme, in order to promote and promote the wide application of the deep ultraviolet LED light source, the chip integration technology is adopted in the front-stage process of the deep ultraviolet LED, integrated chips in various combination forms can be manufactured on COW (chip on wafer), and the integrated chips can achieve the effect of a module. The invention can effectively reduce the material cost, the labor cost and the time cost of production, and the volume of the device is only about 30 percent of that of the original module by taking two parallel and two serial devices as an example, and even the device can be made smaller. The invention is applied to the field of preparation and packaging of LED, in particular to deep ultraviolet LED chips.

According to the invention, through the design of the integrated chip with a plurality of light-emitting units connected in series and/or in parallel on a single wafer substrate, on the basis of the completion of a single-chip COW preparation process, the integration of the chip is realized through adding two photoetching processes (the two photoetching processes are respectively used for matching with the deposition of a second deposition layer and the evaporation of an electric connection metal layer) and a passivation layer process, and a connection process of an electrode, so that the technical effect equivalent to that of the module in the prior art is achieved.

The invention is suitable for integration in various modes, such as m-string and n-parallel integration modes (of course, the invention can be applied to integration of 2 light-emitting units at least). Taking two strings and two parallel as an example (i.e., m is 2, and n is 2), if a module in the conventional prior art is adopted, 4 single-core lamp beads form a module (i.e., a chip of each single light-emitting unit is packaged into a lamp bead, and then each lamp bead is assembled to form a module); the invention only needs to package two series of two parallel integrated chips into the lamp beads, the cost of packaging materials and manpower is only 1/4 of the module (namely 1/(m multiplied by n), and other m multiplied by n conditions are also applicable), and the volume of the device can be greatly reduced.

In addition, the chip integration method is very flexible, and due to the nonuniformity of the deep ultraviolet epitaxial wafer, the required integration mode can be flexibly selected according to COW test data, so that the reject ratio is effectively reduced. That is, the design of the integrated chip of the invention is to carry out integrated manufacturing after completing a single PN junction device, the design can carry out the test of photoelectric parameters after completing a single PN junction process, and the integration mode is flexibly selected through the distribution and yield of test data.

In conclusion, the integrated chip design and the integration method thereof are suitable for integration of various deep ultraviolet LED flip chips. The invention has flexible chip integration mode, reduced volume and reduced packaging cost, can be better integrated and assembled at the deep ultraviolet sterilization and disinfection application product end, is suitable for mass production, and has very wide application prospect in the deep ultraviolet LED module packaging.

Drawings

Fig. 1 is a schematic structural diagram of deep ultraviolet LED chip integration according to an embodiment of the present invention, where the structure shown in the diagram corresponds to two strings of two parallel integrated chips.

Fig. 2 is a flow chart of a deep ultraviolet LED chip integrated manufacturing process according to an embodiment of the present invention.

The meaning of the reference symbols in fig. 1 is as follows: 1-opening of passivation layer, 2-connection of P electrodes of two chips and P electrode flip bonding pad of integrated chip, 3-SiO of passivation layer₂4-two chips P-N electrodes are connected in series, 5-two chips N electrodes are connected and N pole flip bonding pads of the integrated chip are formed.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

In summary, as shown in fig. 2, the main material of the deep ultraviolet LED chip integrated manufacturing method of the present invention is a deep ultraviolet epitaxial material, and the main manufacturing process flow includes chemical cleaning, 9 photolithography processes, dry etching, wet etching, electron beam evaporation, metal alloy, and deposition of a silicon dioxide passivation layer. The method specifically comprises the following steps:

(1) cleaning an AlGaN-based deep ultraviolet epitaxial wafer, wherein the AlGaN-based deep ultraviolet epitaxial wafer is made of sapphire as a substrate and is a wafer with the size of 5.08 cm; the deep ultraviolet epitaxial wafer meets the conventional definition, namely, an AlN buffer layer, AlN/AlGaN superlattice, N-AlGaN, an active area AlGaN multi-quantum well, a P-AlGaN layer and a P-GaN layer are epitaxially grown on a wafer substrate (such as a sapphire substrate, AlN substrate and GaN substrate), and the deep ultraviolet epitaxial wafer can be directly prepared by adopting a commercially available product or can be prepared by a method known in the prior art;

(2) conducting mesa photoetching and etching to reach N-AlGaN so as to manufacture an N electrode;

(3) preparing an N electrode terminal, namely: the method comprises the following steps of N electrode photoetching, N-region metal electrode evaporation and N electrode alloy, wherein the N electrode alloy process is used for forming ohmic contact at a metal-semiconductor interface so as to reduce the voltage of a chip;

(4) preparing a P electrode terminal, namely: p electrode photoetching, P area metal electrode evaporation and P electrode alloy, wherein the P electrode alloy process is also used for forming ohmic contact at a metal-semiconductor interface so as to reduce the voltage of a chip;

(5) the thickened electrodes in the N area and the P area are subjected to photoetching and metal evaporation so as to ensure that the N-P electrode has better ground current expansion and heat dissipation;

(6) deep groove photoetching and deep groove etching are carried out to etch through the epitaxial layer material so as to prevent electric leakage between chips

(7) Depositing a first passivation layer and etching an opening;

(8) preparing a pad electrode, namely: PAD photoetching and electrode evaporation of a single PN junction N-P electrode;

(9) depositing a secondary passivation layer and etching an opening;

(10) and connecting the total bonding pad and the chip electrode by photoetching and metal electrode evaporation to complete the electrode connection between the total flip bonding pad and the integrated chip, as shown in fig. 1. Fig. 1 shows two series and two parallel integrated chips, which may be other integrated manners of m series and n parallel, or even an integrated manner of only m series or only n parallel (where m and n are both integers greater than or equal to 2).

The following are specific examples:

example 1

The embodiment comprises the following steps:

(1) cleaning the AlGaN epitaxial material: respectively mixing 98% concentrated sulfuric acid and 30% hydrogen peroxide solution in a volume ratio of 5: 1, cleaning for 10min at the temperature of about 90 ℃;

(2) mesa photoetching: spin-coating photoresist RD-2900 with the thickness of about 2.8um, and soft-baking at 120 ℃ for 70 s; cover the reticle, 365nm uv source projection exposure, exposure time 5.5s, AZ 400K: h₂O4: 1 development for 90s, film hardening 120 deg.cHot plate for 5 min; dry etching of Mesa in Cl₂And BCl₃Plasma etching the AlGaN material in the mixed atmosphere for 570 s; degumming liquid at 85 ℃ and degumming and cleaning.

(3) N electrode photoetching, N metal evaporation and N electrode RTA annealing: spin-coating photoresist RD-NL700(85CP) with a thickness of about 4.5um, soft-baking at 110 ℃ for 100 s; cover the reticle, 365nm uv source projection exposure, exposure time 3.5s, AZ 400K: h₂Developing for 70s at a ratio of 4:1, hardening a film on a hot plate at 120 ℃ for 2min, developing for 80s, gluing for 200W3min by oxygen plasma, drying by a drying machine, evaporating metal Ti/Al/Ti/Au by using electron beams, stripping a blue film, and removing glue and cleaning by a glue removing liquid at 85 ℃. And (3) annealing the N electrode rapid alloy, wherein the annealing temperature is 950-1 min.

(4) P electrode photoetching, P metal evaporation and P electrode RTA annealing, namely spin-coating photoresist RD-NL700(85CP), wherein the spin-coating thickness is about 4.5um, and soft-baking is carried out for 100s at 110 ℃; cover the reticle, 365nm uv source projection exposure, exposure time 3.5s, AZ 400K: h₂Developing for 70s at a ratio of 4:1, hardening a film on a hot plate at 120 ℃ for 2min, developing for 80s, gluing for 200W3min by oxygen plasma, spin-drying by a spin dryer, evaporating metal Ni/Au by using electron beams, stripping a blue film, and removing the glue by using a glue removing liquid at 85 ℃. And (3) annealing the P electrode rapid alloy at the annealing temperature of 550-3 min.

(5) Thickened electrode NP-THICK photoetching and metal evaporation: spin-coating photoresist RD-NL700(85CP) with a thickness of about 4.5um, soft-baking at 110 ℃ for 100 s; cover the reticle, 365nm uv source projection exposure, exposure time 3.5s, AZ 400K: h₂Developing for 70s at a ratio of 4:1, hardening a film on a hot plate at 120 ℃ for 2min, developing for 80s, gluing for 200W3min by oxygen plasma, drying by a drying machine, evaporating metals Cr/Al/Ti/Pt/Au/Ti by using electron beams, stripping a blue film, and cleaning the removed film at 85 ℃.

(6) Deep groove photoetching and deep groove etching: spin-coating photoresist RD-6100, the thickness of spin-coating is about 12um, and soft-baking is carried out for 150s at 120 ℃; cover the reticle, 365nm uv source projection exposure, exposure time 10s, AZ 400K: h₂Developing for 200s at a ratio of 4:1, hardening the film for 5min on a hot plate at 120 ℃; dry etching of deep trenches in Cl₂And BCl₃Etching the AlGaN material by plasma in the mixed atmosphere for 1260 s; degumming liquid at 85 ℃ and degumming and cleaning.

(7) PECVD deposition of passivation layer SiO₂And photoetching and etching the opening of the passivation layer: PECVD deposition of passivation layer SiO₂Has a thickness ofSpin-coating photoresist RD-6100, the thickness of spin-coating is about 12um, and soft-baking is carried out for 150s at 120 ℃; cover the reticle, 365nm uv source projection exposure, exposure time 10s, AZ 400K: h₂Developing for 200s at a ratio of 4:1, hardening the film for 5min on a hot plate at 120 ℃; SiO 2₂Dry etching in CF₄And BCl₃Plasma etching of SiO in a mixed atmosphere of₂Material, time 1600 s; degumming liquid at 85 ℃ and degumming and cleaning.

(8) PAD photoetching and PAD electrode evaporation: spin-coating photoresist RD-NL700(85CP) with a thickness of about 4.5um, soft-baking at 110 ℃ for 100 s; cover the reticle, 365nm uv source projection exposure, exposure time 3.5s, AZ 400K: h₂Developing for 70s at a ratio of 4:1, hardening a film on a hot plate at 120 ℃ for 2min, developing for 80s, gluing for 200W3min by oxygen plasma, spin-drying by a spin dryer, evaporating metals Cr/Al/Ti/Pt/Au/Ti by electron beams, stripping a blue film, removing the glue by a glue removing liquid at 85 ℃, and cleaning to obtain the COW with a single core.

(9) Second PECVD deposition of passivation layer SiO₂And photoetching and etching the opening of the passivation layer: PECVD deposition of passivation layer SiO₂Has a thickness ofSpin-coating photoresist RD-6100, the thickness of spin-coating is about 12um, and soft-baking is carried out for 150s at 120 ℃; cover the reticle, 365nm uv source projection exposure, exposure time 10s, AZ 400K: h₂Developing for 200s at a ratio of 4:1, hardening the film for 5min on a hot plate at 120 ℃; SiO 2₂Dry etching in CF₄And BCl₃Plasma etching of SiO in a mixed atmosphere of₂Material, time 1600 s; degumming liquid at 85 ℃ and degumming and cleaning.

(10) Connecting electrodes of the integrated chip, photoetching and electrode evaporation: spin-coating photoresist RD-NL700(85CP) with a thickness of about 4.5um, soft-baking at 110 ℃ for 100 s; cover the reticle, 365nm uv source projection exposure, exposure time 3.5s, AZ 400K: h₂O-4: 1 development 70s,hardening the film on a hot plate at 120 ℃ for 2min, developing for 80s, coating oxygen plasma for 200W3min, spin-drying by a spin dryer, evaporating metal Cr/Al/Ti/Pt/Ti/Pt/Au by using electron beams, stripping a blue film, removing the photoresist by using photoresist removing liquid at 85 ℃, and cleaning to obtain the COW of the integrated chip.

In the subsequent packaging process, the lamp beads packaged by two strings of two parallel integrated chips can replace a module consisting of four traditional single-core lamp beads, but the packaging material and the labor cost of the lamp beads are only 1/4 of the module, so that the production period of the module is greatly shortened, and the size of a device can be greatly reduced.

The reagents used in the above examples are all directly commercially available. In addition, the specific parameters and condition settings in the above embodiments are only examples, and other parameters and condition settings may also be adopted based on the present invention, which are not exhaustive.

It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.